[thirdparty/binutils-gdb.git] / opcodes / mips16-opc.c

/* mips16-opc.c.  Mips16 opcode table.
   Copyright (C) 1996-2016 Free Software Foundation, Inc.
   Contributed by Ian Lance Taylor, Cygnus Support

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING.  If not, write to the
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include "sysdep.h"
#include <stdio.h>
#include "opcode/mips.h"
#include "mips-formats.h"

static unsigned char reg_0_map[] = { 0 };
static unsigned char reg_29_map[] = { 29 };
static unsigned char reg_31_map[] = { 31 };
static unsigned char reg_m16_map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
static unsigned char reg32r_map[] = {
  0, 8, 16, 24,
  1, 9, 17, 25,
  2, 10, 18, 26,
  3, 11, 19, 27,
  4, 12, 20, 28,
  5, 13, 21, 29,
  6, 14, 22, 30,
  7, 15, 23, 31
};

/* Return the meaning of operand character TYPE, or null if it isn't
   recognized.  If the operand is affected by the EXTEND instruction,
   EXTENDED_P selects between the extended and unextended forms.
   The extended forms all have an lsb of 0.  */

const struct mips_operand *
decode_mips16_operand (char type, bfd_boolean extended_p)
{
  switch (type)
    {
    case '0': MAPPED_REG (0, 0, GP, reg_0_map);

    case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
    case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST);
    case 'P': SPECIAL (0, 0, PC);
    case 'R': MAPPED_REG (0, 0, GP, reg_31_map);
    case 'S': MAPPED_REG (0, 0, GP, reg_29_map);
    case 'X': REG (5, 0, GP);
    case 'Y': MAPPED_REG (5, 3, GP, reg32r_map);
    case 'Z': MAPPED_REG (3, 0, GP, reg_m16_map);

    case 'a': JUMP (26, 0, 2);
    case 'e': HINT (11, 0);
    case 'i': JALX (26, 0, 2);
    case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST);
    case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST);
    case 'v': OPTIONAL_MAPPED_REG (3, 8, GP, reg_m16_map);
    case 'w': OPTIONAL_MAPPED_REG (3, 5, GP, reg_m16_map);
    case 'x': MAPPED_REG (3, 8, GP, reg_m16_map);
    case 'y': MAPPED_REG (3, 5, GP, reg_m16_map);
    case 'z': MAPPED_REG (3, 2, GP, reg_m16_map);
    }

  if (extended_p)
    switch (type)
      {
      case '<': UINT (5, 0);
      case '[': UINT (6, 0);
      case ']': UINT (6, 0);

      case '4': SINT (15, 0);
      case '5': SINT (16, 0);
      case '6': SINT (16, 0);
      case '8': SINT (16, 0);

      case 'A': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
      case 'B': PCREL (16, 0, TRUE, 0, 3, FALSE, FALSE);
      case 'C': SINT (16, 0);
      case 'D': SINT (16, 0);
      case 'E': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
      case 'H': SINT (16, 0);
      case 'K': SINT (16, 0);
      case 'U': UINT (16, 0);
      case 'V': SINT (16, 0);
      case 'W': SINT (16, 0);

      case 'j': SINT (16, 0);
      case 'k': SINT (16, 0);
      case 'p': BRANCH (16, 0, 1);
      case 'q': BRANCH (16, 0, 1);
      }
  else
    switch (type)
      {
      case '<': INT_ADJ (3, 2, 8, 0, FALSE);
      case '[': INT_ADJ (3, 2, 8, 0, FALSE);
      case ']': INT_ADJ (3, 8, 8, 0, FALSE);

      case '4': SINT (4, 0);
      case '5': UINT (5, 0);
      case '6': UINT (6, 5);
      case '8': UINT (8, 0);

      case 'A': PCREL (8, 0, FALSE, 2, 2, FALSE, FALSE);
      case 'B': PCREL (5, 0, FALSE, 3, 3, FALSE, FALSE);
      case 'C': INT_ADJ (8, 0, 255, 3, FALSE);	/* (0 .. 255) << 3 */
      case 'D': INT_ADJ (5, 0, 31, 3, FALSE);	/* (0 .. 31) << 3 */
      case 'E': PCREL (5, 0, FALSE, 2, 2, FALSE, FALSE);
      case 'H': INT_ADJ (5, 0, 31, 1, FALSE);	/* (0 .. 31) << 1 */
      case 'K': INT_ADJ (8, 0, 127, 3, FALSE);	/* (-128 .. 127) << 3 */
      case 'U': UINT (8, 0);
      case 'V': INT_ADJ (8, 0, 255, 2, FALSE);	/* (0 .. 255) << 2 */
      case 'W': INT_ADJ (5, 0, 31, 2, FALSE);	/* (0 .. 31) << 2 */

      case 'j': SINT (5, 0);
      case 'k': SINT (8, 0);
      case 'p': BRANCH (8, 0, 1);
      case 'q': BRANCH (11, 0, 1);
      }
  return 0;
}

/* This is the opcodes table for the mips16 processor.  The format of
   this table is intentionally identical to the one in mips-opc.c.
   However, the special letters that appear in the argument string are
   different, and the table uses some different flags.  */

/* Use some short hand macros to keep down the length of the lines in
   the opcodes table.  */

#define UBD     INSN_UNCOND_BRANCH_DELAY

#define WR_1	INSN_WRITE_1
#define WR_2	INSN_WRITE_2
#define RD_1	INSN_READ_1
#define RD_2	INSN_READ_2
#define RD_3	INSN_READ_3
#define RD_4	INSN_READ_4
#define MOD_1	(WR_1|RD_1)
#define MOD_2	(WR_2|RD_2)

#define RD_T	INSN_READ_GPR_24
#define WR_T	INSN_WRITE_GPR_24
#define WR_31	INSN_WRITE_GPR_31

#define WR_HI	INSN_WRITE_HI
#define WR_LO	INSN_WRITE_LO
#define RD_HI	INSN_READ_HI
#define RD_LO	INSN_READ_LO

#define NODS	INSN_NO_DELAY_SLOT
#define TRAP	INSN_NO_DELAY_SLOT

#define RD_16	INSN2_READ_GPR_16
#define RD_SP	INSN2_READ_SP
#define WR_SP	INSN2_WRITE_SP
#define MOD_SP	(RD_SP|WR_SP)
#define RD_31	INSN2_READ_GPR_31
#define RD_PC	INSN2_READ_PC
#define UBR	INSN2_UNCOND_BRANCH
#define CBR	INSN2_COND_BRANCH

#define I1	INSN_ISA1
#define I3	INSN_ISA3
#define I32	INSN_ISA32
#define I64	INSN_ISA64
#define T3	INSN_3900

const struct mips_opcode mips16_opcodes[] =
{
/* name,    args,	match,	mask,		pinfo,			pinfo2, membership,	ase,	exclusions */
{"nop",	    "",		0x6500, 0xffff,		0,			RD_16,		I1,	0,	0 }, /* move $0,$Z */
{"la",	    "x,A",	0x0800, 0xf800,		WR_1,			RD_PC,		I1,	0,	0 },
{"abs",	    "x,w",	0, (int) M_ABS,		INSN_MACRO,		0,		I1,	0,	0 },
{"addiu",   "y,x,4",	0x4000, 0xf810,		WR_1|RD_2,		0,		I1,	0,	0 },
{"addiu",   "x,k",	0x4800, 0xf800,		MOD_1,			0,		I1,	0,	0 },
{"addiu",   "S,K",	0x6300, 0xff00,		0,			MOD_SP,		I1,	0,	0 },
{"addiu",   "S,S,K",	0x6300, 0xff00,		0,			MOD_SP,		I1,	0,	0 },
{"addiu",   "x,P,V",	0x0800, 0xf800,		WR_1,			RD_PC,		I1,	0,	0 },
{"addiu",   "x,S,V",	0x0000, 0xf800,		WR_1,			RD_SP,		I1,	0,	0 },
{"addu",    "z,v,y",	0xe001, 0xf803,		WR_1|RD_2|RD_3,		0,		I1,	0,	0 },
{"addu",    "y,x,4",	0x4000, 0xf810,		WR_1|RD_2,		0,		I1,	0,	0 },
{"addu",    "x,k",	0x4800, 0xf800,		MOD_1,			0,		I1,	0,	0 },
{"addu",    "S,K",	0x6300, 0xff00,		0,			MOD_SP,		I1,	0,	0 },
{"addu",    "S,S,K",	0x6300, 0xff00,		0,			MOD_SP,		I1,	0,	0 },
{"addu",    "x,P,V",	0x0800, 0xf800,		WR_1,			RD_PC,		I1,	0,	0 },
{"addu",    "x,S,V",	0x0000, 0xf800,		WR_1,			RD_SP,		I1,	0,	0 },
{"and",	    "x,y",	0xe80c, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
{"b",	    "q",	0x1000, 0xf800,		0,			UBR,		I1,	0,	0 },
{"beq",	    "x,y,p",	0, (int) M_BEQ,		INSN_MACRO,		0,		I1,	0,	0 },
{"beq",     "x,I,p",	0, (int) M_BEQ_I,	INSN_MACRO,		0,		I1,	0,	0 },
{"beqz",    "x,p",	0x2000, 0xf800,		RD_1,			CBR,		I1,	0,	0 },
{"bge",	    "x,y,p",	0, (int) M_BGE,		INSN_MACRO,		0,		I1,	0,	0 },
{"bge",     "x,I,p",	0, (int) M_BGE_I,	INSN_MACRO,		0,		I1,	0,	0 },
{"bgeu",    "x,y,p",	0, (int) M_BGEU,	INSN_MACRO,		0,		I1,	0,	0 },
{"bgeu",    "x,I,p",	0, (int) M_BGEU_I,	INSN_MACRO,		0,		I1,	0,	0 },
{"bgt",	    "x,y,p",	0, (int) M_BGT,		INSN_MACRO,		0,		I1,	0,	0 },
{"bgt",     "x,I,p",	0, (int) M_BGT_I,	INSN_MACRO,		0,		I1,	0,	0 },
{"bgtu",    "x,y,p",	0, (int) M_BGTU,	INSN_MACRO,		0,		I1,	0,	0 },
{"bgtu",    "x,I,p",	0, (int) M_BGTU_I,	INSN_MACRO,		0,		I1,	0,	0 },
{"ble",	    "x,y,p",	0, (int) M_BLE,		INSN_MACRO,		0,		I1,	0,	0 },
{"ble",     "x,I,p",	0, (int) M_BLE_I,	INSN_MACRO,		0,		I1,	0,	0 },
{"bleu",    "x,y,p",	0, (int) M_BLEU,	INSN_MACRO,		0,		I1,	0,	0 },
{"bleu",    "x,I,p",	0, (int) M_BLEU_I,	INSN_MACRO,		0,		I1,	0,	0 },
{"blt",	    "x,y,p",	0, (int) M_BLT,		INSN_MACRO,		0,		I1,	0,	0 },
{"blt",     "x,I,p",	0, (int) M_BLT_I,	INSN_MACRO,		0,		I1,	0,	0 },
{"bltu",    "x,y,p",	0, (int) M_BLTU,	INSN_MACRO,		0,		I1,	0,	0 },
{"bltu",    "x,I,p",	0, (int) M_BLTU_I,	INSN_MACRO,		0,		I1,	0,	0 },
{"bne",	    "x,y,p",	0, (int) M_BNE,		INSN_MACRO,		0,		I1,	0,	0 },
{"bne",     "x,I,p",	0, (int) M_BNE_I,	INSN_MACRO,		0,		I1,	0,	0 },
{"bnez",    "x,p",	0x2800, 0xf800,		RD_1,			CBR,		I1,	0,	0 },
{"break",   "6",	0xe805, 0xf81f,		TRAP,			0,		I1,	0,	0 },
{"bteqz",   "p",	0x6000, 0xff00,		RD_T,			CBR,		I1,	0,	0 },
{"btnez",   "p",	0x6100, 0xff00,		RD_T,			CBR,		I1,	0,	0 },
{"cmpi",    "x,U",	0x7000, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
{"cmp",	    "x,y",	0xe80a, 0xf81f,		RD_1|RD_2|WR_T,		0,		I1,	0,	0 },
{"cmp",     "x,U",	0x7000, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
{"dla",	    "y,E",	0xfe00, 0xff00,		WR_1, 			RD_PC,		I3,	0,	0 },
{"daddiu",  "y,x,4",	0x4010, 0xf810,		WR_1|RD_2, 		0,		I3,	0,	0 },
{"daddiu",  "y,j",	0xfd00, 0xff00,		MOD_1,			0,		I3,	0,	0 },
{"daddiu",  "S,K",	0xfb00, 0xff00,		0,	 		MOD_SP,		I3,	0,	0 },
{"daddiu",  "S,S,K",	0xfb00, 0xff00,		0,	 		MOD_SP,		I3,	0,	0 },
{"daddiu",  "y,P,W",	0xfe00, 0xff00,		WR_1,	 		RD_PC,		I3,	0,	0 },
{"daddiu",  "y,S,W",	0xff00, 0xff00,		WR_1,			RD_SP,		I3,	0,	0 },
{"daddu",   "z,v,y",	0xe000, 0xf803,		WR_1|RD_2|RD_3, 	0,		I3,	0,	0 },
{"daddu",   "y,x,4",	0x4010, 0xf810,		WR_1|RD_2, 		0,		I3,	0,	0 },
{"daddu",   "y,j",	0xfd00, 0xff00,		MOD_1,			0,		I3,	0,	0 },
{"daddu",   "S,K",	0xfb00, 0xff00,		0,	 		MOD_SP,		I3,	0,	0 },
{"daddu",   "S,S,K",	0xfb00, 0xff00,		0,	 		MOD_SP,		I3,	0,	0 },
{"daddu",   "y,P,W",	0xfe00, 0xff00,		WR_1,	 		RD_PC,		I3,	0,	0 },
{"daddu",   "y,S,W",	0xff00, 0xff00,		WR_1,			RD_SP,		I3,	0,	0 },
{"ddiv",    "0,x,y",	0xe81e, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO,	0,		I3,	0,	0 },
{"ddiv",    "z,v,y",	0, (int) M_DDIV_3,	INSN_MACRO,		0,		I3,	0,	0 },
{"ddivu",   "0,x,y",	0xe81f, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO, 	0,		I3,	0,	0 },
{"ddivu",   "z,v,y",	0, (int) M_DDIVU_3,	INSN_MACRO,		0,		I3,	0,	0 },
{"div",     "0,x,y",	0xe81a, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO,	0,		I1,	0,	0 },
{"div",     "z,v,y",	0, (int) M_DIV_3,	INSN_MACRO,		0,		I1,	0,	0 },
{"divu",    "0,x,y",	0xe81b, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO,	0,		I1,	0,	0 },
{"divu",    "z,v,y",	0, (int) M_DIVU_3,	INSN_MACRO,		0,		I1,	0,	0 },
{"dmul",    "z,v,y",	0, (int) M_DMUL,	INSN_MACRO, 		0,		I3,	0,	0 },
{"dmult",   "x,y",	0xe81c, 0xf81f, 	RD_1|RD_2|WR_HI|WR_LO, 	0,		I3,	0,	0 },
{"dmultu",  "x,y",	0xe81d, 0xf81f, 	RD_1|RD_2|WR_HI|WR_LO, 	0,		I3,	0,	0 },
{"drem",    "0,x,y",	0xe81e, 0xf81f, 	RD_2|RD_3|WR_HI|WR_LO, 	0,		I3,	0,	0 },
{"drem",    "z,v,y",	0, (int) M_DREM_3,	INSN_MACRO,		0,		I3,	0,	0 },
{"dremu",   "0,x,y",	0xe81f, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO, 	0,		I3,	0,	0 },
{"dremu",   "z,v,y",	0, (int) M_DREMU_3,	INSN_MACRO,		0,		I3,	0,	0 },
{"dsllv",   "y,x",	0xe814, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
{"dsll",    "x,w,[",	0x3001, 0xf803,		WR_1|RD_2, 		0,		I3,	0,	0 },
{"dsll",    "y,x",	0xe814, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
{"dsrav",   "y,x",	0xe817, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
{"dsra",    "y,]",	0xe813, 0xf81f,		MOD_1,			0,		I3,	0,	0 },
{"dsra",    "y,x",	0xe817, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
{"dsrlv",   "y,x",	0xe816, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
{"dsrl",    "y,]",	0xe808, 0xf81f,		MOD_1,			0,		I3,	0,	0 },
{"dsrl",    "y,x",	0xe816, 0xf81f,		MOD_1|RD_2, 	0,		I3,	0,	0 },
{"dsubu",   "z,v,y",	0xe002, 0xf803,		WR_1|RD_2|RD_3, 	0,		I3,	0,	0 },
{"dsubu",   "y,x,I",	0, (int) M_DSUBU_I,	INSN_MACRO,		0,		I3,	0,	0 },
{"dsubu",   "y,I",	0, (int) M_DSUBU_I_2,	INSN_MACRO, 		0,		I3,	0,	0 },
{"exit",    "L",	0xed09, 0xff1f,		TRAP,			0,		I1,	0,	0 },
{"exit",    "L",	0xee09, 0xff1f,		TRAP,			0,		I1,	0,	0 },
{"exit",    "",		0xef09, 0xffff,		TRAP,			0,		I1,	0,	0 },
{"exit",    "L",	0xef09, 0xff1f,		TRAP,			0,		I1,	0,	0 },
{"entry",   "",		0xe809, 0xffff,		TRAP,			0,		I1,	0,	0 },
{"entry",   "l",	0xe809, 0xf81f,		TRAP,			0,		I1,	0,	0 },
{"extend",  "e",	0xf000, 0xf800,		0,			0,		I1,	0,	0 },
{"jalr",    "x",	0xe840, 0xf8ff,		RD_1|WR_31|UBD,		0,		I1,	0,	0 },
{"jalr",    "R,x",	0xe840, 0xf8ff,		RD_2|WR_31|UBD,		0,		I1,	0,	0 },
{"jal",     "x",	0xe840, 0xf8ff,		RD_1|WR_31|UBD,		0,		I1,	0,	0 },
{"jal",     "R,x",	0xe840, 0xf8ff,		RD_2|WR_31|UBD,		0,		I1,	0,	0 },
{"jal",	    "a",	0x1800, 0xfc00,		WR_31|UBD,		0,		I1,	0,	0 },
{"jalx",    "i",	0x1c00, 0xfc00,		WR_31|UBD,		0,		I1,	0,	0 },
{"jr",	    "x",	0xe800, 0xf8ff,		RD_1|UBD,		0,		I1,	0,	0 },
{"jr",	    "R",	0xe820, 0xffff,		UBD,			RD_31,		I1,	0,	0 },
{"j",	    "x",	0xe800, 0xf8ff,		RD_1|UBD,		0,		I1,	0,	0 },
{"j",	    "R",	0xe820, 0xffff,		UBD,			RD_31,		I1,	0,	0 },
/* MIPS16e compact jumps.  We keep them near the ordinary jumps
   so that we easily find them when converting a normal jump
   to a compact one.  */
{"jalrc",   "x",	0xe8c0, 0xf8ff,		RD_1|WR_31|NODS,	UBR,		I32,	0,	0 },
{"jalrc",   "R,x",	0xe8c0, 0xf8ff,		RD_2|WR_31|NODS,	UBR,		I32,	0,	0 },
{"jrc",	    "x",	0xe880, 0xf8ff,		RD_1|NODS,		UBR,		I32,	0,	0 },
{"jrc",	    "R",	0xe8a0, 0xffff,		NODS,			RD_31|UBR,	I32,	0,	0 },
{"lb",	    "y,5(x)",	0x8000, 0xf800,		WR_1|RD_3,		0,		I1,	0,	0 },
{"lbu",	    "y,5(x)",	0xa000, 0xf800,		WR_1|RD_3,		0,		I1,	0,	0 },
{"ld",	    "y,D(x)",	0x3800, 0xf800,		WR_1|RD_3, 		0,		I3,	0,	0 },
{"ld",	    "y,B",	0xfc00, 0xff00,		WR_1,	 		RD_PC,		I3,	0,	0 },
{"ld",	    "y,D(P)",	0xfc00, 0xff00,		WR_1,	 		RD_PC,		I3,	0,	0 },
{"ld",	    "y,D(S)",	0xf800, 0xff00,		WR_1,			RD_SP,		I3,	0,	0 },
{"lh",	    "y,H(x)",	0x8800, 0xf800,		WR_1|RD_3,		0,		I1,	0,	0 },
{"lhu",	    "y,H(x)",	0xa800, 0xf800,		WR_1|RD_3,		0,		I1,	0,	0 },
{"li",	    "x,U",	0x6800, 0xf800,		WR_1,			0,		I1,	0,	0 },
{"lw",	    "y,W(x)",	0x9800, 0xf800,		WR_1|RD_3,		0,		I1,	0,	0 },
{"lw",	    "x,A",	0xb000, 0xf800,		WR_1,			RD_PC,		I1,	0,	0 },
{"lw",	    "x,V(P)",	0xb000, 0xf800,		WR_1,			RD_PC,		I1,	0,	0 },
{"lw",	    "x,V(S)",	0x9000, 0xf800,		WR_1,			RD_SP,		I1,	0,	0 },
{"lwu",     "y,W(x)",	0xb800, 0xf800,		WR_1|RD_3, 		0,		I3,	0,	0 },
{"mfhi",    "x",	0xe810, 0xf8ff,		WR_1|RD_HI,		0,		I1,	0,	0 },
{"mflo",    "x",	0xe812, 0xf8ff,		WR_1|RD_LO,		0,		I1,	0,	0 },
{"move",    "y,X",	0x6700, 0xff00,		WR_1|RD_2, 		0,		I1,	0,	0 },
{"move",    "Y,Z",	0x6500, 0xff00,		WR_1|RD_2,		0,		I1,	0,	0 },
{"mul",     "z,v,y",	0, (int) M_MUL, 	INSN_MACRO,		0,		I1,	0,	0 },
{"mult",    "x,y",	0xe818, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		I1,	0,	0 },
{"multu",   "x,y",	0xe819, 0xf81f,		RD_1|RD_2|WR_HI|WR_LO,	0,		I1,	0,	0 },
{"neg",	    "x,w",	0xe80b, 0xf81f,		WR_1|RD_2,		0,		I1,	0,	0 },
{"not",	    "x,w",	0xe80f, 0xf81f,		WR_1|RD_2,		0,		I1,	0,	0 },
{"or",	    "x,y",	0xe80d, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
{"rem",     "0,x,y",	0xe81a, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO,	0,		I1,	0,	0 },
{"rem",     "z,v,y",	0, (int) M_REM_3,	INSN_MACRO,		0,		I1,	0,	0 },
{"remu",    "0,x,y",	0xe81b, 0xf81f,		RD_2|RD_3|WR_HI|WR_LO,	0,		I1,	0,	0 },
{"remu",    "z,v,y",	0, (int) M_REMU_3,	INSN_MACRO,		0,		I1,	0,	0 },
{"sb",	    "y,5(x)",	0xc000, 0xf800,		RD_1|RD_3,		0,		I1,	0,	0 },
{"sd",	    "y,D(x)",	0x7800, 0xf800,		RD_1|RD_3, 		0,		I3,	0,	0 },
{"sd",	    "y,D(S)",	0xf900, 0xff00,		RD_1, 			RD_SP,		I3,	0,	0 },
{"sd",	    "R,C(S)",	0xfa00, 0xff00,		0,			RD_31|RD_SP,	I3,	0,	0 },
{"sh",	    "y,H(x)",	0xc800, 0xf800,		RD_1|RD_3,		0,		I1,	0,	0 },
{"sllv",    "y,x",	0xe804, 0xf81f,		MOD_1|RD_2, 	0,		I1,	0,	0 },
{"sll",	    "x,w,<",	0x3000, 0xf803,		WR_1|RD_2,		0,		I1,	0,	0 },
{"sll",     "y,x",	0xe804, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
{"slti",    "x,8",	0x5000, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
{"slt",	    "x,y",	0xe802, 0xf81f,		RD_1|RD_2|WR_T,		0,		I1,	0,	0 },
{"slt",     "x,8",	0x5000, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
{"sltiu",   "x,8",	0x5800, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
{"sltu",    "x,y",	0xe803, 0xf81f,		RD_1|RD_2|WR_T,		0,		I1,	0,	0 },
{"sltu",    "x,8",	0x5800, 0xf800,		RD_1|WR_T,		0,		I1,	0,	0 },
{"srav",    "y,x",	0xe807, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
{"sra",	    "x,w,<",	0x3003, 0xf803,		WR_1|RD_2,		0,		I1,	0,	0 },
{"sra",     "y,x",	0xe807, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
{"srlv",    "y,x",	0xe806, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
{"srl",	    "x,w,<",	0x3002, 0xf803,		WR_1|RD_2,		0,		I1,	0,	0 },
{"srl",     "y,x",	0xe806, 0xf81f,		MOD_1|RD_2,		0,		I1,	0,	0 },
{"subu",    "z,v,y",	0xe003, 0xf803,		WR_1|RD_2|RD_3,		0,		I1,	0,	0 },
{"subu",    "y,x,I",	0, (int) M_SUBU_I,	INSN_MACRO,		0,		I1,	0,	0 },
{"subu",    "x,I",	0, (int) M_SUBU_I_2,	INSN_MACRO,		0,		I1,	0,	0 },
{"sw",	    "y,W(x)",	0xd800, 0xf800,		RD_1|RD_3,		0,		I1,	0,	0 },
{"sw",	    "x,V(S)",	0xd000, 0xf800,		RD_1,			RD_SP,		I1,	0,	0 },
{"sw",	    "R,V(S)",	0x6200, 0xff00,		0,			RD_31|RD_SP,	I1,	0,	0 },
{"xor",	    "x,y",	0xe80e, 0xf81f,		MOD_1|RD_2, 	0,		I1,	0,	0 },
  /* MIPS16e additions; see above for compact jumps.  */
{"restore", "M",	0x6400, 0xff80,		WR_31|NODS,		MOD_SP,		I32,	0,	0 },
{"save",    "m",	0x6480, 0xff80,		NODS,			RD_31|MOD_SP,	I32,	0,	0 },
{"sdbbp",   "6",	0xe801, 0xf81f,		TRAP,			0,		I32,	0,	0 },
{"seb",	    "x",	0xe891, 0xf8ff,		MOD_1,			0,		I32,	0,	0 },
{"seh",	    "x",	0xe8b1, 0xf8ff,		MOD_1,			0,		I32,	0,	0 },
{"sew",	    "x",	0xe8d1, 0xf8ff,		MOD_1,			0,		I64,	0,	0 },
{"zeb",	    "x",	0xe811, 0xf8ff,		MOD_1,			0,		I32,	0,	0 },
{"zeh",	    "x",	0xe831, 0xf8ff,		MOD_1,			0,		I32,	0,	0 },
{"zew",	    "x",	0xe851, 0xf8ff,		MOD_1,			0,		I64,	0,	0 },
};

const int bfd_mips16_num_opcodes =
  ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));
Commit	Line	Data
252b5132	1	/* mips16-opc.c. Mips16 opcode table.
6f2750fe	2	Copyright (C) 1996-2016 Free Software Foundation, Inc.
252b5132 RH	3	Contributed by Ian Lance Taylor, Cygnus Support
252b5132 RH	4
9b201bb5	5	This file is part of the GNU opcodes library.
252b5132	6
9b201bb5 NC	7	This library is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 3, or (at your option)
	10	any later version.
252b5132	11
9b201bb5 NC	12	It is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
252b5132	16
9b201bb5 NC	17	You should have received a copy of the GNU General Public License
	18	along with this file; see the file COPYING. If not, write to the
	19	Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
	20	MA 02110-1301, USA. */
252b5132	21
0d8dfecf	22	#include "sysdep.h"
df7b86aa	23	#include <stdio.h>
252b5132	24	#include "opcode/mips.h"
c3c07478 RS	25	#include "mips-formats.h"
	26
	27	static unsigned char reg_0_map[] = { 0 };
	28	static unsigned char reg_29_map[] = { 29 };
	29	static unsigned char reg_31_map[] = { 31 };
	30	static unsigned char reg_m16_map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
	31	static unsigned char reg32r_map[] = {
	32	0, 8, 16, 24,
	33	1, 9, 17, 25,
	34	2, 10, 18, 26,
	35	3, 11, 19, 27,
	36	4, 12, 20, 28,
	37	5, 13, 21, 29,
	38	6, 14, 22, 30,
	39	7, 15, 23, 31
	40	};
	41
	42	/* Return the meaning of operand character TYPE, or null if it isn't
	43	recognized. If the operand is affected by the EXTEND instruction,
	44	EXTENDED_P selects between the extended and unextended forms.
	45	The extended forms all have an lsb of 0. */
	46
	47	const struct mips_operand *
	48	decode_mips16_operand (char type, bfd_boolean extended_p)
	49	{
	50	switch (type)
	51	{
	52	case '0': MAPPED_REG (0, 0, GP, reg_0_map);
	53
	54	case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
	55	case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST);
	56	case 'P': SPECIAL (0, 0, PC);
	57	case 'R': MAPPED_REG (0, 0, GP, reg_31_map);
	58	case 'S': MAPPED_REG (0, 0, GP, reg_29_map);
	59	case 'X': REG (5, 0, GP);
	60	case 'Y': MAPPED_REG (5, 3, GP, reg32r_map);
	61	case 'Z': MAPPED_REG (3, 0, GP, reg_m16_map);
	62
	63	case 'a': JUMP (26, 0, 2);
f17ecb4b	64	case 'e': HINT (11, 0);
c3c07478 RS	65	case 'i': JALX (26, 0, 2);
	66	case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST);
	67	case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST);
0f35dbc4 RS	68	case 'v': OPTIONAL_MAPPED_REG (3, 8, GP, reg_m16_map);
0f35dbc4 RS	69	case 'w': OPTIONAL_MAPPED_REG (3, 5, GP, reg_m16_map);
c3c07478 RS	70	case 'x': MAPPED_REG (3, 8, GP, reg_m16_map);
	71	case 'y': MAPPED_REG (3, 5, GP, reg_m16_map);
	72	case 'z': MAPPED_REG (3, 2, GP, reg_m16_map);
	73	}
	74
	75	if (extended_p)
	76	switch (type)
	77	{
	78	case '<': UINT (5, 0);
c3c07478 RS	79	case '[': UINT (6, 0);
	80	case ']': UINT (6, 0);
	81
	82	case '4': SINT (15, 0);
	83	case '5': SINT (16, 0);
	84	case '6': SINT (16, 0);
	85	case '8': SINT (16, 0);
	86
3ccad066 RS	87	case 'A': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
3ccad066 RS	88	case 'B': PCREL (16, 0, TRUE, 0, 3, FALSE, FALSE);
c3c07478 RS	89	case 'C': SINT (16, 0);
c3c07478 RS	90	case 'D': SINT (16, 0);
3ccad066	91	case 'E': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
c3c07478 RS	92	case 'H': SINT (16, 0);
	93	case 'K': SINT (16, 0);
	94	case 'U': UINT (16, 0);
	95	case 'V': SINT (16, 0);
	96	case 'W': SINT (16, 0);
	97
	98	case 'j': SINT (16, 0);
	99	case 'k': SINT (16, 0);
	100	case 'p': BRANCH (16, 0, 1);
	101	case 'q': BRANCH (16, 0, 1);
	102	}
	103	else
	104	switch (type)
	105	{
	106	case '<': INT_ADJ (3, 2, 8, 0, FALSE);
c3c07478 RS	107	case '[': INT_ADJ (3, 2, 8, 0, FALSE);
	108	case ']': INT_ADJ (3, 8, 8, 0, FALSE);
	109
	110	case '4': SINT (4, 0);
	111	case '5': UINT (5, 0);
	112	case '6': UINT (6, 5);
	113	case '8': UINT (8, 0);
	114
3ccad066 RS	115	case 'A': PCREL (8, 0, FALSE, 2, 2, FALSE, FALSE);
3ccad066 RS	116	case 'B': PCREL (5, 0, FALSE, 3, 3, FALSE, FALSE);
c3c07478 RS	117	case 'C': INT_ADJ (8, 0, 255, 3, FALSE); /* (0 .. 255) << 3 */
c3c07478 RS	118	case 'D': INT_ADJ (5, 0, 31, 3, FALSE); /* (0 .. 31) << 3 */
3ccad066	119	case 'E': PCREL (5, 0, FALSE, 2, 2, FALSE, FALSE);
c3c07478 RS	120	case 'H': INT_ADJ (5, 0, 31, 1, FALSE); /* (0 .. 31) << 1 */
	121	case 'K': INT_ADJ (8, 0, 127, 3, FALSE); /* (-128 .. 127) << 3 */
	122	case 'U': UINT (8, 0);
	123	case 'V': INT_ADJ (8, 0, 255, 2, FALSE); /* (0 .. 255) << 2 */
	124	case 'W': INT_ADJ (5, 0, 31, 2, FALSE); /* (0 .. 31) << 2 */
	125
	126	case 'j': SINT (5, 0);
	127	case 'k': SINT (8, 0);
	128	case 'p': BRANCH (8, 0, 1);
	129	case 'q': BRANCH (11, 0, 1);
	130	}
	131	return 0;
	132	}
252b5132 RH	133
	134	/* This is the opcodes table for the mips16 processor. The format of
	135	this table is intentionally identical to the one in mips-opc.c.
	136	However, the special letters that appear in the argument string are
	137	different, and the table uses some different flags. */
	138
	139	/* Use some short hand macros to keep down the length of the lines in
	140	the opcodes table. */
	141
	142	#define UBD INSN_UNCOND_BRANCH_DELAY
252b5132	143
fc76e730 RS	144	#define WR_1 INSN_WRITE_1
	145	#define WR_2 INSN_WRITE_2
	146	#define RD_1 INSN_READ_1
	147	#define RD_2 INSN_READ_2
	148	#define RD_3 INSN_READ_3
	149	#define RD_4 INSN_READ_4
	150	#define MOD_1 (WR_1\|RD_1)
	151	#define MOD_2 (WR_2\|RD_2)
252b5132	152
fc76e730 RS	153	#define RD_T INSN_READ_GPR_24
	154	#define WR_T INSN_WRITE_GPR_24
	155	#define WR_31 INSN_WRITE_GPR_31
252b5132 RH	156
	157	#define WR_HI INSN_WRITE_HI
	158	#define WR_LO INSN_WRITE_LO
	159	#define RD_HI INSN_READ_HI
	160	#define RD_LO INSN_READ_LO
	161
bcd530a7 RS	162	#define NODS INSN_NO_DELAY_SLOT
bcd530a7 RS	163	#define TRAP INSN_NO_DELAY_SLOT
252b5132	164
fc76e730 RS	165	#define RD_16 INSN2_READ_GPR_16
	166	#define RD_SP INSN2_READ_SP
	167	#define WR_SP INSN2_WRITE_SP
	168	#define MOD_SP (RD_SP\|WR_SP)
26545944 RS	169	#define RD_31 INSN2_READ_GPR_31
	170	#define RD_PC INSN2_READ_PC
	171	#define UBR INSN2_UNCOND_BRANCH
	172	#define CBR INSN2_COND_BRANCH
	173
9b3f89ee	174	#define I1 INSN_ISA1
252b5132	175	#define I3 INSN_ISA3
9b3f89ee TS	176	#define I32 INSN_ISA32
	177	#define I64 INSN_ISA64
	178	#define T3 INSN_3900
252b5132	179
b23da31b NC	180	const struct mips_opcode mips16_opcodes[] =
b23da31b NC	181	{
343fa690	182	/* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */
fc76e730 RS	183	{"nop", "", 0x6500, 0xffff, 0, RD_16, I1, 0, 0 }, /* move $0,$Z */
fc76e730 RS	184	{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
a8d92fc6	185	{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 RS	186	{"addiu", "y,x,4", 0x4000, 0xf810, WR_1\|RD_2, 0, I1, 0, 0 },
fc76e730 RS	187	{"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
26545944 RS	188	{"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
26545944 RS	189	{"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
fc76e730 RS	190	{"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
	191	{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
	192	{"addu", "z,v,y", 0xe001, 0xf803, WR_1\|RD_2\|RD_3, 0, I1, 0, 0 },
	193	{"addu", "y,x,4", 0x4000, 0xf810, WR_1\|RD_2, 0, I1, 0, 0 },
	194	{"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
26545944 RS	195	{"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
26545944 RS	196	{"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
fc76e730 RS	197	{"addu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
	198	{"addu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
	199	{"and", "x,y", 0xe80c, 0xf81f, MOD_1\|RD_2, 0, I1, 0, 0 },
26545944	200	{"b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 },
a8d92fc6 RS	201	{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 },
a8d92fc6 RS	202	{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
fc76e730	203	{"beqz", "x,p", 0x2000, 0xf800, RD_1, CBR, I1, 0, 0 },
a8d92fc6 RS	204	{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
	205	{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
	206	{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
	207	{"bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 },
	208	{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 },
	209	{"bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 },
	210	{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 },
	211	{"bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 },
	212	{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 },
	213	{"ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 },
	214	{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 },
	215	{"bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 },
	216	{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 },
	217	{"blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 },
	218	{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 },
	219	{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
	220	{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 },
	221	{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
fc76e730	222	{"bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 },
a8d92fc6	223	{"break", "6", 0xe805, 0xf81f, TRAP, 0, I1, 0, 0 },
26545944 RS	224	{"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 },
26545944 RS	225	{"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 },
fc76e730 RS	226	{"cmpi", "x,U", 0x7000, 0xf800, RD_1\|WR_T, 0, I1, 0, 0 },
	227	{"cmp", "x,y", 0xe80a, 0xf81f, RD_1\|RD_2\|WR_T, 0, I1, 0, 0 },
	228	{"cmp", "x,U", 0x7000, 0xf800, RD_1\|WR_T, 0, I1, 0, 0 },
	229	{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
	230	{"daddiu", "y,x,4", 0x4010, 0xf810, WR_1\|RD_2, 0, I3, 0, 0 },
	231	{"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
26545944 RS	232	{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
26545944 RS	233	{"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
fc76e730 RS	234	{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
	235	{"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
	236	{"daddu", "z,v,y", 0xe000, 0xf803, WR_1\|RD_2\|RD_3, 0, I3, 0, 0 },
	237	{"daddu", "y,x,4", 0x4010, 0xf810, WR_1\|RD_2, 0, I3, 0, 0 },
	238	{"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
26545944 RS	239	{"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
26545944 RS	240	{"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
fc76e730 RS	241	{"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
	242	{"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
	243	{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, 0, I3, 0, 0 },
4ebce1a0	244	{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 },
fc76e730	245	{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, 0, I3, 0, 0 },
4ebce1a0	246	{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 },
fc76e730	247	{"div", "0,x,y", 0xe81a, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, 0, I1, 0, 0 },
a8d92fc6	248	{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730	249	{"divu", "0,x,y", 0xe81b, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, 0, I1, 0, 0 },
a8d92fc6 RS	250	{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
a8d92fc6 RS	251	{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
fc76e730 RS	252	{"dmult", "x,y", 0xe81c, 0xf81f, RD_1\|RD_2\|WR_HI\|WR_LO, 0, I3, 0, 0 },
	253	{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1\|RD_2\|WR_HI\|WR_LO, 0, I3, 0, 0 },
	254	{"drem", "0,x,y", 0xe81e, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, 0, I3, 0, 0 },
4ebce1a0	255	{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 },
fc76e730	256	{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, 0, I3, 0, 0 },
4ebce1a0	257	{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 },
fc76e730 RS	258	{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1\|RD_2, 0, I3, 0, 0 },
	259	{"dsll", "x,w,[", 0x3001, 0xf803, WR_1\|RD_2, 0, I3, 0, 0 },
	260	{"dsll", "y,x", 0xe814, 0xf81f, MOD_1\|RD_2, 0, I3, 0, 0 },
	261	{"dsrav", "y,x", 0xe817, 0xf81f, MOD_1\|RD_2, 0, I3, 0, 0 },
	262	{"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 },
	263	{"dsra", "y,x", 0xe817, 0xf81f, MOD_1\|RD_2, 0, I3, 0, 0 },
	264	{"dsrlv", "y,x", 0xe816, 0xf81f, MOD_1\|RD_2, 0, I3, 0, 0 },
	265	{"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 },
	266	{"dsrl", "y,x", 0xe816, 0xf81f, MOD_1\|RD_2, 0, I3, 0, 0 },
	267	{"dsubu", "z,v,y", 0xe002, 0xf803, WR_1\|RD_2\|RD_3, 0, I3, 0, 0 },
4ebce1a0 MR	268	{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 },
4ebce1a0 MR	269	{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I3, 0, 0 },
a8d92fc6 RS	270	{"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1, 0, 0 },
	271	{"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1, 0, 0 },
	272	{"exit", "", 0xef09, 0xffff, TRAP, 0, I1, 0, 0 },
	273	{"exit", "L", 0xef09, 0xff1f, TRAP, 0, I1, 0, 0 },
	274	{"entry", "", 0xe809, 0xffff, TRAP, 0, I1, 0, 0 },
	275	{"entry", "l", 0xe809, 0xf81f, TRAP, 0, I1, 0, 0 },
	276	{"extend", "e", 0xf000, 0xf800, 0, 0, I1, 0, 0 },
fc76e730 RS	277	{"jalr", "x", 0xe840, 0xf8ff, RD_1\|WR_31\|UBD, 0, I1, 0, 0 },
	278	{"jalr", "R,x", 0xe840, 0xf8ff, RD_2\|WR_31\|UBD, 0, I1, 0, 0 },
	279	{"jal", "x", 0xe840, 0xf8ff, RD_1\|WR_31\|UBD, 0, I1, 0, 0 },
	280	{"jal", "R,x", 0xe840, 0xf8ff, RD_2\|WR_31\|UBD, 0, I1, 0, 0 },
	281	{"jal", "a", 0x1800, 0xfc00, WR_31\|UBD, 0, I1, 0, 0 },
	282	{"jalx", "i", 0x1c00, 0xfc00, WR_31\|UBD, 0, I1, 0, 0 },
	283	{"jr", "x", 0xe800, 0xf8ff, RD_1\|UBD, 0, I1, 0, 0 },
26545944	284	{"jr", "R", 0xe820, 0xffff, UBD, RD_31, I1, 0, 0 },
fc76e730	285	{"j", "x", 0xe800, 0xf8ff, RD_1\|UBD, 0, I1, 0, 0 },
26545944	286	{"j", "R", 0xe820, 0xffff, UBD, RD_31, I1, 0, 0 },
63e014fc MR	287	/* MIPS16e compact jumps. We keep them near the ordinary jumps
	288	so that we easily find them when converting a normal jump
	289	to a compact one. */
fc76e730 RS	290	{"jalrc", "x", 0xe8c0, 0xf8ff, RD_1\|WR_31\|NODS, UBR, I32, 0, 0 },
	291	{"jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2\|WR_31\|NODS, UBR, I32, 0, 0 },
	292	{"jrc", "x", 0xe880, 0xf8ff, RD_1\|NODS, UBR, I32, 0, 0 },
	293	{"jrc", "R", 0xe8a0, 0xffff, NODS, RD_31\|UBR, I32, 0, 0 },
	294	{"lb", "y,5(x)", 0x8000, 0xf800, WR_1\|RD_3, 0, I1, 0, 0 },
	295	{"lbu", "y,5(x)", 0xa000, 0xf800, WR_1\|RD_3, 0, I1, 0, 0 },
	296	{"ld", "y,D(x)", 0x3800, 0xf800, WR_1\|RD_3, 0, I3, 0, 0 },
	297	{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
	298	{"ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
	299	{"ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 },
	300	{"lh", "y,H(x)", 0x8800, 0xf800, WR_1\|RD_3, 0, I1, 0, 0 },
	301	{"lhu", "y,H(x)", 0xa800, 0xf800, WR_1\|RD_3, 0, I1, 0, 0 },
	302	{"li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 },
	303	{"lw", "y,W(x)", 0x9800, 0xf800, WR_1\|RD_3, 0, I1, 0, 0 },
	304	{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
	305	{"lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
	306	{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
	307	{"lwu", "y,W(x)", 0xb800, 0xf800, WR_1\|RD_3, 0, I3, 0, 0 },
	308	{"mfhi", "x", 0xe810, 0xf8ff, WR_1\|RD_HI, 0, I1, 0, 0 },
	309	{"mflo", "x", 0xe812, 0xf8ff, WR_1\|RD_LO, 0, I1, 0, 0 },
	310	{"move", "y,X", 0x6700, 0xff00, WR_1\|RD_2, 0, I1, 0, 0 },
	311	{"move", "Y,Z", 0x6500, 0xff00, WR_1\|RD_2, 0, I1, 0, 0 },
a8d92fc6	312	{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 RS	313	{"mult", "x,y", 0xe818, 0xf81f, RD_1\|RD_2\|WR_HI\|WR_LO, 0, I1, 0, 0 },
	314	{"multu", "x,y", 0xe819, 0xf81f, RD_1\|RD_2\|WR_HI\|WR_LO, 0, I1, 0, 0 },
	315	{"neg", "x,w", 0xe80b, 0xf81f, WR_1\|RD_2, 0, I1, 0, 0 },
	316	{"not", "x,w", 0xe80f, 0xf81f, WR_1\|RD_2, 0, I1, 0, 0 },
	317	{"or", "x,y", 0xe80d, 0xf81f, MOD_1\|RD_2, 0, I1, 0, 0 },
	318	{"rem", "0,x,y", 0xe81a, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, 0, I1, 0, 0 },
a8d92fc6	319	{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730	320	{"remu", "0,x,y", 0xe81b, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, 0, I1, 0, 0 },
a8d92fc6	321	{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 RS	322	{"sb", "y,5(x)", 0xc000, 0xf800, RD_1\|RD_3, 0, I1, 0, 0 },
fc76e730 RS	323	{"sd", "y,D(x)", 0x7800, 0xf800, RD_1\|RD_3, 0, I3, 0, 0 },
353abf7c	324	{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 },
c97dda72	325	{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31\|RD_SP, I3, 0, 0 },
fc76e730 RS	326	{"sh", "y,H(x)", 0xc800, 0xf800, RD_1\|RD_3, 0, I1, 0, 0 },
	327	{"sllv", "y,x", 0xe804, 0xf81f, MOD_1\|RD_2, 0, I1, 0, 0 },
	328	{"sll", "x,w,<", 0x3000, 0xf803, WR_1\|RD_2, 0, I1, 0, 0 },
	329	{"sll", "y,x", 0xe804, 0xf81f, MOD_1\|RD_2, 0, I1, 0, 0 },
	330	{"slti", "x,8", 0x5000, 0xf800, RD_1\|WR_T, 0, I1, 0, 0 },
	331	{"slt", "x,y", 0xe802, 0xf81f, RD_1\|RD_2\|WR_T, 0, I1, 0, 0 },
	332	{"slt", "x,8", 0x5000, 0xf800, RD_1\|WR_T, 0, I1, 0, 0 },
	333	{"sltiu", "x,8", 0x5800, 0xf800, RD_1\|WR_T, 0, I1, 0, 0 },
	334	{"sltu", "x,y", 0xe803, 0xf81f, RD_1\|RD_2\|WR_T, 0, I1, 0, 0 },
	335	{"sltu", "x,8", 0x5800, 0xf800, RD_1\|WR_T, 0, I1, 0, 0 },
	336	{"srav", "y,x", 0xe807, 0xf81f, MOD_1\|RD_2, 0, I1, 0, 0 },
	337	{"sra", "x,w,<", 0x3003, 0xf803, WR_1\|RD_2, 0, I1, 0, 0 },
	338	{"sra", "y,x", 0xe807, 0xf81f, MOD_1\|RD_2, 0, I1, 0, 0 },
	339	{"srlv", "y,x", 0xe806, 0xf81f, MOD_1\|RD_2, 0, I1, 0, 0 },
	340	{"srl", "x,w,<", 0x3002, 0xf803, WR_1\|RD_2, 0, I1, 0, 0 },
	341	{"srl", "y,x", 0xe806, 0xf81f, MOD_1\|RD_2, 0, I1, 0, 0 },
	342	{"subu", "z,v,y", 0xe003, 0xf803, WR_1\|RD_2\|RD_3, 0, I1, 0, 0 },
a8d92fc6 RS	343	{"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 },
a8d92fc6 RS	344	{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 RS	345	{"sw", "y,W(x)", 0xd800, 0xf800, RD_1\|RD_3, 0, I1, 0, 0 },
	346	{"sw", "x,V(S)", 0xd000, 0xf800, RD_1, RD_SP, I1, 0, 0 },
	347	{"sw", "R,V(S)", 0x6200, 0xff00, 0, RD_31\|RD_SP, I1, 0, 0 },
	348	{"xor", "x,y", 0xe80e, 0xf81f, MOD_1\|RD_2, 0, I1, 0, 0 },
63e014fc	349	/* MIPS16e additions; see above for compact jumps. */
26545944	350	{"restore", "M", 0x6400, 0xff80, WR_31\|NODS, MOD_SP, I32, 0, 0 },
fc76e730	351	{"save", "m", 0x6480, 0xff80, NODS, RD_31\|MOD_SP, I32, 0, 0 },
a8d92fc6	352	{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32, 0, 0 },
fc76e730 RS	353	{"seb", "x", 0xe891, 0xf8ff, MOD_1, 0, I32, 0, 0 },
	354	{"seh", "x", 0xe8b1, 0xf8ff, MOD_1, 0, I32, 0, 0 },
	355	{"sew", "x", 0xe8d1, 0xf8ff, MOD_1, 0, I64, 0, 0 },
	356	{"zeb", "x", 0xe811, 0xf8ff, MOD_1, 0, I32, 0, 0 },
	357	{"zeh", "x", 0xe831, 0xf8ff, MOD_1, 0, I32, 0, 0 },
	358	{"zew", "x", 0xe851, 0xf8ff, MOD_1, 0, I64, 0, 0 },
252b5132 RH	359	};
	360
	361	const int bfd_mips16_num_opcodes =
	362	((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));