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MIPS16: Simplify extended operand handling
[thirdparty/binutils-gdb.git] / opcodes / mips16-opc.c
CommitLineData
252b5132 1/* mips16-opc.c. Mips16 opcode table.
6f2750fe 2 Copyright (C) 1996-2016 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Ian Lance Taylor, Cygnus Support
4
9b201bb5 5 This file is part of the GNU opcodes library.
252b5132 6
9b201bb5
NC		 7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
252b5132 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
252b5132 16
9b201bb5
NC		 17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
0d8dfecf 22#include "sysdep.h"
df7b86aa 23#include <stdio.h>
252b5132 24#include "opcode/mips.h"
c3c07478
RS		 25#include "mips-formats.h"
26
27static unsigned char reg_0_map[] = { 0 };
28static unsigned char reg_29_map[] = { 29 };
29static unsigned char reg_31_map[] = { 31 };
30static unsigned char reg_m16_map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
31static unsigned char reg32r_map[] = {
32 0, 8, 16, 24,
33 1, 9, 17, 25,
34 2, 10, 18, 26,
35 3, 11, 19, 27,
36 4, 12, 20, 28,
37 5, 13, 21, 29,
38 6, 14, 22, 30,
39 7, 15, 23, 31
40};
41
42/* Return the meaning of operand character TYPE, or null if it isn't
43 recognized. If the operand is affected by the EXTEND instruction,
44 EXTENDED_P selects between the extended and unextended forms.
45 The extended forms all have an lsb of 0. */
46
47const struct mips_operand *
48decode_mips16_operand (char type, bfd_boolean extended_p)
49{
50 switch (type)
51 {
d8722d76
MR		 52 case '.': MAPPED_REG (0, 0, GP, reg_0_map);
53
b2805ed5 54 case '6': UINT (6, 5);
c3c07478
RS		 55
56 case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
57 case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST);
58 case 'P': SPECIAL (0, 0, PC);
59 case 'R': MAPPED_REG (0, 0, GP, reg_31_map);
60 case 'S': MAPPED_REG (0, 0, GP, reg_29_map);
61 case 'X': REG (5, 0, GP);
62 case 'Y': MAPPED_REG (5, 3, GP, reg32r_map);
63 case 'Z': MAPPED_REG (3, 0, GP, reg_m16_map);
64
65 case 'a': JUMP (26, 0, 2);
f17ecb4b 66 case 'e': HINT (11, 0);
c3c07478
RS		 67 case 'i': JALX (26, 0, 2);
68 case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST);
69 case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST);
0f35dbc4
RS		 70 case 'v': OPTIONAL_MAPPED_REG (3, 8, GP, reg_m16_map);
71 case 'w': OPTIONAL_MAPPED_REG (3, 5, GP, reg_m16_map);
c3c07478
RS		 72 case 'x': MAPPED_REG (3, 8, GP, reg_m16_map);
73 case 'y': MAPPED_REG (3, 5, GP, reg_m16_map);
74 case 'z': MAPPED_REG (3, 2, GP, reg_m16_map);
75 }
76
77 if (extended_p)
78 switch (type)
79 {
bdd15286 80 case '<': UINT (5, 22);
c3c07478
RS		 81 case '[': UINT (6, 0);
82 case ']': UINT (6, 0);
83
c3c07478 84 case '5': SINT (16, 0);
c3c07478
RS		 85 case '8': SINT (16, 0);
86
3ccad066
RS		 87 case 'A': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
88 case 'B': PCREL (16, 0, TRUE, 0, 3, FALSE, FALSE);
c3c07478
RS		 89 case 'C': SINT (16, 0);
90 case 'D': SINT (16, 0);
3ccad066 91 case 'E': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
d8722d76 92 case 'F': SINT (15, 0);
c3c07478
RS		 93 case 'H': SINT (16, 0);
94 case 'K': SINT (16, 0);
95 case 'U': UINT (16, 0);
96 case 'V': SINT (16, 0);
97 case 'W': SINT (16, 0);
98
99 case 'j': SINT (16, 0);
100 case 'k': SINT (16, 0);
101 case 'p': BRANCH (16, 0, 1);
102 case 'q': BRANCH (16, 0, 1);
103 }
104 else
105 switch (type)
106 {
107 case '<': INT_ADJ (3, 2, 8, 0, FALSE);
c3c07478
RS		 108 case '[': INT_ADJ (3, 2, 8, 0, FALSE);
109 case ']': INT_ADJ (3, 8, 8, 0, FALSE);
110
c3c07478 111 case '5': UINT (5, 0);
c3c07478
RS		 112 case '8': UINT (8, 0);
113
3ccad066
RS		 114 case 'A': PCREL (8, 0, FALSE, 2, 2, FALSE, FALSE);
115 case 'B': PCREL (5, 0, FALSE, 3, 3, FALSE, FALSE);
c3c07478
RS		 116 case 'C': INT_ADJ (8, 0, 255, 3, FALSE); /* (0 .. 255) << 3 */
117 case 'D': INT_ADJ (5, 0, 31, 3, FALSE); /* (0 .. 31) << 3 */
3ccad066 118 case 'E': PCREL (5, 0, FALSE, 2, 2, FALSE, FALSE);
d8722d76 119 case 'F': SINT (4, 0);
c3c07478
RS		 120 case 'H': INT_ADJ (5, 0, 31, 1, FALSE); /* (0 .. 31) << 1 */
121 case 'K': INT_ADJ (8, 0, 127, 3, FALSE); /* (-128 .. 127) << 3 */
122 case 'U': UINT (8, 0);
123 case 'V': INT_ADJ (8, 0, 255, 2, FALSE); /* (0 .. 255) << 2 */
124 case 'W': INT_ADJ (5, 0, 31, 2, FALSE); /* (0 .. 31) << 2 */
125
126 case 'j': SINT (5, 0);
127 case 'k': SINT (8, 0);
128 case 'p': BRANCH (8, 0, 1);
129 case 'q': BRANCH (11, 0, 1);
130 }
131 return 0;
132}
252b5132
RH		 133
134/* This is the opcodes table for the mips16 processor. The format of
135 this table is intentionally identical to the one in mips-opc.c.
136 However, the special letters that appear in the argument string are
137 different, and the table uses some different flags. */
138
139/* Use some short hand macros to keep down the length of the lines in
140 the opcodes table. */
141
142#define UBD INSN_UNCOND_BRANCH_DELAY
252b5132 143
fc76e730
RS		 144#define WR_1 INSN_WRITE_1
145#define WR_2 INSN_WRITE_2
146#define RD_1 INSN_READ_1
147#define RD_2 INSN_READ_2
148#define RD_3 INSN_READ_3
149#define RD_4 INSN_READ_4
150#define MOD_1 (WR_1|RD_1)
151#define MOD_2 (WR_2|RD_2)
252b5132 152
fc76e730
RS		 153#define RD_T INSN_READ_GPR_24
154#define WR_T INSN_WRITE_GPR_24
155#define WR_31 INSN_WRITE_GPR_31
252b5132
RH		 156
157#define WR_HI INSN_WRITE_HI
158#define WR_LO INSN_WRITE_LO
159#define RD_HI INSN_READ_HI
160#define RD_LO INSN_READ_LO
161
bcd530a7
RS		 162#define NODS INSN_NO_DELAY_SLOT
163#define TRAP INSN_NO_DELAY_SLOT
252b5132 164
fc76e730
RS		 165#define RD_16 INSN2_READ_GPR_16
166#define RD_SP INSN2_READ_SP
167#define WR_SP INSN2_WRITE_SP
168#define MOD_SP (RD_SP|WR_SP)
26545944
RS		 169#define RD_31 INSN2_READ_GPR_31
170#define RD_PC INSN2_READ_PC
171#define UBR INSN2_UNCOND_BRANCH
172#define CBR INSN2_COND_BRANCH
173
0674ee5d
MR		 174#define SH INSN2_SHORT_ONLY
175
9b3f89ee 176#define I1 INSN_ISA1
252b5132 177#define I3 INSN_ISA3
9b3f89ee
TS		 178#define I32 INSN_ISA32
179#define I64 INSN_ISA64
180#define T3 INSN_3900
252b5132 181
b23da31b
NC		 182const struct mips_opcode mips16_opcodes[] =
183{
343fa690 184/* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */
0674ee5d 185{"nop", "", 0x6500, 0xffff, 0, SH|RD_16, I1, 0, 0 }, /* move $0,$Z */
fc76e730 186{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
a8d92fc6 187{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
d8722d76 188{"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
fc76e730 189{"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
26545944
RS		 190{"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
191{"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
fc76e730
RS		 192{"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
193{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
0674ee5d 194{"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
d8722d76 195{"addu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
fc76e730 196{"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
26545944
RS		 197{"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
198{"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
fc76e730
RS		 199{"addu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
200{"addu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
0674ee5d 201{"and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
26545944 202{"b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 },
a8d92fc6
RS		 203{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 },
204{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 205{"beqz", "x,p", 0x2000, 0xf800, RD_1, CBR, I1, 0, 0 },
a8d92fc6
RS		 206{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
207{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
208{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
209{"bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 },
210{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 },
211{"bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 },
212{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 },
213{"bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 },
214{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 },
215{"ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 },
216{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 },
217{"bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 },
218{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 },
219{"blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 },
220{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 },
221{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
222{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 },
223{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
fc76e730 224{"bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 },
0674ee5d 225{"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 },
26545944
RS		 226{"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 },
227{"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 },
fc76e730 228{"cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 229{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
fc76e730
RS		 230{"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
231{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
d8722d76 232{"daddiu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
fc76e730 233{"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
26545944
RS		 234{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
235{"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
fc76e730
RS		 236{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
237{"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
0674ee5d 238{"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
d8722d76 239{"daddu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
fc76e730 240{"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
26545944
RS		 241{"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
242{"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
fc76e730
RS		 243{"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
244{"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
d8722d76 245{"ddiv", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 246{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 },
d8722d76 247{"ddivu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 248{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 },
d8722d76 249{"div", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6 250{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
d8722d76 251{"divu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6
RS		 252{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
253{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
0674ee5d
MR		 254{"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
255{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
d8722d76 256{"drem", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 257{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 },
d8722d76 258{"dremu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
4ebce1a0 259{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 },
0674ee5d 260{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
fc76e730 261{"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 },
0674ee5d
MR		 262{"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
263{"dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
fc76e730 264{"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 },
0674ee5d
MR		 265{"dsra", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
266{"dsrlv", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
fc76e730 267{"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 },
0674ee5d
MR		 268{"dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
269{"dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
4ebce1a0
MR		 270{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 },
271{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I3, 0, 0 },
0674ee5d
MR		 272{"exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 },
273{"exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 },
274{"exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 },
275{"exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 },
276{"entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 },
277{"entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 },
278{"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
279{"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
280{"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
281{"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
7fd53920
MR		 282{"jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
283{"jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
0674ee5d
MR		 284{"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
285{"jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
286{"j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
287{"j", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
63e014fc
MR		 288/* MIPS16e compact jumps. We keep them near the ordinary jumps
289 so that we easily find them when converting a normal jump
290 to a compact one. */
0674ee5d
MR		 291{"jalrc", "x", 0xe8c0, 0xf8ff, RD_1|WR_31|NODS, SH|UBR, I32, 0, 0 },
292{"jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2|WR_31|NODS, SH|UBR, I32, 0, 0 },
293{"jrc", "x", 0xe880, 0xf8ff, RD_1|NODS, SH|UBR, I32, 0, 0 },
294{"jrc", "R", 0xe8a0, 0xffff, NODS, SH|RD_31|UBR, I32, 0, 0 },
fc76e730
RS		 295{"lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
296{"lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
297{"ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
298{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
299{"ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
300{"ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 },
301{"lh", "y,H(x)", 0x8800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
302{"lhu", "y,H(x)", 0xa800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
303{"li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 },
304{"lw", "y,W(x)", 0x9800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
305{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
306{"lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
307{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
308{"lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
0674ee5d
MR		 309{"mfhi", "x", 0xe810, 0xf8ff, WR_1|RD_HI, SH, I1, 0, 0 },
310{"mflo", "x", 0xe812, 0xf8ff, WR_1|RD_LO, SH, I1, 0, 0 },
311{"move", "y,X", 0x6700, 0xff00, WR_1|RD_2, SH, I1, 0, 0 },
312{"move", "Y,Z", 0x6500, 0xff00, WR_1|RD_2, SH, I1, 0, 0 },
a8d92fc6 313{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 },
0674ee5d
MR		 314{"mult", "x,y", 0xe818, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 },
315{"multu", "x,y", 0xe819, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 },
316{"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
317{"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
318{"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
d8722d76 319{"rem", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6 320{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
d8722d76 321{"remu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
a8d92fc6 322{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
fc76e730
RS		 323{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
324{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
353abf7c 325{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 },
c97dda72 326{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I3, 0, 0 },
fc76e730 327{"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
0674ee5d 328{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
fc76e730 329{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
0674ee5d 330{"sll", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
fc76e730 331{"slti", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 332{"slt", "x,y", 0xe802, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
fc76e730
RS		 333{"slt", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
334{"sltiu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 335{"sltu", "x,y", 0xe803, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
fc76e730 336{"sltu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
0674ee5d 337{"srav", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
fc76e730 338{"sra", "x,w,<", 0x3003, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
0674ee5d
MR		 339{"sra", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
340{"srlv", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
fc76e730 341{"srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
0674ee5d
MR		 342{"srl", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
343{"subu", "z,v,y", 0xe003, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
a8d92fc6
RS		 344{"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 },
345{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
fc76e730
RS		 346{"sw", "y,W(x)", 0xd800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
347{"sw", "x,V(S)", 0xd000, 0xf800, RD_1, RD_SP, I1, 0, 0 },
348{"sw", "R,V(S)", 0x6200, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 },
0674ee5d 349{"xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
63e014fc 350 /* MIPS16e additions; see above for compact jumps. */
26545944 351{"restore", "M", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 },
fc76e730 352{"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 },
0674ee5d
MR		 353{"sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 },
354{"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 },
355{"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 },
356{"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 },
357{"zeb", "x", 0xe811, 0xf8ff, MOD_1, SH, I32, 0, 0 },
358{"zeh", "x", 0xe831, 0xf8ff, MOD_1, SH, I32, 0, 0 },
359{"zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 },
7fd53920
MR		 360 /* Place EXTEND last so that it catches any prefix that didn't match
361 anything. */
0674ee5d 362{"extend", "e", 0xf000, 0xf800, NODS, SH, I1, 0, 0 },
252b5132
RH		 363};
364
365const int bfd_mips16_num_opcodes =
366 ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));
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