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87e6d782 NC |
1 | /* Instruction building/extraction support for openrisc. -*- C -*- |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. | |
4 | - the resultant file is machine generated, cgen-ibld.in isn't | |
5 | ||
6 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. | |
7 | ||
8 | This file is part of the GNU Binutils and GDB, the GNU debugger. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software Foundation, Inc., | |
22 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
23 | ||
24 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. | |
25 | Keep that in mind. */ | |
26 | ||
27 | #include "sysdep.h" | |
87e6d782 NC |
28 | #include <stdio.h> |
29 | #include "ansidecl.h" | |
30 | #include "dis-asm.h" | |
31 | #include "bfd.h" | |
32 | #include "symcat.h" | |
33 | #include "openrisc-desc.h" | |
34 | #include "openrisc-opc.h" | |
35 | #include "opintl.h" | |
36 | ||
37 | #undef min | |
38 | #define min(a,b) ((a) < (b) ? (a) : (b)) | |
39 | #undef max | |
40 | #define max(a,b) ((a) > (b) ? (a) : (b)) | |
41 | ||
42 | /* Used by the ifield rtx function. */ | |
43 | #define FLD(f) (fields->f) | |
44 | ||
45 | static const char * insert_normal | |
46 | PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, | |
47 | unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); | |
48 | static const char * insert_insn_normal | |
49 | PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, | |
50 | CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); | |
51 | ||
52 | static int extract_normal | |
53 | PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, | |
54 | unsigned int, unsigned int, unsigned int, unsigned int, | |
55 | unsigned int, unsigned int, bfd_vma, long *)); | |
56 | static int extract_insn_normal | |
57 | PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, | |
58 | CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); | |
59 | static void put_insn_int_value | |
60 | PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); | |
fc05c67f NC |
61 | const char * openrisc_cgen_insert_operand |
62 | PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); | |
63 | int openrisc_cgen_extract_operand | |
64 | PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); | |
65 | int openrisc_cgen_get_int_operand | |
66 | PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); | |
67 | bfd_vma openrisc_cgen_get_vma_operand | |
68 | PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); | |
69 | void openrisc_cgen_set_int_operand | |
70 | PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); | |
71 | void openrisc_cgen_set_vma_operand | |
72 | PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); | |
87e6d782 NC |
73 | \f |
74 | /* Operand insertion. */ | |
75 | ||
76 | #if ! CGEN_INT_INSN_P | |
77 | ||
78 | /* Subroutine of insert_normal. */ | |
79 | ||
80 | static CGEN_INLINE void | |
81 | insert_1 (cd, value, start, length, word_length, bufp) | |
82 | CGEN_CPU_DESC cd; | |
83 | unsigned long value; | |
84 | int start,length,word_length; | |
85 | unsigned char *bufp; | |
86 | { | |
87 | unsigned long x,mask; | |
88 | int shift; | |
89 | int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; | |
90 | ||
91 | x = bfd_get_bits (bufp, word_length, big_p); | |
92 | ||
93 | /* Written this way to avoid undefined behaviour. */ | |
94 | mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
95 | if (CGEN_INSN_LSB0_P) | |
96 | shift = (start + 1) - length; | |
97 | else | |
98 | shift = (word_length - (start + length)); | |
99 | x = (x & ~(mask << shift)) | ((value & mask) << shift); | |
100 | ||
101 | bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p); | |
102 | } | |
103 | ||
104 | #endif /* ! CGEN_INT_INSN_P */ | |
105 | ||
106 | /* Default insertion routine. | |
107 | ||
108 | ATTRS is a mask of the boolean attributes. | |
109 | WORD_OFFSET is the offset in bits from the start of the insn of the value. | |
110 | WORD_LENGTH is the length of the word in bits in which the value resides. | |
111 | START is the starting bit number in the word, architecture origin. | |
112 | LENGTH is the length of VALUE in bits. | |
113 | TOTAL_LENGTH is the total length of the insn in bits. | |
114 | ||
115 | The result is an error message or NULL if success. */ | |
116 | ||
117 | /* ??? This duplicates functionality with bfd's howto table and | |
118 | bfd_install_relocation. */ | |
119 | /* ??? This doesn't handle bfd_vma's. Create another function when | |
120 | necessary. */ | |
121 | ||
122 | static const char * | |
123 | insert_normal (cd, value, attrs, word_offset, start, length, word_length, | |
124 | total_length, buffer) | |
125 | CGEN_CPU_DESC cd; | |
126 | long value; | |
127 | unsigned int attrs; | |
128 | unsigned int word_offset, start, length, word_length, total_length; | |
129 | CGEN_INSN_BYTES_PTR buffer; | |
130 | { | |
131 | static char errbuf[100]; | |
132 | /* Written this way to avoid undefined behaviour. */ | |
133 | unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
134 | ||
135 | /* If LENGTH is zero, this operand doesn't contribute to the value. */ | |
136 | if (length == 0) | |
137 | return NULL; | |
138 | ||
139 | #if 0 | |
140 | if (CGEN_INT_INSN_P | |
141 | && word_offset != 0) | |
142 | abort (); | |
143 | #endif | |
144 | ||
145 | if (word_length > 32) | |
146 | abort (); | |
147 | ||
148 | /* For architectures with insns smaller than the base-insn-bitsize, | |
149 | word_length may be too big. */ | |
150 | if (cd->min_insn_bitsize < cd->base_insn_bitsize) | |
151 | { | |
152 | if (word_offset == 0 | |
153 | && word_length > total_length) | |
154 | word_length = total_length; | |
155 | } | |
156 | ||
157 | /* Ensure VALUE will fit. */ | |
fc7bc883 RH |
158 | if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) |
159 | { | |
160 | long minval = - (1L << (length - 1)); | |
161 | unsigned long maxval = mask; | |
162 | ||
163 | if ((value > 0 && (unsigned long) value > maxval) | |
164 | || value < minval) | |
165 | { | |
166 | /* xgettext:c-format */ | |
167 | sprintf (errbuf, | |
168 | _("operand out of range (%ld not between %ld and %lu)"), | |
169 | value, minval, maxval); | |
170 | return errbuf; | |
171 | } | |
172 | } | |
173 | else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) | |
87e6d782 NC |
174 | { |
175 | unsigned long maxval = mask; | |
176 | ||
177 | if ((unsigned long) value > maxval) | |
178 | { | |
179 | /* xgettext:c-format */ | |
180 | sprintf (errbuf, | |
181 | _("operand out of range (%lu not between 0 and %lu)"), | |
182 | value, maxval); | |
183 | return errbuf; | |
184 | } | |
185 | } | |
186 | else | |
187 | { | |
188 | if (! cgen_signed_overflow_ok_p (cd)) | |
189 | { | |
190 | long minval = - (1L << (length - 1)); | |
191 | long maxval = (1L << (length - 1)) - 1; | |
192 | ||
193 | if (value < minval || value > maxval) | |
194 | { | |
195 | sprintf | |
196 | /* xgettext:c-format */ | |
197 | (errbuf, _("operand out of range (%ld not between %ld and %ld)"), | |
198 | value, minval, maxval); | |
199 | return errbuf; | |
200 | } | |
201 | } | |
202 | } | |
203 | ||
204 | #if CGEN_INT_INSN_P | |
205 | ||
206 | { | |
207 | int shift; | |
208 | ||
209 | if (CGEN_INSN_LSB0_P) | |
210 | shift = (word_offset + start + 1) - length; | |
211 | else | |
212 | shift = total_length - (word_offset + start + length); | |
213 | *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); | |
214 | } | |
215 | ||
216 | #else /* ! CGEN_INT_INSN_P */ | |
217 | ||
218 | { | |
219 | unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; | |
220 | ||
221 | insert_1 (cd, value, start, length, word_length, bufp); | |
222 | } | |
223 | ||
224 | #endif /* ! CGEN_INT_INSN_P */ | |
225 | ||
226 | return NULL; | |
227 | } | |
228 | ||
229 | /* Default insn builder (insert handler). | |
230 | The instruction is recorded in CGEN_INT_INSN_P byte order (meaning | |
231 | that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is | |
232 | recorded in host byte order, otherwise BUFFER is an array of bytes | |
233 | and the value is recorded in target byte order). | |
234 | The result is an error message or NULL if success. */ | |
235 | ||
236 | static const char * | |
237 | insert_insn_normal (cd, insn, fields, buffer, pc) | |
238 | CGEN_CPU_DESC cd; | |
239 | const CGEN_INSN * insn; | |
240 | CGEN_FIELDS * fields; | |
241 | CGEN_INSN_BYTES_PTR buffer; | |
242 | bfd_vma pc; | |
243 | { | |
244 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
245 | unsigned long value; | |
246 | const CGEN_SYNTAX_CHAR_TYPE * syn; | |
247 | ||
248 | CGEN_INIT_INSERT (cd); | |
249 | value = CGEN_INSN_BASE_VALUE (insn); | |
250 | ||
251 | /* If we're recording insns as numbers (rather than a string of bytes), | |
252 | target byte order handling is deferred until later. */ | |
253 | ||
254 | #if CGEN_INT_INSN_P | |
255 | ||
256 | put_insn_int_value (cd, buffer, cd->base_insn_bitsize, | |
257 | CGEN_FIELDS_BITSIZE (fields), value); | |
258 | ||
259 | #else | |
260 | ||
261 | cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize, | |
262 | CGEN_FIELDS_BITSIZE (fields)), | |
263 | value); | |
264 | ||
265 | #endif /* ! CGEN_INT_INSN_P */ | |
266 | ||
267 | /* ??? It would be better to scan the format's fields. | |
268 | Still need to be able to insert a value based on the operand though; | |
269 | e.g. storing a branch displacement that got resolved later. | |
270 | Needs more thought first. */ | |
271 | ||
272 | for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) | |
273 | { | |
274 | const char *errmsg; | |
275 | ||
276 | if (CGEN_SYNTAX_CHAR_P (* syn)) | |
277 | continue; | |
278 | ||
279 | errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), | |
280 | fields, buffer, pc); | |
281 | if (errmsg) | |
282 | return errmsg; | |
283 | } | |
284 | ||
285 | return NULL; | |
286 | } | |
287 | ||
288 | /* Cover function to store an insn value into an integral insn. Must go here | |
289 | because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ | |
290 | ||
291 | static void | |
292 | put_insn_int_value (cd, buf, length, insn_length, value) | |
293 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; | |
294 | CGEN_INSN_BYTES_PTR buf; | |
295 | int length; | |
296 | int insn_length; | |
297 | CGEN_INSN_INT value; | |
298 | { | |
299 | /* For architectures with insns smaller than the base-insn-bitsize, | |
300 | length may be too big. */ | |
301 | if (length > insn_length) | |
302 | *buf = value; | |
303 | else | |
304 | { | |
305 | int shift = insn_length - length; | |
306 | /* Written this way to avoid undefined behaviour. */ | |
307 | CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
308 | *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); | |
309 | } | |
310 | } | |
311 | \f | |
312 | /* Operand extraction. */ | |
313 | ||
314 | #if ! CGEN_INT_INSN_P | |
315 | ||
316 | /* Subroutine of extract_normal. | |
317 | Ensure sufficient bytes are cached in EX_INFO. | |
318 | OFFSET is the offset in bytes from the start of the insn of the value. | |
319 | BYTES is the length of the needed value. | |
320 | Returns 1 for success, 0 for failure. */ | |
321 | ||
322 | static CGEN_INLINE int | |
323 | fill_cache (cd, ex_info, offset, bytes, pc) | |
324 | CGEN_CPU_DESC cd; | |
325 | CGEN_EXTRACT_INFO *ex_info; | |
326 | int offset, bytes; | |
327 | bfd_vma pc; | |
328 | { | |
329 | /* It's doubtful that the middle part has already been fetched so | |
330 | we don't optimize that case. kiss. */ | |
331 | int mask; | |
332 | disassemble_info *info = (disassemble_info *) ex_info->dis_info; | |
333 | ||
334 | /* First do a quick check. */ | |
335 | mask = (1 << bytes) - 1; | |
336 | if (((ex_info->valid >> offset) & mask) == mask) | |
337 | return 1; | |
338 | ||
339 | /* Search for the first byte we need to read. */ | |
340 | for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) | |
341 | if (! (mask & ex_info->valid)) | |
342 | break; | |
343 | ||
344 | if (bytes) | |
345 | { | |
346 | int status; | |
347 | ||
348 | pc += offset; | |
349 | status = (*info->read_memory_func) | |
350 | (pc, ex_info->insn_bytes + offset, bytes, info); | |
351 | ||
352 | if (status != 0) | |
353 | { | |
354 | (*info->memory_error_func) (status, pc, info); | |
355 | return 0; | |
356 | } | |
357 | ||
358 | ex_info->valid |= ((1 << bytes) - 1) << offset; | |
359 | } | |
360 | ||
361 | return 1; | |
362 | } | |
363 | ||
364 | /* Subroutine of extract_normal. */ | |
365 | ||
366 | static CGEN_INLINE long | |
367 | extract_1 (cd, ex_info, start, length, word_length, bufp, pc) | |
368 | CGEN_CPU_DESC cd; | |
369 | CGEN_EXTRACT_INFO *ex_info; | |
370 | int start,length,word_length; | |
371 | unsigned char *bufp; | |
372 | bfd_vma pc; | |
373 | { | |
374 | unsigned long x; | |
375 | int shift; | |
376 | int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; | |
377 | ||
378 | x = bfd_get_bits (bufp, word_length, big_p); | |
379 | ||
380 | if (CGEN_INSN_LSB0_P) | |
381 | shift = (start + 1) - length; | |
382 | else | |
383 | shift = (word_length - (start + length)); | |
384 | return x >> shift; | |
385 | } | |
386 | ||
387 | #endif /* ! CGEN_INT_INSN_P */ | |
388 | ||
389 | /* Default extraction routine. | |
390 | ||
391 | INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, | |
392 | or sometimes less for cases like the m32r where the base insn size is 32 | |
393 | but some insns are 16 bits. | |
394 | ATTRS is a mask of the boolean attributes. We only need `SIGNED', | |
395 | but for generality we take a bitmask of all of them. | |
396 | WORD_OFFSET is the offset in bits from the start of the insn of the value. | |
397 | WORD_LENGTH is the length of the word in bits in which the value resides. | |
398 | START is the starting bit number in the word, architecture origin. | |
399 | LENGTH is the length of VALUE in bits. | |
400 | TOTAL_LENGTH is the total length of the insn in bits. | |
401 | ||
402 | Returns 1 for success, 0 for failure. */ | |
403 | ||
404 | /* ??? The return code isn't properly used. wip. */ | |
405 | ||
406 | /* ??? This doesn't handle bfd_vma's. Create another function when | |
407 | necessary. */ | |
408 | ||
409 | static int | |
410 | extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, | |
411 | word_length, total_length, pc, valuep) | |
412 | CGEN_CPU_DESC cd; | |
413 | #if ! CGEN_INT_INSN_P | |
414 | CGEN_EXTRACT_INFO *ex_info; | |
415 | #else | |
416 | CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; | |
417 | #endif | |
418 | CGEN_INSN_INT insn_value; | |
419 | unsigned int attrs; | |
420 | unsigned int word_offset, start, length, word_length, total_length; | |
421 | #if ! CGEN_INT_INSN_P | |
422 | bfd_vma pc; | |
423 | #else | |
424 | bfd_vma pc ATTRIBUTE_UNUSED; | |
425 | #endif | |
426 | long *valuep; | |
427 | { | |
fc7bc883 | 428 | long value, mask; |
87e6d782 NC |
429 | |
430 | /* If LENGTH is zero, this operand doesn't contribute to the value | |
431 | so give it a standard value of zero. */ | |
432 | if (length == 0) | |
433 | { | |
434 | *valuep = 0; | |
435 | return 1; | |
436 | } | |
437 | ||
438 | #if 0 | |
439 | if (CGEN_INT_INSN_P | |
440 | && word_offset != 0) | |
441 | abort (); | |
442 | #endif | |
443 | ||
444 | if (word_length > 32) | |
445 | abort (); | |
446 | ||
447 | /* For architectures with insns smaller than the insn-base-bitsize, | |
448 | word_length may be too big. */ | |
449 | if (cd->min_insn_bitsize < cd->base_insn_bitsize) | |
450 | { | |
451 | if (word_offset == 0 | |
452 | && word_length > total_length) | |
453 | word_length = total_length; | |
454 | } | |
455 | ||
fc7bc883 | 456 | /* Does the value reside in INSN_VALUE, and at the right alignment? */ |
87e6d782 | 457 | |
fc7bc883 | 458 | if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) |
87e6d782 NC |
459 | { |
460 | if (CGEN_INSN_LSB0_P) | |
461 | value = insn_value >> ((word_offset + start + 1) - length); | |
462 | else | |
463 | value = insn_value >> (total_length - ( word_offset + start + length)); | |
464 | } | |
465 | ||
466 | #if ! CGEN_INT_INSN_P | |
467 | ||
468 | else | |
469 | { | |
470 | unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; | |
471 | ||
472 | if (word_length > 32) | |
473 | abort (); | |
474 | ||
475 | if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) | |
476 | return 0; | |
477 | ||
478 | value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); | |
479 | } | |
480 | ||
481 | #endif /* ! CGEN_INT_INSN_P */ | |
482 | ||
483 | /* Written this way to avoid undefined behaviour. */ | |
484 | mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
485 | ||
486 | value &= mask; | |
487 | /* sign extend? */ | |
488 | if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) | |
489 | && (value & (1L << (length - 1)))) | |
490 | value |= ~mask; | |
491 | ||
492 | *valuep = value; | |
493 | ||
494 | return 1; | |
495 | } | |
496 | ||
497 | /* Default insn extractor. | |
498 | ||
499 | INSN_VALUE is the first base_insn_bitsize bits, translated to host order. | |
500 | The extracted fields are stored in FIELDS. | |
501 | EX_INFO is used to handle reading variable length insns. | |
502 | Return the length of the insn in bits, or 0 if no match, | |
503 | or -1 if an error occurs fetching data (memory_error_func will have | |
504 | been called). */ | |
505 | ||
506 | static int | |
507 | extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) | |
508 | CGEN_CPU_DESC cd; | |
509 | const CGEN_INSN *insn; | |
510 | CGEN_EXTRACT_INFO *ex_info; | |
511 | CGEN_INSN_INT insn_value; | |
512 | CGEN_FIELDS *fields; | |
513 | bfd_vma pc; | |
514 | { | |
515 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
516 | const CGEN_SYNTAX_CHAR_TYPE *syn; | |
517 | ||
518 | CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); | |
519 | ||
520 | CGEN_INIT_EXTRACT (cd); | |
521 | ||
522 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) | |
523 | { | |
524 | int length; | |
525 | ||
526 | if (CGEN_SYNTAX_CHAR_P (*syn)) | |
527 | continue; | |
528 | ||
529 | length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), | |
530 | ex_info, insn_value, fields, pc); | |
531 | if (length <= 0) | |
532 | return length; | |
533 | } | |
534 | ||
535 | /* We recognized and successfully extracted this insn. */ | |
536 | return CGEN_INSN_BITSIZE (insn); | |
537 | } | |
538 | \f | |
539 | /* machine generated code added here */ | |
540 | ||
541 | /* Main entry point for operand insertion. | |
542 | ||
543 | This function is basically just a big switch statement. Earlier versions | |
544 | used tables to look up the function to use, but | |
545 | - if the table contains both assembler and disassembler functions then | |
546 | the disassembler contains much of the assembler and vice-versa, | |
547 | - there's a lot of inlining possibilities as things grow, | |
548 | - using a switch statement avoids the function call overhead. | |
549 | ||
550 | This function could be moved into `parse_insn_normal', but keeping it | |
551 | separate makes clear the interface between `parse_insn_normal' and each of | |
552 | the handlers. It's also needed by GAS to insert operands that couldn't be | |
553 | resolved during parsing. | |
554 | */ | |
555 | ||
556 | const char * | |
557 | openrisc_cgen_insert_operand (cd, opindex, fields, buffer, pc) | |
558 | CGEN_CPU_DESC cd; | |
559 | int opindex; | |
560 | CGEN_FIELDS * fields; | |
561 | CGEN_INSN_BYTES_PTR buffer; | |
562 | bfd_vma pc; | |
563 | { | |
564 | const char * errmsg = NULL; | |
565 | unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); | |
566 | ||
567 | switch (opindex) | |
568 | { | |
569 | case OPENRISC_OPERAND_ABS_26 : | |
570 | { | |
571 | long value = fields->f_abs26; | |
572 | value = ((unsigned int) (pc) >> (2)); | |
573 | errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 25, 26, 32, total_length, buffer); | |
574 | } | |
575 | break; | |
576 | case OPENRISC_OPERAND_DISP_26 : | |
577 | { | |
578 | long value = fields->f_disp26; | |
579 | value = ((int) (((value) - (pc))) >> (2)); | |
580 | errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer); | |
581 | } | |
582 | break; | |
583 | case OPENRISC_OPERAND_HI16 : | |
584 | errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); | |
585 | break; | |
586 | case OPENRISC_OPERAND_LO16 : | |
587 | errmsg = insert_normal (cd, fields->f_lo16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); | |
588 | break; | |
589 | case OPENRISC_OPERAND_OP_F_23 : | |
590 | errmsg = insert_normal (cd, fields->f_op4, 0, 0, 23, 3, 32, total_length, buffer); | |
591 | break; | |
592 | case OPENRISC_OPERAND_OP_F_3 : | |
593 | errmsg = insert_normal (cd, fields->f_op5, 0, 0, 25, 5, 32, total_length, buffer); | |
594 | break; | |
595 | case OPENRISC_OPERAND_RA : | |
596 | errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); | |
597 | break; | |
598 | case OPENRISC_OPERAND_RB : | |
599 | errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); | |
600 | break; | |
601 | case OPENRISC_OPERAND_RD : | |
602 | errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); | |
603 | break; | |
604 | case OPENRISC_OPERAND_SIMM_16 : | |
605 | errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); | |
606 | break; | |
607 | case OPENRISC_OPERAND_UI16NC : | |
608 | { | |
609 | { | |
610 | FLD (f_i16_2) = ((((unsigned int) (FLD (f_i16nc)) >> (11))) & (31)); | |
611 | FLD (f_i16_1) = ((FLD (f_i16nc)) & (2047)); | |
612 | } | |
613 | errmsg = insert_normal (cd, fields->f_i16_1, 0, 0, 10, 11, 32, total_length, buffer); | |
614 | if (errmsg) | |
615 | break; | |
616 | errmsg = insert_normal (cd, fields->f_i16_2, 0, 0, 25, 5, 32, total_length, buffer); | |
617 | if (errmsg) | |
618 | break; | |
619 | } | |
620 | break; | |
621 | case OPENRISC_OPERAND_UIMM_16 : | |
622 | errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer); | |
623 | break; | |
624 | case OPENRISC_OPERAND_UIMM_5 : | |
625 | errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 4, 5, 32, total_length, buffer); | |
626 | break; | |
627 | ||
628 | default : | |
629 | /* xgettext:c-format */ | |
630 | fprintf (stderr, _("Unrecognized field %d while building insn.\n"), | |
631 | opindex); | |
632 | abort (); | |
633 | } | |
634 | ||
635 | return errmsg; | |
636 | } | |
637 | ||
638 | /* Main entry point for operand extraction. | |
639 | The result is <= 0 for error, >0 for success. | |
640 | ??? Actual values aren't well defined right now. | |
641 | ||
642 | This function is basically just a big switch statement. Earlier versions | |
643 | used tables to look up the function to use, but | |
644 | - if the table contains both assembler and disassembler functions then | |
645 | the disassembler contains much of the assembler and vice-versa, | |
646 | - there's a lot of inlining possibilities as things grow, | |
647 | - using a switch statement avoids the function call overhead. | |
648 | ||
649 | This function could be moved into `print_insn_normal', but keeping it | |
650 | separate makes clear the interface between `print_insn_normal' and each of | |
651 | the handlers. | |
652 | */ | |
653 | ||
654 | int | |
655 | openrisc_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) | |
656 | CGEN_CPU_DESC cd; | |
657 | int opindex; | |
658 | CGEN_EXTRACT_INFO *ex_info; | |
659 | CGEN_INSN_INT insn_value; | |
660 | CGEN_FIELDS * fields; | |
661 | bfd_vma pc; | |
662 | { | |
663 | /* Assume success (for those operands that are nops). */ | |
664 | int length = 1; | |
665 | unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); | |
666 | ||
667 | switch (opindex) | |
668 | { | |
669 | case OPENRISC_OPERAND_ABS_26 : | |
670 | { | |
671 | long value; | |
672 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 25, 26, 32, total_length, pc, & value); | |
673 | value = ((value) << (2)); | |
674 | fields->f_abs26 = value; | |
675 | } | |
676 | break; | |
677 | case OPENRISC_OPERAND_DISP_26 : | |
678 | { | |
679 | long value; | |
680 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value); | |
681 | value = ((((value) << (2))) + (pc)); | |
682 | fields->f_disp26 = value; | |
683 | } | |
684 | break; | |
685 | case OPENRISC_OPERAND_HI16 : | |
686 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_simm16); | |
687 | break; | |
688 | case OPENRISC_OPERAND_LO16 : | |
689 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_lo16); | |
690 | break; | |
691 | case OPENRISC_OPERAND_OP_F_23 : | |
692 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 3, 32, total_length, pc, & fields->f_op4); | |
693 | break; | |
694 | case OPENRISC_OPERAND_OP_F_3 : | |
695 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_op5); | |
696 | break; | |
697 | case OPENRISC_OPERAND_RA : | |
698 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); | |
699 | break; | |
700 | case OPENRISC_OPERAND_RB : | |
701 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); | |
702 | break; | |
703 | case OPENRISC_OPERAND_RD : | |
704 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); | |
705 | break; | |
706 | case OPENRISC_OPERAND_SIMM_16 : | |
707 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_simm16); | |
708 | break; | |
709 | case OPENRISC_OPERAND_UI16NC : | |
710 | { | |
711 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_i16_1); | |
712 | if (length <= 0) break; | |
713 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_i16_2); | |
714 | if (length <= 0) break; | |
715 | { | |
fc05c67f NC |
716 | extern long openrisc_sign_extend_16bit PARAMS ((long)); |
717 | ||
87e6d782 NC |
718 | FLD (f_i16nc) = openrisc_sign_extend_16bit (((((FLD (f_i16_2)) << (11))) | (FLD (f_i16_1)))); |
719 | } | |
720 | } | |
721 | break; | |
722 | case OPENRISC_OPERAND_UIMM_16 : | |
723 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16); | |
724 | break; | |
725 | case OPENRISC_OPERAND_UIMM_5 : | |
726 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_uimm5); | |
727 | break; | |
728 | ||
729 | default : | |
730 | /* xgettext:c-format */ | |
731 | fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), | |
732 | opindex); | |
733 | abort (); | |
734 | } | |
735 | ||
736 | return length; | |
737 | } | |
738 | ||
739 | cgen_insert_fn * const openrisc_cgen_insert_handlers[] = | |
740 | { | |
741 | insert_insn_normal, | |
742 | }; | |
743 | ||
744 | cgen_extract_fn * const openrisc_cgen_extract_handlers[] = | |
745 | { | |
746 | extract_insn_normal, | |
747 | }; | |
748 | ||
749 | /* Getting values from cgen_fields is handled by a collection of functions. | |
750 | They are distinguished by the type of the VALUE argument they return. | |
751 | TODO: floating point, inlining support, remove cases where result type | |
752 | not appropriate. */ | |
753 | ||
754 | int | |
755 | openrisc_cgen_get_int_operand (cd, opindex, fields) | |
fc05c67f | 756 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
87e6d782 NC |
757 | int opindex; |
758 | const CGEN_FIELDS * fields; | |
759 | { | |
760 | int value; | |
761 | ||
762 | switch (opindex) | |
763 | { | |
764 | case OPENRISC_OPERAND_ABS_26 : | |
765 | value = fields->f_abs26; | |
766 | break; | |
767 | case OPENRISC_OPERAND_DISP_26 : | |
768 | value = fields->f_disp26; | |
769 | break; | |
770 | case OPENRISC_OPERAND_HI16 : | |
771 | value = fields->f_simm16; | |
772 | break; | |
773 | case OPENRISC_OPERAND_LO16 : | |
774 | value = fields->f_lo16; | |
775 | break; | |
776 | case OPENRISC_OPERAND_OP_F_23 : | |
777 | value = fields->f_op4; | |
778 | break; | |
779 | case OPENRISC_OPERAND_OP_F_3 : | |
780 | value = fields->f_op5; | |
781 | break; | |
782 | case OPENRISC_OPERAND_RA : | |
783 | value = fields->f_r2; | |
784 | break; | |
785 | case OPENRISC_OPERAND_RB : | |
786 | value = fields->f_r3; | |
787 | break; | |
788 | case OPENRISC_OPERAND_RD : | |
789 | value = fields->f_r1; | |
790 | break; | |
791 | case OPENRISC_OPERAND_SIMM_16 : | |
792 | value = fields->f_simm16; | |
793 | break; | |
794 | case OPENRISC_OPERAND_UI16NC : | |
795 | value = fields->f_i16nc; | |
796 | break; | |
797 | case OPENRISC_OPERAND_UIMM_16 : | |
798 | value = fields->f_uimm16; | |
799 | break; | |
800 | case OPENRISC_OPERAND_UIMM_5 : | |
801 | value = fields->f_uimm5; | |
802 | break; | |
803 | ||
804 | default : | |
805 | /* xgettext:c-format */ | |
806 | fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), | |
807 | opindex); | |
808 | abort (); | |
809 | } | |
810 | ||
811 | return value; | |
812 | } | |
813 | ||
814 | bfd_vma | |
815 | openrisc_cgen_get_vma_operand (cd, opindex, fields) | |
fc05c67f | 816 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
87e6d782 NC |
817 | int opindex; |
818 | const CGEN_FIELDS * fields; | |
819 | { | |
820 | bfd_vma value; | |
821 | ||
822 | switch (opindex) | |
823 | { | |
824 | case OPENRISC_OPERAND_ABS_26 : | |
825 | value = fields->f_abs26; | |
826 | break; | |
827 | case OPENRISC_OPERAND_DISP_26 : | |
828 | value = fields->f_disp26; | |
829 | break; | |
830 | case OPENRISC_OPERAND_HI16 : | |
831 | value = fields->f_simm16; | |
832 | break; | |
833 | case OPENRISC_OPERAND_LO16 : | |
834 | value = fields->f_lo16; | |
835 | break; | |
836 | case OPENRISC_OPERAND_OP_F_23 : | |
837 | value = fields->f_op4; | |
838 | break; | |
839 | case OPENRISC_OPERAND_OP_F_3 : | |
840 | value = fields->f_op5; | |
841 | break; | |
842 | case OPENRISC_OPERAND_RA : | |
843 | value = fields->f_r2; | |
844 | break; | |
845 | case OPENRISC_OPERAND_RB : | |
846 | value = fields->f_r3; | |
847 | break; | |
848 | case OPENRISC_OPERAND_RD : | |
849 | value = fields->f_r1; | |
850 | break; | |
851 | case OPENRISC_OPERAND_SIMM_16 : | |
852 | value = fields->f_simm16; | |
853 | break; | |
854 | case OPENRISC_OPERAND_UI16NC : | |
855 | value = fields->f_i16nc; | |
856 | break; | |
857 | case OPENRISC_OPERAND_UIMM_16 : | |
858 | value = fields->f_uimm16; | |
859 | break; | |
860 | case OPENRISC_OPERAND_UIMM_5 : | |
861 | value = fields->f_uimm5; | |
862 | break; | |
863 | ||
864 | default : | |
865 | /* xgettext:c-format */ | |
866 | fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), | |
867 | opindex); | |
868 | abort (); | |
869 | } | |
870 | ||
871 | return value; | |
872 | } | |
873 | ||
874 | /* Stuffing values in cgen_fields is handled by a collection of functions. | |
875 | They are distinguished by the type of the VALUE argument they accept. | |
876 | TODO: floating point, inlining support, remove cases where argument type | |
877 | not appropriate. */ | |
878 | ||
879 | void | |
880 | openrisc_cgen_set_int_operand (cd, opindex, fields, value) | |
fc05c67f | 881 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
87e6d782 NC |
882 | int opindex; |
883 | CGEN_FIELDS * fields; | |
884 | int value; | |
885 | { | |
886 | switch (opindex) | |
887 | { | |
888 | case OPENRISC_OPERAND_ABS_26 : | |
889 | fields->f_abs26 = value; | |
890 | break; | |
891 | case OPENRISC_OPERAND_DISP_26 : | |
892 | fields->f_disp26 = value; | |
893 | break; | |
894 | case OPENRISC_OPERAND_HI16 : | |
895 | fields->f_simm16 = value; | |
896 | break; | |
897 | case OPENRISC_OPERAND_LO16 : | |
898 | fields->f_lo16 = value; | |
899 | break; | |
900 | case OPENRISC_OPERAND_OP_F_23 : | |
901 | fields->f_op4 = value; | |
902 | break; | |
903 | case OPENRISC_OPERAND_OP_F_3 : | |
904 | fields->f_op5 = value; | |
905 | break; | |
906 | case OPENRISC_OPERAND_RA : | |
907 | fields->f_r2 = value; | |
908 | break; | |
909 | case OPENRISC_OPERAND_RB : | |
910 | fields->f_r3 = value; | |
911 | break; | |
912 | case OPENRISC_OPERAND_RD : | |
913 | fields->f_r1 = value; | |
914 | break; | |
915 | case OPENRISC_OPERAND_SIMM_16 : | |
916 | fields->f_simm16 = value; | |
917 | break; | |
918 | case OPENRISC_OPERAND_UI16NC : | |
919 | fields->f_i16nc = value; | |
920 | break; | |
921 | case OPENRISC_OPERAND_UIMM_16 : | |
922 | fields->f_uimm16 = value; | |
923 | break; | |
924 | case OPENRISC_OPERAND_UIMM_5 : | |
925 | fields->f_uimm5 = value; | |
926 | break; | |
927 | ||
928 | default : | |
929 | /* xgettext:c-format */ | |
930 | fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), | |
931 | opindex); | |
932 | abort (); | |
933 | } | |
934 | } | |
935 | ||
936 | void | |
937 | openrisc_cgen_set_vma_operand (cd, opindex, fields, value) | |
fc05c67f | 938 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
87e6d782 NC |
939 | int opindex; |
940 | CGEN_FIELDS * fields; | |
941 | bfd_vma value; | |
942 | { | |
943 | switch (opindex) | |
944 | { | |
945 | case OPENRISC_OPERAND_ABS_26 : | |
946 | fields->f_abs26 = value; | |
947 | break; | |
948 | case OPENRISC_OPERAND_DISP_26 : | |
949 | fields->f_disp26 = value; | |
950 | break; | |
951 | case OPENRISC_OPERAND_HI16 : | |
952 | fields->f_simm16 = value; | |
953 | break; | |
954 | case OPENRISC_OPERAND_LO16 : | |
955 | fields->f_lo16 = value; | |
956 | break; | |
957 | case OPENRISC_OPERAND_OP_F_23 : | |
958 | fields->f_op4 = value; | |
959 | break; | |
960 | case OPENRISC_OPERAND_OP_F_3 : | |
961 | fields->f_op5 = value; | |
962 | break; | |
963 | case OPENRISC_OPERAND_RA : | |
964 | fields->f_r2 = value; | |
965 | break; | |
966 | case OPENRISC_OPERAND_RB : | |
967 | fields->f_r3 = value; | |
968 | break; | |
969 | case OPENRISC_OPERAND_RD : | |
970 | fields->f_r1 = value; | |
971 | break; | |
972 | case OPENRISC_OPERAND_SIMM_16 : | |
973 | fields->f_simm16 = value; | |
974 | break; | |
975 | case OPENRISC_OPERAND_UI16NC : | |
976 | fields->f_i16nc = value; | |
977 | break; | |
978 | case OPENRISC_OPERAND_UIMM_16 : | |
979 | fields->f_uimm16 = value; | |
980 | break; | |
981 | case OPENRISC_OPERAND_UIMM_5 : | |
982 | fields->f_uimm5 = value; | |
983 | break; | |
984 | ||
985 | default : | |
986 | /* xgettext:c-format */ | |
987 | fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), | |
988 | opindex); | |
989 | abort (); | |
990 | } | |
991 | } | |
992 | ||
993 | /* Function to call before using the instruction builder tables. */ | |
994 | ||
995 | void | |
996 | openrisc_cgen_init_ibld_table (cd) | |
997 | CGEN_CPU_DESC cd; | |
998 | { | |
999 | cd->insert_handlers = & openrisc_cgen_insert_handlers[0]; | |
1000 | cd->extract_handlers = & openrisc_cgen_extract_handlers[0]; | |
1001 | ||
1002 | cd->insert_operand = openrisc_cgen_insert_operand; | |
1003 | cd->extract_operand = openrisc_cgen_extract_operand; | |
1004 | ||
1005 | cd->get_int_operand = openrisc_cgen_get_int_operand; | |
1006 | cd->set_int_operand = openrisc_cgen_set_int_operand; | |
1007 | cd->get_vma_operand = openrisc_cgen_get_vma_operand; | |
1008 | cd->set_vma_operand = openrisc_cgen_set_vma_operand; | |
1009 | } |