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252b5132 1/* ppc-opc.c -- PowerPC opcode list
5e8cb021 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
930bb4cf 3 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Ian Lance Taylor, Cygnus Support
5
9b201bb5 6 This file is part of the GNU opcodes library.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
112290ab 18 You should have received a copy of the GNU General Public License
9b201bb5
NC		 19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132
RH		 22
23#include <stdio.h>
0d8dfecf 24#include "sysdep.h"
252b5132
RH		 25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38\f
39/* Local insertion and extraction functions. */
40
fa452fa6
PB		 41static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
42static long extract_bat (unsigned long, ppc_cpu_t, int *);
43static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
44static long extract_bba (unsigned long, ppc_cpu_t, int *);
45static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
46static long extract_bdm (unsigned long, ppc_cpu_t, int *);
47static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
48static long extract_bdp (unsigned long, ppc_cpu_t, int *);
49static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
50static long extract_bo (unsigned long, ppc_cpu_t, int *);
51static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
52static long extract_boe (unsigned long, ppc_cpu_t, int *);
53static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
54static long extract_fxm (unsigned long, ppc_cpu_t, int *);
55static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
56static long extract_mbe (unsigned long, ppc_cpu_t, int *);
57static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
58static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
59static long extract_nb (unsigned long, ppc_cpu_t, int *);
60static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
61static long extract_nsi (unsigned long, ppc_cpu_t, int *);
62static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
63static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
64static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
65static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
66static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
67static long extract_rbs (unsigned long, ppc_cpu_t, int *);
68static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
69static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
70static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
71static long extract_spr (unsigned long, ppc_cpu_t, int *);
72static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
73static long extract_sprg (unsigned long, ppc_cpu_t, int *);
74static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
75static long extract_tbr (unsigned long, ppc_cpu_t, int *);
252b5132
RH		 76\f
77/* The operands table.
78
717bbdf1 79 The fields are bitm, shift, insert, extract, flags.
252b5132
RH		 80
81 We used to put parens around the various additions, like the one
82 for BA just below. However, that caused trouble with feeble
83 compilers with a limit on depth of a parenthesized expression, like
84 (reportedly) the compiler in Microsoft Developer Studio 5. So we
85 omit the parens, since the macros are never used in a context where
86 the addition will be ambiguous. */
87
88const struct powerpc_operand powerpc_operands[] =
89{
90 /* The zero index is used to indicate the end of the list of
91 operands. */
92#define UNUSED 0
bbac1f2a 93 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 94
95 /* The BA field in an XL form instruction. */
96#define BA UNUSED + 1
717bbdf1
AM		 97 /* The BI field in a B form or XL form instruction. */
98#define BI BA
99#define BI_MASK (0x1f << 16)
b84bf58a 100 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 101
102 /* The BA field in an XL form instruction when it must be the same
103 as the BT field in the same instruction. */
104#define BAT BA + 1
b84bf58a 105 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 106
107 /* The BB field in an XL form instruction. */
108#define BB BAT + 1
109#define BB_MASK (0x1f << 11)
b84bf58a 110 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 111
112 /* The BB field in an XL form instruction when it must be the same
113 as the BA field in the same instruction. */
114#define BBA BB + 1
b84bf58a 115 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 116
117 /* The BD field in a B form instruction. The lower two bits are
118 forced to zero. */
119#define BD BBA + 1
b84bf58a 120 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 121
122 /* The BD field in a B form instruction when absolute addressing is
123 used. */
124#define BDA BD + 1
b84bf58a 125 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 126
127 /* The BD field in a B form instruction when the - modifier is used.
128 This sets the y bit of the BO field appropriately. */
129#define BDM BDA + 1
b84bf58a 130 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 131 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 132
133 /* The BD field in a B form instruction when the - modifier is used
134 and absolute address is used. */
135#define BDMA BDM + 1
b84bf58a 136 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 137 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 138
139 /* The BD field in a B form instruction when the + modifier is used.
140 This sets the y bit of the BO field appropriately. */
141#define BDP BDMA + 1
b84bf58a 142 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 143 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 144
145 /* The BD field in a B form instruction when the + modifier is used
146 and absolute addressing is used. */
147#define BDPA BDP + 1
b84bf58a 148 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 149 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 150
151 /* The BF field in an X or XL form instruction. */
152#define BF BDPA + 1
717bbdf1
AM		 153 /* The CRFD field in an X form instruction. */
154#define CRFD BF
b84bf58a 155 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
252b5132 156
ea192fa3
PB		 157 /* The BF field in an X or XL form instruction. */
158#define BFF BF + 1
159 { 0x7, 23, NULL, NULL, 0 },
160
252b5132
RH		 161 /* An optional BF field. This is used for comparison instructions,
162 in which an omitted BF field is taken as zero. */
ea192fa3 163#define OBF BFF + 1
b84bf58a 164 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 165
166 /* The BFA field in an X or XL form instruction. */
167#define BFA OBF + 1
b84bf58a 168 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
252b5132 169
252b5132
RH		 170 /* The BO field in a B form instruction. Certain values are
171 illegal. */
717bbdf1 172#define BO BFA + 1
252b5132 173#define BO_MASK (0x1f << 21)
b84bf58a 174 { 0x1f, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 175
176 /* The BO field in a B form instruction when the + or - modifier is
177 used. This is like the BO field, but it must be even. */
178#define BOE BO + 1
b84bf58a 179 { 0x1e, 21, insert_boe, extract_boe, 0 },
252b5132 180
d0618d1c 181#define BH BOE + 1
b84bf58a 182 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 183
252b5132 184 /* The BT field in an X or XL form instruction. */
d0618d1c 185#define BT BH + 1
b84bf58a 186 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 187
188 /* The condition register number portion of the BI field in a B form
189 or XL form instruction. This is used for the extended
190 conditional branch mnemonics, which set the lower two bits of the
191 BI field. This field is optional. */
192#define CR BT + 1
b84bf58a 193 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 194
23976049
EZ		 195 /* The CRB field in an X form instruction. */
196#define CRB CR + 1
717bbdf1
AM		 197 /* The MB field in an M form instruction. */
198#define MB CRB
199#define MB_MASK (0x1f << 6)
b84bf58a 200 { 0x1f, 6, NULL, NULL, 0 },
23976049 201
23976049 202 /* The CRFS field in an X form instruction. */
717bbdf1 203#define CRFS CRB + 1
b84bf58a 204 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
23976049 205
418c1742 206 /* The CT field in an X form instruction. */
23976049 207#define CT CRFS + 1
717bbdf1
AM		 208 /* The MO field in an mbar instruction. */
209#define MO CT
b84bf58a 210 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 211
252b5132
RH		 212 /* The D field in a D form instruction. This is a displacement off
213 a register, and implies that the next operand is a register in
214 parentheses. */
418c1742 215#define D CT + 1
b84bf58a 216 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 217
418c1742
MG		 218 /* The DE field in a DE form instruction. This is like D, but is 12
219 bits only. */
220#define DE D + 1
b84bf58a 221 { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
418c1742
MG		 222
223 /* The DES field in a DES form instruction. This is like DS, but is 14
224 bits only (12 stored.) */
225#define DES DE + 1
b84bf58a 226 { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
418c1742 227
adadcc0c
AM		 228 /* The DQ field in a DQ form instruction. This is like D, but the
229 lower four bits are forced to zero. */
230#define DQ DES + 1
b84bf58a
AM		 231 { 0xfff0, 0, NULL, NULL,
232 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
adadcc0c 233
252b5132
RH		 234 /* The DS field in a DS form instruction. This is like D, but the
235 lower two bits are forced to zero. */
adadcc0c 236#define DS DQ + 1
b84bf58a
AM		 237 { 0xfffc, 0, NULL, NULL,
238 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132 239
19a6653c
AM		 240 /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
241#define DUIS DS + 1
242 { 0x3ff, 11, NULL, NULL, 0 },
243
252b5132 244 /* The E field in a wrteei instruction. */
c3d65c1c 245 /* And the W bit in the pair singles instructions. */
19a6653c 246#define E DUIS + 1
c3d65c1c 247#define PSW E
b84bf58a 248 { 0x1, 15, NULL, NULL, 0 },
252b5132
RH		 249
250 /* The FL1 field in a POWER SC form instruction. */
251#define FL1 E + 1
717bbdf1
AM		 252 /* The U field in an X form instruction. */
253#define U FL1
b84bf58a 254 { 0xf, 12, NULL, NULL, 0 },
252b5132
RH		 255
256 /* The FL2 field in a POWER SC form instruction. */
257#define FL2 FL1 + 1
b84bf58a 258 { 0x7, 2, NULL, NULL, 0 },
252b5132
RH		 259
260 /* The FLM field in an XFL form instruction. */
261#define FLM FL2 + 1
b84bf58a 262 { 0xff, 17, NULL, NULL, 0 },
252b5132
RH		 263
264 /* The FRA field in an X or A form instruction. */
265#define FRA FLM + 1
266#define FRA_MASK (0x1f << 16)
b84bf58a 267 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 268
269 /* The FRB field in an X or A form instruction. */
270#define FRB FRA + 1
271#define FRB_MASK (0x1f << 11)
b84bf58a 272 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 273
274 /* The FRC field in an A form instruction. */
275#define FRC FRB + 1
276#define FRC_MASK (0x1f << 6)
b84bf58a 277 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 278
279 /* The FRS field in an X form instruction or the FRT field in a D, X
280 or A form instruction. */
281#define FRS FRC + 1
282#define FRT FRS
b84bf58a 283 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 284
285 /* The FXM field in an XFX instruction. */
286#define FXM FRS + 1
b84bf58a 287 { 0xff, 12, insert_fxm, extract_fxm, 0 },
c168870a
AM		 288
289 /* Power4 version for mfcr. */
290#define FXM4 FXM + 1
b84bf58a 291 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
252b5132
RH		 292
293 /* The L field in a D or X form instruction. */
c168870a 294#define L FXM4 + 1
b84bf58a 295 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 296
1ed8e1e4
AM		 297 /* The LEV field in a POWER SVC form instruction. */
298#define SVC_LEV L + 1
b84bf58a 299 { 0x7f, 5, NULL, NULL, 0 },
252b5132 300
1ed8e1e4
AM		 301 /* The LEV field in an SC form instruction. */
302#define LEV SVC_LEV + 1
b84bf58a 303 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
1ed8e1e4 304
252b5132
RH		 305 /* The LI field in an I form instruction. The lower two bits are
306 forced to zero. */
307#define LI LEV + 1
b84bf58a 308 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 309
310 /* The LI field in an I form instruction when used as an absolute
311 address. */
312#define LIA LI + 1
b84bf58a 313 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 314
6ba045b1
AM		 315 /* The LS field in an X (sync) form instruction. */
316#define LS LIA + 1
b84bf58a 317 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
6ba045b1 318
252b5132 319 /* The ME field in an M form instruction. */
717bbdf1 320#define ME LS + 1
252b5132 321#define ME_MASK (0x1f << 1)
b84bf58a 322 { 0x1f, 1, NULL, NULL, 0 },
252b5132
RH		 323
324 /* The MB and ME fields in an M form instruction expressed a single
325 operand which is a bitmask indicating which bits to select. This
326 is a two operand form using PPC_OPERAND_NEXT. See the
327 description in opcode/ppc.h for what this means. */
328#define MBE ME + 1
b84bf58a 329 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
eb42fac1 330 { -1, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 331
332 /* The MB or ME field in an MD or MDS form instruction. The high
333 bit is wrapped to the low end. */
334#define MB6 MBE + 2
335#define ME6 MB6
336#define MB6_MASK (0x3f << 5)
b84bf58a 337 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
252b5132
RH		 338
339 /* The NB field in an X form instruction. The value 32 is stored as
340 0. */
717bbdf1 341#define NB MB6 + 1
b84bf58a 342 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
252b5132
RH		 343
344 /* The NSI field in a D form instruction. This is the same as the
345 SI field, only negated. */
346#define NSI NB + 1
b84bf58a 347 { 0xffff, 0, insert_nsi, extract_nsi,
11b37b7b 348 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132 349
adadcc0c 350 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
914749f6 351#define RA NSI + 1
252b5132 352#define RA_MASK (0x1f << 16)
b84bf58a 353 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 354
fdd12ef3
AM		 355 /* As above, but 0 in the RA field means zero, not r0. */
356#define RA0 RA + 1
b84bf58a 357 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3
AM		 358
359 /* The RA field in the DQ form lq instruction, which has special
adadcc0c 360 value restrictions. */
fdd12ef3 361#define RAQ RA0 + 1
b84bf58a 362 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 363
252b5132
RH		 364 /* The RA field in a D or X form instruction which is an updating
365 load, which means that the RA field may not be zero and may not
366 equal the RT field. */
adadcc0c 367#define RAL RAQ + 1
b84bf58a 368 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 369
370 /* The RA field in an lmw instruction, which has special value
371 restrictions. */
372#define RAM RAL + 1
b84bf58a 373 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 374
375 /* The RA field in a D or X form instruction which is an updating
376 store or an updating floating point load, which means that the RA
377 field may not be zero. */
378#define RAS RAM + 1
b84bf58a 379 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
252b5132 380
1f6c9eb0 381 /* The RA field of the tlbwe instruction, which is optional. */
fdd12ef3 382#define RAOPT RAS + 1
b84bf58a 383 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 384
252b5132 385 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 386#define RB RAOPT + 1
252b5132 387#define RB_MASK (0x1f << 11)
b84bf58a 388 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 389
390 /* The RB field in an X form instruction when it must be the same as
391 the RS field in the instruction. This is used for extended
392 mnemonics like mr. */
393#define RBS RB + 1
b84bf58a 394 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132
RH		 395
396 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
397 instruction or the RT field in a D, DS, X, XFX or XO form
398 instruction. */
399#define RS RBS + 1
400#define RT RS
401#define RT_MASK (0x1f << 21)
b84bf58a 402 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 403
717bbdf1
AM		 404 /* The RS and RT fields of the DS form stq instruction, which have
405 special value restrictions. */
adadcc0c 406#define RSQ RS + 1
717bbdf1 407#define RTQ RSQ
b84bf58a 408 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 409
1f6c9eb0 410 /* The RS field of the tlbwe instruction, which is optional. */
717bbdf1 411#define RSO RSQ + 1
eed0d89a 412#define RTO RSO
b84bf58a 413 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 414
252b5132 415 /* The SH field in an X or M form instruction. */
1f6c9eb0 416#define SH RSO + 1
252b5132 417#define SH_MASK (0x1f << 11)
717bbdf1
AM		 418 /* The other UIMM field in a EVX form instruction. */
419#define EVUIMM SH
b84bf58a 420 { 0x1f, 11, NULL, NULL, 0 },
252b5132
RH		 421
422 /* The SH field in an MD form instruction. This is split. */
423#define SH6 SH + 1
424#define SH6_MASK ((0x1f << 11) | (1 << 1))
b84bf58a 425 { 0x3f, -1, insert_sh6, extract_sh6, 0 },
252b5132 426
1f6c9eb0
ZW		 427 /* The SH field of the tlbwe instruction, which is optional. */
428#define SHO SH6 + 1
b84bf58a 429 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 430
252b5132 431 /* The SI field in a D form instruction. */
1f6c9eb0 432#define SI SHO + 1
b84bf58a 433 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 434
435 /* The SI field in a D form instruction when we accept a wide range
436 of positive values. */
437#define SISIGNOPT SI + 1
b84bf58a 438 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 439
440 /* The SPR field in an XFX form instruction. This is flipped--the
441 lower 5 bits are stored in the upper 5 and vice- versa. */
442#define SPR SISIGNOPT + 1
914749f6 443#define PMR SPR
252b5132 444#define SPR_MASK (0x3ff << 11)
b84bf58a 445 { 0x3ff, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 446
447 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
448#define SPRBAT SPR + 1
449#define SPRBAT_MASK (0x3 << 17)
b84bf58a 450 { 0x3, 17, NULL, NULL, 0 },
252b5132
RH		 451
452 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
453#define SPRG SPRBAT + 1
b84bf58a 454 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
252b5132
RH		 455
456 /* The SR field in an X form instruction. */
457#define SR SPRG + 1
b84bf58a 458 { 0xf, 16, NULL, NULL, 0 },
252b5132 459
f5c120c5
MG		 460 /* The STRM field in an X AltiVec form instruction. */
461#define STRM SR + 1
19a6653c
AM		 462 /* The T field in a tlbilx form instruction. */
463#define T STRM
b84bf58a 464 { 0x3, 21, NULL, NULL, 0 },
f5c120c5 465
252b5132 466 /* The SV field in a POWER SC form instruction. */
f5c120c5 467#define SV STRM + 1
b84bf58a 468 { 0x3fff, 2, NULL, NULL, 0 },
252b5132
RH		 469
470 /* The TBR field in an XFX form instruction. This is like the SPR
471 field, but it is optional. */
472#define TBR SV + 1
b84bf58a 473 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 474
475 /* The TO field in a D or X form instruction. */
476#define TO TBR + 1
19a6653c 477#define DUI TO
252b5132 478#define TO_MASK (0x1f << 21)
b84bf58a 479 { 0x1f, 21, NULL, NULL, 0 },
252b5132 480
252b5132 481 /* The UI field in a D form instruction. */
717bbdf1 482#define UI TO + 1
b84bf58a 483 { 0xffff, 0, NULL, NULL, 0 },
786e2c0f 484
112290ab 485 /* The VA field in a VA, VX or VXR form instruction. */
786e2c0f 486#define VA UI + 1
b84bf58a 487 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 488
112290ab 489 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f 490#define VB VA + 1
b84bf58a 491 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 492
112290ab 493 /* The VC field in a VA form instruction. */
786e2c0f 494#define VC VB + 1
b84bf58a 495 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 496
112290ab 497 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 498#define VD VC + 1
499#define VS VD
b84bf58a 500 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 501
8dbcd839 502 /* The SIMM field in a VX form instruction, and TE in Z form. */
786e2c0f 503#define SIMM VD + 1
8dbcd839 504#define TE SIMM
b84bf58a 505 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 506
8dbcd839 507 /* The UIMM field in a VX form instruction. */
786e2c0f 508#define UIMM SIMM + 1
b84bf58a 509 { 0x1f, 16, NULL, NULL, 0 },
786e2c0f 510
112290ab 511 /* The SHB field in a VA form instruction. */
786e2c0f 512#define SHB UIMM + 1
b84bf58a 513 { 0xf, 6, NULL, NULL, 0 },
ff3a6ee3 514
112290ab 515 /* The other UIMM field in a half word EVX form instruction. */
717bbdf1 516#define EVUIMM_2 SHB + 1
b84bf58a 517 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
23976049 518
112290ab 519 /* The other UIMM field in a word EVX form instruction. */
23976049 520#define EVUIMM_4 EVUIMM_2 + 1
b84bf58a 521 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
23976049 522
112290ab 523 /* The other UIMM field in a double EVX form instruction. */
23976049 524#define EVUIMM_8 EVUIMM_4 + 1
b84bf58a 525 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
23976049 526
ff3a6ee3 527 /* The WS field. */
23976049 528#define WS EVUIMM_8 + 1
b84bf58a 529 { 0x7, 11, NULL, NULL, 0 },
ff3a6ee3 530
c3d65c1c
BE		 531 /* PowerPC paired singles extensions. */
532 /* W bit in the pair singles instructions for x type instructions. */
533#define PSWM WS + 1
534 { 0x1, 10, 0, 0, 0 },
535
536 /* IDX bits for quantization in the pair singles instructions. */
537#define PSQ PSWM + 1
538 { 0x7, 12, 0, 0, 0 },
539
540 /* IDX bits for quantization in the pair singles x-type instructions. */
541#define PSQM PSQ + 1
542 { 0x7, 7, 0, 0, 0 },
543
544 /* Smaller D field for quantization in the pair singles instructions. */
545#define PSD PSQM + 1
546 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
547
548#define A_L PSD + 1
ea192fa3 549#define W A_L
c3d65c1c 550#define MTMSRD_L W
b84bf58a 551 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 552
c3d65c1c 553#define RMC MTMSRD_L + 1
b84bf58a 554 { 0x3, 9, NULL, NULL, 0 },
702f0fb4
PB		 555
556#define R RMC + 1
b84bf58a 557 { 0x1, 16, NULL, NULL, 0 },
702f0fb4
PB		 558
559#define SP R + 1
b84bf58a 560 { 0x3, 19, NULL, NULL, 0 },
702f0fb4
PB		 561
562#define S SP + 1
b84bf58a 563 { 0x1, 20, NULL, NULL, 0 },
702f0fb4
PB		 564
565 /* SH field starting at bit position 16. */
566#define SH16 S + 1
0bbdef92
AM		 567 /* The DCM and DGM fields in a Z form instruction. */
568#define DCM SH16
569#define DGM DCM
b84bf58a 570 { 0x3f, 10, NULL, NULL, 0 },
702f0fb4 571
702f0fb4 572 /* The EH field in larx instruction. */
717bbdf1 573#define EH SH16 + 1
b84bf58a 574 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
ea192fa3
PB		 575
576 /* The L field in an mtfsf or XFL form instruction. */
577#define XFL_L EH + 1
578 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
252b5132
RH		 579};
580
b84bf58a
AM		 581const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
582 / sizeof (powerpc_operands[0]));
583
252b5132
RH		 584/* The functions used to insert and extract complicated operands. */
585
586/* The BA field in an XL form instruction when it must be the same as
587 the BT field in the same instruction. This operand is marked FAKE.
588 The insertion function just copies the BT field into the BA field,
589 and the extraction function just checks that the fields are the
590 same. */
591
252b5132 592static unsigned long
2fbfdc41
AM		 593insert_bat (unsigned long insn,
594 long value ATTRIBUTE_UNUSED,
fa452fa6 595 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 596 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 597{
598 return insn | (((insn >> 21) & 0x1f) << 16);
599}
600
601static long
2fbfdc41 602extract_bat (unsigned long insn,
fa452fa6 603 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 604 int *invalid)
252b5132 605{
8427c424 606 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 607 *invalid = 1;
608 return 0;
609}
610
611/* The BB field in an XL form instruction when it must be the same as
612 the BA field in the same instruction. This operand is marked FAKE.
613 The insertion function just copies the BA field into the BB field,
614 and the extraction function just checks that the fields are the
615 same. */
616
252b5132 617static unsigned long
2fbfdc41
AM		 618insert_bba (unsigned long insn,
619 long value ATTRIBUTE_UNUSED,
fa452fa6 620 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 621 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 622{
623 return insn | (((insn >> 16) & 0x1f) << 11);
624}
625
626static long
2fbfdc41 627extract_bba (unsigned long insn,
fa452fa6 628 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 629 int *invalid)
252b5132 630{
8427c424 631 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 632 *invalid = 1;
633 return 0;
634}
635
252b5132
RH		 636/* The BD field in a B form instruction when the - modifier is used.
637 This modifier means that the branch is not expected to be taken.
94efba12
AM		 638 For chips built to versions of the architecture prior to version 2
639 (ie. not Power4 compatible), we set the y bit of the BO field to 1
640 if the offset is negative. When extracting, we require that the y
641 bit be 1 and that the offset be positive, since if the y bit is 0
642 we just want to print the normal form of the instruction.
643 Power4 compatible targets use two bits, "a", and "t", instead of
644 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
645 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
646 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ba4e851b
AM		 647 for branch on CTR. We only handle the taken/not-taken hint here.
648 Note that we don't relax the conditions tested here when
649 disassembling with -Many because insns using extract_bdm and
650 extract_bdp always occur in pairs. One or the other will always
651 be valid. */
252b5132 652
252b5132 653static unsigned long
2fbfdc41
AM		 654insert_bdm (unsigned long insn,
655 long value,
fa452fa6 656 ppc_cpu_t dialect,
2fbfdc41 657 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 658{
94efba12 659 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 660 {
661 if ((value & 0x8000) != 0)
662 insn |= 1 << 21;
663 }
664 else
665 {
666 if ((insn & (0x14 << 21)) == (0x04 << 21))
667 insn |= 0x02 << 21;
668 else if ((insn & (0x14 << 21)) == (0x10 << 21))
669 insn |= 0x08 << 21;
670 }
252b5132
RH		 671 return insn | (value & 0xfffc);
672}
673
674static long
2fbfdc41 675extract_bdm (unsigned long insn,
fa452fa6 676 ppc_cpu_t dialect,
2fbfdc41 677 int *invalid)
252b5132 678{
8427c424 679 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 680 {
8427c424
AM		 681 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
682 *invalid = 1;
802a735e 683 }
8427c424
AM		 684 else
685 {
686 if ((insn & (0x17 << 21)) != (0x06 << 21)
687 && (insn & (0x1d << 21)) != (0x18 << 21))
688 *invalid = 1;
689 }
690
802a735e 691 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 692}
693
694/* The BD field in a B form instruction when the + modifier is used.
695 This is like BDM, above, except that the branch is expected to be
696 taken. */
697
252b5132 698static unsigned long
2fbfdc41
AM		 699insert_bdp (unsigned long insn,
700 long value,
fa452fa6 701 ppc_cpu_t dialect,
2fbfdc41 702 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 703{
94efba12 704 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 705 {
706 if ((value & 0x8000) == 0)
707 insn |= 1 << 21;
708 }
709 else
710 {
711 if ((insn & (0x14 << 21)) == (0x04 << 21))
712 insn |= 0x03 << 21;
713 else if ((insn & (0x14 << 21)) == (0x10 << 21))
714 insn |= 0x09 << 21;
715 }
252b5132
RH		 716 return insn | (value & 0xfffc);
717}
718
719static long
2fbfdc41 720extract_bdp (unsigned long insn,
fa452fa6 721 ppc_cpu_t dialect,
2fbfdc41 722 int *invalid)
252b5132 723{
8427c424 724 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 725 {
8427c424
AM		 726 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
727 *invalid = 1;
728 }
729 else
730 {
731 if ((insn & (0x17 << 21)) != (0x07 << 21)
732 && (insn & (0x1d << 21)) != (0x19 << 21))
733 *invalid = 1;
802a735e 734 }
8427c424 735
802a735e 736 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 737}
738
739/* Check for legal values of a BO field. */
740
741static int
fa452fa6 742valid_bo (long value, ppc_cpu_t dialect, int extract)
252b5132 743{
94efba12 744 if ((dialect & PPC_OPCODE_POWER4) == 0)
252b5132 745 {
ba4e851b 746 int valid;
802a735e
AM		 747 /* Certain encodings have bits that are required to be zero.
748 These are (z must be zero, y may be anything):
749 001zy
750 011zy
751 1z00y
752 1z01y
753 1z1zz
754 */
755 switch (value & 0x14)
756 {
757 default:
758 case 0:
ba4e851b
AM		 759 valid = 1;
760 break;
802a735e 761 case 0x4:
ba4e851b
AM		 762 valid = (value & 0x2) == 0;
763 break;
802a735e 764 case 0x10:
ba4e851b
AM		 765 valid = (value & 0x8) == 0;
766 break;
802a735e 767 case 0x14:
ba4e851b
AM		 768 valid = value == 0x14;
769 break;
802a735e 770 }
ba4e851b
AM		 771 /* When disassembling with -Many, accept power4 encodings too. */
772 if (valid
773 || (dialect & PPC_OPCODE_ANY) == 0
774 || !extract)
775 return valid;
802a735e 776 }
ba4e851b
AM		 777
778 /* Certain encodings have bits that are required to be zero.
779 These are (z must be zero, a & t may be anything):
780 0000z
781 0001z
782 0100z
783 0101z
784 001at
785 011at
786 1a00t
787 1a01t
788 1z1zz
789 */
790 if ((value & 0x14) == 0)
791 return (value & 0x1) == 0;
792 else if ((value & 0x14) == 0x14)
793 return value == 0x14;
802a735e 794 else
ba4e851b 795 return 1;
252b5132
RH		 796}
797
798/* The BO field in a B form instruction. Warn about attempts to set
799 the field to an illegal value. */
800
801static unsigned long
2fbfdc41
AM		 802insert_bo (unsigned long insn,
803 long value,
fa452fa6 804 ppc_cpu_t dialect,
2fbfdc41 805 const char **errmsg)
252b5132 806{
ba4e851b 807 if (!valid_bo (value, dialect, 0))
252b5132
RH		 808 *errmsg = _("invalid conditional option");
809 return insn | ((value & 0x1f) << 21);
810}
811
812static long
2fbfdc41 813extract_bo (unsigned long insn,
fa452fa6 814 ppc_cpu_t dialect,
2fbfdc41 815 int *invalid)
252b5132
RH		 816{
817 long value;
818
819 value = (insn >> 21) & 0x1f;
ba4e851b 820 if (!valid_bo (value, dialect, 1))
252b5132
RH		 821 *invalid = 1;
822 return value;
823}
824
825/* The BO field in a B form instruction when the + or - modifier is
826 used. This is like the BO field, but it must be even. When
827 extracting it, we force it to be even. */
828
829static unsigned long
2fbfdc41
AM		 830insert_boe (unsigned long insn,
831 long value,
fa452fa6 832 ppc_cpu_t dialect,
2fbfdc41 833 const char **errmsg)
252b5132 834{
ba4e851b 835 if (!valid_bo (value, dialect, 0))
8427c424
AM		 836 *errmsg = _("invalid conditional option");
837 else if ((value & 1) != 0)
838 *errmsg = _("attempt to set y bit when using + or - modifier");
839
252b5132
RH		 840 return insn | ((value & 0x1f) << 21);
841}
842
843static long
2fbfdc41 844extract_boe (unsigned long insn,
fa452fa6 845 ppc_cpu_t dialect,
2fbfdc41 846 int *invalid)
252b5132
RH		 847{
848 long value;
849
850 value = (insn >> 21) & 0x1f;
ba4e851b 851 if (!valid_bo (value, dialect, 1))
252b5132
RH		 852 *invalid = 1;
853 return value & 0x1e;
854}
855
2fbfdc41
AM		 856/* FXM mask in mfcr and mtcrf instructions. */
857
858static unsigned long
859insert_fxm (unsigned long insn,
860 long value,
fa452fa6 861 ppc_cpu_t dialect,
2fbfdc41 862 const char **errmsg)
c168870a 863{
98e69875
AM		 864 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
865 one bit of the mask field is set. */
866 if ((insn & (1 << 20)) != 0)
867 {
868 if (value == 0 || (value & -value) != value)
869 {
870 *errmsg = _("invalid mask field");
871 value = 0;
872 }
873 }
874
c168870a
AM		 875 /* If the optional field on mfcr is missing that means we want to use
876 the old form of the instruction that moves the whole cr. In that
877 case we'll have VALUE zero. There doesn't seem to be a way to
878 distinguish this from the case where someone writes mfcr %r3,0. */
98e69875 879 else if (value == 0)
c168870a
AM		 880 ;
881
882 /* If only one bit of the FXM field is set, we can use the new form
661bd698 883 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 884 encoding, this is not backward compatible. Do not generate the
885 new form unless -mpower4 has been given, or -many and the two
886 operand form of mfcr was used. */
887 else if ((value & -value) == value
888 && ((dialect & PPC_OPCODE_POWER4) != 0
889 || ((dialect & PPC_OPCODE_ANY) != 0
890 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 891 insn |= 1 << 20;
892
893 /* Any other value on mfcr is an error. */
894 else if ((insn & (0x3ff << 1)) == 19 << 1)
895 {
8427c424 896 *errmsg = _("ignoring invalid mfcr mask");
c168870a
AM		 897 value = 0;
898 }
899
900 return insn | ((value & 0xff) << 12);
901}
902
2fbfdc41
AM		 903static long
904extract_fxm (unsigned long insn,
fa452fa6 905 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 906 int *invalid)
c168870a
AM		 907{
908 long mask = (insn >> 12) & 0xff;
909
910 /* Is this a Power4 insn? */
911 if ((insn & (1 << 20)) != 0)
912 {
98e69875
AM		 913 /* Exactly one bit of MASK should be set. */
914 if (mask == 0 || (mask & -mask) != mask)
8427c424 915 *invalid = 1;
c168870a
AM		 916 }
917
918 /* Check that non-power4 form of mfcr has a zero MASK. */
919 else if ((insn & (0x3ff << 1)) == 19 << 1)
920 {
8427c424 921 if (mask != 0)
c168870a
AM		 922 *invalid = 1;
923 }
924
925 return mask;
926}
927
252b5132
RH		 928/* The MB and ME fields in an M form instruction expressed as a single
929 operand which is itself a bitmask. The extraction function always
930 marks it as invalid, since we never want to recognize an
931 instruction which uses a field of this type. */
932
933static unsigned long
2fbfdc41
AM		 934insert_mbe (unsigned long insn,
935 long value,
fa452fa6 936 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 937 const char **errmsg)
252b5132
RH		 938{
939 unsigned long uval, mask;
940 int mb, me, mx, count, last;
941
942 uval = value;
943
944 if (uval == 0)
945 {
8427c424 946 *errmsg = _("illegal bitmask");
252b5132
RH		 947 return insn;
948 }
949
950 mb = 0;
951 me = 32;
952 if ((uval & 1) != 0)
953 last = 1;
954 else
955 last = 0;
956 count = 0;
957
958 /* mb: location of last 0->1 transition */
959 /* me: location of last 1->0 transition */
960 /* count: # transitions */
961
0deb7ac5 962 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 963 {
964 if ((uval & mask) && !last)
965 {
966 ++count;
967 mb = mx;
968 last = 1;
969 }
970 else if (!(uval & mask) && last)
971 {
972 ++count;
973 me = mx;
974 last = 0;
975 }
976 }
977 if (me == 0)
978 me = 32;
979
980 if (count != 2 && (count != 0 || ! last))
8427c424 981 *errmsg = _("illegal bitmask");
252b5132
RH		 982
983 return insn | (mb << 6) | ((me - 1) << 1);
984}
985
986static long
2fbfdc41 987extract_mbe (unsigned long insn,
fa452fa6 988 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 989 int *invalid)
252b5132
RH		 990{
991 long ret;
992 int mb, me;
993 int i;
994
8427c424 995 *invalid = 1;
252b5132
RH		 996
997 mb = (insn >> 6) & 0x1f;
998 me = (insn >> 1) & 0x1f;
999 if (mb < me + 1)
1000 {
1001 ret = 0;
1002 for (i = mb; i <= me; i++)
0deb7ac5 1003 ret |= 1L << (31 - i);
252b5132
RH		 1004 }
1005 else if (mb == me + 1)
8427c424 1006 ret = ~0;
252b5132
RH		 1007 else /* (mb > me + 1) */
1008 {
2fbfdc41 1009 ret = ~0;
252b5132 1010 for (i = me + 1; i < mb; i++)
0deb7ac5 1011 ret &= ~(1L << (31 - i));
252b5132
RH		 1012 }
1013 return ret;
1014}
1015
1016/* The MB or ME field in an MD or MDS form instruction. The high bit
1017 is wrapped to the low end. */
1018
252b5132 1019static unsigned long
2fbfdc41
AM		 1020insert_mb6 (unsigned long insn,
1021 long value,
fa452fa6 1022 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1023 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1024{
1025 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1026}
1027
252b5132 1028static long
2fbfdc41 1029extract_mb6 (unsigned long insn,
fa452fa6 1030 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1031 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1032{
1033 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1034}
1035
1036/* The NB field in an X form instruction. The value 32 is stored as
1037 0. */
1038
252b5132 1039static long
2fbfdc41 1040extract_nb (unsigned long insn,
fa452fa6 1041 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1042 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1043{
1044 long ret;
1045
1046 ret = (insn >> 11) & 0x1f;
1047 if (ret == 0)
1048 ret = 32;
1049 return ret;
1050}
1051
1052/* The NSI field in a D form instruction. This is the same as the SI
1053 field, only negated. The extraction function always marks it as
1054 invalid, since we never want to recognize an instruction which uses
1055 a field of this type. */
1056
252b5132 1057static unsigned long
2fbfdc41
AM		 1058insert_nsi (unsigned long insn,
1059 long value,
fa452fa6 1060 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1061 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1062{
2fbfdc41 1063 return insn | (-value & 0xffff);
252b5132
RH		 1064}
1065
1066static long
2fbfdc41 1067extract_nsi (unsigned long insn,
fa452fa6 1068 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1069 int *invalid)
252b5132 1070{
8427c424 1071 *invalid = 1;
2fbfdc41 1072 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1073}
1074
1075/* The RA field in a D or X form instruction which is an updating
1076 load, which means that the RA field may not be zero and may not
1077 equal the RT field. */
1078
1079static unsigned long
2fbfdc41
AM		 1080insert_ral (unsigned long insn,
1081 long value,
fa452fa6 1082 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1083 const char **errmsg)
252b5132
RH		 1084{
1085 if (value == 0
1086 || (unsigned long) value == ((insn >> 21) & 0x1f))
1087 *errmsg = "invalid register operand when updating";
1088 return insn | ((value & 0x1f) << 16);
1089}
1090
1091/* The RA field in an lmw instruction, which has special value
1092 restrictions. */
1093
1094static unsigned long
2fbfdc41
AM		 1095insert_ram (unsigned long insn,
1096 long value,
fa452fa6 1097 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1098 const char **errmsg)
252b5132
RH		 1099{
1100 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1101 *errmsg = _("index register in load range");
1102 return insn | ((value & 0x1f) << 16);
1103}
1104
fdd12ef3 1105/* The RA field in the DQ form lq instruction, which has special
8427c424 1106 value restrictions. */
adadcc0c 1107
adadcc0c 1108static unsigned long
2fbfdc41
AM		 1109insert_raq (unsigned long insn,
1110 long value,
fa452fa6 1111 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1112 const char **errmsg)
adadcc0c
AM		 1113{
1114 long rtvalue = (insn & RT_MASK) >> 21;
1115
8427c424 1116 if (value == rtvalue)
adadcc0c
AM		 1117 *errmsg = _("source and target register operands must be different");
1118 return insn | ((value & 0x1f) << 16);
1119}
1120
252b5132
RH		 1121/* The RA field in a D or X form instruction which is an updating
1122 store or an updating floating point load, which means that the RA
1123 field may not be zero. */
1124
1125static unsigned long
2fbfdc41
AM		 1126insert_ras (unsigned long insn,
1127 long value,
fa452fa6 1128 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1129 const char **errmsg)
252b5132
RH		 1130{
1131 if (value == 0)
1132 *errmsg = _("invalid register operand when updating");
1133 return insn | ((value & 0x1f) << 16);
1134}
1135
1136/* The RB field in an X form instruction when it must be the same as
1137 the RS field in the instruction. This is used for extended
1138 mnemonics like mr. This operand is marked FAKE. The insertion
1139 function just copies the BT field into the BA field, and the
1140 extraction function just checks that the fields are the same. */
1141
252b5132 1142static unsigned long
2fbfdc41
AM		 1143insert_rbs (unsigned long insn,
1144 long value ATTRIBUTE_UNUSED,
fa452fa6 1145 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1146 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1147{
1148 return insn | (((insn >> 21) & 0x1f) << 11);
1149}
1150
1151static long
2fbfdc41 1152extract_rbs (unsigned long insn,
fa452fa6 1153 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1154 int *invalid)
252b5132 1155{
8427c424 1156 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1157 *invalid = 1;
1158 return 0;
1159}
1160
1161/* The SH field in an MD form instruction. This is split. */
1162
252b5132 1163static unsigned long
2fbfdc41
AM		 1164insert_sh6 (unsigned long insn,
1165 long value,
fa452fa6 1166 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1167 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1168{
1169 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1170}
1171
252b5132 1172static long
2fbfdc41 1173extract_sh6 (unsigned long insn,
fa452fa6 1174 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1175 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1176{
1177 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1178}
1179
1180/* The SPR field in an XFX form instruction. This is flipped--the
1181 lower 5 bits are stored in the upper 5 and vice- versa. */
1182
1183static unsigned long
2fbfdc41
AM		 1184insert_spr (unsigned long insn,
1185 long value,
fa452fa6 1186 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1187 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1188{
1189 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1190}
1191
1192static long
2fbfdc41 1193extract_spr (unsigned long insn,
fa452fa6 1194 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1195 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1196{
1197 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1198}
1199
da99ee72
AM		 1200/* Some dialects have 8 SPRG registers instead of the standard 4. */
1201
1202static unsigned long
1203insert_sprg (unsigned long insn,
1204 long value,
fa452fa6 1205 ppc_cpu_t dialect,
da99ee72
AM		 1206 const char **errmsg)
1207{
1208 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1209 as a synonym. If ever a 405 specific dialect is added this
1210 check should use that instead. */
1211 if (value > 7
1212 || (value > 3
1213 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1214 *errmsg = _("invalid sprg number");
1215
1216 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1217 user mode. Anything else must use spr 272..279. */
1218 if (value <= 3 || (insn & 0x100) != 0)
1219 value |= 0x10;
1220
1221 return insn | ((value & 0x17) << 16);
1222}
1223
1224static long
1225extract_sprg (unsigned long insn,
fa452fa6 1226 ppc_cpu_t dialect,
da99ee72
AM		 1227 int *invalid)
1228{
1229 unsigned long val = (insn >> 16) & 0x1f;
1230
1231 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1232 If not BOOKE or 405, then both use only 272..275. */
1233 if (val <= 3
1234 || (val < 0x10 && (insn & 0x100) != 0)
1235 || (val - 0x10 > 3
1236 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1237 *invalid = 1;
1238 return val & 7;
1239}
1240
252b5132
RH		 1241/* The TBR field in an XFX instruction. This is just like SPR, but it
1242 is optional. When TBR is omitted, it must be inserted as 268 (the
1243 magic number of the TB register). These functions treat 0
1244 (indicating an omitted optional operand) as 268. This means that
1245 ``mftb 4,0'' is not handled correctly. This does not matter very
1246 much, since the architecture manual does not define mftb as
1247 accepting any values other than 268 or 269. */
1248
1249#define TB (268)
1250
1251static unsigned long
2fbfdc41
AM		 1252insert_tbr (unsigned long insn,
1253 long value,
fa452fa6 1254 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1255 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1256{
1257 if (value == 0)
1258 value = TB;
1259 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1260}
1261
1262static long
2fbfdc41 1263extract_tbr (unsigned long insn,
fa452fa6 1264 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1265 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1266{
1267 long ret;
1268
1269 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1270 if (ret == TB)
1271 ret = 0;
1272 return ret;
1273}
1274\f
1275/* Macros used to form opcodes. */
1276
1277/* The main opcode. */
1278#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1279#define OP_MASK OP (0x3f)
1280
1281/* The main opcode combined with a trap code in the TO field of a D
1282 form instruction. Used for extended mnemonics for the trap
1283 instructions. */
1284#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1285#define OPTO_MASK (OP_MASK | TO_MASK)
1286
1287/* The main opcode combined with a comparison size bit in the L field
1288 of a D form or X form instruction. Used for extended mnemonics for
1289 the comparison instructions. */
1290#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1291#define OPL_MASK OPL (0x3f,1)
1292
1293/* An A form instruction. */
1294#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1295#define A_MASK A (0x3f, 0x1f, 1)
1296
1297/* An A_MASK with the FRB field fixed. */
1298#define AFRB_MASK (A_MASK | FRB_MASK)
1299
1300/* An A_MASK with the FRC field fixed. */
1301#define AFRC_MASK (A_MASK | FRC_MASK)
1302
1303/* An A_MASK with the FRA and FRC fields fixed. */
1304#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1305
702f0fb4
PB		 1306/* An AFRAFRC_MASK, but with L bit clear. */
1307#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1308
252b5132
RH		 1309/* A B form instruction. */
1310#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1311#define B_MASK B (0x3f, 1, 1)
1312
1313/* A B form instruction setting the BO field. */
1314#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1315#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1316
1317/* A BBO_MASK with the y bit of the BO field removed. This permits
1318 matching a conditional branch regardless of the setting of the y
94efba12 1319 bit. Similarly for the 'at' bits used for power4 branch hints. */
de866fcc 1320#define Y_MASK (((unsigned long) 1) << 21)
802a735e
AM		 1321#define AT1_MASK (((unsigned long) 3) << 21)
1322#define AT2_MASK (((unsigned long) 9) << 21)
1323#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1324#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1325
1326/* A B form instruction setting the BO field and the condition bits of
1327 the BI field. */
1328#define BBOCB(op, bo, cb, aa, lk) \
1329 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1330#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1331
1332/* A BBOCB_MASK with the y bit of the BO field removed. */
1333#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1334#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1335#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1336
1337/* A BBOYCB_MASK in which the BI field is fixed. */
1338#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1339#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 1340
23976049
EZ		 1341/* An Context form instruction. */
1342#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 1343#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 1344
1345/* An User Context form instruction. */
1346#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 1347#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 1348
252b5132
RH		 1349/* The main opcode mask with the RA field clear. */
1350#define DRA_MASK (OP_MASK | RA_MASK)
1351
1352/* A DS form instruction. */
1353#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1354#define DS_MASK DSO (0x3f, 3)
1355
418c1742
MG		 1356/* A DE form instruction. */
1357#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1358#define DE_MASK DEO (0x3e, 0xf)
1359
23976049
EZ		 1360/* An EVSEL form instruction. */
1361#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1362#define EVSEL_MASK EVSEL(0x3f, 0xff)
1363
252b5132
RH		 1364/* An M form instruction. */
1365#define M(op, rc) (OP (op) | ((rc) & 1))
1366#define M_MASK M (0x3f, 1)
1367
1368/* An M form instruction with the ME field specified. */
1369#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1370
1371/* An M_MASK with the MB and ME fields fixed. */
1372#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1373
1374/* An M_MASK with the SH and ME fields fixed. */
1375#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1376
1377/* An MD form instruction. */
1378#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1379#define MD_MASK MD (0x3f, 0x7, 1)
1380
1381/* An MD_MASK with the MB field fixed. */
1382#define MDMB_MASK (MD_MASK | MB6_MASK)
1383
1384/* An MD_MASK with the SH field fixed. */
1385#define MDSH_MASK (MD_MASK | SH6_MASK)
1386
1387/* An MDS form instruction. */
1388#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1389#define MDS_MASK MDS (0x3f, 0xf, 1)
1390
1391/* An MDS_MASK with the MB field fixed. */
1392#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1393
1394/* An SC form instruction. */
1395#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1396#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1397
112290ab 1398/* An VX form instruction. */
786e2c0f
C		 1399#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1400
112290ab 1401/* The mask for an VX form instruction. */
786e2c0f
C		 1402#define VX_MASK VX(0x3f, 0x7ff)
1403
112290ab 1404/* An VA form instruction. */
2613489e 1405#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 1406
112290ab 1407/* The mask for an VA form instruction. */
2613489e 1408#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 1409
112290ab 1410/* An VXR form instruction. */
786e2c0f
C		 1411#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1412
112290ab 1413/* The mask for a VXR form instruction. */
786e2c0f
C		 1414#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1415
252b5132
RH		 1416/* An X form instruction. */
1417#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1418
702f0fb4
PB		 1419/* A Z form instruction. */
1420#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1421
252b5132
RH		 1422/* An X form instruction with the RC bit specified. */
1423#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1424
702f0fb4
PB		 1425/* A Z form instruction with the RC bit specified. */
1426#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1427
252b5132
RH		 1428/* The mask for an X form instruction. */
1429#define X_MASK XRC (0x3f, 0x3ff, 1)
1430
702f0fb4
PB		 1431/* The mask for a Z form instruction. */
1432#define Z_MASK ZRC (0x3f, 0x1ff, 1)
0bbdef92 1433#define Z2_MASK ZRC (0x3f, 0xff, 1)
702f0fb4 1434
252b5132
RH		 1435/* An X_MASK with the RA field fixed. */
1436#define XRA_MASK (X_MASK | RA_MASK)
1437
ea192fa3
PB		 1438/* An XRA_MASK with the W field clear. */
1439#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1440
252b5132
RH		 1441/* An X_MASK with the RB field fixed. */
1442#define XRB_MASK (X_MASK | RB_MASK)
1443
1444/* An X_MASK with the RT field fixed. */
1445#define XRT_MASK (X_MASK | RT_MASK)
1446
702f0fb4
PB		 1447/* An XRT_MASK mask with the L bits clear. */
1448#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1449
252b5132
RH		 1450/* An X_MASK with the RA and RB fields fixed. */
1451#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1452
112290ab 1453/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 1454#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1455
252b5132
RH		 1456/* An X_MASK with the RT and RA fields fixed. */
1457#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1458
98acc1c5
AM		 1459/* An XRTRA_MASK, but with L bit clear. */
1460#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1461
f3806e43
BE		 1462/* An X form instruction with the L bit specified. */
1463#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132 1464
19a6653c
AM		 1465/* An X form instruction with RT fields specified */
1466#define XRT(op, xop, rt) (X ((op), (xop)) \
1467 | ((((unsigned long)(rt)) & 0x1f) << 21))
1468
1469/* An X form instruction with RT and RA fields specified */
1470#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
1471 | ((((unsigned long)(rt)) & 0x1f) << 21) \
1472 | ((((unsigned long)(ra)) & 0x1f) << 16))
1473
252b5132
RH		 1474/* The mask for an X form comparison instruction. */
1475#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1476
520ceea4
BE		 1477/* The mask for an X form comparison instruction with the L field
1478 fixed. */
1479#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 1480
1481/* An X form trap instruction with the TO field specified. */
1482#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1483#define XTO_MASK (X_MASK | TO_MASK)
1484
e0c21649
GK		 1485/* An X form tlb instruction with the SH field specified. */
1486#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1487#define XTLB_MASK (X_MASK | SH_MASK)
1488
6ba045b1
AM		 1489/* An X form sync instruction. */
1490#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1491
1492/* An X form sync instruction with everything filled in except the LS field. */
1493#define XSYNC_MASK (0xff9fffff)
1494
702f0fb4
PB		 1495/* An X_MASK, but with the EH bit clear. */
1496#define XEH_MASK (X_MASK & ~((unsigned long )1))
1497
f5c120c5
MG		 1498/* An X form AltiVec dss instruction. */
1499#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1500#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1501
252b5132
RH		 1502/* An XFL form instruction. */
1503#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ea192fa3 1504#define XFL_MASK XFL (0x3f, 0x3ff, 1)
252b5132 1505
23976049 1506/* An X form isel instruction. */
de866fcc
AM		 1507#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1508#define XISEL_MASK XISEL(0x3f, 0x1f)
23976049 1509
252b5132
RH		 1510/* An XL form instruction with the LK field set to 0. */
1511#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1512
1513/* An XL form instruction which uses the LK field. */
1514#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1515
1516/* The mask for an XL form instruction. */
1517#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1518
1519/* An XL form instruction which explicitly sets the BO field. */
1520#define XLO(op, bo, xop, lk) \
1521 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1522#define XLO_MASK (XL_MASK | BO_MASK)
1523
1524/* An XL form instruction which explicitly sets the y bit of the BO
1525 field. */
1526#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1527#define XLYLK_MASK (XL_MASK | Y_MASK)
1528
1529/* An XL form instruction which sets the BO field and the condition
1530 bits of the BI field. */
1531#define XLOCB(op, bo, cb, xop, lk) \
1532 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1533#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1534
1535/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1536#define XLBB_MASK (XL_MASK | BB_MASK)
1537#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1538#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1539
d0618d1c
AM		 1540/* A mask for branch instructions using the BH field. */
1541#define XLBH_MASK (XL_MASK | (0x1c << 11))
1542
252b5132
RH		 1543/* An XL_MASK with the BO and BB fields fixed. */
1544#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1545
1546/* An XL_MASK with the BO, BI and BB fields fixed. */
1547#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1548
1549/* An XO form instruction. */
1550#define XO(op, xop, oe, rc) \
1551 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1552#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1553
1554/* An XO_MASK with the RB field fixed. */
1555#define XORB_MASK (XO_MASK | RB_MASK)
1556
c3d65c1c
BE		 1557/* An XOPS form instruction for paired singles. */
1558#define XOPS(op, xop, rc) \
1559 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1560#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1561
1562
252b5132
RH		 1563/* An XS form instruction. */
1564#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1565#define XS_MASK XS (0x3f, 0x1ff, 1)
1566
1567/* A mask for the FXM version of an XFX form instruction. */
98e69875 1568#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 1569
1570/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 1571#define XFXM(op, xop, fxm, p4) \
1572 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1573 | ((unsigned long)(p4) << 20))
252b5132
RH		 1574
1575/* An XFX form instruction with the SPR field filled in. */
1576#define XSPR(op, xop, spr) \
1577 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1578#define XSPR_MASK (X_MASK | SPR_MASK)
1579
1580/* An XFX form instruction with the SPR field filled in except for the
1581 SPRBAT field. */
1582#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1583
1584/* An XFX form instruction with the SPR field filled in except for the
1585 SPRG field. */
b84bf58a 1586#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
252b5132
RH		 1587
1588/* An X form instruction with everything filled in except the E field. */
1589#define XE_MASK (0xffff7fff)
1590
23976049
EZ		 1591/* An X form user context instruction. */
1592#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1593#define XUC_MASK XUC(0x3f, 0x1f)
1594
c3d65c1c
BE		 1595/* An XW form instruction. */
1596#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1597/* The mask for a G form instruction. rc not supported at present. */
1598#define XW_MASK XW (0x3f, 0x3f, 0)
1599
252b5132
RH		 1600/* The BO encodings used in extended conditional branch mnemonics. */
1601#define BODNZF (0x0)
1602#define BODNZFP (0x1)
1603#define BODZF (0x2)
1604#define BODZFP (0x3)
252b5132
RH		 1605#define BODNZT (0x8)
1606#define BODNZTP (0x9)
1607#define BODZT (0xa)
1608#define BODZTP (0xb)
802a735e
AM		 1609
1610#define BOF (0x4)
1611#define BOFP (0x5)
94efba12
AM		 1612#define BOFM4 (0x6)
1613#define BOFP4 (0x7)
252b5132
RH		 1614#define BOT (0xc)
1615#define BOTP (0xd)
94efba12
AM		 1616#define BOTM4 (0xe)
1617#define BOTP4 (0xf)
802a735e 1618
252b5132
RH		 1619#define BODNZ (0x10)
1620#define BODNZP (0x11)
1621#define BODZ (0x12)
1622#define BODZP (0x13)
94efba12
AM		 1623#define BODNZM4 (0x18)
1624#define BODNZP4 (0x19)
1625#define BODZM4 (0x1a)
1626#define BODZP4 (0x1b)
802a735e 1627
252b5132
RH		 1628#define BOU (0x14)
1629
1630/* The BI condition bit encodings used in extended conditional branch
1631 mnemonics. */
1632#define CBLT (0)
1633#define CBGT (1)
1634#define CBEQ (2)
1635#define CBSO (3)
1636
1637/* The TO encodings used in extended trap mnemonics. */
1638#define TOLGT (0x1)
1639#define TOLLT (0x2)
1640#define TOEQ (0x4)
1641#define TOLGE (0x5)
1642#define TOLNL (0x5)
1643#define TOLLE (0x6)
1644#define TOLNG (0x6)
1645#define TOGT (0x8)
1646#define TOGE (0xc)
1647#define TONL (0xc)
1648#define TOLT (0x10)
1649#define TOLE (0x14)
1650#define TONG (0x14)
1651#define TONE (0x18)
1652#define TOU (0x1f)
1653\f
1654/* Smaller names for the flags so each entry in the opcodes table will
1655 fit on a single line. */
1656#undef PPC
de866fcc 1657#define PPC PPC_OPCODE_PPC
661bd698 1658#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
94efba12 1659#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
661bd698 1660#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 1661#define POWER5 PPC_OPCODE_POWER5
702f0fb4 1662#define POWER6 PPC_OPCODE_POWER6
ede602d7 1663#define CELL PPC_OPCODE_CELL
de866fcc
AM		 1664#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1665#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
418c1742 1666#define PPC403 PPC_OPCODE_403
e0c21649 1667#define PPC405 PPC403
7d5b217e 1668#define PPC440 PPC_OPCODE_440
252b5132 1669#define PPC750 PPC
33e8d5ac 1670#define PPC7450 PPC
252b5132 1671#define PPC860 PPC
c3d65c1c 1672#define PPCPS PPC_OPCODE_PPCPS
a404d431 1673#define PPCVEC PPC_OPCODE_ALTIVEC
de866fcc
AM		 1674#define POWER PPC_OPCODE_POWER
1675#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1676#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1677#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1678#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1679#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1680#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
661bd698 1681#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
de866fcc
AM		 1682#define MFDEC1 PPC_OPCODE_POWER
1683#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
418c1742 1684#define BOOKE PPC_OPCODE_BOOKE
de866fcc
AM		 1685#define BOOKE64 PPC_OPCODE_BOOKE64
1686#define CLASSIC PPC_OPCODE_CLASSIC
36ae0db3 1687#define PPCE300 PPC_OPCODE_E300
23976049 1688#define PPCSPE PPC_OPCODE_SPE
de866fcc 1689#define PPCISEL PPC_OPCODE_ISEL
23976049 1690#define PPCEFS PPC_OPCODE_EFS
de866fcc 1691#define PPCBRLK PPC_OPCODE_BRLOCK
23976049 1692#define PPCPMR PPC_OPCODE_PMR
de866fcc 1693#define PPCCHLK PPC_OPCODE_CACHELCK
dde1b132 1694#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
23976049 1695#define PPCRFMCI PPC_OPCODE_RFMCI
19a6653c 1696#define E500MC PPC_OPCODE_E500MC
252b5132
RH		 1697\f
1698/* The opcode table.
1699
1700 The format of the opcode table is:
1701
de866fcc 1702 NAME OPCODE MASK FLAGS {OPERANDS}
252b5132
RH		 1703
1704 NAME is the name of the instruction.
1705 OPCODE is the instruction opcode.
1706 MASK is the opcode mask; this is used to tell the disassembler
1707 which bits in the actual opcode must match OPCODE.
1708 FLAGS are flags indicated what processors support the instruction.
1709 OPERANDS is the list of operands.
1710
1711 The disassembler reads the table in order and prints the first
1712 instruction which matches, so this table is sorted to put more
de866fcc
AM		 1713 specific instructions before more general instructions.
1714
1715 This table must be sorted by major opcode. Please try to keep it
1716 vaguely sorted within major opcode too, except of course where
1717 constrained otherwise by disassembler operation. */
252b5132
RH		 1718
1719const struct powerpc_opcode powerpc_opcodes[] = {
de866fcc
AM		 1720{"attn", X(0,256), X_MASK, POWER4, {0}},
1721{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, {RA, SI}},
1722{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, {RA, SI}},
1723{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, {RA, SI}},
1724{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, {RA, SI}},
1725{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, {RA, SI}},
1726{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, {RA, SI}},
1727{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, {RA, SI}},
1728{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, {RA, SI}},
1729{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, {RA, SI}},
1730{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, {RA, SI}},
1731{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, {RA, SI}},
1732{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, {RA, SI}},
1733{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, {RA, SI}},
1734{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, {RA, SI}},
1735{"tdi", OP(2), OP_MASK, PPC64, {TO, RA, SI}},
1736
1737{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, {RA, SI}},
1738{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, {RA, SI}},
1739{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, {RA, SI}},
1740{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, {RA, SI}},
1741{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, {RA, SI}},
1742{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, {RA, SI}},
1743{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, {RA, SI}},
1744{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, {RA, SI}},
1745{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, {RA, SI}},
1746{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, {RA, SI}},
1747{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, {RA, SI}},
1748{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, {RA, SI}},
1749{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, {RA, SI}},
1750{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, {RA, SI}},
1751{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, {RA, SI}},
1752{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, {RA, SI}},
1753{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, {RA, SI}},
1754{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, {RA, SI}},
1755{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, {RA, SI}},
1756{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, {RA, SI}},
1757{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, {RA, SI}},
1758{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, {RA, SI}},
1759{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, {RA, SI}},
1760{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, {RA, SI}},
1761{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, {RA, SI}},
1762{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, {RA, SI}},
1763{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, {RA, SI}},
1764{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, {RA, SI}},
1765{"twi", OP(3), OP_MASK, PPCCOM, {TO, RA, SI}},
1766{"ti", OP(3), OP_MASK, PWRCOM, {TO, RA, SI}},
1767
1768{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
1769{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, {VD, VA, VB}},
1770{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, {VD, VA, VB}},
1771{"vrlb", VX (4, 4), VX_MASK, PPCVEC, {VD, VA, VB}},
1772{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1773{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, {VD, VA, VB}},
1774{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, {VD, VA, VB}},
1775{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}},
1776{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, {VD, VA, VB}},
1777{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}},
1778{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, {VD, VA, VB}},
1779{"mulhhwu", XRC(4, 8,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1780{"mulhhwu.", XRC(4, 8,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1781{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1782{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1783{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1784{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1785{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1786{"machhwu", XO (4, 12,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1787{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1788{"machhwu.", XO (4, 12,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1789{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1790{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1791{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1792{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1793{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1794{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1795{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1796{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1797{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1798{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1799{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1800{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1801{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1802{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1803{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1804{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1805{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1806{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1807{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1808{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1809{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1810{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}},
1811{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
1812{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, {VD, VA, VB, SHB}},
1813{"ps_sel", A (4, 23,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1814{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, {VD, VA, VC, VB}},
1815{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1816{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, {VD, VA, VC, VB}},
1817{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
1818{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
1819{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1820{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}},
1821{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
1822{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}},
1823{"ps_msub", A (4, 28,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1824{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1825{"ps_madd", A (4, 29,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1826{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1827{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1828{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1829{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1830{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
1831{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
1832{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, {VD, VA, VB}},
1833{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, {VD, VA, VB}},
1834{"vrlh", VX (4, 68), VX_MASK, PPCVEC, {VD, VA, VB}},
1835{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1836{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, {VD, VA, VB}},
1837{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, {VD, VA, VB}},
1838{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}},
1839{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, {VD, VA, VB}},
1840{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}},
1841{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, {VD, VA, VB}},
1842{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, {FRT, FRB}},
1843{"mulhhw", XRC(4, 40,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1844{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, {FRT, FRB}},
1845{"mulhhw.", XRC(4, 40,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1846{"machhw", XO (4, 44,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1847{"machhw.", XO (4, 44,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1848{"nmachhw", XO (4, 46,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1849{"nmachhw.", XO (4, 46,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1850{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
1851{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, {VD, VA, VB}},
1852{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, {VD, VA, VB}},
1853{"vrlw", VX (4, 132), VX_MASK, PPCVEC, {VD, VA, VB}},
1854{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1855{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, {VD, VA, VB}},
1856{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, {VD, VA, VB}},
1857{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, {FRT, FRB}},
1858{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, {FRT, FRB}},
1859{"machhwsu", XO (4, 76,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1860{"machhwsu.", XO (4, 76,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1861{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}},
1862{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1863{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, {VD, VA, VB}},
1864{"machhws", XO (4, 108,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1865{"machhws.", XO (4, 108,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1866{"nmachhws", XO (4, 110,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1867{"nmachhws.", XO (4, 110,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1868{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, {VD, VA, VB}},
1869{"vslb", VX (4, 260), VX_MASK, PPCVEC, {VD, VA, VB}},
1870{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, {VD, VA, VB}},
1871{"vrefp", VX (4, 266), VX_MASK, PPCVEC, {VD, VB}},
1872{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, {VD, VA, VB}},
1873{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, {VD, VA, VB}},
1874{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, {FRT, FRB}},
1875{"mulchwu", XRC(4, 136,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1876{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, {FRT, FRB}},
1877{"mulchwu.", XRC(4, 136,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1878{"macchwu", XO (4, 140,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1879{"macchwu.", XO (4, 140,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1880{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, {VD, VA, VB}},
1881{"vslh", VX (4, 324), VX_MASK, PPCVEC, {VD, VA, VB}},
1882{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, {VD, VA, VB}},
1883{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, {VD, VB}},
1884{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, {VD, VA, VB}},
1885{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, {VD, VA, VB}},
1886{"mulchw", XRC(4, 168,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1887{"mulchw.", XRC(4, 168,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
1888{"macchw", XO (4, 172,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1889{"macchw.", XO (4, 172,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1890{"nmacchw", XO (4, 174,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1891{"nmacchw.", XO (4, 174,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1892{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, {VD, VA, VB}},
1893{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, {VD, VA, VB}},
1894{"vslw", VX (4, 388), VX_MASK, PPCVEC, {VD, VA, VB}},
1895{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, {VD, VB}},
1896{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, {VD, VA, VB}},
1897{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, {VD, VA, VB}},
1898{"macchwsu", XO (4, 204,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1899{"macchwsu.", XO (4, 204,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1900{"vsl", VX (4, 452), VX_MASK, PPCVEC, {VD, VA, VB}},
1901{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1902{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, {VD, VB}},
1903{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, {VD, VA, VB}},
1904{"macchws", XO (4, 236,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1905{"macchws.", XO (4, 236,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1906{"nmacchws", XO (4, 238,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1907{"nmacchws.", XO (4, 238,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
1908{"evaddw", VX (4, 512), VX_MASK, PPCSPE, {RS, RA, RB}},
1909{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, {VD, VA, VB}},
1910{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, {RS, RB, UIMM}},
1911{"vminub", VX (4, 514), VX_MASK, PPCVEC, {VD, VA, VB}},
1912{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, {RS, RA, RB}},
1913{"evsubw", VX (4, 516), VX_MASK, PPCSPE, {RS, RB, RA}},
1914{"vsrb", VX (4, 516), VX_MASK, PPCVEC, {VD, VA, VB}},
1915{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, {RS, UIMM, RB}},
1916{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, {RS, RB, UIMM}},
1917{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1918{"evabs", VX (4, 520), VX_MASK, PPCSPE, {RS, RA}},
1919{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, {VD, VA, VB}},
1920{"evneg", VX (4, 521), VX_MASK, PPCSPE, {RS, RA}},
1921{"evextsb", VX (4, 522), VX_MASK, PPCSPE, {RS, RA}},
1922{"vrfin", VX (4, 522), VX_MASK, PPCVEC, {VD, VB}},
1923{"evextsh", VX (4, 523), VX_MASK, PPCSPE, {RS, RA}},
1924{"evrndw", VX (4, 524), VX_MASK, PPCSPE, {RS, RA}},
1925{"vspltb", VX (4, 524), VX_MASK, PPCVEC, {VD, VB, UIMM}},
1926{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, {RS, RA}},
1927{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, {RS, RA}},
1928{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, {VD, VB}},
1929{"brinc", VX (4, 527), VX_MASK, PPCSPE, {RS, RA, RB}},
1930{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, {FRT, FRB}},
1931{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, {FRT, FRB}},
1932{"evand", VX (4, 529), VX_MASK, PPCSPE, {RS, RA, RB}},
1933{"evandc", VX (4, 530), VX_MASK, PPCSPE, {RS, RA, RB}},
1934{"evxor", VX (4, 534), VX_MASK, PPCSPE, {RS, RA, RB}},
1935{"evmr", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, BBA}},
1936{"evor", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, RB}},
1937{"evnor", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, RB}},
1938{"evnot", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, BBA}},
1939{"eveqv", VX (4, 537), VX_MASK, PPCSPE, {RS, RA, RB}},
1940{"evorc", VX (4, 539), VX_MASK, PPCSPE, {RS, RA, RB}},
1941{"evnand", VX (4, 542), VX_MASK, PPCSPE, {RS, RA, RB}},
1942{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, {RS, RA, RB}},
1943{"evsrws", VX (4, 545), VX_MASK, PPCSPE, {RS, RA, RB}},
1944{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
1945{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
1946{"evslw", VX (4, 548), VX_MASK, PPCSPE, {RS, RA, RB}},
1947{"evslwi", VX (4, 550), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
1948{"evrlw", VX (4, 552), VX_MASK, PPCSPE, {RS, RA, RB}},
1949{"evsplati", VX (4, 553), VX_MASK, PPCSPE, {RS, SIMM}},
1950{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
1951{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, {RS, SIMM}},
1952{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, {RS, RA, RB}},
1953{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, {RS, RA, RB}},
1954{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, {RS, RA, RB}},
1955{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, {RS, RA, RB}},
1956{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1957{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1958{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1959{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1960{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1961{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, {VD, VA, VB}},
1962{"vminuh", VX (4, 578), VX_MASK, PPCVEC, {VD, VA, VB}},
1963{"vsrh", VX (4, 580), VX_MASK, PPCVEC, {VD, VA, VB}},
1964{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1965{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, {VD, VA, VB}},
1966{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, {VD, VB}},
1967{"vsplth", VX (4, 588), VX_MASK, PPCVEC, {VD, VB, UIMM}},
1968{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, {VD, VB}},
1969{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, {RS, RA, RB, CRFS}},
1970{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, {RS, RA, RB}},
1971{"vadduws", VX (4, 640), VX_MASK, PPCVEC, {VD, VA, VB}},
1972{"evfssub", VX (4, 641), VX_MASK, PPCSPE, {RS, RA, RB}},
1973{"vminuw", VX (4, 642), VX_MASK, PPCVEC, {VD, VA, VB}},
1974{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, {RS, RA}},
1975{"vsrw", VX (4, 644), VX_MASK, PPCVEC, {VD, VA, VB}},
1976{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, {RS, RA}},
1977{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, {RS, RA}},
1978{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
1979{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, {RS, RA, RB}},
1980{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, {RS, RA, RB}},
1981{"vrfip", VX (4, 650), VX_MASK, PPCVEC, {VD, VB}},
1982{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1983{"vspltw", VX (4, 652), VX_MASK, PPCVEC, {VD, VB, UIMM}},
1984{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1985{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1986{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, {VD, VB}},
1987{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, {RS, RB}},
1988{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, {RS, RB}},
1989{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, {RS, RB}},
1990{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, {RS, RB}},
1991{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, {RS, RB}},
1992{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, {RS, RB}},
1993{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, {RS, RB}},
1994{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, {RS, RB}},
1995{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, {RS, RB}},
1996{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, {RS, RB}},
1997{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1998{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, {CRFD, RA, RB}},
1999{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, {CRFD, RA, RB}},
2000{"efsadd", VX (4, 704), VX_MASK, PPCEFS, {RS, RA, RB}},
2001{"efssub", VX (4, 705), VX_MASK, PPCEFS, {RS, RA, RB}},
2002{"efsabs", VX (4, 708), VX_MASK, PPCEFS, {RS, RA}},
2003{"vsr", VX (4, 708), VX_MASK, PPCVEC, {VD, VA, VB}},
2004{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, {RS, RA}},
2005{"efsneg", VX (4, 710), VX_MASK, PPCEFS, {RS, RA}},
2006{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
2007{"efsmul", VX (4, 712), VX_MASK, PPCEFS, {RS, RA, RB}},
2008{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, {RS, RA, RB}},
2009{"vrfim", VX (4, 714), VX_MASK, PPCVEC, {VD, VB}},
2010{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2011{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2012{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2013{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, {VD, VB}},
2014{"efscfd", VX (4, 719), VX_MASK, PPCEFS, {RS, RB}},
2015{"efscfui", VX (4, 720), VX_MASK, PPCEFS, {RS, RB}},
2016{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, {RS, RB}},
2017{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, {RS, RB}},
2018{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, {RS, RB}},
2019{"efsctui", VX (4, 724), VX_MASK, PPCEFS, {RS, RB}},
2020{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, {RS, RB}},
2021{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, {RS, RB}},
2022{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, {RS, RB}},
2023{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, {RS, RB}},
2024{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, {RS, RB}},
2025{"efststgt", VX (4, 732), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2026{"efststlt", VX (4, 733), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2027{"efststeq", VX (4, 734), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2028{"efdadd", VX (4, 736), VX_MASK, PPCEFS, {RS, RA, RB}},
2029{"efdsub", VX (4, 737), VX_MASK, PPCEFS, {RS, RA, RB}},
2030{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, {RS, RB}},
2031{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, {RS, RB}},
2032{"efdabs", VX (4, 740), VX_MASK, PPCEFS, {RS, RA}},
2033{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, {RS, RA}},
2034{"efdneg", VX (4, 742), VX_MASK, PPCEFS, {RS, RA}},
2035{"efdmul", VX (4, 744), VX_MASK, PPCEFS, {RS, RA, RB}},
2036{"efddiv", VX (4, 745), VX_MASK, PPCEFS, {RS, RA, RB}},
2037{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, {RS, RB}},
2038{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, {RS, RB}},
2039{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2040{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2041{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2042{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, {RS, RB}},
2043{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, {RS, RB}},
2044{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, {RS, RB}},
2045{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, {RS, RB}},
2046{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, {RS, RB}},
2047{"efdctui", VX (4, 756), VX_MASK, PPCEFS, {RS, RB}},
2048{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, {RS, RB}},
2049{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, {RS, RB}},
2050{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, {RS, RB}},
2051{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, {RS, RB}},
2052{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, {RS, RB}},
2053{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2054{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2055{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, {CRFD, RA, RB}},
2056{"evlddx", VX (4, 768), VX_MASK, PPCSPE, {RS, RA, RB}},
2057{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, {VD, VA, VB}},
2058{"evldd", VX (4, 769), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2059{"evldwx", VX (4, 770), VX_MASK, PPCSPE, {RS, RA, RB}},
2060{"vminsb", VX (4, 770), VX_MASK, PPCVEC, {VD, VA, VB}},
2061{"evldw", VX (4, 771), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2062{"evldhx", VX (4, 772), VX_MASK, PPCSPE, {RS, RA, RB}},
2063{"vsrab", VX (4, 772), VX_MASK, PPCVEC, {VD, VA, VB}},
2064{"evldh", VX (4, 773), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2065{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
2066{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, {RS, RA, RB}},
2067{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, {VD, VA, VB}},
2068{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
2069{"vcfux", VX (4, 778), VX_MASK, PPCVEC, {VD, VB, UIMM}},
2070{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, {RS, RA, RB}},
2071{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, {VD, SIMM}},
2072{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
2073{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, {RS, RA, RB}},
2074{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, {VD, VA, VB}},
2075{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
2076{"mullhwu", XRC(4, 392,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
2077{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, {RS, RA, RB}},
2078{"mullhwu.", XRC(4, 392,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
2079{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2080{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, {RS, RA, RB}},
2081{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2082{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, {RS, RA, RB}},
2083{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2084{"maclhwu", XO (4, 396,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2085{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, {RS, RA, RB}},
2086{"maclhwu.", XO (4, 396,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2087{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2088{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, {RS, RA, RB}},
2089{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2090{"evstddx", VX (4, 800), VX_MASK, PPCSPE, {RS, RA, RB}},
2091{"evstdd", VX (4, 801), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2092{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, {RS, RA, RB}},
2093{"evstdw", VX (4, 803), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2094{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, {RS, RA, RB}},
2095{"evstdh", VX (4, 805), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
2096{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, {RS, RA, RB}},
2097{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2098{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, {RS, RA, RB}},
2099{"evstwho", VX (4, 821), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2100{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, {RS, RA, RB}},
2101{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2102{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, {RS, RA, RB}},
2103{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
2104{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, {VD, VA, VB}},
2105{"vminsh", VX (4, 834), VX_MASK, PPCVEC, {VD, VA, VB}},
2106{"vsrah", VX (4, 836), VX_MASK, PPCVEC, {VD, VA, VB}},
2107{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
2108{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, {VD, VA, VB}},
2109{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, {VD, VB, UIMM}},
2110{"vspltish", VX (4, 844), VX_MASK, PPCVEC, {VD, SIMM}},
2111{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, {VD, VB}},
2112{"mullhw", XRC(4, 424,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
2113{"mullhw.", XRC(4, 424,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
2114{"maclhw", XO (4, 428,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2115{"maclhw.", XO (4, 428,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2116{"nmaclhw", XO (4, 430,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2117{"nmaclhw.", XO (4, 430,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2118{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, {VD, VA, VB}},
2119{"vminsw", VX (4, 898), VX_MASK, PPCVEC, {VD, VA, VB}},
2120{"vsraw", VX (4, 900), VX_MASK, PPCVEC, {VD, VA, VB}},
2121{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
2122{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, {VD, VB, UIMM}},
2123{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, {VD, SIMM}},
2124{"maclhwsu", XO (4, 460,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2125{"maclhwsu.", XO (4, 460,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2126{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
2127{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, {VD, VB, UIMM}},
2128{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, {VD, VB}},
2129{"maclhws", XO (4, 492,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2130{"maclhws.", XO (4, 492,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2131{"nmaclhws", XO (4, 494,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2132{"nmaclhws.", XO (4, 494,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2133{"vsububm", VX (4,1024), VX_MASK, PPCVEC, {VD, VA, VB}},
2134{"vavgub", VX (4,1026), VX_MASK, PPCVEC, {VD, VA, VB}},
2135{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, {RS, RA, RB}},
2136{"vand", VX (4,1028), VX_MASK, PPCVEC, {VD, VA, VB}},
2137{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2138{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, {RS, RA, RB}},
2139{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, {RS, RA, RB}},
2140{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, {RS, RA, RB}},
2141{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, {VD, VA, VB}},
2142{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, {RS, RA, RB}},
2143{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, {RS, RA, RB}},
2144{"vslo", VX (4,1036), VX_MASK, PPCVEC, {VD, VA, VB}},
2145{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, {RS, RA, RB}},
2146{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, {RS, RA, RB}},
2147{"machhwuo", XO (4, 12,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2148{"machhwuo.", XO (4, 12,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2149{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2150{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2151{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, {RS, RA, RB}},
2152{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, {RS, RA, RB}},
2153{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, {RS, RA, RB}},
2154{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, {RS, RA, RB}},
2155{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, {RS, RA, RB}},
2156{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, {RS, RA, RB}},
2157{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, {RS, RA, RB}},
2158{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, {RS, RA, RB}},
2159{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, {VD, VA, VB}},
2160{"vavguh", VX (4,1090), VX_MASK, PPCVEC, {VD, VA, VB}},
2161{"vandc", VX (4,1092), VX_MASK, PPCVEC, {VD, VA, VB}},
2162{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2163{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, {RS, RA, RB}},
2164{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, {RS, RA, RB}},
2165{"vminfp", VX (4,1098), VX_MASK, PPCVEC, {VD, VA, VB}},
2166{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, {RS, RA, RB}},
2167{"vsro", VX (4,1100), VX_MASK, PPCVEC, {VD, VA, VB}},
2168{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, {RS, RA, RB}},
2169{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, {RS, RA, RB}},
2170{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, {RS, RA, RB}},
2171{"machhwo", XO (4, 44,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2172{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, {RS, RA, RB}},
2173{"machhwo.", XO (4, 44,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2174{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, {RS, RA, RB}},
2175{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, {RS, RA, RB}},
2176{"nmachhwo", XO (4, 46,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2177{"nmachhwo.", XO (4, 46,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2178{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2179{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2180{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, {RS, RA, RB}},
2181{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, {RS, RA, RB}},
2182{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, {RS, RA, RB}},
2183{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, {RS, RA, RB}},
2184{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, {RS, RA, RB}},
2185{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, {RS, RA, RB}},
2186{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, {RS, RA, RB}},
2187{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, {RS, RA, RB}},
2188{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, {RS, RA, RB}},
2189{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, {VD, VA, VB}},
2190{"vavguw", VX (4,1154), VX_MASK, PPCVEC, {VD, VA, VB}},
2191{"vor", VX (4,1156), VX_MASK, PPCVEC, {VD, VA, VB}},
2192{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2193{"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2194{"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2195{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2196{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2197{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, {RS, RA}},
2198{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, {RS, RA}},
2199{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, {RS, RA}},
2200{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, {RS, RA}},
2201{"evmra", VX (4,1220), VX_MASK, PPCSPE, {RS, RA}},
2202{"vxor", VX (4,1220), VX_MASK, PPCVEC, {VD, VA, VB}},
2203{"evdivws", VX (4,1222), VX_MASK, PPCSPE, {RS, RA, RB}},
2204{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2205{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, {RS, RA, RB}},
2206{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, {RS, RA}},
2207{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, {RS, RA}},
2208{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, {RS, RA}},
2209{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, {RS, RA}},
2210{"machhwso", XO (4, 108,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2211{"machhwso.", XO (4, 108,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2212{"nmachhwso", XO (4, 110,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2213{"nmachhwso.", XO (4, 110,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2214{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2215{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
2216{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, {RS, RA, RB}},
2217{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, {RS, RA, RB}},
2218{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, {VD, VA, VB}},
2219{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, {RS, RA, RB}},
2220{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, {RS, RA, RB}},
2221{"vnor", VX (4,1284), VX_MASK, PPCVEC, {VD, VA, VB}},
2222{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, {RS, RA, RB}},
2223{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, {RS, RA, RB}},
2224{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, {RS, RA, RB}},
2225{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, {RS, RA, RB}},
2226{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, {RS, RA, RB}},
2227{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, {RS, RA, RB}},
2228{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, {RS, RA, RB}},
2229{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, {RS, RA, RB}},
2230{"macchwuo", XO (4, 140,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2231{"macchwuo.", XO (4, 140,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2232{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, {RS, RA, RB}},
2233{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, {RS, RA, RB}},
2234{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, {RS, RA, RB}},
2235{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, {RS, RA, RB}},
2236{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, {RS, RA, RB}},
2237{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, {RS, RA, RB}},
2238{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, {RS, RA, RB}},
2239{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, {RS, RA, RB}},
2240{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, {VD, VA, VB}},
2241{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, {RS, RA, RB}},
2242{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, {RS, RA, RB}},
2243{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, {RS, RA, RB}},
2244{"macchwo", XO (4, 172,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2245{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, {RS, RA, RB}},
2246{"macchwo.", XO (4, 172,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2247{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, {RS, RA, RB}},
2248{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, {RS, RA, RB}},
2249{"nmacchwo", XO (4, 174,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2250{"nmacchwo.", XO (4, 174,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2251{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, {RS, RA, RB}},
2252{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, {VD, VA, VB}},
2253{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, {RS, RA, RB}},
2254{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, {VD, VA, VB}},
2255{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, {RS, RA, RB}},
2256{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, {RS, RA, RB}},
2257{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, {RS, RA, RB}},
2258{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, {RS, RA, RB}},
2259{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, {RS, RA, RB}},
2260{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, {RS, RA, RB}},
2261{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, {RS, RA, RB}},
2262{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, {RS, RA, RB}},
2263{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, {RS, RA, RB}},
2264{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, {RS, RA, RB}},
2265{"macchwsuo", XO (4, 204,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2266{"macchwsuo.", XO (4, 204,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2267{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, {RS, RA, RB}},
2268{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, {RS, RA, RB}},
2269{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, {RS, RA, RB}},
2270{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, {RS, RA, RB}},
2271{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, {RS, RA, RB}},
2272{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, {RS, RA, RB}},
2273{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, {RS, RA, RB}},
2274{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, {RS, RA, RB}},
2275{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2276{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, {RS, RA, RB}},
2277{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, {RS, RA, RB}},
2278{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, {RS, RA, RB}},
2279{"macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2280{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, {RS, RA, RB}},
2281{"macchwso.", XO (4, 236,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2282{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, {RS, RA, RB}},
2283{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, {RS, RA, RB}},
2284{"nmacchwso", XO (4, 238,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2285{"nmacchwso.", XO (4, 238,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2286{"vsububs", VX (4,1536), VX_MASK, PPCVEC, {VD, VA, VB}},
2287{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, {VD}},
2288{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2289{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, {VD, VA, VB}},
2290{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, {VD, VA, VB}},
2291{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, {VB}},
2292{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2293{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, {VD, VA, VB}},
2294{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, {VD, VA, VB}},
2295{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2296{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, {VD, VA, VB}},
2297{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2298{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, {VD, VA, VB}},
2299{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2300{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, {VD, VA, VB}},
2301{"maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2302{"maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2303{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, {VD, VA, VB}},
2304{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2305{"maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2306{"maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2307{"nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2308{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2309{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, {VD, VA, VB}},
2310{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2311{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, {VD, VA, VB}},
2312{"maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2313{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2314{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
2315{"maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2316{"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2317{"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2318{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
2319{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, {RA, RB}},
2320
2321{"mulli", OP(7), OP_MASK, PPCCOM, {RT, RA, SI}},
2322{"muli", OP(7), OP_MASK, PWRCOM, {RT, RA, SI}},
2323
2324{"subfic", OP(8), OP_MASK, PPCCOM, {RT, RA, SI}},
2325{"sfi", OP(8), OP_MASK, PWRCOM, {RT, RA, SI}},
2326
2327{"dozi", OP(9), OP_MASK, M601, {RT, RA, SI}},
2328
2329{"bce", B(9,0,0), B_MASK, BOOKE64, {BO, BI, BD}},
2330{"bcel", B(9,0,1), B_MASK, BOOKE64, {BO, BI, BD}},
2331{"bcea", B(9,1,0), B_MASK, BOOKE64, {BO, BI, BDA}},
2332{"bcela", B(9,1,1), B_MASK, BOOKE64, {BO, BI, BDA}},
2333
2334{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, {OBF, RA, UI}},
2335{"cmpldi", OPL(10,1), OPL_MASK, PPC64, {OBF, RA, UI}},
2336{"cmpli", OP(10), OP_MASK, PPC, {BF, L, RA, UI}},
2337{"cmpli", OP(10), OP_MASK, PWRCOM, {BF, RA, UI}},
2338
2339{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, {OBF, RA, SI}},
2340{"cmpdi", OPL(11,1), OPL_MASK, PPC64, {OBF, RA, SI}},
2341{"cmpi", OP(11), OP_MASK, PPC, {BF, L, RA, SI}},
2342{"cmpi", OP(11), OP_MASK, PWRCOM, {BF, RA, SI}},
2343
2344{"addic", OP(12), OP_MASK, PPCCOM, {RT, RA, SI}},
2345{"ai", OP(12), OP_MASK, PWRCOM, {RT, RA, SI}},
2346{"subic", OP(12), OP_MASK, PPCCOM, {RT, RA, NSI}},
2347
2348{"addic.", OP(13), OP_MASK, PPCCOM, {RT, RA, SI}},
2349{"ai.", OP(13), OP_MASK, PWRCOM, {RT, RA, SI}},
2350{"subic.", OP(13), OP_MASK, PPCCOM, {RT, RA, NSI}},
2351
2352{"li", OP(14), DRA_MASK, PPCCOM, {RT, SI}},
2353{"lil", OP(14), DRA_MASK, PWRCOM, {RT, SI}},
2354{"addi", OP(14), OP_MASK, PPCCOM, {RT, RA0, SI}},
2355{"cal", OP(14), OP_MASK, PWRCOM, {RT, D, RA0}},
2356{"subi", OP(14), OP_MASK, PPCCOM, {RT, RA0, NSI}},
2357{"la", OP(14), OP_MASK, PPCCOM, {RT, D, RA0}},
2358
2359{"lis", OP(15), DRA_MASK, PPCCOM, {RT, SISIGNOPT}},
2360{"liu", OP(15), DRA_MASK, PWRCOM, {RT, SISIGNOPT}},
2361{"addis", OP(15), OP_MASK, PPCCOM, {RT, RA0, SISIGNOPT}},
2362{"cau", OP(15), OP_MASK, PWRCOM, {RT, RA0, SISIGNOPT}},
2363{"subis", OP(15), OP_MASK, PPCCOM, {RT, RA0, NSI}},
2364
2365{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}},
2366{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}},
2367{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BD}},
2368{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, {BD}},
2369{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}},
2370{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}},
2371{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BD}},
2372{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, {BD}},
2373{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}},
2374{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}},
2375{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDA}},
2376{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, {BDA}},
2377{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}},
2378{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}},
2379{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDA}},
2380{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, {BDA}},
2381{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}},
2382{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}},
2383{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, {BD}},
2384{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}},
2385{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}},
2386{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, {BD}},
2387{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}},
2388{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}},
2389{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, {BDA}},
2390{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}},
2391{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}},
2392{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, {BDA}},
2393
2394{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2395{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2396{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2397{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2398{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2399{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2400{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2401{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2402{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2403{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2404{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2405{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2406{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2407{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2408{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2409{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2410{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2411{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2412{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2413{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2414{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2415{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2416{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2417{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2418{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2419{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2420{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2421{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2422{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2423{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2424{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2425{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2426{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2427{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2428{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2429{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2430{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2431{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2432{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2433{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2434{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2435{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2436{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2437{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2438{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2439{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2440{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2441{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2442{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2443{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2444{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}},
2445{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2446{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2447{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}},
2448{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2449{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2450{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2451{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2452{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2453{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2454{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2455{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2456{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}},
2457{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2458{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2459{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}},
2460{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2461{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2462{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}},
2463{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2464{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2465{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}},
2466{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2467{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2468{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2469{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2470{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2471{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}},
2472{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2473{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2474{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2475{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2476{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2477{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}},
2478
2479{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2480{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2481{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2482{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2483{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2484{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2485{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2486{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2487{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2488{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2489{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2490{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2491{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2492{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2493{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}},
2494{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2495{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2496{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}},
2497{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2498{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2499{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2500{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2501{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2502{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2503{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2504{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2505{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}},
2506{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2507{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2508{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}},
2509{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2510{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2511{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2512{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2513{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2514{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2515{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2516{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2517{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}},
2518{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2519{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2520{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}},
2521{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2522{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2523{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}},
2524{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
2525{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
2526{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}},
2527{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2528{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2529{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}},
2530{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2531{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2532{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}},
2533{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2534{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2535{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}},
2536{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
2537{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
2538{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}},
2539
2540{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
2541{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
2542{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
2543{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
2544{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
2545{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
2546{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2547{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2548{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
2549{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2550{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2551{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
2552{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
2553{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
2554{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
2555{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
2556{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
2557{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
2558{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2559{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2560{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
2561{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2562{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2563{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
2564
2565{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}},
2566{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}},
2567{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BD}},
2568{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, {BI, BD}},
2569{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}},
2570{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}},
2571{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BD}},
2572{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, {BI, BD}},
2573{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}},
2574{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}},
2575{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}},
2576{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}},
2577{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}},
2578{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}},
2579{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}},
2580{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}},
2581
2582{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
2583{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
2584{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
2585{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
2586{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
2587{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
2588{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2589{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2590{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
2591{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2592{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2593{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
2594{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
2595{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
2596{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
2597{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
2598{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
2599{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
2600{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2601{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2602{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
2603{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
2604{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
2605{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
2606
2607{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}},
2608{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}},
2609{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BD}},
2610{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, {BI, BD}},
2611{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}},
2612{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}},
2613{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BD}},
2614{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, {BI, BD}},
2615{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}},
2616{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}},
2617{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}},
2618{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}},
2619{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}},
2620{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}},
2621{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}},
2622{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}},
2623
2624{"bc-", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDM}},
2625{"bc+", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDP}},
2626{"bc", B(16,0,0), B_MASK, COM, {BO, BI, BD}},
2627{"bcl-", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDM}},
2628{"bcl+", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDP}},
2629{"bcl", B(16,0,1), B_MASK, COM, {BO, BI, BD}},
2630{"bca-", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDMA}},
2631{"bca+", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDPA}},
2632{"bca", B(16,1,0), B_MASK, COM, {BO, BI, BDA}},
2633{"bcla-", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDMA}},
2634{"bcla+", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDPA}},
2635{"bcla", B(16,1,1), B_MASK, COM, {BO, BI, BDA}},
2636
2637{"svc", SC(17,0,0), SC_MASK, POWER, {SVC_LEV, FL1, FL2}},
2638{"svcl", SC(17,0,1), SC_MASK, POWER, {SVC_LEV, FL1, FL2}},
2639{"sc", SC(17,1,0), SC_MASK, PPC, {LEV}},
2640{"svca", SC(17,1,0), SC_MASK, PWRCOM, {SV}},
2641{"svcla", SC(17,1,1), SC_MASK, POWER, {SV}},
2642
2643{"b", B(18,0,0), B_MASK, COM, {LI}},
2644{"bl", B(18,0,1), B_MASK, COM, {LI}},
2645{"ba", B(18,1,0), B_MASK, COM, {LIA}},
2646{"bla", B(18,1,1), B_MASK, COM, {LIA}},
2647
2648{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}},
2649
2650{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}},
2651{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
2652{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}},
2653{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
2654{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
2655{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
2656{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}},
2657{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
2658{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}},
2659{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
2660{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
2661{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}},
2662{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, {0}},
2663{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, {0}},
2664{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, {0}},
2665{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, {0}},
2666{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, {0}},
2667{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, {0}},
2668{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, {0}},
2669{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, {0}},
2670{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, {0}},
2671{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, {0}},
2672{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, {0}},
2673{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, {0}},
2674
2675{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2676{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2677{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2678{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2679{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2680{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2681{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2682{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2683{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2684{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2685{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2686{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2687{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2688{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2689{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2690{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2691{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2692{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2693{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2694{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2695{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2696{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2697{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2698{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2699{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2700{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2701{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2702{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2703{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2704{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2705{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2706{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2707{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2708{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2709{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2710{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2711{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2712{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2713{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2714{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2715{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2716{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2717{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2718{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2719{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2720{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2721{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2722{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2723{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2724{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2725{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2726{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2727{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2728{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2729{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2730{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2731{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2732{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2733{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2734{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2735{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2736{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2737{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2738{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2739{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2740{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2741{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2742{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2743{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2744{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2745{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2746{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2747{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2748{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2749{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2750{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2751{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2752{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2753{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2754{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2755{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2756{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2757{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2758{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2759{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2760{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2761{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2762{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2763{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2764{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2765{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2766{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2767{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2768{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2769{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2770{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2771{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2772{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2773{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2774{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2775{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2776{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2777{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
2778{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2779{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2780{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2781{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2782{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
2783{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2784{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2785{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2786{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2787{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2788{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2789{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2790{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2791{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2792{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2793{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2794{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2795{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2796{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2797{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2798{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2799{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2800{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2801{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2802{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2803{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2804{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2805{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2806{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2807{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2808{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2809{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2810{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2811{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2812{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
2813{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2814{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
2815
2816{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2817{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2818{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2819{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2820{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2821{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2822{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2823{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2824{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2825{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2826{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2827{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2828{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2829{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2830{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, {BI}},
2831{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2832{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2833{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, {BI}},
2834{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2835{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2836{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, {BI}},
2837{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, {BI}},
2838{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, {BI}},
2839{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, {BI}},
2840{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2841{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2842{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2843{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2844{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2845{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2846{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2847{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2848{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2849{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2850{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2851{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2852{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, {BI}},
2853{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2854{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, {BI}},
2855{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, {BI}},
2856{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2857{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, {BI}},
2858{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
2859{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
2860{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, {BI}},
2861{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, {BI}},
2862{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, {BI}},
2863{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, {BI}},
2864
2865{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
2866{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
2867{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
2868{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
2869{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, {BO, BI, BH}},
2870{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, {BO, BI}},
2871{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
2872{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, {BO, BI}},
2873
2874{"bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, {BO, BI}},
2875{"bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, {BO, BI}},
2876
2877{"rfid", XL(19,18), 0xffffffff, PPC64, {0}},
2878
2879{"crnot", XL(19,33), XL_MASK, PPCCOM, {BT, BA, BBA}},
2880{"crnor", XL(19,33), XL_MASK, COM, {BT, BA, BB}},
2881{"rfmci", X(19,38), 0xffffffff, PPCRFMCI, {0}},
2882
19a6653c 2883{"rfdi", XL(19,39), 0xffffffff, E500MC, {0}},
de866fcc
AM		 2884{"rfi", XL(19,50), 0xffffffff, COM, {0}},
2885{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE, {0}},
2886
2887{"rfsvc", XL(19,82), 0xffffffff, POWER, {0}},
2888
19a6653c
AM		 2889{"rfgi", XL(19,102), 0xffffffff, E500MC, {0}},
2890
de866fcc
AM		 2891{"crandc", XL(19,129), XL_MASK, COM, {BT, BA, BB}},
2892
2893{"isync", XL(19,150), 0xffffffff, PPCCOM, {0}},
2894{"ics", XL(19,150), 0xffffffff, PWRCOM, {0}},
2895
2896{"crclr", XL(19,193), XL_MASK, PPCCOM, {BT, BAT, BBA}},
2897{"crxor", XL(19,193), XL_MASK, COM, {BT, BA, BB}},
2898
19a6653c
AM		 2899{"dnh", X(19,198), X_MASK, E500MC, {DUI, DUIS}},
2900
de866fcc
AM		 2901{"crnand", XL(19,225), XL_MASK, COM, {BT, BA, BB}},
2902
2903{"crand", XL(19,257), XL_MASK, COM, {BT, BA, BB}},
2904
2905{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, {0}},
2906
2907{"crset", XL(19,289), XL_MASK, PPCCOM, {BT, BAT, BBA}},
2908{"creqv", XL(19,289), XL_MASK, COM, {BT, BA, BB}},
2909
2910{"doze", XL(19,402), 0xffffffff, POWER6, {0}},
2911
2912{"crorc", XL(19,417), XL_MASK, COM, {BT, BA, BB}},
2913
2914{"nap", XL(19,434), 0xffffffff, POWER6, {0}},
2915
2916{"crmove", XL(19,449), XL_MASK, PPCCOM, {BT, BA, BBA}},
2917{"cror", XL(19,449), XL_MASK, COM, {BT, BA, BB}},
2918
2919{"sleep", XL(19,466), 0xffffffff, POWER6, {0}},
2920{"rvwinkle", XL(19,498), 0xffffffff, POWER6, {0}},
2921
2922{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, {0}},
2923{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, {0}},
2924
2925{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2926{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2927{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2928{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2929{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2930{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2931{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2932{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2933{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2934{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2935{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2936{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2937{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2938{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2939{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2940{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2941{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2942{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2943{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2944{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2945{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2946{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2947{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2948{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2949{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2950{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2951{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2952{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2953{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2954{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2955{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2956{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2957{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2958{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2959{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2960{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2961{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2962{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2963{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2964{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2965{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2966{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2967{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2968{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2969{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2970{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2971{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2972{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2973{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2974{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2975{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2976{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2977{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2978{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2979{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2980{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2981{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2982{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2983{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2984{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2985{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2986{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2987{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2988{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2989{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2990{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2991{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2992{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
2993{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2994{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
2995{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
2996{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
2997{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
2998{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
2999{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
3000{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
3001{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
3002{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
3003{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
3004{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
3005{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
3006{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
3007{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
3008{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
3009{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
3010{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
3011{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
3012{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
3013{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
3014{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
3015{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
3016{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
3017{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
3018{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
3019{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
3020{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
3021{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
3022{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
3023{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
3024{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
3025{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3026{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3027{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3028{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3029{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3030{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3031{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3032{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3033{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3034{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3035{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3036{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3037{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3038{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3039{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3040{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3041{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3042{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
3043{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3044{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
3045
3046{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, {BI}},
3047{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
3048{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, {BI}},
3049{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
3050{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
3051{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
3052{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, {BI}},
3053{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, {BI}},
3054{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, {BI}},
3055{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, {BI}},
3056{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, {BI}},
3057{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
3058{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, {BI}},
3059{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
3060{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
3061{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
3062{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, {BI}},
3063{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, {BI}},
3064{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, {BI}},
3065{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, {BI}},
3066
3067{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
3068{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
3069{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
3070{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
3071{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, {BO, BI, BH}},
3072{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, {BO, BI}},
3073{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
3074{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, {BO, BI}},
3075
3076{"bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, {BO, BI}},
3077{"bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, {BO, BI}},
3078
3079{"rlwimi", M(20,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
3080{"rlimi", M(20,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
3081
3082{"rlwimi.", M(20,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
3083{"rlimi.", M(20,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
3084
3085{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, {RA, RS, SH}},
3086{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, {RA, RS, MB}},
3087{"rlwinm", M(21,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
3088{"rlinm", M(21,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
3089{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, {RA, RS, SH}},
3090{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, {RA, RS, MB}},
3091{"rlwinm.", M(21,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
3092{"rlinm.", M(21,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
3093
3094{"rlmi", M(22,0), M_MASK, M601, {RA, RS, RB, MBE, ME}},
3095{"be", B(22,0,0), B_MASK, BOOKE64, {LI}},
3096{"bel", B(22,0,1), B_MASK, BOOKE64, {LI}},
3097{"rlmi.", M(22,1), M_MASK, M601, {RA, RS, RB, MBE, ME}},
3098{"bea", B(22,1,0), B_MASK, BOOKE64, {LIA}},
3099{"bela", B(22,1,1), B_MASK, BOOKE64, {LIA}},
3100
3101{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, {RA, RS, RB}},
3102{"rlwnm", M(23,0), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}},
3103{"rlnm", M(23,0), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}},
3104{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, {RA, RS, RB}},
3105{"rlwnm.", M(23,1), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}},
3106{"rlnm.", M(23,1), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}},
3107
3108{"nop", OP(24), 0xffffffff, PPCCOM, {0}},
3109{"ori", OP(24), OP_MASK, PPCCOM, {RA, RS, UI}},
3110{"oril", OP(24), OP_MASK, PWRCOM, {RA, RS, UI}},
3111
3112{"oris", OP(25), OP_MASK, PPCCOM, {RA, RS, UI}},
3113{"oriu", OP(25), OP_MASK, PWRCOM, {RA, RS, UI}},
3114
3115{"xori", OP(26), OP_MASK, PPCCOM, {RA, RS, UI}},
3116{"xoril", OP(26), OP_MASK, PWRCOM, {RA, RS, UI}},
3117
3118{"xoris", OP(27), OP_MASK, PPCCOM, {RA, RS, UI}},
3119{"xoriu", OP(27), OP_MASK, PWRCOM, {RA, RS, UI}},
3120
3121{"andi.", OP(28), OP_MASK, PPCCOM, {RA, RS, UI}},
3122{"andil.", OP(28), OP_MASK, PWRCOM, {RA, RS, UI}},
3123
3124{"andis.", OP(29), OP_MASK, PPCCOM, {RA, RS, UI}},
3125{"andiu.", OP(29), OP_MASK, PWRCOM, {RA, RS, UI}},
3126
3127{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, {RA, RS, SH6}},
3128{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, {RA, RS, MB6}},
3129{"rldicl", MD(30,0,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3130{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, {RA, RS, SH6}},
3131{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, {RA, RS, MB6}},
3132{"rldicl.", MD(30,0,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3133
3134{"rldicr", MD(30,1,0), MD_MASK, PPC64, {RA, RS, SH6, ME6}},
3135{"rldicr.", MD(30,1,1), MD_MASK, PPC64, {RA, RS, SH6, ME6}},
3136
3137{"rldic", MD(30,2,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3138{"rldic.", MD(30,2,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3139
3140{"rldimi", MD(30,3,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3141{"rldimi.", MD(30,3,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}},
3142
3143{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, {RA, RS, RB}},
3144{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, {RA, RS, RB, MB6}},
3145{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, {RA, RS, RB}},
3146{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, {RA, RS, RB, MB6}},
3147
3148{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, {RA, RS, RB, ME6}},
3149{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, {RA, RS, RB, ME6}},
3150
3151{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}},
3152{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, {OBF, RA, RB}},
3153{"cmp", X(31,0), XCMP_MASK, PPC, {BF, L, RA, RB}},
3154{"cmp", X(31,0), XCMPL_MASK, PWRCOM, {BF, RA, RB}},
3155
3156{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, {RA, RB}},
3157{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, {RA, RB}},
3158{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, {RA, RB}},
3159{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, {RA, RB}},
3160{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, {RA, RB}},
3161{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, {RA, RB}},
3162{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, {RA, RB}},
3163{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, {RA, RB}},
3164{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, {RA, RB}},
3165{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, {RA, RB}},
3166{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, {RA, RB}},
3167{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, {RA, RB}},
3168{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, {RA, RB}},
3169{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, {RA, RB}},
3170{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, {RA, RB}},
3171{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, {RA, RB}},
3172{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, {RA, RB}},
3173{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, {RA, RB}},
3174{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, {RA, RB}},
3175{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, {RA, RB}},
3176{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, {RA, RB}},
3177{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, {RA, RB}},
3178{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, {RA, RB}},
3179{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, {RA, RB}},
3180{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, {RA, RB}},
3181{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, {RA, RB}},
3182{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, {RA, RB}},
3183{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, {RA, RB}},
3184{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, {0}},
3185{"tw", X(31,4), X_MASK, PPCCOM, {TO, RA, RB}},
3186{"t", X(31,4), X_MASK, PWRCOM, {TO, RA, RB}},
3187
3188{"lvsl", X(31,6), X_MASK, PPCVEC, {VD, RA, RB}},
3189{"lvebx", X(31,7), X_MASK, PPCVEC, {VD, RA, RB}},
3190
3191{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3192{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3193{"subc", XO(31,8,0,0), XO_MASK, PPC, {RT, RB, RA}},
3194{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3195{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
3196{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RB, RA}},
3197
3198{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, {RT, RA, RB}},
3199{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, {RT, RA, RB}},
3200
3201{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3202{"a", XO(31,10,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3203{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3204{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
3205
3206{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, {RT, RA, RB}},
3207{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, {RT, RA, RB}},
3208
3209{"isellt", X(31,15), X_MASK, PPCISEL, {RT, RA, RB}},
3210
3211{"mfcr", XFXM(31,19,0,0), XRARB_MASK, NOPOWER4|COM, {RT}},
3212{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, {RT, FXM4}},
3213{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, {RT, FXM}},
3214
3215{"lwarx", X(31,20), XEH_MASK, PPC, {RT, RA0, RB, EH}},
3216
3217{"ldx", X(31,21), X_MASK, PPC64, {RT, RA0, RB}},
3218
3219{"icbt", X(31,22), X_MASK, BOOKE|PPCE300, {CT, RA, RB}},
3220
3221{"lwzx", X(31,23), X_MASK, PPCCOM, {RT, RA0, RB}},
3222{"lx", X(31,23), X_MASK, PWRCOM, {RT, RA, RB}},
3223
3224{"slw", XRC(31,24,0), X_MASK, PPCCOM, {RA, RS, RB}},
3225{"sl", XRC(31,24,0), X_MASK, PWRCOM, {RA, RS, RB}},
3226{"slw.", XRC(31,24,1), X_MASK, PPCCOM, {RA, RS, RB}},
3227{"sl.", XRC(31,24,1), X_MASK, PWRCOM, {RA, RS, RB}},
3228
3229{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, {RA, RS}},
3230{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, {RA, RS}},
3231{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, {RA, RS}},
3232{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, {RA, RS}},
3233
3234{"sld", XRC(31,27,0), X_MASK, PPC64, {RA, RS, RB}},
3235{"sld.", XRC(31,27,1), X_MASK, PPC64, {RA, RS, RB}},
3236
3237{"and", XRC(31,28,0), X_MASK, COM, {RA, RS, RB}},
3238{"and.", XRC(31,28,1), X_MASK, COM, {RA, RS, RB}},
3239
3240{"maskg", XRC(31,29,0), X_MASK, M601, {RA, RS, RB}},
3241{"maskg.", XRC(31,29,1), X_MASK, M601, {RA, RS, RB}},
3242
19a6653c
AM		 3243{"ldepx", X(31,29), X_MASK, E500MC, {RT, RA, RB}},
3244
de866fcc
AM		 3245{"icbte", X(31,30), X_MASK, BOOKE64, {CT, RA, RB}},
3246
3247{"lwzxe", X(31,31), X_MASK, BOOKE64, {RT, RA0, RB}},
19a6653c 3248{"lwepx", X(31,31), X_MASK, E500MC, {RT, RA, RB}},
de866fcc
AM		 3249
3250{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}},
3251{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, {OBF, RA, RB}},
3252{"cmpl", X(31,32), XCMP_MASK, PPC, {BF, L, RA, RB}},
3253{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, {BF, RA, RB}},
3254
3255{"lvsr", X(31,38), X_MASK, PPCVEC, {VD, RA, RB}},
3256{"lvehx", X(31,39), X_MASK, PPCVEC, {VD, RA, RB}},
3257
3258{"iselgt", X(31,47), X_MASK, PPCISEL, {RT, RA, RB}},
3259
3260{"lvewx", X(31,71), X_MASK, PPCVEC, {VD, RA, RB}},
3261
3262{"iseleq", X(31,79), X_MASK, PPCISEL, {RT, RA, RB}},
3263
3264{"isel", XISEL(31,15), XISEL_MASK, PPCISEL, {RT, RA, RB, CRB}},
3265
3266{"subf", XO(31,40,0,0), XO_MASK, PPC, {RT, RA, RB}},
3267{"sub", XO(31,40,0,0), XO_MASK, PPC, {RT, RB, RA}},
3268{"subf.", XO(31,40,0,1), XO_MASK, PPC, {RT, RA, RB}},
3269{"sub.", XO(31,40,0,1), XO_MASK, PPC, {RT, RB, RA}},
3270
3271{"ldux", X(31,53), X_MASK, PPC64, {RT, RAL, RB}},
3272
3273{"dcbst", X(31,54), XRT_MASK, PPC, {RA, RB}},
3274
3275{"lwzux", X(31,55), X_MASK, PPCCOM, {RT, RAL, RB}},
3276{"lux", X(31,55), X_MASK, PWRCOM, {RT, RA, RB}},
3277
3278{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, {RA, RS}},
3279{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, {RA, RS}},
3280
3281{"andc", XRC(31,60,0), X_MASK, COM, {RA, RS, RB}},
3282{"andc.", XRC(31,60,1), X_MASK, COM, {RA, RS, RB}},
3283
3284{"dcbste", X(31,62), XRT_MASK, BOOKE64, {RA, RB}},
3285
19a6653c
AM		 3286{"wait", X(31,62), 0xffffffff, E500MC, {0}},
3287
de866fcc
AM		 3288{"lwzuxe", X(31,63), X_MASK, BOOKE64, {RT, RAL, RB}},
3289
19a6653c
AM		 3290{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, {RA, RB}},
3291
de866fcc
AM		 3292{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, {RA, RB}},
3293{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, {RA, RB}},
3294{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, {RA, RB}},
3295{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, {RA, RB}},
3296{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, {RA, RB}},
3297{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, {RA, RB}},
3298{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, {RA, RB}},
3299{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, {RA, RB}},
3300{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, {RA, RB}},
3301{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, {RA, RB}},
3302{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, {RA, RB}},
3303{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, {RA, RB}},
3304{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, {RA, RB}},
3305{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, {RA, RB}},
3306{"td", X(31,68), X_MASK, PPC64, {TO, RA, RB}},
3307
3308{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, {RT, RA, RB}},
3309{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, {RT, RA, RB}},
3310
3311{"mulhw", XO(31,75,0,0), XO_MASK, PPC, {RT, RA, RB}},
3312{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, {RT, RA, RB}},
3313
3314{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, {RA, RS, RB}},
3315{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, {RA, RS, RB}},
3316
3317{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, {SR, RS}},
3318
3319{"mfmsr", X(31,83), XRARB_MASK, COM, {RT}},
3320
3321{"ldarx", X(31,84), XEH_MASK, PPC64, {RT, RA0, RB, EH}},
3322
3323{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, {RA, RB}},
3324{"dcbf", X(31,86), XLRT_MASK, PPC, {RA, RB, L}},
3325
3326{"lbzx", X(31,87), X_MASK, COM, {RT, RA0, RB}},
3327
3328{"dcbfe", X(31,94), XRT_MASK, BOOKE64, {RA, RB}},
3329
3330{"lbzxe", X(31,95), X_MASK, BOOKE64, {RT, RA0, RB}},
19a6653c 3331{"lbepx", X(31,95), X_MASK, E500MC, {RT, RA, RB}},
de866fcc
AM		 3332
3333{"lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}},
3334
3335{"neg", XO(31,104,0,0), XORB_MASK, COM, {RT, RA}},
3336{"neg.", XO(31,104,0,1), XORB_MASK, COM, {RT, RA}},
3337
3338{"mul", XO(31,107,0,0), XO_MASK, M601, {RT, RA, RB}},
3339{"mul.", XO(31,107,0,1), XO_MASK, M601, {RT, RA, RB}},
3340
3341{"mtsrdin", X(31,114), XRA_MASK, PPC64, {RS, RB}},
3342
3343{"clf", X(31,118), XTO_MASK, POWER, {RA, RB}},
3344
3345{"lbzux", X(31,119), X_MASK, COM, {RT, RAL, RB}},
3346
3347{"popcntb", X(31,122), XRB_MASK, POWER5, {RA, RS}},
3348
3349{"not", XRC(31,124,0), X_MASK, COM, {RA, RS, RBS}},
3350{"nor", XRC(31,124,0), X_MASK, COM, {RA, RS, RB}},
3351{"not.", XRC(31,124,1), X_MASK, COM, {RA, RS, RBS}},
3352{"nor.", XRC(31,124,1), X_MASK, COM, {RA, RS, RB}},
3353
3354{"lwarxe", X(31,126), X_MASK, BOOKE64, {RT, RA0, RB}},
3355
3356{"lbzuxe", X(31,127), X_MASK, BOOKE64, {RT, RAL, RB}},
3357
19a6653c
AM		 3358{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, {RA, RB}},
3359
de866fcc
AM		 3360{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, {RS}},
3361
3362{"dcbtstls", X(31,134), X_MASK, PPCCHLK, {CT, RA, RB}},
3363
3364{"stvebx", X(31,135), X_MASK, PPCVEC, {VS, RA, RB}},
3365
3366{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3367{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3368{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3369{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
3370
3371{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3372{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3373{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3374{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
3375
3376{"dcbtstlse", X(31,142), X_MASK, PPCCHLK64, {CT, RA, RB}},
3377
3378{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, {RS}},
3379{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, {FXM, RS}},
3380{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, {FXM, RS}},
3381
3382{"mtmsr", X(31,146), XRLARB_MASK, COM, {RS, A_L}},
3383
3384{"stdx", X(31,149), X_MASK, PPC64, {RS, RA0, RB}},
3385
3386{"stwcx.", XRC(31,150,1), X_MASK, PPC, {RS, RA0, RB}},
3387
3388{"stwx", X(31,151), X_MASK, PPCCOM, {RS, RA0, RB}},
3389{"stx", X(31,151), X_MASK, PWRCOM, {RS, RA, RB}},
3390
3391{"slq", XRC(31,152,0), X_MASK, M601, {RA, RS, RB}},
3392{"slq.", XRC(31,152,1), X_MASK, M601, {RA, RS, RB}},
3393
3394{"sle", XRC(31,153,0), X_MASK, M601, {RA, RS, RB}},
3395{"sle.", XRC(31,153,1), X_MASK, M601, {RA, RS, RB}},
3396
3397{"prtyw", X(31,154), XRB_MASK, POWER6, {RA, RS}},
3398
19a6653c
AM		 3399{"stdepx", X(31,157), X_MASK, E500MC, {RS, RA, RB}},
3400
de866fcc
AM		 3401{"stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, {RS, RA0, RB}},
3402
3403{"stwxe", X(31,159), X_MASK, BOOKE64, {RS, RA0, RB}},
19a6653c 3404{"stwepx", X(31,159), X_MASK, E500MC, {RS, RA, RB}},
de866fcc
AM		 3405
3406{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, {E}},
3407
3408{"dcbtls", X(31,166), X_MASK, PPCCHLK, {CT, RA, RB}},
3409
3410{"stvehx", X(31,167), X_MASK, PPCVEC, {VS, RA, RB}},
3411
3412{"dcbtlse", X(31,174), X_MASK, PPCCHLK64, {CT, RA, RB}},
3413
3414{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, {RS, A_L}},
3415
3416{"stdux", X(31,181), X_MASK, PPC64, {RS, RAS, RB}},
3417
3418{"stwux", X(31,183), X_MASK, PPCCOM, {RS, RAS, RB}},
3419{"stux", X(31,183), X_MASK, PWRCOM, {RS, RA0, RB}},
3420
3421{"sliq", XRC(31,184,0), X_MASK, M601, {RA, RS, SH}},
3422{"sliq.", XRC(31,184,1), X_MASK, M601, {RA, RS, SH}},
3423
3424{"prtyd", X(31,186), XRB_MASK, POWER6, {RA, RS}},
252b5132 3425
de866fcc 3426{"stwuxe", X(31,191), X_MASK, BOOKE64, {RS, RAS, RB}},
252b5132 3427
de866fcc 3428{"stvewx", X(31,199), X_MASK, PPCVEC, {VS, RA, RB}},
252b5132 3429
de866fcc
AM		 3430{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, {RT, RA}},
3431{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, {RT, RA}},
3432{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, {RT, RA}},
3433{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, {RT, RA}},
252b5132 3434
de866fcc
AM		 3435{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, {RT, RA}},
3436{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, {RT, RA}},
3437{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, {RT, RA}},
3438{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, {RT, RA}},
418c1742 3439
19a6653c
AM		 3440{"msgsnd", XRTRA(31,206,0,0),XRTRA_MASK,E500MC, {RB}},
3441
de866fcc 3442{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, {SR, RS}},
418c1742 3443
de866fcc 3444{"stdcx.", XRC(31,214,1), X_MASK, PPC64, {RS, RA0, RB}},
252b5132 3445
de866fcc 3446{"stbx", X(31,215), X_MASK, COM, {RS, RA0, RB}},
252b5132 3447
de866fcc
AM		 3448{"sllq", XRC(31,216,0), X_MASK, M601, {RA, RS, RB}},
3449{"sllq.", XRC(31,216,1), X_MASK, M601, {RA, RS, RB}},
252b5132 3450
de866fcc
AM		 3451{"sleq", XRC(31,217,0), X_MASK, M601, {RA, RS, RB}},
3452{"sleq.", XRC(31,217,1), X_MASK, M601, {RA, RS, RB}},
252b5132 3453
de866fcc 3454{"stbxe", X(31,223), X_MASK, BOOKE64, {RS, RA0, RB}},
19a6653c 3455{"stbepx", X(31,223), X_MASK, E500MC, {RS, RA, RB}},
252b5132 3456
de866fcc 3457{"icblc", X(31,230), X_MASK, PPCCHLK, {CT, RA, RB}},
7d5b217e 3458
de866fcc 3459{"stvx", X(31,231), X_MASK, PPCVEC, {VS, RA, RB}},
f509565f 3460
de866fcc
AM		 3461{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, {RT, RA}},
3462{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, {RT, RA}},
3463{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, {RT, RA}},
3464{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, {RT, RA}},
252b5132 3465
de866fcc
AM		 3466{"mulld", XO(31,233,0,0), XO_MASK, PPC64, {RT, RA, RB}},
3467{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, {RT, RA, RB}},
252b5132 3468
de866fcc
AM		 3469{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, {RT, RA}},
3470{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, {RT, RA}},
3471{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, {RT, RA}},
3472{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, {RT, RA}},
252b5132 3473
de866fcc
AM		 3474{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3475{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3476{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3477{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
252b5132 3478
19a6653c 3479{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, {RB}},
de866fcc
AM		 3480{"icblce", X(31,238), X_MASK, PPCCHLK64, {CT, RA, RB}},
3481{"mtsrin", X(31,242), XRA_MASK, PPC32, {RS, RB}},
3482{"mtsri", X(31,242), XRA_MASK, POWER32, {RS, RB}},
418c1742 3483
de866fcc 3484{"dcbtst", X(31,246), X_MASK, PPC, {CT, RA, RB}},
418c1742 3485
de866fcc 3486{"stbux", X(31,247), X_MASK, COM, {RS, RAS, RB}},
252b5132 3487
de866fcc
AM		 3488{"slliq", XRC(31,248,0), X_MASK, M601, {RA, RS, SH}},
3489{"slliq.", XRC(31,248,1), X_MASK, M601, {RA, RS, SH}},
252b5132 3490
de866fcc 3491{"dcbtste", X(31,253), X_MASK, BOOKE64, {CT, RA, RB}},
f509565f 3492
de866fcc 3493{"stbuxe", X(31,255), X_MASK, BOOKE64, {RS, RAS, RB}},
252b5132 3494
19a6653c
AM		 3495{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, {RT, RA, RB}},
3496
de866fcc 3497{"mfdcrx", X(31,259), X_MASK, BOOKE, {RS, RA}},
252b5132 3498
de866fcc 3499{"icbt", X(31,262), XRT_MASK, PPC403, {RA, RB}},
1ed8e1e4 3500
de866fcc
AM		 3501{"doz", XO(31,264,0,0), XO_MASK, M601, {RT, RA, RB}},
3502{"doz.", XO(31,264,0,1), XO_MASK, M601, {RT, RA, RB}},
252b5132 3503
de866fcc
AM		 3504{"add", XO(31,266,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
3505{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
3506{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
3507{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
418c1742 3508
19a6653c
AM		 3509{"ehpriv", X(31,270), 0xffffffff, E500MC, {0}},
3510
de866fcc 3511{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, {RB, L}},
418c1742 3512
de866fcc 3513{"mfapidi", X(31,275), X_MASK, BOOKE, {RT, RA}},
252b5132 3514
de866fcc
AM		 3515{"lscbx", XRC(31,277,0), X_MASK, M601, {RT, RA, RB}},
3516{"lscbx.", XRC(31,277,1), X_MASK, M601, {RT, RA, RB}},
23976049 3517
de866fcc
AM		 3518{"dcbt", X(31,278), X_MASK, PPC, {CT, RA, RB}},
3519
3520{"lhzx", X(31,279), X_MASK, COM, {RT, RA0, RB}},
3521
3522{"eqv", XRC(31,284,0), X_MASK, COM, {RA, RS, RB}},
3523{"eqv.", XRC(31,284,1), X_MASK, COM, {RA, RS, RB}},
3524
3525{"dcbte", X(31,286), X_MASK, BOOKE64, {CT, RA, RB}},
3526
3527{"lhzxe", X(31,287), X_MASK, BOOKE64, {RT, RA0, RB}},
19a6653c 3528{"lhepx", X(31,287), X_MASK, E500MC, {RT, RA, RB}},
de866fcc
AM		 3529
3530{"tlbie", X(31,306), XRTLRA_MASK, PPC, {RB, L}},
3531{"tlbi", X(31,306), XRT_MASK, POWER, {RA0, RB}},
3532
3533{"eciwx", X(31,310), X_MASK, PPC, {RT, RA, RB}},
3534
3535{"lhzux", X(31,311), X_MASK, COM, {RT, RAL, RB}},
3536
3537{"xor", XRC(31,316,0), X_MASK, COM, {RA, RS, RB}},
3538{"xor.", XRC(31,316,1), X_MASK, COM, {RA, RS, RB}},
3539
3540{"lhzuxe", X(31,319), X_MASK, BOOKE64, {RT, RAL, RB}},
3541
19a6653c
AM		 3542{"dcbtep", XRT(31,319,0), X_MASK, E500MC, {RT, RA, RB}},
3543
de866fcc
AM		 3544{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, {RT}},
3545{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, {RT}},
3546{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, {RT}},
3547{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, {RT}},
3548{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, {RT}},
3549{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, {RT}},
3550{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, {RT}},
3551{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, {RT}},
3552{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, {RT}},
3553{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, {RT}},
3554{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, {RT}},
3555{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, {RT}},
3556{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, {RT}},
3557{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, {RT}},
3558{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, {RT}},
3559{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, {RT}},
3560{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, {RT}},
3561{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, {RT}},
3562{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, {RT}},
3563{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, {RT}},
3564{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, {RT}},
3565{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, {RT}},
3566{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, {RT}},
3567{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, {RT}},
3568{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, {RT}},
3569{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, {RT}},
3570{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, {RT}},
3571{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, {RT}},
3572{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, {RT}},
3573{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, {RT}},
3574{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, {RT}},
3575{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, {RT}},
3576{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, {RT}},
3577{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, {RT}},
3578{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE, {RT, SPR}},
3579
3580{"div", XO(31,331,0,0), XO_MASK, M601, {RT, RA, RB}},
3581{"div.", XO(31,331,0,1), XO_MASK, M601, {RT, RA, RB}},
3582
3583{"mfpmr", X(31,334), X_MASK, PPCPMR, {RT, PMR}},
3584
3585{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, {RT}},
3586{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, {RT}},
3587{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, {RT}},
3588{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, {RT}},
3589{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, {RT}},
3590{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, {RT}},
3591{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, {RT}},
3592{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, {RT}},
3593{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, {RT}},
3594{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, {RT}},
3595{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, {RT}},
3596{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, {RT}},
3597{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, {RT}},
3598{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, {RT}},
3599{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, {RT}},
3600{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, {RT}},
3601{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, {RT}},
3602{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, {RT}},
3603{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, {RT}},
3604{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, {RT}},
3605{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, {RT}},
3606{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, {RT}},
3607{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, {RT}},
3608{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, {RT}},
3609{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, {RT}},
3610{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, {RT}},
3611{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, {RT}},
3612{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, {RT}},
3613{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, {RT}},
3614{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, {RT}},
3615{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, {RT}},
3616{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, {RT}},
3617{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, {RT}},
3618{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, {RT}},
3619{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, {RT}},
3620{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, {RT}},
3621{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, {RT}},
3622{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, {RT}},
3623{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, {RT}},
3624{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, {RT}},
3625{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, {RT, SPRG}},
3626{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, {RT}},
3627{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, {RT}},
3628{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, {RT}},
3629{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, {RT}},
3630{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}},
3631{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}},
3632{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, {RT}},
3633{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, {RT}},
3634{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, {RT}},
3635{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, {RT}},
3636{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, {RT}},
3637{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, {RT}},
3638{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, {RT}},
3639{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, {RT}},
3640{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, {RT}},
3641{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, {RT}},
3642{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, {RT}},
3643{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, {RT}},
3644{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, {RT}},
3645{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, {RT}},
3646{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, {RT}},
3647{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, {RT}},
3648{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, {RT}},
3649{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, {RT}},
3650{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, {RT}},
3651{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, {RT}},
3652{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, {RT}},
3653{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, {RT}},
3654{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, {RT}},
3655{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, {RT}},
3656{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, {RT}},
3657{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, {RT}},
3658{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, {RT}},
3659{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, {RT}},
3660{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, {RT}},
3661{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, {RT}},
3662{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, {RT}},
3663{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, {RT}},
3664{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, {RT}},
3665{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, {RT}},
3666{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, {RT}},
3667{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, {RT}},
3668{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, {RT}},
3669{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, {RT}},
3670{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, {RT}},
3671{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, {RT}},
3672{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, {RT}},
3673{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, {RT}},
3674{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, {RT}},
3675{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
3676{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, {RT}},
3677{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
3678{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, {RT}},
3679{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, {RT}},
3680{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
3681{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
3682{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, {RT}},
3683{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, {RT}},
3684{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, {RT}},
3685{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, {RT}},
3686{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, {RT}},
3687{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, {RT}},
3688{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, {RT}},
3689{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, {RT}},
3690{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, {RT}},
3691{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, {RT}},
3692{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, {RT}},
3693{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, {RT}},
3694{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, {RT}},
3695{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, {RT}},
3696{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, {RT}},
3697{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, {RT}},
3698{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, {RT}},
3699{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, {RT}},
3700{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, {RT}},
3701{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, {RT}},
3702{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, {RT}},
3703{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, {RT}},
3704{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, {RT}},
3705{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, {RT}},
3706{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, {RT}},
3707{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, {RT}},
3708{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, {RT}},
3709{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, {RT}},
3710{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, {RT}},
3711{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, {RT}},
3712{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, {RT}},
3713{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, {RT}},
3714{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, {RT}},
3715{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, {RT}},
3716{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, {RT}},
3717{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, {RT}},
3718{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, {RT}},
3719{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, {RT}},
3720{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, {RT}},
3721{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, {RT}},
3722{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, {RT}},
3723{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, {RT}},
3724{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, {RT}},
3725{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, {RT}},
3726{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, {RT}},
3727{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, {RT}},
3728{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, {RT}},
3729{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, {RT}},
3730{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, {RT}},
3731{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, {RT}},
3732{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, {RT}},
3733{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, {RT}},
3734{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, {RT}},
3735{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, {RT}},
3736{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, {RT}},
3737{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, {RT}},
3738{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, {RT}},
3739{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, {RT}},
3740{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, {RT}},
3741{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, {RT}},
3742{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, {RT}},
3743{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, {RT}},
3744{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, {RT}},
3745{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, {RT}},
3746{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, {RT}},
3747{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, {RT}},
3748{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, {RT}},
3749{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, {RT}},
3750{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, {RT}},
3751{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, {RT}},
3752{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, {RT}},
3753{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, {RT}},
3754{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, {RT}},
3755{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, {RT}},
3756{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, {RT}},
3757{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, {RT}},
3758{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, {RT}},
3759{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, {RT}},
3760{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, {RT}},
3761{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, {RT}},
3762{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, {RT}},
3763{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, {RT}},
3764{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, {RT}},
3765{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, {RT}},
3766{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, {RT}},
3767{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, {RT}},
3768{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, {RT}},
3769{"mfspr", X(31,339), X_MASK, COM, {RT, SPR}},
3770
3771{"lwax", X(31,341), X_MASK, PPC64, {RT, RA0, RB}},
3772
3773{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
3774
3775{"lhax", X(31,343), X_MASK, COM, {RT, RA0, RB}},
3776
3777{"lhaxe", X(31,351), X_MASK, BOOKE64, {RT, RA0, RB}},
3778
3779{"lvxl", X(31,359), X_MASK, PPCVEC, {VD, RA, RB}},
3780
3781{"abs", XO(31,360,0,0), XORB_MASK, M601, {RT, RA}},
3782{"abs.", XO(31,360,0,1), XORB_MASK, M601, {RT, RA}},
3783
3784{"divs", XO(31,363,0,0), XO_MASK, M601, {RT, RA, RB}},
3785{"divs.", XO(31,363,0,1), XO_MASK, M601, {RT, RA, RB}},
3786
3787{"tlbia", X(31,370), 0xffffffff, PPC, {0}},
3788
3789{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, {RT}},
3790{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, {RT}},
3791{"mftb", X(31,371), X_MASK, CLASSIC, {RT, TBR}},
3792
3793{"lwaux", X(31,373), X_MASK, PPC64, {RT, RAL, RB}},
3794
3795{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
3796
3797{"lhaux", X(31,375), X_MASK, COM, {RT, RAL, RB}},
3798
3799{"lhauxe", X(31,383), X_MASK, BOOKE64, {RT, RAL, RB}},
3800
3801{"mtdcrx", X(31,387), X_MASK, BOOKE, {RA, RS}},
3802
3803{"dcblc", X(31,390), X_MASK, PPCCHLK, {CT, RA, RB}},
3804
3805{"subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, {RT, RA, RB}},
3806
3807{"adde64", XO(31,394,0,0), XO_MASK, BOOKE64, {RT, RA, RB}},
3808
3809{"dcblce", X(31,398), X_MASK, PPCCHLK64, {CT, RA, RB}},
3810
3811{"slbmte", X(31,402), XRA_MASK, PPC64, {RS, RB}},
3812
3813{"sthx", X(31,407), X_MASK, COM, {RS, RA0, RB}},
3814
3815{"orc", XRC(31,412,0), X_MASK, COM, {RA, RS, RB}},
3816{"orc.", XRC(31,412,1), X_MASK, COM, {RA, RS, RB}},
3817
3818{"sthxe", X(31,415), X_MASK, BOOKE64, {RS, RA0, RB}},
19a6653c 3819{"sthepx", X(31,415), X_MASK, E500MC, {RS, RA, RB}},
de866fcc
AM		 3820
3821{"slbie", X(31,434), XRTRA_MASK, PPC64, {RB}},
3822
3823{"ecowx", X(31,438), X_MASK, PPC, {RT, RA, RB}},
3824
3825{"sthux", X(31,439), X_MASK, COM, {RS, RAS, RB}},
3826
19a6653c
AM		 3827{"mdors", 0x7f9ce378, 0xffffffff, E500MC, {0}},
3828
de866fcc
AM		 3829{"mr", XRC(31,444,0), X_MASK, COM, {RA, RS, RBS}},
3830{"or", XRC(31,444,0), X_MASK, COM, {RA, RS, RB}},
3831{"mr.", XRC(31,444,1), X_MASK, COM, {RA, RS, RBS}},
3832{"or.", XRC(31,444,1), X_MASK, COM, {RA, RS, RB}},
3833
3834{"sthuxe", X(31,447), X_MASK, BOOKE64, {RS, RAS, RB}},
3835
3836{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, {RS}},
3837{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, {RS}},
3838{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, {RS}},
3839{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, {RS}},
3840{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, {RS}},
3841{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, {RS}},
3842{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, {RS}},
3843{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, {RS}},
3844{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, {RS}},
3845{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, {RS}},
3846{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, {RS}},
3847{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, {RS}},
3848{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, {RS}},
3849{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, {RS}},
3850{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, {RS}},
3851{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, {RS}},
3852{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, {RS}},
3853{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, {RS}},
3854{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, {RS}},
3855{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, {RS}},
3856{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, {RS}},
3857{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, {RS}},
3858{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, {RS}},
3859{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, {RS}},
3860{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, {RS}},
3861{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, {RS}},
3862{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, {RS}},
3863{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, {RS}},
3864{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, {RS}},
3865{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, {RS}},
3866{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, {RS}},
3867{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, {RS}},
3868{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, {RS}},
3869{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, {RS}},
3870{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE, {SPR, RS}},
3871
3872{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, {RA, RB}},
3873
3874{"subfze64", XO(31,456,0,0), XORB_MASK, BOOKE64, {RT, RA}},
3875
3876{"divdu", XO(31,457,0,0), XO_MASK, PPC64, {RT, RA, RB}},
3877{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, {RT, RA, RB}},
3878
3879{"addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, {RT, RA}},
3880
3881{"divwu", XO(31,459,0,0), XO_MASK, PPC, {RT, RA, RB}},
3882{"divwu.", XO(31,459,0,1), XO_MASK, PPC, {RT, RA, RB}},
3883
3884{"mtpmr", X(31,462), X_MASK, PPCPMR, {PMR, RS}},
3885
3886{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, {RS}},
3887{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, {RS}},
3888{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, {RS}},
3889{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, {RS}},
3890{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, {RS}},
3891{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, {RS}},
3892{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, {RS}},
3893{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, {RS}},
3894{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, {RS}},
3895{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, {RS}},
3896{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, {RS}},
3897{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, {RS}},
3898{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, {RS}},
3899{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, {RS}},
3900{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, {RS}},
3901{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, {RS}},
3902{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, {RS}},
3903{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, {RS}},
3904{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, {RS}},
3905{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, {RS}},
3906{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, {RS}},
3907{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, {RS}},
3908{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, {RS}},
3909{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, {RS}},
3910{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, {RS}},
3911{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, {RS}},
3912{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, {RS}},
3913{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, {RS}},
3914{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, {RS}},
3915{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, {RS}},
3916{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, {RS}},
3917{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, {RS}},
3918{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, {RS}},
3919{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, {RS}},
3920{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, {RS}},
3921{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, {RS}},
3922{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, {RS}},
3923{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, {RS}},
3924{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, {RS}},
3925{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, {RS}},
3926{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, {SPRG, RS}},
3927{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, {RS}},
3928{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, {RS}},
3929{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, {RS}},
3930{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, {RS}},
3931{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, {RS}},
3932{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, {RS}},
3933{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, {RS}},
3934{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, {RS}},
3935{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, {RS}},
3936{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, {RS}},
3937{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, {RS}},
3938{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, {RS}},
3939{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, {RS}},
3940{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, {RS}},
3941{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, {RS}},
3942{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, {RS}},
3943{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, {RS}},
3944{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, {RS}},
3945{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, {RS}},
3946{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, {RS}},
3947{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, {RS}},
3948{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, {RS}},
3949{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, {RS}},
3950{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, {RS}},
3951{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, {RS}},
3952{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, {RS}},
3953{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, {RS}},
3954{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, {RS}},
3955{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, {RS}},
3956{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, {RS}},
3957{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, {RS}},
3958{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, {RS}},
3959{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, {RS}},
3960{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, {RS}},
3961{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, {RS}},
3962{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, {RS}},
3963{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, {RS}},
3964{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, {RS}},
3965{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, {RS}},
3966{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, {RS}},
3967{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, {RS}},
3968{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, {RS}},
3969{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, {RS}},
3970{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, {RS}},
3971{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, {RS}},
3972{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, {RS}},
3973{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
3974{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, {RS}},
3975{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
3976{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, {RS}},
3977{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, {RS}},
3978{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
3979{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
3980{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, {RS}},
3981{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, {RS}},
3982{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, {RS}},
3983{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, {RS}},
3984{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, {RS}},
3985{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, {RS}},
3986{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, {RS}},
3987{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, {RS}},
3988{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, {RS}},
3989{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, {RS}},
3990{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, {RS}},
3991{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, {RS}},
3992{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, {RS}},
3993{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, {RS}},
3994{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, {RS}},
3995{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, {RS}},
3996{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, {RS}},
3997{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, {RS}},
3998{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, {RS}},
3999{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, {RS}},
4000{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, {RS}},
4001{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, {RS}},
4002{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, {RS}},
4003{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, {RS}},
4004{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, {RS}},
4005{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, {RS}},
4006{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, {RS}},
4007{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, {RS}},
4008{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, {RS}},
4009{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, {RS}},
4010{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, {RS}},
4011{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, {RS}},
4012{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, {RS}},
4013{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, {RS}},
4014{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, {RS}},
4015{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, {RS}},
4016{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, {RS}},
4017{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, {RS}},
4018{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, {RS}},
4019{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, {RS}},
4020{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, {RS}},
4021{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, {RS}},
4022{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, {RS}},
4023{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, {RS}},
4024{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, {RS}},
4025{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, {RS}},
4026{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, {RS}},
4027{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, {RS}},
4028{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, {RS}},
4029{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, {RS}},
4030{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, {RS}},
4031{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, {RS}},
4032{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, {RS}},
4033{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, {RS}},
4034{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, {RS}},
4035{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, {RS}},
4036{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, {RS}},
4037{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, {RS}},
4038{"mtspr", X(31,467), X_MASK, COM, {SPR, RS}},
4039
4040{"dcbi", X(31,470), XRT_MASK, PPC, {RA, RB}},
4041
4042{"nand", XRC(31,476,0), X_MASK, COM, {RA, RS, RB}},
4043{"nand.", XRC(31,476,1), X_MASK, COM, {RA, RS, RB}},
4044
4045{"dcbie", X(31,478), XRT_MASK, BOOKE64, {RA, RB}},
4046
19a6653c
AM		 4047{"dsn", X(31,483), XRT_MASK, E500MC, {RA, RB}},
4048
de866fcc
AM		 4049{"dcread", X(31,486), X_MASK, PPC403|PPC440, {RT, RA, RB}},
4050
4051{"icbtls", X(31,486), X_MASK, PPCCHLK, {CT, RA, RB}},
4052
4053{"stvxl", X(31,487), X_MASK, PPCVEC, {VS, RA, RB}},
4054
4055{"nabs", XO(31,488,0,0), XORB_MASK, M601, {RT, RA}},
4056{"subfme64", XO(31,488,0,0), XORB_MASK, BOOKE64, {RT, RA}},
4057{"nabs.", XO(31,488,0,1), XORB_MASK, M601, {RT, RA}},
4058
4059{"divd", XO(31,489,0,0), XO_MASK, PPC64, {RT, RA, RB}},
4060{"divd.", XO(31,489,0,1), XO_MASK, PPC64, {RT, RA, RB}},
4061
4062{"addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, {RT, RA}},
4063
4064{"divw", XO(31,491,0,0), XO_MASK, PPC, {RT, RA, RB}},
4065{"divw.", XO(31,491,0,1), XO_MASK, PPC, {RT, RA, RB}},
4066
4067{"icbtlse", X(31,494), X_MASK, PPCCHLK64, {CT, RA, RB}},
4068
4069{"slbia", X(31,498), 0xffffffff, PPC64, {0}},
4070
4071{"cli", X(31,502), XRB_MASK, POWER, {RT, RA}},
252b5132 4072
de866fcc 4073{"cmpb", X(31,508), X_MASK, POWER6, {RA, RS, RB}},
252b5132 4074
de866fcc 4075{"stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, {RS, RA, RB}},
23976049 4076
de866fcc 4077{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, {BF}},
252b5132 4078
19a6653c
AM		 4079{"lbdx", X(31,515), X_MASK, E500MC, {RT, RA, RB}},
4080
de866fcc 4081{"bblels", X(31,518), X_MASK, PPCBRLK, {0}},
252b5132 4082
de866fcc 4083{"lvlx", X(31,519), X_MASK, CELL, {VD, RA0, RB}},
252b5132 4084
de866fcc
AM		 4085{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4086{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4087{"subco", XO(31,8,1,0), XO_MASK, PPC, {RT, RB, RA}},
4088{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4089{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
4090{"subco.", XO(31,8,1,1), XO_MASK, PPC, {RT, RB, RA}},
252b5132 4091
de866fcc
AM		 4092{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4093{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4094{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4095{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4096
de866fcc 4097{"clcs", X(31,531), XRB_MASK, M601, {RT, RA}},
418c1742 4098
de866fcc 4099{"ldbrx", X(31,532), X_MASK, CELL, {RT, RA0, RB}},
418c1742 4100
de866fcc
AM		 4101{"lswx", X(31,533), X_MASK, PPCCOM, {RT, RA0, RB}},
4102{"lsx", X(31,533), X_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4103
de866fcc
AM		 4104{"lwbrx", X(31,534), X_MASK, PPCCOM, {RT, RA0, RB}},
4105{"lbrx", X(31,534), X_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4106
de866fcc 4107{"lfsx", X(31,535), X_MASK, COM, {FRT, RA0, RB}},
702f0fb4 4108
de866fcc
AM		 4109{"srw", XRC(31,536,0), X_MASK, PPCCOM, {RA, RS, RB}},
4110{"sr", XRC(31,536,0), X_MASK, PWRCOM, {RA, RS, RB}},
4111{"srw.", XRC(31,536,1), X_MASK, PPCCOM, {RA, RS, RB}},
4112{"sr.", XRC(31,536,1), X_MASK, PWRCOM, {RA, RS, RB}},
252b5132 4113
de866fcc
AM		 4114{"rrib", XRC(31,537,0), X_MASK, M601, {RA, RS, RB}},
4115{"rrib.", XRC(31,537,1), X_MASK, M601, {RA, RS, RB}},
23976049 4116
de866fcc
AM		 4117{"srd", XRC(31,539,0), X_MASK, PPC64, {RA, RS, RB}},
4118{"srd.", XRC(31,539,1), X_MASK, PPC64, {RA, RS, RB}},
f509565f 4119
de866fcc
AM		 4120{"maskir", XRC(31,541,0), X_MASK, M601, {RA, RS, RB}},
4121{"maskir.", XRC(31,541,1), X_MASK, M601, {RA, RS, RB}},
252b5132 4122
de866fcc 4123{"lwbrxe", X(31,542), X_MASK, BOOKE64, {RT, RA0, RB}},
252b5132 4124
de866fcc 4125{"lfsxe", X(31,543), X_MASK, BOOKE64, {FRT, RA0, RB}},
252b5132 4126
de866fcc 4127{"mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}},
702f0fb4 4128
19a6653c
AM		 4129{"lhdx", X(31,547), X_MASK, E500MC, {RT, RA, RB}},
4130
de866fcc 4131{"bbelr", X(31,550), X_MASK, PPCBRLK, {0}},
418c1742 4132
de866fcc 4133{"lvrx", X(31,551), X_MASK, CELL, {VD, RA0, RB}},
252b5132 4134
de866fcc
AM		 4135{"subfo", XO(31,40,1,0), XO_MASK, PPC, {RT, RA, RB}},
4136{"subo", XO(31,40,1,0), XO_MASK, PPC, {RT, RB, RA}},
4137{"subfo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RA, RB}},
4138{"subo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RB, RA}},
252b5132 4139
de866fcc 4140{"tlbsync", X(31,566), 0xffffffff, PPC, {0}},
252b5132 4141
de866fcc 4142{"lfsux", X(31,567), X_MASK, COM, {FRT, RAS, RB}},
252b5132 4143
de866fcc 4144{"lfsuxe", X(31,575), X_MASK, BOOKE64, {FRT, RAS, RB}},
252b5132 4145
19a6653c
AM		 4146{"lwdx", X(31,579), X_MASK, E500MC, {RT, RA, RB}},
4147
de866fcc 4148{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, {RT, SR}},
252b5132 4149
de866fcc
AM		 4150{"lswi", X(31,597), X_MASK, PPCCOM, {RT, RA0, NB}},
4151{"lsi", X(31,597), X_MASK, PWRCOM, {RT, RA0, NB}},
252b5132 4152
de866fcc
AM		 4153{"msync", X(31,598), 0xffffffff, BOOKE, {0}},
4154{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, {0}},
4155{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, {0}},
4156{"sync", X(31,598), XSYNC_MASK, PPCCOM, {LS}},
4157{"dcs", X(31,598), 0xffffffff, PWRCOM, {0}},
418c1742 4158
de866fcc 4159{"lfdx", X(31,599), X_MASK, COM, {FRT, RA0, RB}},
23976049 4160
de866fcc 4161{"lfdxe", X(31,607), X_MASK, BOOKE64, {FRT, RA0, RB}},
19a6653c 4162{"lfdepx", X(31,607), X_MASK, E500MC, {RT, RA, RB}},
de866fcc 4163{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, {FRT, RB}},
252b5132 4164
19a6653c
AM		 4165{"lddx", X(31,611), X_MASK, E500MC, {RT, RA, RB}},
4166
de866fcc
AM		 4167{"nego", XO(31,104,1,0), XORB_MASK, COM, {RT, RA}},
4168{"nego.", XO(31,104,1,1), XORB_MASK, COM, {RT, RA}},
252b5132 4169
de866fcc
AM		 4170{"mulo", XO(31,107,1,0), XO_MASK, M601, {RT, RA, RB}},
4171{"mulo.", XO(31,107,1,1), XO_MASK, M601, {RT, RA, RB}},
252b5132 4172
de866fcc 4173{"mfsri", X(31,627), X_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4174
de866fcc 4175{"dclst", X(31,630), XRB_MASK, PWRCOM, {RS, RA}},
252b5132 4176
de866fcc 4177{"lfdux", X(31,631), X_MASK, COM, {FRT, RAS, RB}},
252b5132 4178
de866fcc 4179{"lfduxe", X(31,639), X_MASK, BOOKE64, {FRT, RAS, RB}},
252b5132 4180
19a6653c
AM		 4181{"stbdx", X(31,643), X_MASK, E500MC, {RS, RA, RB}},
4182
de866fcc 4183{"stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}},
23976049 4184
de866fcc
AM		 4185{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4186{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4187{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4188{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4189
de866fcc
AM		 4190{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4191{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4192{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4193{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4194
de866fcc 4195{"mfsrin", X(31,659), XRA_MASK, PPC32, {RT, RB}},
418c1742 4196
de866fcc 4197{"stdbrx", X(31,660), X_MASK, CELL, {RS, RA0, RB}},
252b5132 4198
de866fcc
AM		 4199{"stswx", X(31,661), X_MASK, PPCCOM, {RS, RA0, RB}},
4200{"stsx", X(31,661), X_MASK, PWRCOM, {RS, RA0, RB}},
418c1742 4201
de866fcc
AM		 4202{"stwbrx", X(31,662), X_MASK, PPCCOM, {RS, RA0, RB}},
4203{"stbrx", X(31,662), X_MASK, PWRCOM, {RS, RA0, RB}},
252b5132 4204
de866fcc 4205{"stfsx", X(31,663), X_MASK, COM, {FRS, RA0, RB}},
ede602d7 4206
de866fcc
AM		 4207{"srq", XRC(31,664,0), X_MASK, M601, {RA, RS, RB}},
4208{"srq.", XRC(31,664,1), X_MASK, M601, {RA, RS, RB}},
252b5132 4209
de866fcc
AM		 4210{"sre", XRC(31,665,0), X_MASK, M601, {RA, RS, RB}},
4211{"sre.", XRC(31,665,1), X_MASK, M601, {RA, RS, RB}},
252b5132 4212
de866fcc 4213{"stwbrxe", X(31,670), X_MASK, BOOKE64, {RS, RA0, RB}},
252b5132 4214
de866fcc 4215{"stfsxe", X(31,671), X_MASK, BOOKE64, {FRS, RA0, RB}},
252b5132 4216
19a6653c
AM		 4217{"sthdx", X(31,675), X_MASK, E500MC, {RS, RA, RB}},
4218
de866fcc 4219{"stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}},
252b5132 4220
de866fcc 4221{"stfsux", X(31,695), X_MASK, COM, {FRS, RAS, RB}},
252b5132 4222
de866fcc
AM		 4223{"sriq", XRC(31,696,0), X_MASK, M601, {RA, RS, SH}},
4224{"sriq.", XRC(31,696,1), X_MASK, M601, {RA, RS, SH}},
252b5132 4225
de866fcc 4226{"stfsuxe", X(31,703), X_MASK, BOOKE64, {FRS, RAS, RB}},
418c1742 4227
19a6653c
AM		 4228{"stwdx", X(31,707), X_MASK, E500MC, {RS, RA, RB}},
4229
de866fcc
AM		 4230{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, {RT, RA}},
4231{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, {RT, RA}},
4232{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, {RT, RA}},
4233{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, {RT, RA}},
418c1742 4234
de866fcc
AM		 4235{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, {RT, RA}},
4236{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, {RT, RA}},
4237{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, {RT, RA}},
4238{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, {RT, RA}},
fdd12ef3 4239
de866fcc
AM		 4240{"stswi", X(31,725), X_MASK, PPCCOM, {RS, RA0, NB}},
4241{"stsi", X(31,725), X_MASK, PWRCOM, {RS, RA0, NB}},
252b5132 4242
de866fcc 4243{"stfdx", X(31,727), X_MASK, COM, {FRS, RA0, RB}},
252b5132 4244
de866fcc
AM		 4245{"srlq", XRC(31,728,0), X_MASK, M601, {RA, RS, RB}},
4246{"srlq.", XRC(31,728,1), X_MASK, M601, {RA, RS, RB}},
418c1742 4247
de866fcc
AM		 4248{"sreq", XRC(31,729,0), X_MASK, M601, {RA, RS, RB}},
4249{"sreq.", XRC(31,729,1), X_MASK, M601, {RA, RS, RB}},
252b5132 4250
de866fcc 4251{"stfdxe", X(31,735), X_MASK, BOOKE64, {FRS, RA0, RB}},
19a6653c 4252{"stfdepx", X(31,735), X_MASK, E500MC, {RS, RA, RB}},
de866fcc 4253{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, {RT, FRB}},
252b5132 4254
19a6653c
AM		 4255{"stddx", X(31,739), X_MASK, E500MC, {RS, RA, RB}},
4256
de866fcc
AM		 4257{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, {RT, RA}},
4258{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, {RT, RA}},
4259{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, {RT, RA}},
4260{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, {RT, RA}},
252b5132 4261
de866fcc
AM		 4262{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, {RT, RA, RB}},
4263{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, {RT, RA, RB}},
252b5132 4264
de866fcc
AM		 4265{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, {RT, RA}},
4266{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, {RT, RA}},
4267{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, {RT, RA}},
4268{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, {RT, RA}},
418c1742 4269
de866fcc
AM		 4270{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4271{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4272{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4273{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
702f0fb4 4274
de866fcc 4275{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, {RA, RB}},
19a6653c 4276{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, {RA, RB}},
252b5132 4277
de866fcc 4278{"stfdux", X(31,759), X_MASK, COM, {FRS, RAS, RB}},
252b5132 4279
de866fcc
AM		 4280{"srliq", XRC(31,760,0), X_MASK, M601, {RA, RS, SH}},
4281{"srliq.", XRC(31,760,1), X_MASK, M601, {RA, RS, SH}},
252b5132 4282
de866fcc 4283{"dcbae", X(31,766), XRT_MASK, BOOKE64, {RA, RB}},
418c1742 4284
de866fcc 4285{"stfduxe", X(31,767), X_MASK, BOOKE64, {FRS, RAS, RB}},
252b5132 4286
de866fcc 4287{"lvlxl", X(31,775), X_MASK, CELL, {VD, RA0, RB}},
ede602d7 4288
de866fcc
AM		 4289{"dozo", XO(31,264,1,0), XO_MASK, M601, {RT, RA, RB}},
4290{"dozo.", XO(31,264,1,1), XO_MASK, M601, {RT, RA, RB}},
252b5132 4291
de866fcc
AM		 4292{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
4293{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
4294{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
4295{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4296
de866fcc
AM		 4297{"tlbivax", X(31,786), XRT_MASK, BOOKE, {RA, RB}},
4298{"tlbivaxe", X(31,787), XRT_MASK, BOOKE64, {RA, RB}},
19a6653c
AM		 4299{"tlbilx", X(31,787), X_MASK, E500MC, {T, RA0, RB}},
4300{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, {0}},
4301{"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, {0}},
4302{"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, {RA0, RB}},
252b5132 4303
de866fcc 4304{"lwzcix", X(31,789), X_MASK, POWER6, {RT, RA0, RB}},
252b5132 4305
de866fcc 4306{"lhbrx", X(31,790), X_MASK, COM, {RT, RA0, RB}},
252b5132 4307
de866fcc
AM		 4308{"lfqx", X(31,791), X_MASK, POWER2, {FRT, RA, RB}},
4309{"lfdpx", X(31,791), X_MASK, POWER6, {FRT, RA, RB}},
418c1742 4310
de866fcc
AM		 4311{"sraw", XRC(31,792,0), X_MASK, PPCCOM, {RA, RS, RB}},
4312{"sra", XRC(31,792,0), X_MASK, PWRCOM, {RA, RS, RB}},
4313{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, {RA, RS, RB}},
4314{"sra.", XRC(31,792,1), X_MASK, PWRCOM, {RA, RS, RB}},
fdd12ef3 4315
de866fcc
AM		 4316{"srad", XRC(31,794,0), X_MASK, PPC64, {RA, RS, RB}},
4317{"srad.", XRC(31,794,1), X_MASK, PPC64, {RA, RS, RB}},
252b5132 4318
de866fcc 4319{"lhbrxe", X(31,798), X_MASK, BOOKE64, {RT, RA0, RB}},
252b5132 4320
de866fcc 4321{"ldxe", X(31,799), X_MASK, BOOKE64, {RT, RA0, RB}},
418c1742 4322
19a6653c
AM		 4323{"lfddx", X(31,803), X_MASK, E500MC, {FRT, RA, RB}},
4324
de866fcc 4325{"lvrxl", X(31,807), X_MASK, CELL, {VD, RA0, RB}},
252b5132 4326
de866fcc 4327{"rac", X(31,818), X_MASK, PWRCOM, {RT, RA, RB}},
252b5132 4328
de866fcc 4329{"lhzcix", X(31,821), X_MASK, POWER6, {RT, RA0, RB}},
252b5132 4330
de866fcc 4331{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, {STRM}},
252b5132 4332
de866fcc 4333{"lfqux", X(31,823), X_MASK, POWER2, {FRT, RA, RB}},
fdd12ef3 4334
de866fcc
AM		 4335{"srawi", XRC(31,824,0), X_MASK, PPCCOM, {RA, RS, SH}},
4336{"srai", XRC(31,824,0), X_MASK, PWRCOM, {RA, RS, SH}},
4337{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, {RA, RS, SH}},
4338{"srai.", XRC(31,824,1), X_MASK, PWRCOM, {RA, RS, SH}},
702f0fb4 4339
de866fcc
AM		 4340{"sradi", XS(31,413,0), XS_MASK, PPC64, {RA, RS, SH6}},
4341{"sradi.", XS(31,413,1), XS_MASK, PPC64, {RA, RS, SH6}},
e0c21649 4342
de866fcc
AM		 4343{"divo", XO(31,331,1,0), XO_MASK, M601, {RT, RA, RB}},
4344{"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}},
4345{"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}},
252b5132 4346
de866fcc 4347{"slbmfev", X(31,851), XRA_MASK, PPC64, {RT, RB}},
252b5132 4348
de866fcc 4349{"lbzcix", X(31,853), X_MASK, POWER6, {RT, RA0, RB}},
418c1742 4350
de866fcc
AM		 4351{"mbar", X(31,854), X_MASK, BOOKE, {MO}},
4352{"eieio", X(31,854), 0xffffffff, PPC, {0}},
418c1742 4353
de866fcc 4354{"lfiwax", X(31,855), X_MASK, POWER6, {FRT, RA0, RB}},
418c1742 4355
de866fcc
AM		 4356{"abso", XO(31,360,1,0), XORB_MASK, M601, {RT, RA}},
4357{"abso.", XO(31,360,1,1), XORB_MASK, M601, {RT, RA}},
702f0fb4 4358
de866fcc
AM		 4359{"divso", XO(31,363,1,0), XO_MASK, M601, {RT, RA, RB}},
4360{"divso.", XO(31,363,1,1), XO_MASK, M601, {RT, RA, RB}},
252b5132 4361
de866fcc 4362{"ldcix", X(31,885), X_MASK, POWER6, {RT, RA0, RB}},
252b5132 4363
de866fcc 4364{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}},
252b5132 4365
de866fcc 4366{"subfe64o", XO(31,392,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
418c1742 4367
de866fcc 4368{"adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
418c1742 4369
de866fcc
AM		 4370{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, {RTO, RA, RB}},
4371{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, {RTO, RA, RB}},
252b5132 4372
de866fcc
AM		 4373{"tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, {RTO, RA, RB}},
4374{"tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, {RTO, RA, RB}},
4375{"slbmfee", X(31,915), XRA_MASK, PPC64, {RT, RB}},
702f0fb4 4376
de866fcc 4377{"stwcix", X(31,917), X_MASK, POWER6, {RS, RA0, RB}},
f5c120c5 4378
de866fcc 4379{"sthbrx", X(31,918), X_MASK, COM, {RS, RA0, RB}},
252b5132 4380
de866fcc
AM		 4381{"stfqx", X(31,919), X_MASK, POWER2, {FRS, RA, RB}},
4382{"stfdpx", X(31,919), X_MASK, POWER6, {FRS, RA, RB}},
6ba045b1 4383
de866fcc
AM		 4384{"sraq", XRC(31,920,0), X_MASK, M601, {RA, RS, RB}},
4385{"sraq.", XRC(31,920,1), X_MASK, M601, {RA, RS, RB}},
702f0fb4 4386
de866fcc
AM		 4387{"srea", XRC(31,921,0), X_MASK, M601, {RA, RS, RB}},
4388{"srea.", XRC(31,921,1), X_MASK, M601, {RA, RS, RB}},
252b5132 4389
de866fcc
AM		 4390{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, {RA, RS}},
4391{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, {RA, RS}},
4392{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, {RA, RS}},
4393{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, {RA, RS}},
702f0fb4 4394
de866fcc 4395{"sthbrxe", X(31,926), X_MASK, BOOKE64, {RS, RA0, RB}},
702f0fb4 4396
de866fcc 4397{"stdxe", X(31,927), X_MASK, BOOKE64, {RS, RA0, RB}},
418c1742 4398
19a6653c
AM		 4399{"stfddx", X(31,931), X_MASK, E500MC, {FRS, RA, RB}},
4400
de866fcc 4401{"stvrxl", X(31,935), X_MASK, CELL, {VS, RA0, RB}},
6ba045b1 4402
de866fcc
AM		 4403{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, {RT, RA}},
4404{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, {RT, RA}},
4405{"tlbre", X(31,946), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}},
702f0fb4 4406
de866fcc 4407{"sthcix", X(31,949), X_MASK, POWER6, {RS, RA0, RB}},
252b5132 4408
de866fcc 4409{"stfqux", X(31,951), X_MASK, POWER2, {FRS, RA, RB}},
252b5132 4410
de866fcc
AM		 4411{"sraiq", XRC(31,952,0), X_MASK, M601, {RA, RS, SH}},
4412{"sraiq.", XRC(31,952,1), X_MASK, M601, {RA, RS, SH}},
252b5132 4413
de866fcc
AM		 4414{"extsb", XRC(31,954,0), XRB_MASK, PPC, {RA, RS}},
4415{"extsb.", XRC(31,954,1), XRB_MASK, PPC, {RA, RS}},
252b5132 4416
de866fcc 4417{"stduxe", X(31,959), X_MASK, BOOKE64, {RS, RAS, RB}},
418c1742 4418
de866fcc 4419{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, {RA, RB}},
418c1742 4420
de866fcc 4421{"subfze64o", XO(31,456,1,0), XORB_MASK, BOOKE64, {RT, RA}},
252b5132 4422
de866fcc
AM		 4423{"divduo", XO(31,457,1,0), XO_MASK, PPC64, {RT, RA, RB}},
4424{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, {RT, RA, RB}},
702f0fb4 4425
de866fcc 4426{"addze64o", XO(31,458,1,0), XORB_MASK, BOOKE64, {RT, RA}},
252b5132 4427
de866fcc
AM		 4428{"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}},
4429{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}},
252b5132 4430
de866fcc
AM		 4431{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, {RT, RA}},
4432{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, {RT, RA}},
4433{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}},
4434{"tlbld", X(31,978), XRTRA_MASK, PPC, {RB}},
418c1742 4435
de866fcc 4436{"stbcix", X(31,981), X_MASK, POWER6, {RS, RA0, RB}},
252b5132 4437
de866fcc 4438{"icbi", X(31,982), XRT_MASK, PPC, {RA, RB}},
252b5132 4439
de866fcc 4440{"stfiwx", X(31,983), X_MASK, PPC, {FRS, RA0, RB}},
702f0fb4 4441
de866fcc
AM		 4442{"extsw", XRC(31,986,0), XRB_MASK, PPC64|BOOKE64, {RA, RS}},
4443{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, {RA, RS}},
252b5132 4444
de866fcc
AM		 4445{"icbie", X(31,990), XRT_MASK, BOOKE64, {RA, RB}},
4446{"stfiwxe", X(31,991), X_MASK, BOOKE64, {FRS, RA0, RB}},
252b5132 4447
19a6653c
AM		 4448{"icbiep", XRT(31,991,0), XRT_MASK, E500MC, {RA, RB}},
4449
de866fcc 4450{"icread", X(31,998), XRT_MASK, PPC403|PPC440, {RA, RB}},
252b5132 4451
de866fcc
AM		 4452{"nabso", XO(31,488,1,0), XORB_MASK, M601, {RT, RA}},
4453{"subfme64o", XO(31,488,1,0), XORB_MASK, BOOKE64, {RT, RA}},
4454{"nabso.", XO(31,488,1,1), XORB_MASK, M601, {RT, RA}},
252b5132 4455
de866fcc
AM		 4456{"divdo", XO(31,489,1,0), XO_MASK, PPC64, {RT, RA, RB}},
4457{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, {RT, RA, RB}},
418c1742 4458
de866fcc 4459{"addme64o", XO(31,490,1,0), XORB_MASK, BOOKE64, {RT, RA}},
252b5132 4460
de866fcc
AM		 4461{"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}},
4462{"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}},
702f0fb4 4463
de866fcc 4464{"tlbli", X(31,1010), XRTRA_MASK, PPC, {RB}},
252b5132 4465
de866fcc 4466{"stdcix", X(31,1013), X_MASK, POWER6, {RS, RA0, RB}},
418c1742 4467
de866fcc
AM		 4468{"dcbz", X(31,1014), XRT_MASK, PPC, {RA, RB}},
4469{"dclz", X(31,1014), XRT_MASK, PPC, {RA, RB}},
786e2c0f 4470
de866fcc 4471{"dcbze", X(31,1022), XRT_MASK, BOOKE64, {RA, RB}},
19a6653c 4472{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, {RA, RB}},
ede602d7 4473
de866fcc 4474{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}},
19a6653c 4475{"dcbzl", XOPL(31,1014,1), XRT_MASK, NOPOWER4|E500MC,{RA, RB}},
252b5132 4476
de866fcc
AM		 4477{"cctpl", 0x7c210b78, 0xffffffff, CELL, {0}},
4478{"cctpm", 0x7c421378, 0xffffffff, CELL, {0}},
4479{"cctph", 0x7c631b78, 0xffffffff, CELL, {0}},
252b5132 4480
de866fcc
AM		 4481{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
4482{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
4483{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, {0}},
252b5132 4484
de866fcc
AM		 4485{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, {0}},
4486{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, {0}},
4487{"db12cyc", 0x7fdef378, 0xffffffff, CELL, {0}},
4488{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, {0}},
252b5132 4489
de866fcc
AM		 4490{"lwz", OP(32), OP_MASK, PPCCOM, {RT, D, RA0}},
4491{"l", OP(32), OP_MASK, PWRCOM, {RT, D, RA0}},
252b5132 4492
de866fcc
AM		 4493{"lwzu", OP(33), OP_MASK, PPCCOM, {RT, D, RAL}},
4494{"lu", OP(33), OP_MASK, PWRCOM, {RT, D, RA0}},
252b5132 4495
de866fcc 4496{"lbz", OP(34), OP_MASK, COM, {RT, D, RA0}},
252b5132 4497
de866fcc 4498{"lbzu", OP(35), OP_MASK, COM, {RT, D, RAL}},
252b5132 4499
de866fcc
AM		 4500{"stw", OP(36), OP_MASK, PPCCOM, {RS, D, RA0}},
4501{"st", OP(36), OP_MASK, PWRCOM, {RS, D, RA0}},
252b5132 4502
de866fcc
AM		 4503{"stwu", OP(37), OP_MASK, PPCCOM, {RS, D, RAS}},
4504{"stu", OP(37), OP_MASK, PWRCOM, {RS, D, RA0}},
252b5132 4505
de866fcc 4506{"stb", OP(38), OP_MASK, COM, {RS, D, RA0}},
252b5132 4507
de866fcc 4508{"stbu", OP(39), OP_MASK, COM, {RS, D, RAS}},
252b5132 4509
de866fcc 4510{"lhz", OP(40), OP_MASK, COM, {RT, D, RA0}},
252b5132 4511
de866fcc 4512{"lhzu", OP(41), OP_MASK, COM, {RT, D, RAL}},
252b5132 4513
de866fcc 4514{"lha", OP(42), OP_MASK, COM, {RT, D, RA0}},
252b5132 4515
de866fcc 4516{"lhau", OP(43), OP_MASK, COM, {RT, D, RAL}},
252b5132 4517
de866fcc 4518{"sth", OP(44), OP_MASK, COM, {RS, D, RA0}},
252b5132 4519
de866fcc 4520{"sthu", OP(45), OP_MASK, COM, {RS, D, RAS}},
252b5132 4521
de866fcc
AM		 4522{"lmw", OP(46), OP_MASK, PPCCOM, {RT, D, RAM}},
4523{"lm", OP(46), OP_MASK, PWRCOM, {RT, D, RA0}},
252b5132 4524
de866fcc
AM		 4525{"stmw", OP(47), OP_MASK, PPCCOM, {RS, D, RA0}},
4526{"stm", OP(47), OP_MASK, PWRCOM, {RS, D, RA0}},
252b5132 4527
de866fcc 4528{"lfs", OP(48), OP_MASK, COM, {FRT, D, RA0}},
252b5132 4529
de866fcc 4530{"lfsu", OP(49), OP_MASK, COM, {FRT, D, RAS}},
252b5132 4531
de866fcc 4532{"lfd", OP(50), OP_MASK, COM, {FRT, D, RA0}},
252b5132 4533
de866fcc 4534{"lfdu", OP(51), OP_MASK, COM, {FRT, D, RAS}},
252b5132 4535
de866fcc 4536{"stfs", OP(52), OP_MASK, COM, {FRS, D, RA0}},
adadcc0c 4537
de866fcc 4538{"stfsu", OP(53), OP_MASK, COM, {FRS, D, RAS}},
252b5132 4539
de866fcc 4540{"stfd", OP(54), OP_MASK, COM, {FRS, D, RA0}},
c3d65c1c 4541
de866fcc 4542{"stfdu", OP(55), OP_MASK, COM, {FRS, D, RAS}},
252b5132 4543
de866fcc 4544{"lq", OP(56), OP_MASK, POWER4, {RTQ, DQ, RAQ}},
c3d65c1c 4545
de866fcc 4546{"lfq", OP(56), OP_MASK, POWER2, {FRT, D, RA0}},
702f0fb4 4547
de866fcc 4548{"psq_l", OP(56), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}},
418c1742 4549
de866fcc 4550{"lfqu", OP(57), OP_MASK, POWER2, {FRT, D, RA0}},
802a735e 4551
de866fcc 4552{"psq_lu", OP(57), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}},
802a735e 4553
de866fcc 4554{"lfdp", OP(57), OP_MASK, POWER6, {FRT, D, RA0}},
fdd12ef3 4555
de866fcc
AM		 4556{"lbze", DEO(58,0), DE_MASK, BOOKE64, {RT, DE, RA0}},
4557{"lbzue", DEO(58,1), DE_MASK, BOOKE64, {RT, DE, RAL}},
4558{"lhze", DEO(58,2), DE_MASK, BOOKE64, {RT, DE, RA0}},
4559{"lhzue", DEO(58,3), DE_MASK, BOOKE64, {RT, DE, RAL}},
4560{"lhae", DEO(58,4), DE_MASK, BOOKE64, {RT, DE, RA0}},
4561{"lhaue", DEO(58,5), DE_MASK, BOOKE64, {RT, DE, RAL}},
4562{"lwze", DEO(58,6), DE_MASK, BOOKE64, {RT, DE, RA0}},
4563{"lwzue", DEO(58,7), DE_MASK, BOOKE64, {RT, DE, RAL}},
4564{"stbe", DEO(58,8), DE_MASK, BOOKE64, {RS, DE, RA0}},
4565{"stbue", DEO(58,9), DE_MASK, BOOKE64, {RS, DE, RAS}},
4566{"sthe", DEO(58,10), DE_MASK, BOOKE64, {RS, DE, RA0}},
4567{"sthue", DEO(58,11), DE_MASK, BOOKE64, {RS, DE, RAS}},
4568{"stwe", DEO(58,14), DE_MASK, BOOKE64, {RS, DE, RA0}},
4569{"stwue", DEO(58,15), DE_MASK, BOOKE64, {RS, DE, RAS}},
702f0fb4 4570
de866fcc
AM		 4571{"ld", DSO(58,0), DS_MASK, PPC64, {RT, DS, RA0}},
4572{"ldu", DSO(58,1), DS_MASK, PPC64, {RT, DS, RAL}},
4573{"lwa", DSO(58,2), DS_MASK, PPC64, {RT, DS, RA0}},
702f0fb4 4574
de866fcc
AM		 4575{"dadd", XRC(59,2,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4576{"dadd.", XRC(59,2,1), X_MASK, POWER6, {FRT, FRA, FRB}},
252b5132 4577
de866fcc
AM		 4578{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}},
4579{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}},
252b5132 4580
de866fcc
AM		 4581{"fdivs", A(59,18,0), AFRC_MASK, PPC, {FRT, FRA, FRB}},
4582{"fdivs.", A(59,18,1), AFRC_MASK, PPC, {FRT, FRA, FRB}},
252b5132 4583
de866fcc
AM		 4584{"fsubs", A(59,20,0), AFRC_MASK, PPC, {FRT, FRA, FRB}},
4585{"fsubs.", A(59,20,1), AFRC_MASK, PPC, {FRT, FRA, FRB}},
252b5132 4586
de866fcc
AM		 4587{"fadds", A(59,21,0), AFRC_MASK, PPC, {FRT, FRA, FRB}},
4588{"fadds.", A(59,21,1), AFRC_MASK, PPC, {FRT, FRA, FRB}},
252b5132 4589
de866fcc
AM		 4590{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, {FRT, FRB}},
4591{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, {FRT, FRB}},
252b5132 4592
de866fcc
AM		 4593{"fres", A(59,24,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
4594{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
1ed8e1e4 4595
de866fcc
AM		 4596{"fmuls", A(59,25,0), AFRB_MASK, PPC, {FRT, FRA, FRC}},
4597{"fmuls.", A(59,25,1), AFRB_MASK, PPC, {FRT, FRA, FRC}},
252b5132 4598
de866fcc
AM		 4599{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
4600{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
252b5132 4601
de866fcc
AM		 4602{"fmsubs", A(59,28,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
4603{"fmsubs.", A(59,28,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
252b5132 4604
de866fcc
AM		 4605{"fmadds", A(59,29,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
4606{"fmadds.", A(59,29,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
252b5132 4607
de866fcc
AM		 4608{"fnmsubs", A(59,30,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
4609{"fnmsubs.", A(59,30,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
702f0fb4 4610
de866fcc
AM		 4611{"fnmadds", A(59,31,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
4612{"fnmadds.", A(59,31,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
702f0fb4 4613
de866fcc
AM		 4614{"dmul", XRC(59,34,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4615{"dmul.", XRC(59,34,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4616
de866fcc
AM		 4617{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
4618{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
702f0fb4 4619
de866fcc
AM		 4620{"dscli", ZRC(59,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
4621{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
702f0fb4 4622
de866fcc
AM		 4623{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}},
4624{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}},
702f0fb4 4625
de866fcc
AM		 4626{"dscri", ZRC(59,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
4627{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
702f0fb4 4628
de866fcc
AM		 4629{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
4630{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
702f0fb4 4631
de866fcc 4632{"dcmpo", X(59,130), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4633
de866fcc
AM		 4634{"dtstex", X(59,162), X_MASK, POWER6, {BF, FRA, FRB}},
4635{"dtstdc", Z(59,194), Z_MASK, POWER6, {BF, FRA, DCM}},
4636{"dtstdg", Z(59,226), Z_MASK, POWER6, {BF, FRA, DGM}},
702f0fb4 4637
de866fcc
AM		 4638{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
4639{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
702f0fb4 4640
de866fcc
AM		 4641{"dctdp", XRC(59,258,0), X_MASK, POWER6, {FRT, FRB}},
4642{"dctdp.", XRC(59,258,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4643
de866fcc
AM		 4644{"dctfix", XRC(59,290,0), X_MASK, POWER6, {FRT, FRB}},
4645{"dctfix.", XRC(59,290,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4646
de866fcc
AM		 4647{"ddedpd", XRC(59,322,0), X_MASK, POWER6, {SP, FRT, FRB}},
4648{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, {SP, FRT, FRB}},
702f0fb4 4649
de866fcc
AM		 4650{"dxex", XRC(59,354,0), X_MASK, POWER6, {FRT, FRB}},
4651{"dxex.", XRC(59,354,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4652
de866fcc
AM		 4653{"dsub", XRC(59,514,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4654{"dsub.", XRC(59,514,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4655
de866fcc
AM		 4656{"ddiv", XRC(59,546,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4657{"ddiv.", XRC(59,546,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4658
de866fcc 4659{"dcmpu", X(59,642), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4660
de866fcc 4661{"dtstsf", X(59,674), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4662
de866fcc
AM		 4663{"drsp", XRC(59,770,0), X_MASK, POWER6, {FRT, FRB}},
4664{"drsp.", XRC(59,770,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4665
de866fcc
AM		 4666{"denbcd", XRC(59,834,0), X_MASK, POWER6, {S, FRT, FRB}},
4667{"denbcd.", XRC(59,834,1), X_MASK, POWER6, {S, FRT, FRB}},
252b5132 4668
de866fcc
AM		 4669{"diex", XRC(59,866,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4670{"diex.", XRC(59,866,1), X_MASK, POWER6, {FRT, FRA, FRB}},
8dbcd839 4671
de866fcc 4672{"stfq", OP(60), OP_MASK, POWER2, {FRS, D, RA}},
252b5132 4673
de866fcc
AM		 4674{"psq_st", OP(60), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
4675{"psq_stu", OP(61), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
702f0fb4 4676
de866fcc 4677{"stfqu", OP(61), OP_MASK, POWER2, {FRS, D, RA}},
418c1742 4678
de866fcc 4679{"stfdp", OP(61), OP_MASK, POWER6, {FRT, D, RA0}},
802a735e 4680
de866fcc
AM		 4681{"lde", DEO(62,0), DE_MASK, BOOKE64, {RT, DES, RA0}},
4682{"ldue", DEO(62,1), DE_MASK, BOOKE64, {RT, DES, RA0}},
4683{"lfse", DEO(62,4), DE_MASK, BOOKE64, {FRT, DES, RA0}},
4684{"lfsue", DEO(62,5), DE_MASK, BOOKE64, {FRT, DES, RAS}},
4685{"lfde", DEO(62,6), DE_MASK, BOOKE64, {FRT, DES, RA0}},
4686{"lfdue", DEO(62,7), DE_MASK, BOOKE64, {FRT, DES, RAS}},
4687{"stde", DEO(62,8), DE_MASK, BOOKE64, {RS, DES, RA0}},
4688{"stdue", DEO(62,9), DE_MASK, BOOKE64, {RS, DES, RAS}},
4689{"stfse", DEO(62,12), DE_MASK, BOOKE64, {FRS, DES, RA0}},
4690{"stfsue", DEO(62,13), DE_MASK, BOOKE64, {FRS, DES, RAS}},
4691{"stfde", DEO(62,14), DE_MASK, BOOKE64, {FRS, DES, RA0}},
4692{"stfdue", DEO(62,15), DE_MASK, BOOKE64, {FRS, DES, RAS}},
802a735e 4693
de866fcc
AM		 4694{"std", DSO(62,0), DS_MASK, PPC64, {RS, DS, RA0}},
4695{"stdu", DSO(62,1), DS_MASK, PPC64, {RS, DS, RAS}},
4696{"stq", DSO(62,2), DS_MASK, POWER4, {RSQ, DS, RA0}},
fdd12ef3 4697
de866fcc 4698{"fcmpu", X(63,0), X_MASK|(3<<21), COM, {BF, FRA, FRB}},
252b5132 4699
de866fcc
AM		 4700{"daddq", XRC(63,2,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4701{"daddq.", XRC(63,2,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4702
de866fcc
AM		 4703{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
4704{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
702f0fb4 4705
de866fcc
AM		 4706{"fcpsgn", XRC(63,8,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4707{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4708
de866fcc
AM		 4709{"frsp", XRC(63,12,0), XRA_MASK, COM, {FRT, FRB}},
4710{"frsp.", XRC(63,12,1), XRA_MASK, COM, {FRT, FRB}},
252b5132 4711
de866fcc
AM		 4712{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, {FRT, FRB}},
4713{"fcir", XRC(63,14,0), XRA_MASK, POWER2, {FRT, FRB}},
4714{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, {FRT, FRB}},
4715{"fcir.", XRC(63,14,1), XRA_MASK, POWER2, {FRT, FRB}},
252b5132 4716
de866fcc
AM		 4717{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, {FRT, FRB}},
4718{"fcirz", XRC(63,15,0), XRA_MASK, POWER2, {FRT, FRB}},
4719{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, {FRT, FRB}},
4720{"fcirz.", XRC(63,15,1), XRA_MASK, POWER2, {FRT, FRB}},
252b5132 4721
de866fcc
AM		 4722{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4723{"fd", A(63,18,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
4724{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4725{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
252b5132 4726
de866fcc
AM		 4727{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4728{"fs", A(63,20,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
4729{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4730{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
252b5132 4731
de866fcc
AM		 4732{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4733{"fa", A(63,21,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
4734{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}},
4735{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}},
252b5132 4736
de866fcc
AM		 4737{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}},
4738{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}},
252b5132 4739
de866fcc
AM		 4740{"fsel", A(63,23,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
4741{"fsel.", A(63,23,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}},
252b5132 4742
de866fcc
AM		 4743{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
4744{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}},
1ed8e1e4 4745
de866fcc
AM		 4746{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}},
4747{"fm", A(63,25,0), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}},
4748{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}},
4749{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}},
252b5132 4750
de866fcc
AM		 4751{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
4752{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}},
252b5132 4753
de866fcc
AM		 4754{"fmsub", A(63,28,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4755{"fms", A(63,28,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
4756{"fmsub.", A(63,28,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4757{"fms.", A(63,28,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
252b5132 4758
de866fcc
AM		 4759{"fmadd", A(63,29,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4760{"fma", A(63,29,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
4761{"fmadd.", A(63,29,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4762{"fma.", A(63,29,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
252b5132 4763
de866fcc
AM		 4764{"fnmsub", A(63,30,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4765{"fnms", A(63,30,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
4766{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4767{"fnms.", A(63,30,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
252b5132 4768
de866fcc
AM		 4769{"fnmadd", A(63,31,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4770{"fnma", A(63,31,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
4771{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}},
4772{"fnma.", A(63,31,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}},
252b5132 4773
de866fcc 4774{"fcmpo", X(63,32), X_MASK|(3<<21), COM, {BF, FRA, FRB}},
252b5132 4775
de866fcc
AM		 4776{"dmulq", XRC(63,34,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4777{"dmulq.", XRC(63,34,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4778
de866fcc
AM		 4779{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
4780{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}},
702f0fb4 4781
de866fcc
AM		 4782{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, {BT}},
4783{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, {BT}},
252b5132 4784
de866fcc
AM		 4785{"fneg", XRC(63,40,0), XRA_MASK, COM, {FRT, FRB}},
4786{"fneg.", XRC(63,40,1), XRA_MASK, COM, {FRT, FRB}},
252b5132 4787
de866fcc 4788{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}},
252b5132 4789
de866fcc
AM		 4790{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
4791{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
702f0fb4 4792
de866fcc
AM		 4793{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}},
4794{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}},
702f0fb4 4795
de866fcc
AM		 4796{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, {BT}},
4797{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, {BT}},
252b5132 4798
de866fcc
AM		 4799{"fmr", XRC(63,72,0), XRA_MASK, COM, {FRT, FRB}},
4800{"fmr.", XRC(63,72,1), XRA_MASK, COM, {FRT, FRB}},
252b5132 4801
de866fcc
AM		 4802{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
4803{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
702f0fb4 4804
de866fcc
AM		 4805{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
4806{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
702f0fb4 4807
de866fcc 4808{"dcmpoq", X(63,130), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4809
de866fcc
AM		 4810{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}},
4811{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}},
252b5132 4812
de866fcc
AM		 4813{"fnabs", XRC(63,136,0), XRA_MASK, COM, {FRT, FRB}},
4814{"fnabs.", XRC(63,136,1), XRA_MASK, COM, {FRT, FRB}},
252b5132 4815
de866fcc
AM		 4816{"dtstexq", X(63,162), X_MASK, POWER6, {BF, FRA, FRB}},
4817{"dtstdcq", Z(63,194), Z_MASK, POWER6, {BF, FRA, DCM}},
4818{"dtstdgq", Z(63,226), Z_MASK, POWER6, {BF, FRA, DGM}},
702f0fb4 4819
de866fcc
AM		 4820{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
4821{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}},
702f0fb4 4822
de866fcc
AM		 4823{"dctqpq", XRC(63,258,0), X_MASK, POWER6, {FRT, FRB}},
4824{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4825
de866fcc
AM		 4826{"fabs", XRC(63,264,0), XRA_MASK, COM, {FRT, FRB}},
4827{"fabs.", XRC(63,264,1), XRA_MASK, COM, {FRT, FRB}},
252b5132 4828
de866fcc
AM		 4829{"dctfixq", XRC(63,290,0), X_MASK, POWER6, {FRT, FRB}},
4830{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4831
de866fcc
AM		 4832{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, {SP, FRT, FRB}},
4833{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, {SP, FRT, FRB}},
702f0fb4 4834
de866fcc
AM		 4835{"dxexq", XRC(63,354,0), X_MASK, POWER6, {FRT, FRB}},
4836{"dxexq.", XRC(63,354,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4837
de866fcc
AM		 4838{"frin", XRC(63,392,0), XRA_MASK, POWER5, {FRT, FRB}},
4839{"frin.", XRC(63,392,1), XRA_MASK, POWER5, {FRT, FRB}},
4840{"friz", XRC(63,424,0), XRA_MASK, POWER5, {FRT, FRB}},
4841{"friz.", XRC(63,424,1), XRA_MASK, POWER5, {FRT, FRB}},
4842{"frip", XRC(63,456,0), XRA_MASK, POWER5, {FRT, FRB}},
4843{"frip.", XRC(63,456,1), XRA_MASK, POWER5, {FRT, FRB}},
4844{"frim", XRC(63,488,0), XRA_MASK, POWER5, {FRT, FRB}},
4845{"frim.", XRC(63,488,1), XRA_MASK, POWER5, {FRT, FRB}},
ce7a772b 4846
de866fcc
AM		 4847{"dsubq", XRC(63,514,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4848{"dsubq.", XRC(63,514,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4849
de866fcc
AM		 4850{"ddivq", XRC(63,546,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4851{"ddivq.", XRC(63,546,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4852
de866fcc
AM		 4853{"mffs", XRC(63,583,0), XRARB_MASK, COM, {FRT}},
4854{"mffs.", XRC(63,583,1), XRARB_MASK, COM, {FRT}},
252b5132 4855
de866fcc 4856{"dcmpuq", X(63,642), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4857
de866fcc 4858{"dtstsfq", X(63,674), X_MASK, POWER6, {BF, FRA, FRB}},
702f0fb4 4859
de866fcc
AM		 4860{"mtfsf", XFL(63,711,0), XFL_MASK, COM, {FLM, FRB, XFL_L, W}},
4861{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, {FLM, FRB, XFL_L, W}},
252b5132 4862
de866fcc
AM		 4863{"drdpq", XRC(63,770,0), X_MASK, POWER6, {FRT, FRB}},
4864{"drdpq.", XRC(63,770,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4865
de866fcc
AM		 4866{"dcffixq", XRC(63,802,0), X_MASK, POWER6, {FRT, FRB}},
4867{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, {FRT, FRB}},
702f0fb4 4868
de866fcc
AM		 4869{"fctid", XRC(63,814,0), XRA_MASK, PPC64, {FRT, FRB}},
4870{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, {FRT, FRB}},
252b5132 4871
de866fcc
AM		 4872{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, {FRT, FRB}},
4873{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, {FRT, FRB}},
252b5132 4874
de866fcc
AM		 4875{"denbcdq", XRC(63,834,0), X_MASK, POWER6, {S, FRT, FRB}},
4876{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, {S, FRT, FRB}},
702f0fb4 4877
de866fcc
AM		 4878{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, {FRT, FRB}},
4879{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, {FRT, FRB}},
252b5132 4880
de866fcc
AM		 4881{"diexq", XRC(63,866,0), X_MASK, POWER6, {FRT, FRA, FRB}},
4882{"diexq.", XRC(63,866,1), X_MASK, POWER6, {FRT, FRA, FRB}},
702f0fb4 4883
252b5132
RH		 4884};
4885
4886const int powerpc_num_opcodes =
4887 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4888\f
4889/* The macro table. This is only used by the assembler. */
4890
4891/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4892 when x=0; 32-x when x is between 1 and 31; are negative if x is
4893 negative; and are 32 or more otherwise. This is what you want
4894 when, for instance, you are emulating a right shift by a
4895 rotate-left-and-mask, because the underlying instructions support
4896 shifts of size 0 but not shifts of size 32. By comparison, when
4897 extracting x bits from some word you want to use just 32-x, because
4898 the underlying instructions don't support extracting 0 bits but do
4899 support extracting the whole word (32 bits in this case). */
4900
4901const struct powerpc_macro powerpc_macros[] = {
de866fcc
AM		 4902{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
4903{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
4904{"extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)"},
4905{"extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)"},
4906{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
4907{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
4908{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
4909{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
4910{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
4911{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
4912{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
4913{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
4914{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
4915{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
4916{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
4917{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
4918
4919{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
4920{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
4921{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
4922{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
4923{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4924{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4925{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4926{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4927{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
4928{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
4929{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
4930{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
4931{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
4932{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
4933{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4934{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4935{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4936{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4937{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
4938{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
4939{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
4940{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
252b5132
RH		 4941};
4942
4943const int powerpc_num_macros =
4944 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
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