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e23eba97 | 1 | /* RISC-V opcode list |
fd67aa11 | 2 | Copyright (C) 2011-2024 Free Software Foundation, Inc. |
e23eba97 NC |
3 | |
4 | Contributed by Andrew Waterman (andrew@sifive.com). | |
5 | Based on MIPS target. | |
6 | ||
7 | This file is part of the GNU opcodes library. | |
8 | ||
9 | This library is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | It is distributed in the hope that it will be useful, but WITHOUT | |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "sysdep.h" | |
24 | #include "opcode/riscv.h" | |
25 | #include <stdio.h> | |
26 | ||
27 | /* Register names used by gas and objdump. */ | |
28 | ||
02a63525 | 29 | const char riscv_gpr_names_numeric[NGPR][NRC] = |
e23eba97 NC |
30 | { |
31 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
32 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
33 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
34 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31" | |
35 | }; | |
36 | ||
02a63525 | 37 | const char riscv_gpr_names_abi[NGPR][NRC] = |
1942a048 NC |
38 | { |
39 | "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", | |
40 | "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", | |
41 | "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", | |
42 | "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" | |
e23eba97 NC |
43 | }; |
44 | ||
02a63525 | 45 | const char riscv_fpr_names_numeric[NFPR][NRC] = |
e23eba97 NC |
46 | { |
47 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
48 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
49 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
50 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
51 | }; | |
52 | ||
02a63525 | 53 | const char riscv_fpr_names_abi[NFPR][NRC] = |
1942a048 NC |
54 | { |
55 | "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", | |
56 | "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", | |
57 | "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", | |
58 | "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" | |
e23eba97 NC |
59 | }; |
60 | ||
3d9d92c2 TO |
61 | /* Rounding modes. */ |
62 | const char * const riscv_rm[8] = | |
63 | { | |
64 | "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" | |
65 | }; | |
66 | ||
67 | /* FENCE: predecessor/successor sets. */ | |
68 | const char * const riscv_pred_succ[16] = | |
69 | { | |
70 | 0, "w", "r", "rw", "o", "ow", "or", "orw", | |
71 | "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw" | |
72 | }; | |
73 | ||
65e4a99a | 74 | /* RVV registers. */ |
02a63525 | 75 | const char riscv_vecr_names_numeric[NVECR][NRC] = |
65e4a99a NC |
76 | { |
77 | "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", | |
78 | "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", | |
79 | "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", | |
80 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" | |
81 | }; | |
82 | ||
83 | /* RVV mask registers. */ | |
02a63525 | 84 | const char riscv_vecm_names_numeric[NVECM][NRC] = |
65e4a99a NC |
85 | { |
86 | "v0.t" | |
87 | }; | |
88 | ||
89 | /* The vsetvli vsew constants. */ | |
90 | const char * const riscv_vsew[8] = | |
91 | { | |
ee083a9e | 92 | "e8", "e16", "e32", "e64", NULL, NULL, NULL, NULL |
65e4a99a NC |
93 | }; |
94 | ||
95 | /* The vsetvli vlmul constants. */ | |
96 | const char * const riscv_vlmul[8] = | |
97 | { | |
ee083a9e | 98 | "m1", "m2", "m4", "m8", NULL, "mf8", "mf4", "mf2" |
65e4a99a NC |
99 | }; |
100 | ||
101 | /* The vsetvli vta constants. */ | |
102 | const char * const riscv_vta[2] = | |
103 | { | |
104 | "tu", "ta" | |
105 | }; | |
106 | ||
107 | /* The vsetvli vma constants. */ | |
108 | const char * const riscv_vma[2] = | |
109 | { | |
110 | "mu", "ma" | |
111 | }; | |
112 | ||
6a95962e JM |
113 | /* XTheadVector, List of vsetvli vlmul constants. */ |
114 | const char * const riscv_th_vlen[4] = | |
115 | { | |
116 | "m1", "m2", "m4", "m8" | |
117 | }; | |
118 | ||
119 | /* XTheadVector, List of vsetvli vediv constants. */ | |
120 | const char * const riscv_th_vediv[4] = | |
121 | { | |
122 | "d1", "d2", "d4", "d8" | |
123 | }; | |
124 | ||
1f3fc45b CM |
125 | /* The FLI.[HSDQ] symbolic constants (NULL for numeric constant). */ |
126 | const char * const riscv_fli_symval[32] = | |
127 | { | |
128 | NULL, "min", NULL, NULL, NULL, NULL, NULL, NULL, | |
129 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
130 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
131 | NULL, NULL, NULL, NULL, NULL, NULL, "inf", "nan", | |
132 | }; | |
133 | ||
134 | /* The FLI.[HSDQ] numeric constants (0.0 for symbolic constants). | |
135 | The constants use the hex floating-point literal representation | |
136 | that is printed when using the printf %a format specifier, | |
137 | which matches the output that is generated by the disassembler. */ | |
138 | const float riscv_fli_numval[32] = | |
139 | { | |
140 | -0x1p+0, 0x0p+0, 0x1p-16, 0x1p-15, 0x1p-8, 0x1p-7, 0x1p-4, 0x1p-3, | |
141 | 0x1p-2, 0x1.4p-2, 0x1.8p-2, 0x1.cp-2, 0x1p-1, 0x1.4p-1, 0x1.8p-1, 0x1.cp-1, | |
142 | 0x1p+0, 0x1.4p+0, 0x1.8p+0, 0x1.cp+0, 0x1p+1, 0x1.4p+1, 0x1.8p+1, 0x1p+2, | |
143 | 0x1p+3, 0x1p+4, 0x1p+7, 0x1p+8, 0x1p+15, 0x1p+16, 0x0p+0, 0x0p+0 | |
144 | }; | |
145 | ||
e23eba97 NC |
146 | #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) |
147 | #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) | |
148 | #define MASK_RD (OP_MASK_RD << OP_SH_RD) | |
149 | #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) | |
1d65abb5 | 150 | #define MASK_IMM ENCODE_ITYPE_IMM (-1U) |
5a9f5403 | 151 | #define MASK_RVC_IMM ENCODE_CITYPE_IMM (-1U) |
1d65abb5 | 152 | #define MASK_UIMM ENCODE_UTYPE_IMM (-1U) |
e23eba97 NC |
153 | #define MASK_RM (OP_MASK_RM << OP_SH_RM) |
154 | #define MASK_PRED (OP_MASK_PRED << OP_SH_PRED) | |
155 | #define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC) | |
156 | #define MASK_AQ (OP_MASK_AQ << OP_SH_AQ) | |
157 | #define MASK_RL (OP_MASK_RL << OP_SH_RL) | |
158 | #define MASK_AQRL (MASK_AQ | MASK_RL) | |
80d49d6a KLC |
159 | #define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT) |
160 | #define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT) | |
161 | #define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT) | |
3d1cafa0 | 162 | #define MATCH_SHAMT_BREV8 (0b00111 << OP_SH_SHAMT) |
163 | #define MATCH_SHAMT_ZIP_32 (0b1111 << OP_SH_SHAMT) | |
80d49d6a | 164 | #define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT) |
65e4a99a NC |
165 | #define MASK_VD (OP_MASK_VD << OP_SH_VD) |
166 | #define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1) | |
167 | #define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2) | |
168 | #define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK) | |
ccb388ca MB |
169 | /* Vendor-specific (CORE-V) masks. */ |
170 | #define MASK_CV_IS3_UIMM5 ENCODE_CV_IS3_UIMM5 (-1U) | |
e23eba97 NC |
171 | |
172 | static int | |
173 | match_opcode (const struct riscv_opcode *op, insn_t insn) | |
174 | { | |
175 | return ((insn ^ op->match) & op->mask) == 0; | |
176 | } | |
177 | ||
e23eba97 NC |
178 | static int |
179 | match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn) | |
180 | { | |
181 | int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; | |
182 | int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; | |
183 | return match_opcode (op, insn) && rs1 == rs2; | |
184 | } | |
185 | ||
186 | static int | |
187 | match_rd_nonzero (const struct riscv_opcode *op, insn_t insn) | |
188 | { | |
27b33966 JB |
189 | return (op->pinfo == INSN_MACRO || match_opcode (op, insn)) |
190 | && ((insn & MASK_RD) != 0); | |
191 | } | |
192 | ||
193 | static int | |
194 | match_rs1_nonzero (const struct riscv_opcode *op ATTRIBUTE_UNUSED, insn_t insn) | |
195 | { | |
196 | return (insn & MASK_RS1) != 0; | |
e23eba97 NC |
197 | } |
198 | ||
199 | static int | |
200 | match_c_add (const struct riscv_opcode *op, insn_t insn) | |
201 | { | |
202 | return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0); | |
203 | } | |
204 | ||
21a186f2 JW |
205 | /* We don't allow mv zero,X to become a c.mv hint, so we need a separate |
206 | matching function for this. */ | |
207 | ||
208 | static int | |
209 | match_c_add_with_hint (const struct riscv_opcode *op, insn_t insn) | |
210 | { | |
211 | return match_opcode (op, insn) && ((insn & MASK_CRS2) != 0); | |
212 | } | |
213 | ||
2721d702 JW |
214 | static int |
215 | match_c_nop (const struct riscv_opcode *op, insn_t insn) | |
216 | { | |
217 | return (match_opcode (op, insn) | |
218 | && (((insn & MASK_RD) >> OP_SH_RD) == 0)); | |
219 | } | |
220 | ||
63a25ea0 AW |
221 | static int |
222 | match_c_addi16sp (const struct riscv_opcode *op, insn_t insn) | |
223 | { | |
224 | return (match_opcode (op, insn) | |
5a9f5403 | 225 | && (((insn & MASK_RD) >> OP_SH_RD) == 2)); |
63a25ea0 AW |
226 | } |
227 | ||
e23eba97 NC |
228 | static int |
229 | match_c_lui (const struct riscv_opcode *op, insn_t insn) | |
230 | { | |
63a25ea0 AW |
231 | return (match_rd_nonzero (op, insn) |
232 | && (((insn & MASK_RD) >> OP_SH_RD) != 2) | |
5a9f5403 | 233 | && EXTRACT_CITYPE_LUI_IMM (insn) != 0); |
63a25ea0 AW |
234 | } |
235 | ||
21a186f2 JW |
236 | /* We don't allow lui zero,X to become a c.lui hint, so we need a separate |
237 | matching function for this. */ | |
238 | ||
239 | static int | |
240 | match_c_lui_with_hint (const struct riscv_opcode *op, insn_t insn) | |
241 | { | |
242 | return (match_opcode (op, insn) | |
243 | && (((insn & MASK_RD) >> OP_SH_RD) != 2) | |
5a9f5403 | 244 | && EXTRACT_CITYPE_LUI_IMM (insn) != 0); |
21a186f2 JW |
245 | } |
246 | ||
63a25ea0 AW |
247 | static int |
248 | match_c_addi4spn (const struct riscv_opcode *op, insn_t insn) | |
249 | { | |
5a9f5403 | 250 | return match_opcode (op, insn) && EXTRACT_CIWTYPE_ADDI4SPN_IMM (insn) != 0; |
e23eba97 NC |
251 | } |
252 | ||
e6f372ba JW |
253 | /* This requires a non-zero shift. A zero rd is a hint, so is allowed. */ |
254 | ||
255 | static int | |
256 | match_c_slli (const struct riscv_opcode *op, insn_t insn) | |
257 | { | |
5a9f5403 | 258 | return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0; |
e6f372ba JW |
259 | } |
260 | ||
261 | /* This requires a non-zero rd, and a non-zero shift. */ | |
262 | ||
263 | static int | |
264 | match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn) | |
265 | { | |
5a9f5403 | 266 | return match_rd_nonzero (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0; |
e6f372ba JW |
267 | } |
268 | ||
269 | /* This requires a zero shift. A zero rd is a hint, so is allowed. */ | |
270 | ||
271 | static int | |
272 | match_c_slli64 (const struct riscv_opcode *op, insn_t insn) | |
273 | { | |
5a9f5403 | 274 | return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) == 0; |
e6f372ba JW |
275 | } |
276 | ||
277 | /* This is used for both srli and srai. This requires a non-zero shift. | |
278 | A zero rd is not possible. */ | |
279 | ||
280 | static int | |
281 | match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn) | |
282 | { | |
5a9f5403 | 283 | return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0; |
e6f372ba JW |
284 | } |
285 | ||
65e4a99a NC |
286 | static int |
287 | match_vs1_eq_vs2 (const struct riscv_opcode *op, | |
288 | insn_t insn) | |
289 | { | |
290 | int vs1 = (insn & MASK_VS1) >> OP_SH_VS1; | |
291 | int vs2 = (insn & MASK_VS2) >> OP_SH_VS2; | |
292 | ||
293 | return match_opcode (op, insn) && vs1 == vs2; | |
294 | } | |
295 | ||
296 | static int | |
297 | match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op, | |
298 | insn_t insn) | |
299 | { | |
300 | int vd = (insn & MASK_VD) >> OP_SH_VD; | |
301 | int vs1 = (insn & MASK_VS1) >> OP_SH_VS1; | |
302 | int vs2 = (insn & MASK_VS2) >> OP_SH_VS2; | |
303 | ||
304 | return match_opcode (op, insn) && vd == vs1 && vs1 == vs2; | |
305 | } | |
306 | ||
27cfd142 CM |
307 | static int |
308 | match_th_load_inc(const struct riscv_opcode *op, | |
309 | insn_t insn) | |
310 | { | |
311 | /* Load-increment has the following restriction: | |
312 | * The values of rd and rs1 must not be the same. */ | |
313 | int rd = (insn & MASK_RD) >> OP_SH_RD; | |
314 | int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; | |
315 | ||
316 | return rd != rs1 && match_opcode (op, insn); | |
317 | } | |
318 | ||
6e17ae62 CM |
319 | static int |
320 | match_th_load_pair(const struct riscv_opcode *op, | |
321 | insn_t insn) | |
322 | { | |
323 | /* Load pair instructions use the following encoding: | |
324 | * - rd1 = RD (insn[11:7]) | |
325 | * - rd2 = RS2 (insn[24:20]) | |
326 | * - rs = RS1 ([19:15]) | |
327 | * This function matches if the following restriction is met: | |
328 | * The values of rd1, rd2, and rs1 must not be the same. */ | |
329 | int rd1 = (insn & MASK_RD) >> OP_SH_RD; | |
330 | int rd2 = (insn & MASK_RS2) >> OP_SH_RS2; | |
331 | int rs = (insn & MASK_RS1) >> OP_SH_RS1; | |
332 | ||
333 | return rd1 != rd2 && rd1 != rs && rd2 != rs && match_opcode (op, insn); | |
334 | } | |
335 | ||
8d27b09d JB |
336 | /* The order of overloaded instructions matters. Label arguments and |
337 | register arguments look the same. Instructions that can have either | |
338 | for arguments must apear in the correct order in this table for the | |
339 | assembler to pick the right one. In other words, entries with | |
340 | immediate operands must apear after the same instruction with | |
341 | registers. | |
342 | ||
343 | Because of the lookup algorithm used, entries with the same opcode | |
344 | name must be contiguous. */ | |
345 | ||
e23eba97 NC |
346 | const struct riscv_opcode riscv_opcodes[] = |
347 | { | |
dcd709e0 | 348 | /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ |
cda4092e TO |
349 | |
350 | /* Standard hints. */ | |
54bca63b TO |
351 | {"prefetch.i", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, |
352 | {"prefetch.r", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, | |
353 | {"prefetch.w", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, | |
2266f863 TO |
354 | {"ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_P1, MASK_C_NTL_P1, match_opcode, INSN_ALIAS }, |
355 | {"ntl.p1", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_P1, MASK_NTL_P1, match_opcode, 0 }, | |
356 | {"ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_PALL, MASK_C_NTL_PALL, match_opcode, INSN_ALIAS }, | |
357 | {"ntl.pall", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_PALL, MASK_NTL_PALL, match_opcode, 0 }, | |
358 | {"ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_S1, MASK_C_NTL_S1, match_opcode, INSN_ALIAS }, | |
359 | {"ntl.s1", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_S1, MASK_NTL_S1, match_opcode, 0 }, | |
360 | {"ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_ALL, MASK_C_NTL_ALL, match_opcode, INSN_ALIAS }, | |
361 | {"ntl.all", 0, INSN_CLASS_ZIHINTNTL, "", MATCH_NTL_ALL, MASK_NTL_ALL, match_opcode, 0 }, | |
362 | {"c.ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_P1, MASK_C_NTL_P1, match_opcode, 0 }, | |
363 | {"c.ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_PALL, MASK_C_NTL_PALL, match_opcode, 0 }, | |
364 | {"c.ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_S1, MASK_C_NTL_S1, match_opcode, 0 }, | |
365 | {"c.ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_C, "", MATCH_C_NTL_ALL, MASK_C_NTL_ALL, match_opcode, 0 }, | |
cda4092e TO |
366 | {"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, |
367 | ||
368 | /* Basic RVI instructions and aliases. */ | |
1942a048 NC |
369 | {"unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, INSN_ALIAS }, |
370 | {"unimp", 0, INSN_CLASS_I, "", MATCH_CSRRW|(CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ | |
371 | {"ebreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, | |
372 | {"ebreak", 0, INSN_CLASS_I, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 }, | |
373 | {"sbreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, | |
374 | {"sbreak", 0, INSN_CLASS_I, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS }, | |
375 | {"ret", 0, INSN_CLASS_C, "", MATCH_C_JR|(X_RA << OP_SH_RD), MASK_C_JR|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, | |
376 | {"ret", 0, INSN_CLASS_I, "", MATCH_JALR|(X_RA << OP_SH_RS1), MASK_JALR|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH }, | |
377 | {"jr", 0, INSN_CLASS_C, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS|INSN_BRANCH }, | |
378 | {"jr", 0, INSN_CLASS_I, "s", MATCH_JALR, MASK_JALR|MASK_RD|MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH }, | |
379 | {"jr", 0, INSN_CLASS_I, "o(s)", MATCH_JALR, MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, | |
380 | {"jr", 0, INSN_CLASS_I, "s,j", MATCH_JALR, MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, | |
381 | {"jalr", 0, INSN_CLASS_C, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS|INSN_JSR }, | |
382 | {"jalr", 0, INSN_CLASS_I, "s", MATCH_JALR|(X_RA << OP_SH_RD), MASK_JALR|MASK_RD|MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR }, | |
383 | {"jalr", 0, INSN_CLASS_I, "o(s)", MATCH_JALR|(X_RA << OP_SH_RD), MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, | |
384 | {"jalr", 0, INSN_CLASS_I, "s,j", MATCH_JALR|(X_RA << OP_SH_RD), MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, | |
385 | {"jalr", 0, INSN_CLASS_I, "d,s", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR }, | |
386 | {"jalr", 0, INSN_CLASS_I, "d,o(s)", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, | |
04d35250 | 387 | {"jalr", 0, INSN_CLASS_I, "d,s,1", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_JSR }, |
1942a048 NC |
388 | {"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, |
389 | {"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH }, | |
390 | {"j", 0, INSN_CLASS_I, "a", MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, | |
a3c2d248 | 391 | {"jal", 32, INSN_CLASS_C, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR }, |
839189bc | 392 | {"jal", 0, INSN_CLASS_I, "a", MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, |
1942a048 | 393 | {"jal", 0, INSN_CLASS_I, "d,a", MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR }, |
27b33966 JB |
394 | {"call", 0, INSN_CLASS_I, "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO }, |
395 | {"call", 0, INSN_CLASS_I, "c", (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, NULL, INSN_MACRO }, | |
396 | {"tail", 0, INSN_CLASS_I, "c", (X_T1 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO }, | |
397 | {"jump", 0, INSN_CLASS_I, "c,s", 0, (int) M_CALL, match_rs1_nonzero, INSN_MACRO }, | |
1942a048 NC |
398 | {"nop", 0, INSN_CLASS_C, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, |
399 | {"nop", 0, INSN_CLASS_I, "", MATCH_ADDI, MASK_ADDI|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS }, | |
400 | {"lui", 0, INSN_CLASS_C, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, | |
401 | {"lui", 0, INSN_CLASS_I, "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 }, | |
402 | {"li", 0, INSN_CLASS_C, "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, | |
403 | {"li", 0, INSN_CLASS_C, "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, | |
404 | {"li", 0, INSN_CLASS_I, "d,j", MATCH_ADDI, MASK_ADDI|MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */ | |
27b33966 | 405 | {"li", 0, INSN_CLASS_I, "d,I", 0, (int) M_LI, NULL, INSN_MACRO }, |
1942a048 NC |
406 | {"mv", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, |
407 | {"mv", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS }, | |
408 | {"move", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, | |
409 | {"move", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS }, | |
b5c37946 | 410 | {"zext.b", 0, INSN_CLASS_ZCB, "Cs,Cw", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, INSN_ALIAS }, |
1942a048 | 411 | {"zext.b", 0, INSN_CLASS_I, "d,s", MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS }, |
f438659a JB |
412 | {"andi", 0, INSN_CLASS_ZCB, "Cs,Cw,Wcf",MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, INSN_ALIAS }, |
413 | {"andi", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, | |
414 | {"andi", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 }, | |
1942a048 NC |
415 | {"and", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, |
416 | {"and", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, | |
417 | {"and", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, | |
418 | {"and", 0, INSN_CLASS_I, "d,s,t", MATCH_AND, MASK_AND, match_opcode, 0 }, | |
419 | {"and", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS }, | |
420 | {"beqz", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
421 | {"beqz", 0, INSN_CLASS_I, "s,p", MATCH_BEQ, MASK_BEQ|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
422 | {"beq", 0, INSN_CLASS_C, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
423 | {"beq", 0, INSN_CLASS_I, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH }, | |
424 | {"blez", 0, INSN_CLASS_I, "t,p", MATCH_BGE, MASK_BGE|MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
425 | {"bgez", 0, INSN_CLASS_I, "s,p", MATCH_BGE, MASK_BGE|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
426 | {"bge", 0, INSN_CLASS_I, "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_CONDBRANCH }, | |
427 | {"bgeu", 0, INSN_CLASS_I, "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_CONDBRANCH }, | |
428 | {"ble", 0, INSN_CLASS_I, "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
429 | {"bleu", 0, INSN_CLASS_I, "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
430 | {"bltz", 0, INSN_CLASS_I, "s,p", MATCH_BLT, MASK_BLT|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
431 | {"bgtz", 0, INSN_CLASS_I, "t,p", MATCH_BLT, MASK_BLT|MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
432 | {"blt", 0, INSN_CLASS_I, "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_CONDBRANCH }, | |
433 | {"bltu", 0, INSN_CLASS_I, "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_CONDBRANCH }, | |
434 | {"bgt", 0, INSN_CLASS_I, "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
435 | {"bgtu", 0, INSN_CLASS_I, "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
436 | {"bnez", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
437 | {"bnez", 0, INSN_CLASS_I, "s,p", MATCH_BNE, MASK_BNE|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
438 | {"bne", 0, INSN_CLASS_C, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, | |
439 | {"bne", 0, INSN_CLASS_I, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH }, | |
f438659a JB |
440 | {"addi", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, |
441 | {"addi", 0, INSN_CLASS_C, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, | |
442 | {"addi", 0, INSN_CLASS_C, "d,CU,z", MATCH_C_NOP, MASK_C_ADDI|MASK_RVC_IMM, match_c_nop, INSN_ALIAS }, | |
443 | {"addi", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, | |
444 | {"addi", 0, INSN_CLASS_C, "d,Cz,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, | |
445 | {"addi", 0, INSN_CLASS_C, "d,CV,z", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, | |
446 | {"addi", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, | |
1942a048 NC |
447 | {"add", 0, INSN_CLASS_C, "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, |
448 | {"add", 0, INSN_CLASS_C, "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, | |
449 | {"add", 0, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, | |
450 | {"add", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, | |
451 | {"add", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, | |
452 | {"add", 0, INSN_CLASS_C, "d,Cz,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, | |
453 | {"add", 0, INSN_CLASS_I, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, | |
454 | {"add", 0, INSN_CLASS_I, "d,s,t,1", MATCH_ADD, MASK_ADD, match_opcode, 0 }, | |
455 | {"add", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS }, | |
27b33966 JB |
456 | {"la", 0, INSN_CLASS_I, "d,B", 0, (int) M_LA, match_rd_nonzero, INSN_MACRO }, |
457 | {"lla", 0, INSN_CLASS_I, "d,B", 0, (int) M_LLA, NULL, INSN_MACRO }, | |
458 | {"lga", 0, INSN_CLASS_I, "d,B", 0, (int) M_LGA, match_rd_nonzero, INSN_MACRO }, | |
459 | {"la.tls.gd", 0, INSN_CLASS_I, "d,A", 0, (int) M_LA_TLS_GD, NULL, INSN_MACRO }, | |
460 | {"la.tls.ie", 0, INSN_CLASS_I, "d,A", 0, (int) M_LA_TLS_IE, match_rd_nonzero, INSN_MACRO }, | |
1942a048 | 461 | {"neg", 0, INSN_CLASS_I, "d,t", MATCH_SUB, MASK_SUB|MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ |
f438659a JB |
462 | {"slli", 0, INSN_CLASS_C, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, |
463 | {"slli", 0, INSN_CLASS_I, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 }, | |
1942a048 NC |
464 | {"sll", 0, INSN_CLASS_C, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, |
465 | {"sll", 0, INSN_CLASS_I, "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, | |
466 | {"sll", 0, INSN_CLASS_I, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, | |
f438659a JB |
467 | {"srli", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS }, |
468 | {"srli", 0, INSN_CLASS_I, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, | |
1942a048 NC |
469 | {"srl", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS }, |
470 | {"srl", 0, INSN_CLASS_I, "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, | |
471 | {"srl", 0, INSN_CLASS_I, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, | |
f438659a JB |
472 | {"srai", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS }, |
473 | {"srai", 0, INSN_CLASS_I, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, | |
1942a048 NC |
474 | {"sra", 0, INSN_CLASS_C, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS }, |
475 | {"sra", 0, INSN_CLASS_I, "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, | |
476 | {"sra", 0, INSN_CLASS_I, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, | |
477 | {"sub", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, | |
478 | {"sub", 0, INSN_CLASS_I, "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 }, | |
479 | {"lb", 0, INSN_CLASS_I, "d,o(s)", MATCH_LB, MASK_LB, match_opcode, INSN_DREF|INSN_1_BYTE }, | |
27b33966 | 480 | {"lb", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, |
b5c37946 | 481 | {"lbu", 0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_LBU, MASK_C_LBU, match_opcode, INSN_ALIAS|INSN_DREF|INSN_1_BYTE }, |
1942a048 | 482 | {"lbu", 0, INSN_CLASS_I, "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, INSN_DREF|INSN_1_BYTE }, |
27b33966 | 483 | {"lbu", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, |
b5c37946 | 484 | {"lh", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LH, MASK_C_LH, match_opcode, INSN_ALIAS|INSN_DREF|INSN_2_BYTE }, |
1942a048 | 485 | {"lh", 0, INSN_CLASS_I, "d,o(s)", MATCH_LH, MASK_LH, match_opcode, INSN_DREF|INSN_2_BYTE }, |
27b33966 | 486 | {"lh", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, |
b5c37946 | 487 | {"lhu", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LHU, MASK_C_LHU, match_opcode, INSN_ALIAS|INSN_DREF|INSN_2_BYTE }, |
1942a048 | 488 | {"lhu", 0, INSN_CLASS_I, "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, INSN_DREF|INSN_2_BYTE }, |
27b33966 | 489 | {"lhu", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, |
1942a048 NC |
490 | {"lw", 0, INSN_CLASS_C, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, |
491 | {"lw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, | |
492 | {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
27b33966 | 493 | {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, |
b5c37946 | 494 | {"not", 0, INSN_CLASS_ZCB, "Cs,Cw", MATCH_C_NOT, MASK_C_NOT, match_opcode, INSN_ALIAS }, |
1942a048 | 495 | {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS }, |
f438659a | 496 | {"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 }, |
839189bc | 497 | {"or", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS }, |
1942a048 NC |
498 | {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, |
499 | {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, | |
500 | {"or", 0, INSN_CLASS_I, "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 }, | |
1942a048 NC |
501 | {"auipc", 0, INSN_CLASS_I, "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 }, |
502 | {"seqz", 0, INSN_CLASS_I, "d,s", MATCH_SLTIU|ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS }, | |
503 | {"snez", 0, INSN_CLASS_I, "d,t", MATCH_SLTU, MASK_SLTU|MASK_RS1, match_opcode, INSN_ALIAS }, | |
504 | {"sltz", 0, INSN_CLASS_I, "d,s", MATCH_SLT, MASK_SLT|MASK_RS2, match_opcode, INSN_ALIAS }, | |
505 | {"sgtz", 0, INSN_CLASS_I, "d,t", MATCH_SLT, MASK_SLT|MASK_RS1, match_opcode, INSN_ALIAS }, | |
506 | {"slti", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 }, | |
507 | {"slt", 0, INSN_CLASS_I, "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 }, | |
508 | {"slt", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS }, | |
509 | {"sltiu", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 }, | |
510 | {"sltu", 0, INSN_CLASS_I, "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 }, | |
511 | {"sltu", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS }, | |
512 | {"sgt", 0, INSN_CLASS_I, "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS }, | |
513 | {"sgtu", 0, INSN_CLASS_I, "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS }, | |
b5c37946 | 514 | {"sb", 0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_SB, MASK_C_SB, match_opcode, INSN_DREF|INSN_1_BYTE|INSN_ALIAS }, |
1942a048 | 515 | {"sb", 0, INSN_CLASS_I, "t,q(s)", MATCH_SB, MASK_SB, match_opcode, INSN_DREF|INSN_1_BYTE }, |
27b33966 | 516 | {"sb", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, |
b5c37946 | 517 | {"sh", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_SH, MASK_C_SH, match_opcode, INSN_DREF|INSN_2_BYTE|INSN_ALIAS }, |
1942a048 | 518 | {"sh", 0, INSN_CLASS_I, "t,q(s)", MATCH_SH, MASK_SH, match_opcode, INSN_DREF|INSN_2_BYTE }, |
27b33966 | 519 | {"sh", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, |
1942a048 NC |
520 | {"sw", 0, INSN_CLASS_C, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, |
521 | {"sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, | |
522 | {"sw", 0, INSN_CLASS_I, "t,q(s)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
27b33966 | 523 | {"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, |
1942a048 NC |
524 | {"fence", 0, INSN_CLASS_I, "", MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS }, |
525 | {"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, | |
526 | {"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 }, | |
d988b231 | 527 | {"fence.tso", 0, INSN_CLASS_I, "", MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, 0 }, |
1942a048 NC |
528 | {"rdcycle", 0, INSN_CLASS_I, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS }, |
529 | {"rdinstret", 0, INSN_CLASS_I, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS }, | |
530 | {"rdtime", 0, INSN_CLASS_I, "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS }, | |
531 | {"rdcycleh", 32, INSN_CLASS_I, "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS }, | |
532 | {"rdinstreth", 32, INSN_CLASS_I, "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS }, | |
533 | {"rdtimeh", 32, INSN_CLASS_I, "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS }, | |
534 | {"ecall", 0, INSN_CLASS_I, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, | |
535 | {"scall", 0, INSN_CLASS_I, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, | |
f438659a | 536 | {"xori", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 }, |
839189bc | 537 | {"xor", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS }, |
1942a048 NC |
538 | {"xor", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, |
539 | {"xor", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, | |
540 | {"xor", 0, INSN_CLASS_I, "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 }, | |
1942a048 | 541 | {"lwu", 64, INSN_CLASS_I, "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, INSN_DREF|INSN_4_BYTE }, |
27b33966 | 542 | {"lwu", 64, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, |
7e9ad3a3 | 543 | {"ld", 64, INSN_CLASS_C, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, |
1942a048 NC |
544 | {"ld", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, |
545 | {"ld", 64, INSN_CLASS_I, "d,o(s)", MATCH_LD, MASK_LD, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
27b33966 | 546 | {"ld", 64, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_rd_nonzero, INSN_MACRO }, |
1942a048 NC |
547 | {"sd", 64, INSN_CLASS_C, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, |
548 | {"sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, | |
549 | {"sd", 64, INSN_CLASS_I, "t,q(s)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
27b33966 | 550 | {"sd", 64, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, |
1942a048 NC |
551 | {"sext.w", 64, INSN_CLASS_C, "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, |
552 | {"sext.w", 64, INSN_CLASS_I, "d,s", MATCH_ADDIW, MASK_ADDIW|MASK_IMM, match_opcode, INSN_ALIAS }, | |
f438659a JB |
553 | {"addiw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, |
554 | {"addiw", 64, INSN_CLASS_I, "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 }, | |
7e9ad3a3 JW |
555 | {"addw", 64, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, |
556 | {"addw", 64, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, | |
1942a048 NC |
557 | {"addw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, |
558 | {"addw", 64, INSN_CLASS_I, "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, 0 }, | |
559 | {"addw", 64, INSN_CLASS_I, "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS }, | |
560 | {"negw", 64, INSN_CLASS_I, "d,t", MATCH_SUBW, MASK_SUBW|MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ | |
f438659a | 561 | {"slliw", 64, INSN_CLASS_I, "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 }, |
1942a048 NC |
562 | {"sllw", 64, INSN_CLASS_I, "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, 0 }, |
563 | {"sllw", 64, INSN_CLASS_I, "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS }, | |
f438659a | 564 | {"srliw", 64, INSN_CLASS_I, "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 }, |
1942a048 NC |
565 | {"srlw", 64, INSN_CLASS_I, "d,s,t", MATCH_SRLW, MASK_SRLW, match_opcode, 0 }, |
566 | {"srlw", 64, INSN_CLASS_I, "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS }, | |
f438659a | 567 | {"sraiw", 64, INSN_CLASS_I, "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 }, |
1942a048 NC |
568 | {"sraw", 64, INSN_CLASS_I, "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, 0 }, |
569 | {"sraw", 64, INSN_CLASS_I, "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS }, | |
7e9ad3a3 | 570 | {"subw", 64, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS }, |
1942a048 | 571 | {"subw", 64, INSN_CLASS_I, "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 }, |
e23eba97 | 572 | |
dcd709e0 | 573 | /* Atomic memory operation instruction subset. */ |
1942a048 NC |
574 | {"lr.w", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, |
575 | {"sc.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
576 | {"amoadd.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
577 | {"amoswap.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
578 | {"amoand.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
579 | {"amoor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
580 | {"amoxor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
581 | {"amomax.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
582 | {"amomaxu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
583 | {"amomin.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
584 | {"amominu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
585 | {"lr.w.aq", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQ, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
586 | {"sc.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQ, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
587 | {"amoadd.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQ, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
588 | {"amoswap.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
589 | {"amoand.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQ, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
590 | {"amoor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQ, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
591 | {"amoxor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQ, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
592 | {"amomax.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQ, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
593 | {"amomaxu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
594 | {"amomin.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQ, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
595 | {"amominu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
596 | {"lr.w.rl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_RL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
597 | {"sc.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_RL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
598 | {"amoadd.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_RL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
599 | {"amoswap.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_RL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
600 | {"amoand.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_RL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
601 | {"amoor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_RL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
602 | {"amoxor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_RL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
603 | {"amomax.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_RL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
604 | {"amomaxu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_RL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
605 | {"amomin.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_RL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
606 | {"amominu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_RL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
607 | {"lr.w.aqrl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQRL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
608 | {"sc.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQRL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
609 | {"amoadd.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
610 | {"amoswap.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
611 | {"amoand.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
612 | {"amoor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQRL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
613 | {"amoxor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
614 | {"amomax.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
615 | {"amomaxu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
616 | {"amomin.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
617 | {"amominu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
618 | {"lr.d", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
619 | {"sc.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
620 | {"amoadd.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
621 | {"amoswap.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
622 | {"amoand.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
623 | {"amoor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
624 | {"amoxor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
625 | {"amomax.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
626 | {"amomaxu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
627 | {"amomin.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
628 | {"amominu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
629 | {"lr.d.aq", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQ, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
630 | {"sc.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQ, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
631 | {"amoadd.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQ, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
632 | {"amoswap.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
633 | {"amoand.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQ, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
634 | {"amoor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQ, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
635 | {"amoxor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQ, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
636 | {"amomax.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQ, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
637 | {"amomaxu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
638 | {"amomin.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQ, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
639 | {"amominu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
640 | {"lr.d.rl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_RL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
641 | {"sc.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_RL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
642 | {"amoadd.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_RL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
643 | {"amoswap.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_RL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
644 | {"amoand.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_RL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
645 | {"amoor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_RL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
646 | {"amoxor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_RL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
647 | {"amomax.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_RL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
648 | {"amomaxu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_RL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
649 | {"amomin.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_RL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
650 | {"amominu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_RL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
651 | {"lr.d.aqrl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQRL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
652 | {"sc.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQRL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
653 | {"amoadd.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
654 | {"amoswap.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
655 | {"amoand.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
656 | {"amoor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQRL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
657 | {"amoxor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
658 | {"amomax.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
659 | {"amomaxu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
660 | {"amomin.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
661 | {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
e23eba97 | 662 | |
dcd709e0 | 663 | /* Multiply/Divide instruction subset. */ |
b5c37946 | 664 | {"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS }, |
0938b032 TO |
665 | {"mul", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, |
666 | {"mulh", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, | |
667 | {"mulhu", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, | |
668 | {"mulhsu", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 }, | |
669 | {"div", 0, INSN_CLASS_M, "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 }, | |
670 | {"divu", 0, INSN_CLASS_M, "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 }, | |
671 | {"rem", 0, INSN_CLASS_M, "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 }, | |
672 | {"remu", 0, INSN_CLASS_M, "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 }, | |
673 | {"mulw", 64, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 }, | |
674 | {"divw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 }, | |
675 | {"divuw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 }, | |
676 | {"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 }, | |
677 | {"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 }, | |
e23eba97 | 678 | |
035784e3 | 679 | /* Half-precision floating-point instruction subset. */ |
045f385d | 680 | {"flh", 0, INSN_CLASS_ZFHMIN, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE }, |
27b33966 | 681 | {"flh", 0, INSN_CLASS_ZFHMIN, "D,A,s", 0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO }, |
045f385d | 682 | {"fsh", 0, INSN_CLASS_ZFHMIN, "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE }, |
27b33966 | 683 | {"fsh", 0, INSN_CLASS_ZFHMIN, "T,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, |
045f385d TO |
684 | {"fmv.x.h", 0, INSN_CLASS_ZFHMIN, "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 }, |
685 | {"fmv.h.x", 0, INSN_CLASS_ZFHMIN, "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 }, | |
136ea874 NC |
686 | {"fmv.h", 0, INSN_CLASS_ZFH_INX, "D,U", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS }, |
687 | {"fneg.h", 0, INSN_CLASS_ZFH_INX, "D,U", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS }, | |
688 | {"fabs.h", 0, INSN_CLASS_ZFH_INX, "D,U", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS }, | |
689 | {"fsgnj.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 }, | |
690 | {"fsgnjn.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 }, | |
691 | {"fsgnjx.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 }, | |
692 | {"fadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 }, | |
693 | {"fadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 }, | |
694 | {"fsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 }, | |
695 | {"fsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 }, | |
696 | {"fmul.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 }, | |
697 | {"fmul.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 }, | |
698 | {"fdiv.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 }, | |
699 | {"fdiv.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 }, | |
700 | {"fsqrt.h", 0, INSN_CLASS_ZFH_INX, "D,S", MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 }, | |
701 | {"fsqrt.h", 0, INSN_CLASS_ZFH_INX, "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 }, | |
702 | {"fmin.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 }, | |
703 | {"fmax.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 }, | |
704 | {"fmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 }, | |
705 | {"fmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 }, | |
706 | {"fnmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 }, | |
707 | {"fnmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 }, | |
708 | {"fmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 }, | |
709 | {"fmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 }, | |
710 | {"fnmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 }, | |
711 | {"fnmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 }, | |
712 | {"fcvt.w.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 }, | |
713 | {"fcvt.w.h", 0, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 }, | |
714 | {"fcvt.wu.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 }, | |
715 | {"fcvt.wu.h", 0, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 }, | |
716 | {"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 }, | |
717 | {"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 }, | |
718 | {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 }, | |
719 | {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, | |
720 | {"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 }, | |
721 | {"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 }, | |
722 | {"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, | |
723 | {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 }, | |
724 | {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, | |
725 | {"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 }, | |
726 | {"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 }, | |
727 | {"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 }, | |
728 | {"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S,m", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 }, | |
729 | {"fclass.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 }, | |
730 | {"feq.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 }, | |
731 | {"flt.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, | |
732 | {"fle.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 }, | |
733 | {"fgt.h", 0, INSN_CLASS_ZFH_INX, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, | |
734 | {"fge.h", 0, INSN_CLASS_ZFH_INX, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 }, | |
735 | {"fcvt.l.h", 64, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 }, | |
736 | {"fcvt.l.h", 64, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 }, | |
737 | {"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 }, | |
738 | {"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 }, | |
739 | {"fcvt.h.l", 64, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 }, | |
740 | {"fcvt.h.l", 64, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 }, | |
741 | {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 }, | |
742 | {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, | |
035784e3 | 743 | |
dcd709e0 | 744 | /* Single-precision floating-point instruction subset. */ |
136ea874 NC |
745 | {"frcsr", 0, INSN_CLASS_F_INX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, |
746 | {"frsr", 0, INSN_CLASS_F_INX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, | |
747 | {"fscsr", 0, INSN_CLASS_F_INX, "s", MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS }, | |
748 | {"fscsr", 0, INSN_CLASS_F_INX, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, | |
749 | {"fssr", 0, INSN_CLASS_F_INX, "s", MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS }, | |
750 | {"fssr", 0, INSN_CLASS_F_INX, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, | |
751 | {"frrm", 0, INSN_CLASS_F_INX, "d", MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS }, | |
752 | {"fsrm", 0, INSN_CLASS_F_INX, "s", MATCH_FSRM, MASK_FSRM|MASK_RD, match_opcode, INSN_ALIAS }, | |
753 | {"fsrm", 0, INSN_CLASS_F_INX, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS }, | |
754 | {"fsrmi", 0, INSN_CLASS_F_INX, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS }, | |
755 | {"fsrmi", 0, INSN_CLASS_F_INX, "Z", MATCH_FSRMI, MASK_FSRMI|MASK_RD, match_opcode, INSN_ALIAS }, | |
756 | {"frflags", 0, INSN_CLASS_F_INX, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS }, | |
757 | {"fsflags", 0, INSN_CLASS_F_INX, "s", MATCH_FSFLAGS, MASK_FSFLAGS|MASK_RD, match_opcode, INSN_ALIAS }, | |
758 | {"fsflags", 0, INSN_CLASS_F_INX, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS }, | |
759 | {"fsflagsi", 0, INSN_CLASS_F_INX, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS }, | |
760 | {"fsflagsi", 0, INSN_CLASS_F_INX, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS }, | |
1942a048 NC |
761 | {"flw", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, |
762 | {"flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, | |
763 | {"flw", 0, INSN_CLASS_F, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
27b33966 | 764 | {"flw", 0, INSN_CLASS_F, "D,A,s", 0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO }, |
1942a048 NC |
765 | {"fsw", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, |
766 | {"fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, | |
767 | {"fsw", 0, INSN_CLASS_F, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
27b33966 | 768 | {"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, |
1942a048 NC |
769 | {"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, |
770 | {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, | |
771 | {"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, | |
772 | {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, | |
136ea874 NC |
773 | {"fmv.s", 0, INSN_CLASS_F_INX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, |
774 | {"fneg.s", 0, INSN_CLASS_F_INX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, | |
775 | {"fabs.s", 0, INSN_CLASS_F_INX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, | |
776 | {"fsgnj.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, | |
777 | {"fsgnjn.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 }, | |
778 | {"fsgnjx.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 }, | |
779 | {"fadd.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 }, | |
780 | {"fadd.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 }, | |
781 | {"fsub.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 }, | |
782 | {"fsub.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 }, | |
783 | {"fmul.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 }, | |
784 | {"fmul.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 }, | |
785 | {"fdiv.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 }, | |
786 | {"fdiv.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 }, | |
787 | {"fsqrt.s", 0, INSN_CLASS_F_INX, "D,S", MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 }, | |
788 | {"fsqrt.s", 0, INSN_CLASS_F_INX, "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 }, | |
789 | {"fmin.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 }, | |
790 | {"fmax.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 }, | |
791 | {"fmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 }, | |
792 | {"fmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 }, | |
793 | {"fnmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 }, | |
794 | {"fnmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 }, | |
795 | {"fmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 }, | |
796 | {"fmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 }, | |
797 | {"fnmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 }, | |
798 | {"fnmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 }, | |
799 | {"fcvt.w.s", 0, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 }, | |
800 | {"fcvt.w.s", 0, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 }, | |
801 | {"fcvt.wu.s", 0, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 }, | |
802 | {"fcvt.wu.s", 0, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, | |
803 | {"fcvt.s.w", 0, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 }, | |
804 | {"fcvt.s.w", 0, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, | |
805 | {"fcvt.s.wu", 0, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, 0 }, | |
806 | {"fcvt.s.wu", 0, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, | |
807 | {"fclass.s", 0, INSN_CLASS_F_INX, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, | |
808 | {"feq.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, | |
809 | {"flt.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, | |
810 | {"fle.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, | |
811 | {"fgt.s", 0, INSN_CLASS_F_INX, "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, | |
812 | {"fge.s", 0, INSN_CLASS_F_INX, "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, | |
813 | {"fcvt.l.s", 64, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 }, | |
814 | {"fcvt.l.s", 64, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, | |
815 | {"fcvt.lu.s", 64, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 }, | |
816 | {"fcvt.lu.s", 64, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, | |
817 | {"fcvt.s.l", 64, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 }, | |
818 | {"fcvt.s.l", 64, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, | |
819 | {"fcvt.s.lu", 64, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, | |
820 | {"fcvt.s.lu", 64, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, | |
e23eba97 | 821 | |
dcd709e0 | 822 | /* Double-precision floating-point instruction subset. */ |
1942a048 NC |
823 | {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, |
824 | {"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, | |
825 | {"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
27b33966 | 826 | {"fld", 0, INSN_CLASS_D, "D,A,s", 0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO }, |
1942a048 NC |
827 | {"fsd", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, |
828 | {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, | |
829 | {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
27b33966 | 830 | {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, |
136ea874 NC |
831 | {"fmv.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, |
832 | {"fneg.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, | |
833 | {"fabs.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, | |
834 | {"fsgnj.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, | |
835 | {"fsgnjn.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, | |
836 | {"fsgnjx.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, | |
837 | {"fadd.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, | |
838 | {"fadd.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, | |
839 | {"fsub.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, | |
840 | {"fsub.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, | |
841 | {"fmul.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, | |
842 | {"fmul.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, | |
843 | {"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, | |
844 | {"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, | |
845 | {"fsqrt.d", 0, INSN_CLASS_D_INX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, | |
846 | {"fsqrt.d", 0, INSN_CLASS_D_INX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, | |
847 | {"fmin.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, | |
848 | {"fmax.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, | |
849 | {"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, | |
850 | {"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, | |
851 | {"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, | |
852 | {"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, | |
853 | {"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, | |
854 | {"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, | |
855 | {"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, | |
856 | {"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, | |
857 | {"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, | |
858 | {"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, | |
859 | {"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, | |
860 | {"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, | |
861 | {"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, | |
862 | {"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, | |
863 | {"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, | |
864 | {"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, | |
865 | {"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, | |
866 | {"fclass.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, | |
867 | {"feq.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, | |
868 | {"flt.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, | |
869 | {"fle.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, | |
870 | {"fgt.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, | |
871 | {"fge.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, | |
1942a048 NC |
872 | {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, |
873 | {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, | |
136ea874 NC |
874 | {"fcvt.l.d", 64, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, |
875 | {"fcvt.l.d", 64, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, | |
876 | {"fcvt.lu.d", 64, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, | |
877 | {"fcvt.lu.d", 64, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, | |
878 | {"fcvt.d.l", 64, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, | |
879 | {"fcvt.d.l", 64, INSN_CLASS_D_INX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, | |
880 | {"fcvt.d.lu", 64, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, | |
881 | {"fcvt.d.lu", 64, INSN_CLASS_D_INX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, | |
e23eba97 | 882 | |
dcd709e0 | 883 | /* Quad-precision floating-point instruction subset. */ |
1942a048 | 884 | {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, |
27b33966 | 885 | {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO }, |
1942a048 | 886 | {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, |
27b33966 | 887 | {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, |
136ea874 NC |
888 | {"fmv.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, |
889 | {"fneg.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, | |
890 | {"fabs.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, | |
891 | {"fsgnj.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, | |
892 | {"fsgnjn.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, | |
893 | {"fsgnjx.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, | |
894 | {"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, | |
895 | {"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, | |
896 | {"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, | |
897 | {"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, | |
898 | {"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, | |
899 | {"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, | |
900 | {"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, | |
901 | {"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, | |
902 | {"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, | |
903 | {"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, | |
904 | {"fmin.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, | |
905 | {"fmax.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, | |
906 | {"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, | |
907 | {"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, | |
908 | {"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, | |
909 | {"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, | |
910 | {"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, | |
911 | {"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, | |
912 | {"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, | |
913 | {"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, | |
914 | {"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, | |
915 | {"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, | |
916 | {"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, | |
917 | {"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, | |
918 | {"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, | |
919 | {"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, | |
920 | {"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, | |
921 | {"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, | |
922 | {"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, | |
923 | {"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, | |
924 | {"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, | |
925 | {"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, | |
926 | {"fclass.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, | |
927 | {"feq.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, | |
928 | {"flt.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, | |
929 | {"fle.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, | |
930 | {"fgt.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, | |
931 | {"fge.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, | |
932 | {"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, | |
933 | {"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, | |
934 | {"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, | |
935 | {"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, | |
936 | {"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, | |
937 | {"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, | |
938 | {"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, | |
939 | {"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, | |
cc917fd9 | 940 | |
e23eba97 | 941 | /* Compressed instructions. */ |
1942a048 NC |
942 | {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, |
943 | {"c.ebreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 }, | |
944 | {"c.jr", 0, INSN_CLASS_C, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_BRANCH }, | |
945 | {"c.jalr", 0, INSN_CLASS_C, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_JSR }, | |
946 | {"c.j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_BRANCH }, | |
947 | {"c.jal", 32, INSN_CLASS_C, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_JSR }, | |
948 | {"c.beqz", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_CONDBRANCH }, | |
949 | {"c.bnez", 0, INSN_CLASS_C, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_CONDBRANCH }, | |
7e9ad3a3 | 950 | {"c.lwsp", 0, INSN_CLASS_C, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 }, |
1942a048 NC |
951 | {"c.lw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, |
952 | {"c.swsp", 0, INSN_CLASS_C, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
953 | {"c.sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
954 | {"c.nop", 0, INSN_CLASS_C, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, | |
955 | {"c.nop", 0, INSN_CLASS_C, "Cj", MATCH_C_ADDI, MASK_C_ADDI|MASK_RD, match_opcode, INSN_ALIAS }, | |
956 | {"c.mv", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add_with_hint, 0 }, | |
957 | {"c.lui", 0, INSN_CLASS_C, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui_with_hint, 0 }, | |
958 | {"c.li", 0, INSN_CLASS_C, "d,Co", MATCH_C_LI, MASK_C_LI, match_opcode, 0 }, | |
959 | {"c.addi4spn", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 }, | |
960 | {"c.addi16sp", 0, INSN_CLASS_C, "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 }, | |
961 | {"c.addi", 0, INSN_CLASS_C, "d,Co", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 }, | |
962 | {"c.add", 0, INSN_CLASS_C, "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add_with_hint, 0 }, | |
963 | {"c.sub", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 }, | |
964 | {"c.and", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 }, | |
965 | {"c.or", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 }, | |
966 | {"c.xor", 0, INSN_CLASS_C, "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 }, | |
967 | {"c.slli", 0, INSN_CLASS_C, "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_c_slli, 0 }, | |
968 | {"c.srli", 0, INSN_CLASS_C, "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_c_slli, 0 }, | |
969 | {"c.srai", 0, INSN_CLASS_C, "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_c_slli, 0 }, | |
970 | {"c.slli64", 0, INSN_CLASS_C, "d", MATCH_C_SLLI64, MASK_C_SLLI64, match_c_slli64, 0 }, | |
971 | {"c.srli64", 0, INSN_CLASS_C, "Cs", MATCH_C_SRLI64, MASK_C_SRLI64, match_c_slli64, 0 }, | |
972 | {"c.srai64", 0, INSN_CLASS_C, "Cs", MATCH_C_SRAI64, MASK_C_SRAI64, match_c_slli64, 0 }, | |
973 | {"c.andi", 0, INSN_CLASS_C, "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, | |
974 | {"c.addiw", 64, INSN_CLASS_C, "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, | |
975 | {"c.addw", 64, INSN_CLASS_C, "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, | |
976 | {"c.subw", 64, INSN_CLASS_C, "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 }, | |
977 | {"c.ldsp", 64, INSN_CLASS_C, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_DREF|INSN_8_BYTE }, | |
978 | {"c.ld", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
979 | {"c.sdsp", 64, INSN_CLASS_C, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
980 | {"c.sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
981 | {"c.fldsp", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
982 | {"c.fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
983 | {"c.fsdsp", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
984 | {"c.fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
7e9ad3a3 | 985 | {"c.flwsp", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, |
1942a048 NC |
986 | {"c.flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, |
987 | {"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
988 | {"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
e23eba97 | 989 | |
41d6ac5d TO |
990 | /* Zicbom and Zicboz instructions. */ |
991 | {"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 }, | |
992 | {"cbo.flush", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 }, | |
993 | {"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 }, | |
994 | {"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 }, | |
995 | ||
b625eff8 PT |
996 | /* Zicond instructions. */ |
997 | {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, | |
998 | {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, | |
999 | ||
eb668e50 CM |
1000 | /* Zawrs instructions. */ |
1001 | {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, | |
1002 | {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 }, | |
1003 | ||
1f3fc45b CM |
1004 | /* Zfa instructions. */ |
1005 | {"fli.s", 0, INSN_CLASS_ZFA, "D,Wfv", MATCH_FLI_S, MASK_FLI_S, match_opcode, 0 }, | |
1006 | {"fli.d", 0, INSN_CLASS_D_AND_ZFA, "D,Wfv", MATCH_FLI_D, MASK_FLI_D, match_opcode, 0 }, | |
1007 | {"fli.q", 0, INSN_CLASS_Q_AND_ZFA, "D,Wfv", MATCH_FLI_Q, MASK_FLI_Q, match_opcode, 0 }, | |
239af8cb | 1008 | {"fli.h", 0, INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA, "D,Wfv", MATCH_FLI_H, MASK_FLI_H, match_opcode, 0 }, |
1f3fc45b CM |
1009 | {"fminm.s", 0, INSN_CLASS_ZFA, "D,S,T", MATCH_FMINM_S, MASK_FMINM_S, match_opcode, 0 }, |
1010 | {"fmaxm.s", 0, INSN_CLASS_ZFA, "D,S,T", MATCH_FMAXM_S, MASK_FMAXM_S, match_opcode, 0 }, | |
1011 | {"fminm.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,T", MATCH_FMINM_D, MASK_FMINM_D, match_opcode, 0 }, | |
1012 | {"fmaxm.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,T", MATCH_FMAXM_D, MASK_FMAXM_D, match_opcode, 0 }, | |
1013 | {"fminm.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,T", MATCH_FMINM_Q, MASK_FMINM_Q, match_opcode, 0 }, | |
1014 | {"fmaxm.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,T", MATCH_FMAXM_Q, MASK_FMAXM_Q, match_opcode, 0 }, | |
1015 | {"fminm.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,T", MATCH_FMINM_H, MASK_FMINM_H, match_opcode, 0 }, | |
1016 | {"fmaxm.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,T", MATCH_FMAXM_H, MASK_FMAXM_H, match_opcode, 0 }, | |
1017 | {"fround.s", 0, INSN_CLASS_ZFA, "D,S", MATCH_FROUND_S|MASK_RM, MASK_FROUND_S|MASK_RM, match_opcode, 0 }, | |
1018 | {"fround.s", 0, INSN_CLASS_ZFA, "D,S,m", MATCH_FROUND_S, MASK_FROUND_S, match_opcode, 0 }, | |
1019 | {"froundnx.s", 0, INSN_CLASS_ZFA, "D,S", MATCH_FROUNDNX_S|MASK_RM, MASK_FROUNDNX_S|MASK_RM, match_opcode, 0 }, | |
1020 | {"froundnx.s", 0, INSN_CLASS_ZFA, "D,S,m", MATCH_FROUNDNX_S, MASK_FROUNDNX_S, match_opcode, 0 }, | |
1021 | {"fround.d", 0, INSN_CLASS_D_AND_ZFA, "D,S", MATCH_FROUND_D|MASK_RM, MASK_FROUND_D|MASK_RM, match_opcode, 0 }, | |
1022 | {"fround.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,m", MATCH_FROUND_D, MASK_FROUND_D, match_opcode, 0 }, | |
1023 | {"froundnx.d", 0, INSN_CLASS_D_AND_ZFA, "D,S", MATCH_FROUNDNX_D|MASK_RM, MASK_FROUNDNX_D|MASK_RM, match_opcode, 0 }, | |
1024 | {"froundnx.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,m", MATCH_FROUNDNX_D, MASK_FROUNDNX_D, match_opcode, 0 }, | |
1025 | {"fround.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S", MATCH_FROUND_Q|MASK_RM, MASK_FROUND_Q|MASK_RM, match_opcode, 0 }, | |
1026 | {"fround.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,m", MATCH_FROUND_Q, MASK_FROUND_Q, match_opcode, 0 }, | |
1027 | {"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S", MATCH_FROUNDNX_Q|MASK_RM, MASK_FROUNDNX_Q|MASK_RM, match_opcode, 0 }, | |
1028 | {"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,m", MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q, match_opcode, 0 }, | |
1029 | {"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S", MATCH_FROUND_H|MASK_RM, MASK_FROUND_H|MASK_RM, match_opcode, 0 }, | |
1030 | {"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,m", MATCH_FROUND_H, MASK_FROUND_H, match_opcode, 0 }, | |
1031 | {"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S", MATCH_FROUNDNX_H|MASK_RM, MASK_FROUNDNX_H|MASK_RM, match_opcode, 0 }, | |
1032 | {"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,m", MATCH_FROUNDNX_H, MASK_FROUNDNX_H, match_opcode, 0 }, | |
1033 | {"fcvtmod.w.d", 0, INSN_CLASS_D_AND_ZFA, "d,S,m", MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D, match_opcode, 0 }, | |
1034 | {"fmvh.x.d", 32, INSN_CLASS_D_AND_ZFA, "d,S", MATCH_FMVH_X_D, MASK_FMVH_X_D, match_opcode, 0 }, | |
1035 | {"fmvp.d.x", 32, INSN_CLASS_D_AND_ZFA, "D,s,t", MATCH_FMVP_D_X, MASK_FMVP_D_X, match_opcode, 0 }, | |
1036 | {"fmvh.x.q", 64, INSN_CLASS_Q_AND_ZFA, "d,S", MATCH_FMVH_X_Q, MASK_FMVH_X_Q, match_opcode, 0 }, | |
1037 | {"fmvp.q.x", 64, INSN_CLASS_Q_AND_ZFA, "D,s,t", MATCH_FMVP_Q_X, MASK_FMVP_Q_X, match_opcode, 0 }, | |
1038 | {"fltq.s", 0, INSN_CLASS_ZFA, "d,S,T", MATCH_FLTQ_S, MASK_FLTQ_S, match_opcode, 0 }, | |
1039 | {"fleq.s", 0, INSN_CLASS_ZFA, "d,S,T", MATCH_FLEQ_S, MASK_FLEQ_S, match_opcode, 0 }, | |
1040 | {"fltq.d", 0, INSN_CLASS_D_AND_ZFA, "d,S,T", MATCH_FLTQ_D, MASK_FLTQ_D, match_opcode, 0 }, | |
1041 | {"fleq.d", 0, INSN_CLASS_D_AND_ZFA, "d,S,T", MATCH_FLEQ_D, MASK_FLEQ_D, match_opcode, 0 }, | |
1042 | {"fltq.q", 0, INSN_CLASS_Q_AND_ZFA, "d,S,T", MATCH_FLTQ_Q, MASK_FLTQ_Q, match_opcode, 0 }, | |
1043 | {"fleq.q", 0, INSN_CLASS_Q_AND_ZFA, "d,S,T", MATCH_FLEQ_Q, MASK_FLEQ_Q, match_opcode, 0 }, | |
1044 | {"fltq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLTQ_H, MASK_FLTQ_H, match_opcode, 0 }, | |
1045 | {"fleq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLEQ_H, MASK_FLEQ_H, match_opcode, 0 }, | |
1046 | ||
3d1cafa0 | 1047 | /* Zbb or zbkb instructions. */ |
80d49d6a KLC |
1048 | {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 }, |
1049 | {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 }, | |
1050 | {"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 }, | |
1051 | {"min", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 }, | |
1052 | {"max", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 }, | |
1053 | {"minu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 }, | |
1054 | {"maxu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 }, | |
b5c37946 | 1055 | {"sext.b", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_SEXT_B, MASK_C_SEXT_B, match_opcode, INSN_ALIAS }, |
80d49d6a | 1056 | {"sext.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 }, |
27b33966 | 1057 | {"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, NULL, INSN_MACRO }, |
b5c37946 | 1058 | {"sext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_SEXT_H, MASK_C_SEXT_H, match_opcode, INSN_ALIAS }, |
80d49d6a | 1059 | {"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 }, |
eb5e952f | 1060 | {"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_EXTH, NULL, INSN_MACRO }, |
b5c37946 | 1061 | {"zext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_ZEXT_H, MASK_C_ZEXT_H, match_opcode, INSN_ALIAS }, |
80d49d6a KLC |
1062 | {"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 }, |
1063 | {"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 }, | |
eb5e952f | 1064 | {"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_EXTH, NULL, INSN_MACRO }, |
80d49d6a KLC |
1065 | {"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 }, |
1066 | {"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 }, | |
1067 | {"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 }, | |
1068 | {"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 }, | |
3d1cafa0 | 1069 | {"brev8", 32, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 }, |
1070 | {"brev8", 64, INSN_CLASS_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 }, | |
d988b231 JB |
1071 | {"zip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 }, |
1072 | {"unzip", 32, INSN_CLASS_ZBKB, "d,s", MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 }, | |
3d1cafa0 | 1073 | {"pack", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 }, |
1074 | {"packh", 0, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 }, | |
1075 | {"packw", 64, INSN_CLASS_ZBKB, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 }, | |
1076 | {"andn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 }, | |
1077 | {"orn", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 }, | |
1078 | {"xnor", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 }, | |
1079 | {"rol", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 }, | |
f438659a | 1080 | {"rori", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 }, |
3d1cafa0 | 1081 | {"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 }, |
1082 | {"ror", 0, INSN_CLASS_ZBB_OR_ZBKB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS }, | |
1083 | {"rev8", 32, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32, MASK_GREVI | MASK_SHAMT, match_opcode, 0 }, | |
1084 | {"rev8", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64, MASK_GREVI | MASK_SHAMT, match_opcode, 0 }, | |
1085 | {"rolw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 }, | |
f438659a | 1086 | {"roriw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 }, |
3d1cafa0 | 1087 | {"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 }, |
839189bc | 1088 | {"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS }, |
3d1cafa0 | 1089 | |
1090 | /* Zba instructions. */ | |
80d49d6a KLC |
1091 | {"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 }, |
1092 | {"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 }, | |
1093 | {"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 }, | |
1094 | {"sh1add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 }, | |
1095 | {"sh2add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 }, | |
1096 | {"sh3add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 }, | |
b5c37946 | 1097 | {"zext.w", 64, INSN_CLASS_ZCB_AND_ZBA, "Cs,Cw", MATCH_C_ZEXT_W, MASK_C_ZEXT_W, match_opcode, INSN_ALIAS }, |
80d49d6a | 1098 | {"zext.w", 64, INSN_CLASS_ZBA, "d,s", MATCH_ADD_UW, MASK_ADD_UW | MASK_RS2, match_opcode, INSN_ALIAS }, |
27b33966 | 1099 | {"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, NULL, INSN_MACRO }, |
80d49d6a KLC |
1100 | {"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 }, |
1101 | {"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 }, | |
cda0561f | 1102 | |
3d1cafa0 | 1103 | /* Zbc or zbkc instructions. */ |
1104 | {"clmul", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 }, | |
1105 | {"clmulh", 0, INSN_CLASS_ZBC_OR_ZBKC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 }, | |
80d49d6a KLC |
1106 | {"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 }, |
1107 | ||
3d1cafa0 | 1108 | /* Zbs instructions. */ |
f438659a | 1109 | {"bclri", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 }, |
9455c919 | 1110 | {"bclr", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 }, |
8baf3d07 | 1111 | {"bclr", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS }, |
f438659a | 1112 | {"bseti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, 0 }, |
9455c919 | 1113 | {"bset", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 }, |
8baf3d07 | 1114 | {"bset", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS }, |
f438659a | 1115 | {"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 }, |
9455c919 | 1116 | {"binv", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 }, |
8baf3d07 | 1117 | {"binv", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS }, |
f438659a | 1118 | {"bexti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 }, |
9455c919 | 1119 | {"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 }, |
8baf3d07 | 1120 | {"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS }, |
e23eba97 | 1121 | |
3d1cafa0 | 1122 | /* Zbkx instructions. */ |
1123 | {"xperm4", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 }, | |
1124 | {"xperm8", 0, INSN_CLASS_ZBKX, "d,s,t", MATCH_XPERM8, MASK_XPERM8, match_opcode, 0 }, | |
1125 | ||
1126 | /* Zknd instructions. */ | |
1127 | {"aes32dsi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSI, MASK_AES32DSI, match_opcode, 0 }, | |
1128 | {"aes32dsmi", 32, INSN_CLASS_ZKND, "d,s,t,y", MATCH_AES32DSMI, MASK_AES32DSMI, match_opcode, 0 }, | |
1129 | {"aes64ds", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DS, MASK_AES64DS, match_opcode, 0 }, | |
1130 | {"aes64dsm", 64, INSN_CLASS_ZKND, "d,s,t", MATCH_AES64DSM, MASK_AES64DSM, match_opcode, 0 }, | |
1131 | {"aes64im", 64, INSN_CLASS_ZKND, "d,s", MATCH_AES64IM, MASK_AES64IM, match_opcode, 0 }, | |
1132 | {"aes64ks1i", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,Y", MATCH_AES64KS1I, MASK_AES64KS1I, match_opcode, 0 }, | |
1133 | {"aes64ks2", 64, INSN_CLASS_ZKND_OR_ZKNE, "d,s,t", MATCH_AES64KS2, MASK_AES64KS2, match_opcode, 0 }, | |
1134 | ||
1135 | /* Zkne instructions. */ | |
1136 | {"aes32esi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESI, MASK_AES32ESI, match_opcode, 0 }, | |
1137 | {"aes32esmi", 32, INSN_CLASS_ZKNE, "d,s,t,y", MATCH_AES32ESMI, MASK_AES32ESMI, match_opcode, 0 }, | |
1138 | {"aes64es", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ES, MASK_AES64ES, match_opcode, 0 }, | |
1139 | {"aes64esm", 64, INSN_CLASS_ZKNE, "d,s,t", MATCH_AES64ESM, MASK_AES64ESM, match_opcode, 0 }, | |
1140 | ||
1141 | /* Zknh instructions. */ | |
1142 | {"sha256sig0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG0, MASK_SHA256SIG0, match_opcode, 0 }, | |
1143 | {"sha256sig1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SIG1, MASK_SHA256SIG1, match_opcode, 0 }, | |
1144 | {"sha256sum0", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM0, MASK_SHA256SUM0, match_opcode, 0 }, | |
1145 | {"sha256sum1", 0, INSN_CLASS_ZKNH, "d,s", MATCH_SHA256SUM1, MASK_SHA256SUM1, match_opcode, 0 }, | |
1146 | {"sha512sig0h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0H, MASK_SHA512SIG0H, match_opcode, 0 }, | |
1147 | {"sha512sig0l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG0L, MASK_SHA512SIG0L, match_opcode, 0 }, | |
1148 | {"sha512sig1h", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1H, MASK_SHA512SIG1H, match_opcode, 0 }, | |
1149 | {"sha512sig1l", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SIG1L, MASK_SHA512SIG1L, match_opcode, 0 }, | |
1150 | {"sha512sum0r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM0R, MASK_SHA512SUM0R, match_opcode, 0 }, | |
1151 | {"sha512sum1r", 32, INSN_CLASS_ZKNH, "d,s,t", MATCH_SHA512SUM1R, MASK_SHA512SUM1R, match_opcode, 0 }, | |
1152 | {"sha512sig0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG0, MASK_SHA512SIG0, match_opcode, 0 }, | |
1153 | {"sha512sig1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SIG1, MASK_SHA512SIG1, match_opcode, 0 }, | |
1154 | {"sha512sum0", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM0, MASK_SHA512SUM0, match_opcode, 0 }, | |
1155 | {"sha512sum1", 64, INSN_CLASS_ZKNH, "d,s", MATCH_SHA512SUM1, MASK_SHA512SUM1, match_opcode, 0 }, | |
1156 | ||
1157 | /* Zksed instructions. */ | |
1158 | {"sm4ed", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4ED, MASK_SM4ED, match_opcode, 0 }, | |
1159 | {"sm4ks", 0, INSN_CLASS_ZKSED, "d,s,t,y", MATCH_SM4KS, MASK_SM4KS, match_opcode, 0 }, | |
1160 | ||
1161 | /* Zksh instructions */ | |
1162 | {"sm3p0", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P0, MASK_SM3P0, match_opcode, 0 }, | |
1163 | {"sm3p1", 0, INSN_CLASS_ZKSH, "d,s", MATCH_SM3P1, MASK_SM3P1, match_opcode, 0 }, | |
1164 | ||
65e4a99a NC |
1165 | /* RVV instructions. */ |
1166 | {"vsetvl", 0, INSN_CLASS_V, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0}, | |
1167 | {"vsetvli", 0, INSN_CLASS_V, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0}, | |
1168 | {"vsetivli", 0, INSN_CLASS_V, "d,Z,Vb", MATCH_VSETIVLI, MASK_VSETIVLI, match_opcode, 0}, | |
1169 | ||
1170 | {"vlm.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VLMV, MASK_VLMV, match_opcode, INSN_DREF }, | |
1171 | {"vsm.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VSMV, MASK_VSMV, match_opcode, INSN_DREF }, | |
1172 | {"vle1.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VLMV, MASK_VLMV, match_opcode, INSN_DREF|INSN_ALIAS }, | |
1173 | {"vse1.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VSMV, MASK_VSMV, match_opcode, INSN_DREF|INSN_ALIAS }, | |
1174 | ||
1175 | {"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF }, | |
1176 | {"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF }, | |
1177 | {"vle32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF }, | |
1178 | {"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1179 | ||
1180 | {"vse8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF }, | |
1181 | {"vse16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF }, | |
1182 | {"vse32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF }, | |
1183 | {"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1184 | ||
1185 | {"vlse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF }, | |
1186 | {"vlse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF }, | |
1187 | {"vlse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF }, | |
1188 | {"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1189 | ||
1190 | {"vsse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF }, | |
1191 | {"vsse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF }, | |
1192 | {"vsse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF }, | |
1193 | {"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1194 | ||
1195 | {"vloxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_opcode, INSN_DREF }, | |
1196 | {"vloxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_opcode, INSN_DREF }, | |
1197 | {"vloxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_opcode, INSN_DREF }, | |
1198 | {"vloxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1199 | ||
1200 | {"vsoxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_opcode, INSN_DREF }, | |
1201 | {"vsoxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_opcode, INSN_DREF }, | |
1202 | {"vsoxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_opcode, INSN_DREF }, | |
1203 | {"vsoxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1204 | ||
1205 | {"vluxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_opcode, INSN_DREF }, | |
1206 | {"vluxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_opcode, INSN_DREF }, | |
1207 | {"vluxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_opcode, INSN_DREF }, | |
1208 | {"vluxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1209 | ||
1210 | {"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF }, | |
1211 | {"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF }, | |
1212 | {"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF }, | |
1213 | {"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1214 | ||
1215 | {"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF }, | |
1216 | {"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF }, | |
1217 | {"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF }, | |
1218 | {"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1219 | ||
1220 | {"vlseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_opcode, INSN_DREF }, | |
1221 | {"vsseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF }, | |
1222 | {"vlseg3e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_opcode, INSN_DREF }, | |
1223 | {"vsseg3e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_opcode, INSN_DREF }, | |
1224 | {"vlseg4e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_opcode, INSN_DREF }, | |
1225 | {"vsseg4e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_opcode, INSN_DREF }, | |
1226 | {"vlseg5e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_opcode, INSN_DREF }, | |
1227 | {"vsseg5e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_opcode, INSN_DREF }, | |
1228 | {"vlseg6e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_opcode, INSN_DREF }, | |
1229 | {"vsseg6e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_opcode, INSN_DREF }, | |
1230 | {"vlseg7e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_opcode, INSN_DREF }, | |
1231 | {"vsseg7e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_opcode, INSN_DREF }, | |
1232 | {"vlseg8e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_opcode, INSN_DREF }, | |
1233 | {"vsseg8e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_opcode, INSN_DREF }, | |
1234 | ||
1235 | {"vlseg2e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_opcode, INSN_DREF }, | |
1236 | {"vsseg2e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_opcode, INSN_DREF }, | |
1237 | {"vlseg3e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_opcode, INSN_DREF }, | |
1238 | {"vsseg3e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_opcode, INSN_DREF }, | |
1239 | {"vlseg4e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_opcode, INSN_DREF }, | |
1240 | {"vsseg4e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_opcode, INSN_DREF }, | |
1241 | {"vlseg5e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_opcode, INSN_DREF }, | |
1242 | {"vsseg5e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_opcode, INSN_DREF }, | |
1243 | {"vlseg6e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_opcode, INSN_DREF }, | |
1244 | {"vsseg6e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_opcode, INSN_DREF }, | |
1245 | {"vlseg7e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_opcode, INSN_DREF }, | |
1246 | {"vsseg7e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_opcode, INSN_DREF }, | |
1247 | {"vlseg8e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_opcode, INSN_DREF }, | |
1248 | {"vsseg8e16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_opcode, INSN_DREF }, | |
1249 | ||
1250 | {"vlseg2e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_opcode, INSN_DREF }, | |
1251 | {"vsseg2e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_opcode, INSN_DREF }, | |
1252 | {"vlseg3e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_opcode, INSN_DREF }, | |
1253 | {"vsseg3e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_opcode, INSN_DREF }, | |
1254 | {"vlseg4e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_opcode, INSN_DREF }, | |
1255 | {"vsseg4e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_opcode, INSN_DREF }, | |
1256 | {"vlseg5e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_opcode, INSN_DREF }, | |
1257 | {"vsseg5e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_opcode, INSN_DREF }, | |
1258 | {"vlseg6e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_opcode, INSN_DREF }, | |
1259 | {"vsseg6e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_opcode, INSN_DREF }, | |
1260 | {"vlseg7e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_opcode, INSN_DREF }, | |
1261 | {"vsseg7e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_opcode, INSN_DREF }, | |
1262 | {"vlseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_opcode, INSN_DREF }, | |
1263 | {"vsseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF }, | |
1264 | ||
1265 | {"vlseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1266 | {"vsseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1267 | {"vlseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1268 | {"vsseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1269 | {"vlseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1270 | {"vsseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1271 | {"vlseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1272 | {"vsseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1273 | {"vlseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1274 | {"vsseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1275 | {"vlseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1276 | {"vsseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1277 | {"vlseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1278 | {"vsseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1279 | ||
1280 | {"vlsseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_opcode, INSN_DREF }, | |
1281 | {"vssseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF }, | |
1282 | {"vlsseg3e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_opcode, INSN_DREF }, | |
1283 | {"vssseg3e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_opcode, INSN_DREF }, | |
1284 | {"vlsseg4e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_opcode, INSN_DREF }, | |
1285 | {"vssseg4e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_opcode, INSN_DREF }, | |
1286 | {"vlsseg5e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_opcode, INSN_DREF }, | |
1287 | {"vssseg5e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_opcode, INSN_DREF }, | |
1288 | {"vlsseg6e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_opcode, INSN_DREF }, | |
1289 | {"vssseg6e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_opcode, INSN_DREF }, | |
1290 | {"vlsseg7e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_opcode, INSN_DREF }, | |
1291 | {"vssseg7e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_opcode, INSN_DREF }, | |
1292 | {"vlsseg8e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_opcode, INSN_DREF }, | |
1293 | {"vssseg8e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_opcode, INSN_DREF }, | |
1294 | ||
1295 | {"vlsseg2e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_opcode, INSN_DREF }, | |
1296 | {"vssseg2e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF }, | |
1297 | {"vlsseg3e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_opcode, INSN_DREF }, | |
1298 | {"vssseg3e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_opcode, INSN_DREF }, | |
1299 | {"vlsseg4e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_opcode, INSN_DREF }, | |
1300 | {"vssseg4e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_opcode, INSN_DREF }, | |
1301 | {"vlsseg5e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_opcode, INSN_DREF }, | |
1302 | {"vssseg5e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_opcode, INSN_DREF }, | |
1303 | {"vlsseg6e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_opcode, INSN_DREF }, | |
1304 | {"vssseg6e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_opcode, INSN_DREF }, | |
1305 | {"vlsseg7e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_opcode, INSN_DREF }, | |
1306 | {"vssseg7e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_opcode, INSN_DREF }, | |
1307 | {"vlsseg8e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_opcode, INSN_DREF }, | |
1308 | {"vssseg8e16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_opcode, INSN_DREF }, | |
1309 | ||
1310 | {"vlsseg2e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_opcode, INSN_DREF }, | |
1311 | {"vssseg2e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF }, | |
1312 | {"vlsseg3e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_opcode, INSN_DREF }, | |
1313 | {"vssseg3e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_opcode, INSN_DREF }, | |
1314 | {"vlsseg4e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_opcode, INSN_DREF }, | |
1315 | {"vssseg4e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_opcode, INSN_DREF }, | |
1316 | {"vlsseg5e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_opcode, INSN_DREF }, | |
1317 | {"vssseg5e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_opcode, INSN_DREF }, | |
1318 | {"vlsseg6e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_opcode, INSN_DREF }, | |
1319 | {"vssseg6e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_opcode, INSN_DREF }, | |
1320 | {"vlsseg7e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_opcode, INSN_DREF }, | |
1321 | {"vssseg7e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_opcode, INSN_DREF }, | |
1322 | {"vlsseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_opcode, INSN_DREF }, | |
1323 | {"vssseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF }, | |
1324 | ||
1325 | {"vlsseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1326 | {"vssseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1327 | {"vlsseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1328 | {"vssseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1329 | {"vlsseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1330 | {"vssseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1331 | {"vlsseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1332 | {"vssseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1333 | {"vlsseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1334 | {"vssseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1335 | {"vlsseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1336 | {"vssseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1337 | {"vlsseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1338 | {"vssseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1339 | ||
1340 | {"vloxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_opcode, INSN_DREF }, | |
1341 | {"vsoxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_opcode, INSN_DREF }, | |
1342 | {"vloxseg3ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_opcode, INSN_DREF }, | |
1343 | {"vsoxseg3ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_opcode, INSN_DREF }, | |
1344 | {"vloxseg4ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_opcode, INSN_DREF }, | |
1345 | {"vsoxseg4ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_opcode, INSN_DREF }, | |
1346 | {"vloxseg5ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_opcode, INSN_DREF }, | |
1347 | {"vsoxseg5ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_opcode, INSN_DREF }, | |
1348 | {"vloxseg6ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_opcode, INSN_DREF }, | |
1349 | {"vsoxseg6ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_opcode, INSN_DREF }, | |
1350 | {"vloxseg7ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_opcode, INSN_DREF }, | |
1351 | {"vsoxseg7ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_opcode, INSN_DREF }, | |
1352 | {"vloxseg8ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_opcode, INSN_DREF }, | |
1353 | {"vsoxseg8ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_opcode, INSN_DREF }, | |
1354 | ||
1355 | {"vloxseg2ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_opcode, INSN_DREF }, | |
1356 | {"vsoxseg2ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_opcode, INSN_DREF }, | |
1357 | {"vloxseg3ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_opcode, INSN_DREF }, | |
1358 | {"vsoxseg3ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_opcode, INSN_DREF }, | |
1359 | {"vloxseg4ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_opcode, INSN_DREF }, | |
1360 | {"vsoxseg4ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_opcode, INSN_DREF }, | |
1361 | {"vloxseg5ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_opcode, INSN_DREF }, | |
1362 | {"vsoxseg5ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_opcode, INSN_DREF }, | |
1363 | {"vloxseg6ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_opcode, INSN_DREF }, | |
1364 | {"vsoxseg6ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_opcode, INSN_DREF }, | |
1365 | {"vloxseg7ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_opcode, INSN_DREF }, | |
1366 | {"vsoxseg7ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_opcode, INSN_DREF }, | |
1367 | {"vloxseg8ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_opcode, INSN_DREF }, | |
1368 | {"vsoxseg8ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_opcode, INSN_DREF }, | |
1369 | ||
1370 | {"vloxseg2ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_opcode, INSN_DREF }, | |
1371 | {"vsoxseg2ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_opcode, INSN_DREF }, | |
1372 | {"vloxseg3ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_opcode, INSN_DREF }, | |
1373 | {"vsoxseg3ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_opcode, INSN_DREF }, | |
1374 | {"vloxseg4ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_opcode, INSN_DREF }, | |
1375 | {"vsoxseg4ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_opcode, INSN_DREF }, | |
1376 | {"vloxseg5ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_opcode, INSN_DREF }, | |
1377 | {"vsoxseg5ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_opcode, INSN_DREF }, | |
1378 | {"vloxseg6ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_opcode, INSN_DREF }, | |
1379 | {"vsoxseg6ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_opcode, INSN_DREF }, | |
1380 | {"vloxseg7ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_opcode, INSN_DREF }, | |
1381 | {"vsoxseg7ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_opcode, INSN_DREF }, | |
1382 | {"vloxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_opcode, INSN_DREF }, | |
1383 | {"vsoxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_opcode, INSN_DREF }, | |
1384 | ||
1385 | {"vloxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1386 | {"vsoxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1387 | {"vloxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1388 | {"vsoxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1389 | {"vloxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1390 | {"vsoxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1391 | {"vloxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1392 | {"vsoxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1393 | {"vloxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1394 | {"vsoxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1395 | {"vloxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1396 | {"vsoxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1397 | {"vloxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1398 | {"vsoxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1399 | ||
1400 | {"vluxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_opcode, INSN_DREF }, | |
1401 | {"vsuxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_opcode, INSN_DREF }, | |
1402 | {"vluxseg3ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI8V, MASK_VLUXSEG3EI8V, match_opcode, INSN_DREF }, | |
1403 | {"vsuxseg3ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI8V, MASK_VSUXSEG3EI8V, match_opcode, INSN_DREF }, | |
1404 | {"vluxseg4ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI8V, MASK_VLUXSEG4EI8V, match_opcode, INSN_DREF }, | |
1405 | {"vsuxseg4ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI8V, MASK_VSUXSEG4EI8V, match_opcode, INSN_DREF }, | |
1406 | {"vluxseg5ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI8V, MASK_VLUXSEG5EI8V, match_opcode, INSN_DREF }, | |
1407 | {"vsuxseg5ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI8V, MASK_VSUXSEG5EI8V, match_opcode, INSN_DREF }, | |
1408 | {"vluxseg6ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI8V, MASK_VLUXSEG6EI8V, match_opcode, INSN_DREF }, | |
1409 | {"vsuxseg6ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI8V, MASK_VSUXSEG6EI8V, match_opcode, INSN_DREF }, | |
1410 | {"vluxseg7ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI8V, MASK_VLUXSEG7EI8V, match_opcode, INSN_DREF }, | |
1411 | {"vsuxseg7ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI8V, MASK_VSUXSEG7EI8V, match_opcode, INSN_DREF }, | |
1412 | {"vluxseg8ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI8V, MASK_VLUXSEG8EI8V, match_opcode, INSN_DREF }, | |
1413 | {"vsuxseg8ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI8V, MASK_VSUXSEG8EI8V, match_opcode, INSN_DREF }, | |
1414 | ||
1415 | {"vluxseg2ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI16V, MASK_VLUXSEG2EI16V, match_opcode, INSN_DREF }, | |
1416 | {"vsuxseg2ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI16V, MASK_VSUXSEG2EI16V, match_opcode, INSN_DREF }, | |
1417 | {"vluxseg3ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI16V, MASK_VLUXSEG3EI16V, match_opcode, INSN_DREF }, | |
1418 | {"vsuxseg3ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI16V, MASK_VSUXSEG3EI16V, match_opcode, INSN_DREF }, | |
1419 | {"vluxseg4ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI16V, MASK_VLUXSEG4EI16V, match_opcode, INSN_DREF }, | |
1420 | {"vsuxseg4ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI16V, MASK_VSUXSEG4EI16V, match_opcode, INSN_DREF }, | |
1421 | {"vluxseg5ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI16V, MASK_VLUXSEG5EI16V, match_opcode, INSN_DREF }, | |
1422 | {"vsuxseg5ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI16V, MASK_VSUXSEG5EI16V, match_opcode, INSN_DREF }, | |
1423 | {"vluxseg6ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI16V, MASK_VLUXSEG6EI16V, match_opcode, INSN_DREF }, | |
1424 | {"vsuxseg6ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI16V, MASK_VSUXSEG6EI16V, match_opcode, INSN_DREF }, | |
1425 | {"vluxseg7ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI16V, MASK_VLUXSEG7EI16V, match_opcode, INSN_DREF }, | |
1426 | {"vsuxseg7ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI16V, MASK_VSUXSEG7EI16V, match_opcode, INSN_DREF }, | |
1427 | {"vluxseg8ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI16V, MASK_VLUXSEG8EI16V, match_opcode, INSN_DREF }, | |
1428 | {"vsuxseg8ei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI16V, MASK_VSUXSEG8EI16V, match_opcode, INSN_DREF }, | |
1429 | ||
1430 | {"vluxseg2ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI32V, MASK_VLUXSEG2EI32V, match_opcode, INSN_DREF }, | |
1431 | {"vsuxseg2ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI32V, MASK_VSUXSEG2EI32V, match_opcode, INSN_DREF }, | |
1432 | {"vluxseg3ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI32V, MASK_VLUXSEG3EI32V, match_opcode, INSN_DREF }, | |
1433 | {"vsuxseg3ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI32V, MASK_VSUXSEG3EI32V, match_opcode, INSN_DREF }, | |
1434 | {"vluxseg4ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI32V, MASK_VLUXSEG4EI32V, match_opcode, INSN_DREF }, | |
1435 | {"vsuxseg4ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI32V, MASK_VSUXSEG4EI32V, match_opcode, INSN_DREF }, | |
1436 | {"vluxseg5ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI32V, MASK_VLUXSEG5EI32V, match_opcode, INSN_DREF }, | |
1437 | {"vsuxseg5ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI32V, MASK_VSUXSEG5EI32V, match_opcode, INSN_DREF }, | |
1438 | {"vluxseg6ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI32V, MASK_VLUXSEG6EI32V, match_opcode, INSN_DREF }, | |
1439 | {"vsuxseg6ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI32V, MASK_VSUXSEG6EI32V, match_opcode, INSN_DREF }, | |
1440 | {"vluxseg7ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI32V, MASK_VLUXSEG7EI32V, match_opcode, INSN_DREF }, | |
1441 | {"vsuxseg7ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI32V, MASK_VSUXSEG7EI32V, match_opcode, INSN_DREF }, | |
1442 | {"vluxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_opcode, INSN_DREF }, | |
1443 | {"vsuxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_opcode, INSN_DREF }, | |
1444 | ||
1445 | {"vluxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1446 | {"vsuxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1447 | {"vluxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1448 | {"vsuxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1449 | {"vluxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1450 | {"vsuxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1451 | {"vluxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1452 | {"vsuxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1453 | {"vluxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1454 | {"vsuxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1455 | {"vluxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1456 | {"vsuxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1457 | {"vluxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1458 | {"vsuxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1459 | ||
1460 | {"vlseg2e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_opcode, INSN_DREF }, | |
1461 | {"vlseg3e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_opcode, INSN_DREF }, | |
1462 | {"vlseg4e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_opcode, INSN_DREF }, | |
1463 | {"vlseg5e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_opcode, INSN_DREF }, | |
1464 | {"vlseg6e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_opcode, INSN_DREF }, | |
1465 | {"vlseg7e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_opcode, INSN_DREF }, | |
1466 | {"vlseg8e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_opcode, INSN_DREF }, | |
1467 | ||
1468 | {"vlseg2e16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_opcode, INSN_DREF }, | |
1469 | {"vlseg3e16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_opcode, INSN_DREF }, | |
1470 | {"vlseg4e16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_opcode, INSN_DREF }, | |
1471 | {"vlseg5e16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_opcode, INSN_DREF }, | |
1472 | {"vlseg6e16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_opcode, INSN_DREF }, | |
1473 | {"vlseg7e16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_opcode, INSN_DREF }, | |
1474 | {"vlseg8e16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_opcode, INSN_DREF }, | |
1475 | ||
1476 | {"vlseg2e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_opcode, INSN_DREF }, | |
1477 | {"vlseg3e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_opcode, INSN_DREF }, | |
1478 | {"vlseg4e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_opcode, INSN_DREF }, | |
1479 | {"vlseg5e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_opcode, INSN_DREF }, | |
1480 | {"vlseg6e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_opcode, INSN_DREF }, | |
1481 | {"vlseg7e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_opcode, INSN_DREF }, | |
1482 | {"vlseg8e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_opcode, INSN_DREF }, | |
1483 | ||
1484 | {"vlseg2e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1485 | {"vlseg3e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1486 | {"vlseg4e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1487 | {"vlseg5e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1488 | {"vlseg6e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1489 | {"vlseg7e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1490 | {"vlseg8e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1491 | ||
1492 | {"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, | |
1493 | {"vl1re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF }, | |
1494 | {"vl1re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_opcode, INSN_DREF }, | |
1495 | {"vl1re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_opcode, INSN_DREF }, | |
1496 | {"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1497 | ||
1498 | {"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, | |
1499 | {"vl2re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF }, | |
1500 | {"vl2re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_opcode, INSN_DREF }, | |
1501 | {"vl2re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_opcode, INSN_DREF }, | |
1502 | {"vl2re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1503 | ||
1504 | {"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, | |
1505 | {"vl4re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF }, | |
1506 | {"vl4re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_opcode, INSN_DREF }, | |
1507 | {"vl4re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_opcode, INSN_DREF }, | |
1508 | {"vl4re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1509 | ||
1510 | {"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, | |
1511 | {"vl8re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF }, | |
1512 | {"vl8re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_opcode, INSN_DREF }, | |
1513 | {"vl8re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_opcode, INSN_DREF }, | |
1514 | {"vl8re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, | |
1515 | ||
1516 | {"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF }, | |
1517 | {"vs2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_opcode, INSN_DREF }, | |
1518 | {"vs4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_opcode, INSN_DREF }, | |
1519 | {"vs8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_opcode, INSN_DREF }, | |
1520 | ||
1521 | {"vneg.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_opcode, INSN_ALIAS }, | |
1522 | ||
1523 | {"vadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 }, | |
1524 | {"vadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 }, | |
1525 | {"vadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 }, | |
1526 | {"vsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 }, | |
1527 | {"vsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 }, | |
1528 | {"vrsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 }, | |
1529 | {"vrsub.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 }, | |
1530 | ||
1531 | {"vwcvt.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_opcode, INSN_ALIAS }, | |
1532 | {"vwcvtu.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_opcode, INSN_ALIAS }, | |
1533 | ||
1534 | {"vwaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_opcode, 0 }, | |
1535 | {"vwaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_opcode, 0 }, | |
1536 | {"vwsubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_opcode, 0 }, | |
1537 | {"vwsubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_opcode, 0 }, | |
1538 | {"vwadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_opcode, 0 }, | |
1539 | {"vwadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_opcode, 0 }, | |
1540 | {"vwsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_opcode, 0 }, | |
1541 | {"vwsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_opcode, 0 }, | |
1542 | {"vwaddu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_opcode, 0 }, | |
1543 | {"vwaddu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_opcode, 0 }, | |
1544 | {"vwsubu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_opcode, 0 }, | |
1545 | {"vwsubu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_opcode, 0 }, | |
1546 | {"vwadd.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_opcode, 0 }, | |
1547 | {"vwadd.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_opcode, 0 }, | |
1548 | {"vwsub.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_opcode, 0 }, | |
1549 | {"vwsub.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_opcode, 0 }, | |
1550 | ||
1551 | {"vzext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_opcode, 0 }, | |
1552 | {"vsext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_opcode, 0 }, | |
1553 | {"vzext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_opcode, 0 }, | |
1554 | {"vsext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_opcode, 0 }, | |
1555 | {"vzext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_opcode, 0 }, | |
1556 | {"vsext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_opcode, 0 }, | |
1557 | ||
1558 | {"vadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_opcode, 0 }, | |
1559 | {"vadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_opcode, 0 }, | |
1560 | {"vadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_opcode, 0 }, | |
1561 | {"vmadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 }, | |
1562 | {"vmadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 }, | |
1563 | {"vmadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 }, | |
1564 | {"vmadc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 }, | |
1565 | {"vmadc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 }, | |
1566 | {"vmadc.vi", 0, INSN_CLASS_V, "Vd,Vt,Vi", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 }, | |
1567 | {"vsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_opcode, 0 }, | |
1568 | {"vsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_opcode, 0 }, | |
1569 | {"vmsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 }, | |
1570 | {"vmsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 }, | |
1571 | {"vmsbc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 }, | |
1572 | {"vmsbc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 }, | |
1573 | ||
1574 | {"vnot.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS }, | |
1575 | ||
1576 | {"vand.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 }, | |
1577 | {"vand.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 }, | |
1578 | {"vand.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 }, | |
1579 | {"vor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 }, | |
1580 | {"vor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 }, | |
1581 | {"vor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 }, | |
1582 | {"vxor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 }, | |
1583 | {"vxor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 }, | |
1584 | {"vxor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 }, | |
1585 | ||
1586 | {"vsll.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 }, | |
1587 | {"vsll.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 }, | |
1588 | {"vsll.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 }, | |
1589 | {"vsrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 }, | |
1590 | {"vsrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 }, | |
1591 | {"vsrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 }, | |
1592 | {"vsra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 }, | |
1593 | {"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 }, | |
1594 | {"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 }, | |
1595 | ||
1596 | {"vncvt.x.x.w",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_opcode, INSN_ALIAS }, | |
1597 | ||
1598 | {"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_opcode, 0 }, | |
1599 | {"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_opcode, 0 }, | |
1600 | {"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_opcode, 0 }, | |
1601 | {"vnsra.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_opcode, 0 }, | |
1602 | {"vnsra.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_opcode, 0 }, | |
1603 | {"vnsra.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_opcode, 0 }, | |
1604 | ||
1605 | {"vmseq.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 }, | |
1606 | {"vmseq.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 }, | |
1607 | {"vmseq.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 }, | |
1608 | {"vmsne.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 }, | |
1609 | {"vmsne.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 }, | |
1610 | {"vmsne.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 }, | |
1611 | {"vmsltu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 }, | |
1612 | {"vmsltu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 }, | |
1613 | {"vmslt.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 }, | |
1614 | {"vmslt.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 }, | |
1615 | {"vmsleu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 }, | |
1616 | {"vmsleu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 }, | |
1617 | {"vmsleu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 }, | |
1618 | {"vmsle.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 }, | |
1619 | {"vmsle.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 }, | |
1620 | {"vmsle.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 }, | |
1621 | {"vmsgtu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 }, | |
1622 | {"vmsgtu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 }, | |
1623 | {"vmsgt.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 }, | |
1624 | {"vmsgt.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 }, | |
1625 | {"vmsgt.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS }, | |
1626 | {"vmsgtu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS }, | |
1627 | {"vmsge.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS }, | |
1628 | {"vmsgeu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS }, | |
1629 | {"vmslt.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS }, | |
1630 | {"vmsltu.vi", 0, INSN_CLASS_V, "Vd,Vu,0Vm", MATCH_VMSNEVV, MASK_VMSNEVV, match_vs1_eq_vs2, INSN_ALIAS }, | |
1631 | {"vmsltu.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS }, | |
1632 | {"vmsge.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS }, | |
1633 | {"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vu,0Vm", MATCH_VMSEQVV, MASK_VMSEQVV, match_vs1_eq_vs2, INSN_ALIAS }, | |
1634 | {"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS }, | |
1635 | ||
27b33966 JB |
1636 | {"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, NULL, INSN_MACRO }, |
1637 | {"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, NULL, INSN_MACRO }, | |
1638 | {"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 1, (int) M_VMSGE, NULL, INSN_MACRO }, | |
1639 | {"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, NULL, INSN_MACRO }, | |
65e4a99a NC |
1640 | |
1641 | {"vminu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0}, | |
1642 | {"vminu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0}, | |
1643 | {"vmin.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0}, | |
1644 | {"vmin.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0}, | |
1645 | {"vmaxu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0}, | |
1646 | {"vmaxu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0}, | |
1647 | {"vmax.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0}, | |
1648 | {"vmax.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0}, | |
1649 | ||
1650 | {"vmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 }, | |
1651 | {"vmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 }, | |
1652 | {"vmulh.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 }, | |
1653 | {"vmulh.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 }, | |
1654 | {"vmulhu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 }, | |
1655 | {"vmulhu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 }, | |
1656 | {"vmulhsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 }, | |
1657 | {"vmulhsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 }, | |
1658 | ||
1659 | {"vwmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_opcode, 0 }, | |
1660 | {"vwmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_opcode, 0 }, | |
1661 | {"vwmulu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_opcode, 0 }, | |
1662 | {"vwmulu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_opcode, 0 }, | |
1663 | {"vwmulsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_opcode, 0 }, | |
1664 | {"vwmulsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_opcode, 0 }, | |
1665 | ||
1666 | {"vmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0}, | |
1667 | {"vmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0}, | |
1668 | {"vnmsac.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0}, | |
1669 | {"vnmsac.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0}, | |
1670 | {"vmadd.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0}, | |
1671 | {"vmadd.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0}, | |
1672 | {"vnmsub.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0}, | |
1673 | {"vnmsub.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0}, | |
1674 | ||
1675 | {"vwmaccu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_opcode, 0}, | |
1676 | {"vwmaccu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_opcode, 0}, | |
1677 | {"vwmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_opcode, 0}, | |
1678 | {"vwmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_opcode, 0}, | |
1679 | {"vwmaccsu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_opcode, 0}, | |
1680 | {"vwmaccsu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_opcode, 0}, | |
1681 | {"vwmaccus.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_opcode, 0}, | |
1682 | ||
1683 | {"vdivu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 }, | |
1684 | {"vdivu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 }, | |
1685 | {"vdiv.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 }, | |
1686 | {"vdiv.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 }, | |
1687 | {"vremu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 }, | |
1688 | {"vremu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 }, | |
1689 | {"vrem.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 }, | |
1690 | {"vrem.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 }, | |
1691 | ||
1692 | {"vmerge.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 }, | |
1693 | {"vmerge.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 }, | |
1694 | {"vmerge.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 }, | |
1695 | ||
1696 | {"vmv.v.v", 0, INSN_CLASS_V, "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 }, | |
1697 | {"vmv.v.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 }, | |
1698 | {"vmv.v.i", 0, INSN_CLASS_V, "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 }, | |
1699 | ||
1700 | {"vsaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 }, | |
1701 | {"vsaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 }, | |
1702 | {"vsaddu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 }, | |
1703 | {"vsadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 }, | |
1704 | {"vsadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 }, | |
1705 | {"vsadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 }, | |
1706 | {"vssubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 }, | |
1707 | {"vssubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 }, | |
1708 | {"vssub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 }, | |
1709 | {"vssub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 }, | |
1710 | ||
1711 | {"vaaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_opcode, 0 }, | |
1712 | {"vaaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_opcode, 0 }, | |
1713 | {"vaadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_opcode, 0 }, | |
1714 | {"vaadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_opcode, 0 }, | |
1715 | {"vasubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_opcode, 0 }, | |
1716 | {"vasubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_opcode, 0 }, | |
1717 | {"vasub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_opcode, 0 }, | |
1718 | {"vasub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_opcode, 0 }, | |
1719 | ||
1720 | {"vsmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 }, | |
1721 | {"vsmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 }, | |
1722 | ||
1723 | {"vssrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 }, | |
1724 | {"vssrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 }, | |
1725 | {"vssrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 }, | |
1726 | {"vssra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 }, | |
1727 | {"vssra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 }, | |
1728 | {"vssra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 }, | |
1729 | ||
1730 | {"vnclipu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_opcode, 0 }, | |
1731 | {"vnclipu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_opcode, 0 }, | |
1732 | {"vnclipu.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_opcode, 0 }, | |
1733 | {"vnclip.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_opcode, 0 }, | |
1734 | {"vnclip.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_opcode, 0 }, | |
1735 | {"vnclip.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_opcode, 0 }, | |
1736 | ||
1737 | {"vfadd.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0}, | |
1738 | {"vfadd.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0}, | |
1739 | {"vfsub.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0}, | |
1740 | {"vfsub.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0}, | |
1741 | {"vfrsub.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0}, | |
1742 | ||
1743 | {"vfwadd.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_opcode, 0}, | |
1744 | {"vfwadd.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_opcode, 0}, | |
1745 | {"vfwsub.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_opcode, 0}, | |
1746 | {"vfwsub.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_opcode, 0}, | |
1747 | {"vfwadd.wv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_opcode, 0}, | |
1748 | {"vfwadd.wf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_opcode, 0}, | |
1749 | {"vfwsub.wv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_opcode, 0}, | |
1750 | {"vfwsub.wf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_opcode, 0}, | |
1751 | ||
1752 | {"vfmul.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0}, | |
1753 | {"vfmul.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0}, | |
1754 | {"vfdiv.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0}, | |
1755 | {"vfdiv.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0}, | |
1756 | {"vfrdiv.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0}, | |
1757 | ||
1758 | {"vfwmul.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_opcode, 0}, | |
1759 | {"vfwmul.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_opcode, 0}, | |
1760 | ||
1761 | {"vfmadd.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0}, | |
1762 | {"vfmadd.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0}, | |
1763 | {"vfnmadd.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0}, | |
1764 | {"vfnmadd.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0}, | |
1765 | {"vfmsub.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0}, | |
1766 | {"vfmsub.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0}, | |
1767 | {"vfnmsub.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0}, | |
1768 | {"vfnmsub.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0}, | |
1769 | {"vfmacc.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0}, | |
1770 | {"vfmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0}, | |
1771 | {"vfnmacc.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0}, | |
1772 | {"vfnmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0}, | |
1773 | {"vfmsac.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0}, | |
1774 | {"vfmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0}, | |
1775 | {"vfnmsac.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0}, | |
1776 | {"vfnmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0}, | |
1777 | ||
1778 | {"vfwmacc.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_opcode, 0}, | |
1779 | {"vfwmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_opcode, 0}, | |
1780 | {"vfwnmacc.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_opcode, 0}, | |
1781 | {"vfwnmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_opcode, 0}, | |
1782 | {"vfwmsac.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_opcode, 0}, | |
1783 | {"vfwmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_opcode, 0}, | |
1784 | {"vfwnmsac.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_opcode, 0}, | |
1785 | {"vfwnmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_opcode, 0}, | |
1786 | ||
1787 | {"vfsqrt.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_opcode, 0}, | |
1788 | {"vfrsqrt7.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_opcode, 0}, | |
1789 | {"vfrsqrte7.v",0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_opcode, 0}, | |
1790 | {"vfrec7.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_opcode, 0}, | |
1791 | {"vfrece7.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_opcode, 0}, | |
1792 | {"vfclass.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0}, | |
1793 | ||
1794 | {"vfmin.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0}, | |
1795 | {"vfmin.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0}, | |
1796 | {"vfmax.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0}, | |
1797 | {"vfmax.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0}, | |
1798 | ||
1799 | {"vfneg.v", 0, INSN_CLASS_ZVEF, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2, INSN_ALIAS }, | |
1800 | {"vfabs.v", 0, INSN_CLASS_ZVEF, "Vd,VuVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vs1_eq_vs2, INSN_ALIAS }, | |
1801 | ||
1802 | {"vfsgnj.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0}, | |
1803 | {"vfsgnj.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0}, | |
1804 | {"vfsgnjn.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0}, | |
1805 | {"vfsgnjn.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0}, | |
1806 | {"vfsgnjx.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0}, | |
1807 | {"vfsgnjx.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0}, | |
1808 | ||
1809 | {"vmfeq.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0}, | |
1810 | {"vmfeq.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0}, | |
1811 | {"vmfne.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0}, | |
1812 | {"vmfne.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0}, | |
1813 | {"vmflt.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0}, | |
1814 | {"vmflt.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0}, | |
1815 | {"vmfle.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0}, | |
1816 | {"vmfle.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0}, | |
1817 | {"vmfgt.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0}, | |
1818 | {"vmfge.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0}, | |
1819 | ||
1820 | /* These aliases are for assembly but not disassembly. */ | |
1821 | {"vmfgt.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS}, | |
1822 | {"vmfge.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS}, | |
1823 | ||
1824 | {"vfmerge.vfm",0, INSN_CLASS_ZVEF, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0}, | |
1825 | {"vfmv.v.f", 0, INSN_CLASS_ZVEF, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 }, | |
1826 | ||
1827 | {"vfcvt.xu.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_opcode, 0}, | |
1828 | {"vfcvt.x.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_opcode, 0}, | |
1829 | {"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_opcode, 0}, | |
1830 | {"vfcvt.rtz.x.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_opcode, 0}, | |
1831 | {"vfcvt.f.xu.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_opcode, 0}, | |
1832 | {"vfcvt.f.x.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_opcode, 0}, | |
1833 | ||
1834 | {"vfwcvt.xu.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_opcode, 0}, | |
1835 | {"vfwcvt.x.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_opcode, 0}, | |
1836 | {"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_opcode, 0}, | |
1837 | {"vfwcvt.rtz.x.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_opcode, 0}, | |
1838 | {"vfwcvt.f.xu.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_opcode, 0}, | |
1839 | {"vfwcvt.f.x.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_opcode, 0}, | |
1840 | {"vfwcvt.f.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_opcode, 0}, | |
1841 | ||
1842 | {"vfncvt.xu.f.w", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_opcode, 0}, | |
1843 | {"vfncvt.x.f.w", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_opcode, 0}, | |
1844 | {"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_opcode, 0}, | |
1845 | {"vfncvt.rtz.x.f.w", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_opcode, 0}, | |
1846 | {"vfncvt.f.xu.w", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_opcode, 0}, | |
1847 | {"vfncvt.f.x.w", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_opcode, 0}, | |
1848 | {"vfncvt.f.f.w", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_opcode, 0}, | |
1849 | {"vfncvt.rod.f.f.w", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_opcode, 0}, | |
1850 | ||
1851 | {"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0}, | |
1852 | {"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0}, | |
1853 | {"vredmax.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0}, | |
1854 | {"vredminu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0}, | |
1855 | {"vredmin.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0}, | |
1856 | {"vredand.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0}, | |
1857 | {"vredor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0}, | |
1858 | {"vredxor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0}, | |
1859 | ||
1860 | {"vwredsumu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0}, | |
1861 | {"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0}, | |
1862 | ||
1863 | {"vfredosum.vs",0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0}, | |
1864 | {"vfredusum.vs",0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, 0}, | |
1865 | {"vfredsum.vs", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, INSN_ALIAS}, | |
1866 | {"vfredmax.vs", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0}, | |
1867 | {"vfredmin.vs", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0}, | |
1868 | ||
1869 | {"vfwredosum.vs",0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0}, | |
1870 | {"vfwredusum.vs",0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0}, | |
1871 | {"vfwredsum.vs", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, INSN_ALIAS}, | |
1872 | ||
1873 | {"vmmv.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS}, | |
1874 | {"vmcpy.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS}, | |
1875 | {"vmclr.m", 0, INSN_CLASS_V, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS}, | |
1876 | {"vmset.m", 0, INSN_CLASS_V, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS}, | |
1877 | {"vmnot.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS}, | |
1878 | ||
1879 | {"vmand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0}, | |
1880 | {"vmnand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0}, | |
1881 | {"vmandn.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, 0}, | |
1882 | {"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, INSN_ALIAS}, | |
1883 | {"vmxor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0}, | |
1884 | {"vmor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0}, | |
1885 | {"vmnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0}, | |
1886 | {"vmorn.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, 0}, | |
1887 | {"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, INSN_ALIAS}, | |
1888 | {"vmxnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0}, | |
1889 | ||
1890 | {"vcpop.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, 0}, | |
1891 | {"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, INSN_ALIAS}, | |
1892 | {"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0}, | |
1893 | {"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_opcode, 0}, | |
1894 | {"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_opcode, 0}, | |
1895 | {"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_opcode, 0}, | |
1896 | {"viota.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_opcode, 0}, | |
1897 | {"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_opcode, 0}, | |
1898 | ||
1899 | {"vmv.x.s", 0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0}, | |
1900 | {"vmv.s.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0}, | |
1901 | ||
1902 | {"vfmv.f.s", 0, INSN_CLASS_ZVEF, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0}, | |
1903 | {"vfmv.s.f", 0, INSN_CLASS_ZVEF, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0}, | |
1904 | ||
1905 | {"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_opcode, 0}, | |
1906 | {"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_opcode, 0}, | |
1907 | {"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0}, | |
1908 | {"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0}, | |
1909 | ||
1910 | {"vslide1up.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_opcode, 0}, | |
1911 | {"vslide1down.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0}, | |
1912 | {"vfslide1up.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_opcode, 0}, | |
1913 | {"vfslide1down.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_opcode, 0}, | |
1914 | ||
1915 | {"vrgather.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_opcode, 0}, | |
1916 | {"vrgather.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_opcode, 0}, | |
1917 | {"vrgather.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_opcode, 0}, | |
1918 | {"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_opcode, 0}, | |
1919 | ||
1920 | {"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_opcode, 0}, | |
1921 | ||
1922 | {"vmv1r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_opcode, 0}, | |
1923 | {"vmv2r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_opcode, 0}, | |
1924 | {"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0}, | |
1925 | {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0}, | |
1926 | ||
ea1bd007 CM |
1927 | /* Zvbb/Zvkb instructions. */ |
1928 | {"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0}, | |
1929 | {"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0}, | |
c8cb3734 | 1930 | {"vbrev.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VBREV_V, MASK_VBREV_V, match_opcode, 0}, |
ea1bd007 CM |
1931 | {"vbrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VBREV8_V, MASK_VBREV8_V, match_opcode, 0}, |
1932 | {"vrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VREV8_V, MASK_VREV8_V, match_opcode, 0}, | |
c8cb3734 CM |
1933 | {"vclz.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCLZ_V, MASK_VCLZ_V, match_opcode, 0}, |
1934 | {"vctz.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCTZ_V, MASK_VCTZ_V, match_opcode, 0}, | |
1935 | {"vcpop.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCPOP_V, MASK_VCPOP_V, match_opcode, 0}, | |
ea1bd007 CM |
1936 | {"vrol.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VROL_VV, MASK_VROL_VV, match_opcode, 0}, |
1937 | {"vrol.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VROL_VX, MASK_VROL_VX, match_opcode, 0}, | |
1938 | {"vror.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VROR_VV, MASK_VROR_VV, match_opcode, 0}, | |
1939 | {"vror.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VROR_VX, MASK_VROR_VX, match_opcode, 0}, | |
1940 | {"vror.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,VlVm", MATCH_VROR_VI, MASK_VROR_VI, match_opcode, 0}, | |
c8cb3734 CM |
1941 | {"vwsll.vv", 0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VWSLL_VV, MASK_VWSLL_VV, match_opcode, 0}, |
1942 | {"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0}, | |
1943 | {"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0}, | |
1944 | ||
c0a98a85 NH |
1945 | /* Zvbc instructions. */ |
1946 | {"vclmul.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0}, | |
1947 | {"vclmul.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0}, | |
1948 | {"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0}, | |
1949 | {"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0}, | |
1950 | ||
9d469329 CM |
1951 | /* Zvkg instructions. */ |
1952 | {"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0}, | |
1953 | {"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0}, | |
1954 | ||
fce8fef9 CM |
1955 | /* Zvkned instructions. */ |
1956 | {"vaesdf.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VV, MASK_VAESDF_VV, match_opcode, 0}, | |
1957 | {"vaesdf.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VS, MASK_VAESDF_VV, match_opcode, 0}, | |
1958 | {"vaesdm.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VV, MASK_VAESDM_VV, match_opcode, 0}, | |
1959 | {"vaesdm.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VS, MASK_VAESDM_VV, match_opcode, 0}, | |
1960 | {"vaesef.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VV, MASK_VAESEF_VV, match_opcode, 0}, | |
1961 | {"vaesef.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VS, MASK_VAESEF_VV, match_opcode, 0}, | |
1962 | {"vaesem.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VV, MASK_VAESEM_VV, match_opcode, 0}, | |
1963 | {"vaesem.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VS, MASK_VAESEM_VV, match_opcode, 0}, | |
1964 | {"vaeskf1.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF1_VI, MASK_VAESKF1_VI, match_opcode, 0}, | |
1965 | {"vaeskf2.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI, MASK_VAESKF2_VI, match_opcode, 0}, | |
1966 | {"vaesz.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS, MASK_VAESZ_VS, match_opcode, 0}, | |
1967 | ||
62edb233 CM |
1968 | /* Zvknh[a,b] instructions. */ |
1969 | {"vsha2ch.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV, match_opcode, 0}, | |
1970 | {"vsha2cl.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV, match_opcode, 0}, | |
1971 | {"vsha2ms.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV, match_opcode, 0}, | |
1972 | ||
5ec6edd0 CM |
1973 | /* Zvksed instructions. */ |
1974 | {"vsm4k.vi", 0, INSN_CLASS_ZVKSED, "Vd,Vt,Vj", MATCH_VSM4K_VI, MASK_VSM4K_VI, match_opcode, 0}, | |
1975 | {"vsm4r.vv", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VV, MASK_VSM4R_VV, match_opcode, 0}, | |
1976 | {"vsm4r.vs", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VS, MASK_VSM4R_VS, match_opcode, 0}, | |
1977 | ||
259a2647 CM |
1978 | /* Zvksh instructions. */ |
1979 | {"vsm3c.vi", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vj", MATCH_VSM3C_VI, MASK_VSM3C_VI, match_opcode, 0}, | |
1980 | {"vsm3me.vv", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3ME_VV, MASK_VSM3ME_VV, match_opcode, 0}, | |
1981 | ||
b5c37946 SJ |
1982 | /* ZCB instructions. */ |
1983 | {"c.lbu", 0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_LBU, MASK_C_LBU, match_opcode, INSN_DREF|INSN_1_BYTE }, | |
1984 | {"c.lhu", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LHU, MASK_C_LHU, match_opcode, INSN_DREF|INSN_2_BYTE }, | |
1985 | {"c.lh", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LH, MASK_C_LH, match_opcode, INSN_DREF|INSN_2_BYTE }, | |
1986 | {"c.sb", 0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_SB, MASK_C_SB, match_opcode, INSN_DREF|INSN_1_BYTE }, | |
1987 | {"c.sh", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_SH, MASK_C_SH, match_opcode, INSN_DREF|INSN_2_BYTE }, | |
1988 | {"c.not", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_NOT, MASK_C_NOT, match_opcode, 0 }, | |
1989 | {"c.mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, 0 }, | |
1990 | {"c.sext.b", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs", MATCH_C_SEXT_B, MASK_C_SEXT_B, match_opcode, 0 }, | |
1991 | {"c.sext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs", MATCH_C_SEXT_H, MASK_C_SEXT_H, match_opcode, 0 }, | |
1992 | {"c.zext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs", MATCH_C_ZEXT_H, MASK_C_ZEXT_H, match_opcode, 0 }, | |
1993 | {"c.zext.w", 64, INSN_CLASS_ZCB_AND_ZBA, "Cs", MATCH_C_ZEXT_W, MASK_C_ZEXT_W, match_opcode, 0 }, | |
1994 | {"c.zext.b", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 }, | |
1995 | {"c.sext.w", 64, INSN_CLASS_ZCB, "d", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, | |
1996 | ||
01292987 TO |
1997 | /* Supervisor instructions. */ |
1998 | {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, | |
f438659a | 1999 | {"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS }, |
01292987 TO |
2000 | {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS }, |
2001 | {"csrw", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS }, | |
f438659a | 2002 | {"csrsi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS }, |
01292987 TO |
2003 | {"csrs", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRS, MASK_CSRRS|MASK_RD, match_opcode, INSN_ALIAS }, |
2004 | {"csrs", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS }, | |
f438659a | 2005 | {"csrci", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS }, |
01292987 TO |
2006 | {"csrc", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRC, MASK_CSRRC|MASK_RD, match_opcode, INSN_ALIAS }, |
2007 | {"csrc", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS }, | |
f438659a | 2008 | {"csrrwi", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 }, |
01292987 TO |
2009 | {"csrrw", 0, INSN_CLASS_ZICSR, "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 }, |
2010 | {"csrrw", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS }, | |
f438659a | 2011 | {"csrrsi", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 }, |
01292987 TO |
2012 | {"csrrs", 0, INSN_CLASS_ZICSR, "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 }, |
2013 | {"csrrs", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS }, | |
f438659a | 2014 | {"csrrci", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 }, |
01292987 TO |
2015 | {"csrrc", 0, INSN_CLASS_ZICSR, "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 }, |
2016 | {"csrrc", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS }, | |
01292987 TO |
2017 | {"uret", 0, INSN_CLASS_I, "", MATCH_URET, MASK_URET, match_opcode, 0 }, |
2018 | {"sret", 0, INSN_CLASS_I, "", MATCH_SRET, MASK_SRET, match_opcode, 0 }, | |
2019 | {"hret", 0, INSN_CLASS_I, "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, | |
2020 | {"mret", 0, INSN_CLASS_I, "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, | |
2021 | {"dret", 0, INSN_CLASS_I, "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, | |
2022 | {"sfence.vm", 0, INSN_CLASS_I, "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, | |
2023 | {"sfence.vm", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, | |
2024 | {"sfence.vma", 0, INSN_CLASS_I, "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS }, | |
2025 | {"sfence.vma", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS2, match_opcode, INSN_ALIAS }, | |
2026 | {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, | |
2027 | {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, | |
2028 | ||
23ff54c2 NC |
2029 | /* Svinval instructions. */ |
2030 | {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 }, | |
2031 | {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 }, | |
2032 | {"sfence.inval.ir", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR, match_opcode, 0 }, | |
2033 | {"hinval.vvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 }, | |
2034 | {"hinval.gvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 }, | |
2035 | ||
a63375ac | 2036 | /* Hypervisor instructions. */ |
c625f4ed NC |
2037 | {"hfence.vvma", 0, INSN_CLASS_H, "", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS }, |
2038 | {"hfence.vvma", 0, INSN_CLASS_H, "s", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA|MASK_RS2, match_opcode, INSN_ALIAS }, | |
2039 | {"hfence.vvma", 0, INSN_CLASS_H, "s,t", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 }, | |
2040 | {"hfence.gvma", 0, INSN_CLASS_H, "", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS }, | |
2041 | {"hfence.gvma", 0, INSN_CLASS_H, "s", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, INSN_ALIAS }, | |
2042 | {"hfence.gvma", 0, INSN_CLASS_H, "s,t", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 }, | |
2043 | {"hlv.b", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLV_B, MASK_HLV_B, match_opcode, INSN_DREF|INSN_1_BYTE }, | |
2044 | {"hlv.bu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLV_BU, MASK_HLV_BU, match_opcode, INSN_DREF|INSN_1_BYTE }, | |
2045 | {"hlv.h", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLV_H, MASK_HLV_H, match_opcode, INSN_DREF|INSN_2_BYTE }, | |
2046 | {"hlv.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLV_HU, MASK_HLV_HU, match_opcode, INSN_DREF|INSN_2_BYTE }, | |
2047 | {"hlvx.hu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVX_HU, MASK_HLVX_HU, match_opcode, INSN_DREF|INSN_2_BYTE }, | |
2048 | {"hlv.w", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLV_W, MASK_HLV_W, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
2049 | {"hlv.wu", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLV_WU, MASK_HLV_WU, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
2050 | {"hlvx.wu", 0, INSN_CLASS_H, "d,0(s)", MATCH_HLVX_WU, MASK_HLVX_WU, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
2051 | {"hlv.d", 64, INSN_CLASS_H, "d,0(s)", MATCH_HLV_D, MASK_HLV_D, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
2052 | {"hsv.b", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_B, MASK_HSV_B, match_opcode, INSN_DREF|INSN_1_BYTE }, | |
2053 | {"hsv.h", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_H, MASK_HSV_H, match_opcode, INSN_DREF|INSN_2_BYTE }, | |
2054 | {"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE }, | |
2055 | {"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE }, | |
a63375ac | 2056 | |
ccb388ca MB |
2057 | /* Vendor-specific (CORE-V) Xcvmac instructions. */ |
2058 | {"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MAC, match_opcode, 0}, | |
2059 | {"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MSU, match_opcode, 0}, | |
2060 | {"cv.mulsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULSN, MASK_CV_MULSN, match_opcode, 0}, | |
2061 | {"cv.muls", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULSN, MASK_CV_MULSN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS}, | |
2062 | {"cv.mulsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULSRN, MASK_CV_MULSRN, match_opcode, 0}, | |
2063 | {"cv.mulhhsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHSN, MASK_CV_MULHHSN, match_opcode, 0}, | |
2064 | {"cv.mulhhs", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULHHSN, MASK_CV_MULHHSN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS}, | |
2065 | {"cv.mulhhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHSRN, MASK_CV_MULHHSRN, match_opcode, 0}, | |
2066 | {"cv.mulun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULUN, MASK_CV_MULUN, match_opcode, 0}, | |
2067 | {"cv.mulu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULUN, MASK_CV_MULUN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS}, | |
2068 | {"cv.mulurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULURN, MASK_CV_MULURN, match_opcode, 0}, | |
2069 | {"cv.mulhhun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHUN, MASK_CV_MULHHUN, match_opcode, 0}, | |
2070 | {"cv.mulhhu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MULHHUN, MASK_CV_MULHHUN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS}, | |
2071 | {"cv.mulhhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHURN, MASK_CV_MULHHURN, match_opcode, 0}, | |
2072 | {"cv.macsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACSN, MASK_CV_MACSN, match_opcode, 0}, | |
2073 | {"cv.machhsn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHSN, MASK_CV_MACHHSN, match_opcode, 0}, | |
2074 | {"cv.macsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACSRN, MASK_CV_MACSRN, match_opcode, 0}, | |
2075 | {"cv.machhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHSRN, MASK_CV_MACHHSRN, match_opcode, 0}, | |
2076 | {"cv.macun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACUN, MASK_CV_MACUN, match_opcode, 0}, | |
2077 | {"cv.machhun", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHUN, MASK_CV_MACHHUN, match_opcode, 0}, | |
2078 | {"cv.macurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACURN, MASK_CV_MACURN, match_opcode, 0}, | |
2079 | {"cv.machhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHURN, MASK_CV_MACHHURN, match_opcode, 0}, | |
2080 | ||
d1bd9787 MB |
2081 | /* Vendor-specific (CORE-V) Xcvalu instructions. */ |
2082 | {"cv.abs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_ABS, MASK_CV_ABS, match_opcode, 0}, | |
2083 | {"cv.exths", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHS, MASK_CV_EXTHS, match_opcode, 0}, | |
2084 | {"cv.exthz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHZ, MASK_CV_EXTHZ, match_opcode, 0}, | |
2085 | {"cv.extbs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBS, MASK_CV_EXTBS, match_opcode, 0}, | |
2086 | {"cv.extbz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBZ, MASK_CV_EXTBZ, match_opcode, 0}, | |
2087 | {"cv.sle", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLE, MASK_CV_SLE, match_opcode, 0}, | |
2088 | {"cv.slet", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLET, MASK_CV_SLET, match_opcode, INSN_ALIAS}, | |
2089 | {"cv.sleu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLEU, MASK_CV_SLEU, match_opcode, 0}, | |
2090 | {"cv.sletu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLETU, MASK_CV_SLETU, match_opcode, INSN_ALIAS}, | |
2091 | {"cv.min", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MIN, MASK_CV_MIN, match_opcode, 0}, | |
2092 | {"cv.minu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MINU, MASK_CV_MINU, match_opcode, 0}, | |
2093 | {"cv.max", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAX, MASK_CV_MAX, match_opcode, 0}, | |
2094 | {"cv.maxu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAXU, MASK_CV_MAXU, match_opcode, 0}, | |
2095 | {"cv.clip", 0, INSN_CLASS_XCVALU, "d,s,Xc2", MATCH_CV_CLIP, MASK_CV_CLIP, match_opcode, 0}, | |
2096 | {"cv.clipu", 0, INSN_CLASS_XCVALU, "d,s,Xc2", MATCH_CV_CLIPU, MASK_CV_CLIPU, match_opcode, 0}, | |
2097 | {"cv.clipr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPR, MASK_CV_CLIPR, match_opcode, 0}, | |
2098 | {"cv.clipur", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPUR, MASK_CV_CLIPUR, match_opcode, 0}, | |
2099 | {"cv.addn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDN, MASK_CV_ADDN, match_opcode, 0}, | |
2100 | {"cv.addun", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDUN, MASK_CV_ADDUN, match_opcode, 0}, | |
2101 | {"cv.addunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDUNR, MASK_CV_ADDUNR, match_opcode, 0}, | |
2102 | {"cv.addrn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDRN, MASK_CV_ADDRN, match_opcode, 0}, | |
2103 | {"cv.addurn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_ADDURN, MASK_CV_ADDURN, match_opcode, 0}, | |
2104 | {"cv.addnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDNR, MASK_CV_ADDNR, match_opcode, 0}, | |
2105 | {"cv.addrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDRNR, MASK_CV_ADDRNR, match_opcode, 0}, | |
2106 | {"cv.addurnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDURNR, MASK_CV_ADDURNR, match_opcode, 0}, | |
2107 | {"cv.subn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBN, MASK_CV_SUBN, match_opcode, 0}, | |
2108 | {"cv.subun", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBUN, MASK_CV_SUBUN, match_opcode, 0}, | |
2109 | {"cv.subrn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBRN, MASK_CV_SUBRN, match_opcode, 0}, | |
2110 | {"cv.suburn", 0, INSN_CLASS_XCVALU, "d,s,t,Xc3", MATCH_CV_SUBURN, MASK_CV_SUBURN, match_opcode, 0}, | |
2111 | {"cv.subnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBNR, MASK_CV_SUBNR, match_opcode, 0}, | |
2112 | {"cv.subunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBUNR, MASK_CV_SUBUNR, match_opcode, 0}, | |
2113 | {"cv.subrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBRNR, MASK_CV_SUBRNR, match_opcode, 0}, | |
2114 | {"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBURNR, MASK_CV_SUBURNR, match_opcode, 0}, | |
2115 | ||
8254c3d2 | 2116 | /* Vendor-specific (T-Head) XTheadBa instructions. */ |
6de11ff6 | 2117 | {"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xtu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0}, |
8254c3d2 CM |
2118 | |
2119 | /* Vendor-specific (T-Head) XTheadBb instructions. */ | |
6de11ff6 NC |
2120 | {"th.srri", 0, INSN_CLASS_XTHEADBB, "d,s,Xtu6@20", MATCH_TH_SRRI, MASK_TH_SRRI, match_opcode, 0}, |
2121 | {"th.srriw", 64, INSN_CLASS_XTHEADBB, "d,s,Xtu5@20", MATCH_TH_SRRIW, MASK_TH_SRRIW, match_opcode, 0}, | |
2122 | {"th.ext", 0, INSN_CLASS_XTHEADBB, "d,s,Xtu6@26,Xtu6@20", MATCH_TH_EXT, MASK_TH_EXT, match_opcode, 0}, | |
2123 | {"th.extu", 0, INSN_CLASS_XTHEADBB, "d,s,Xtu6@26,Xtu6@20", MATCH_TH_EXTU, MASK_TH_EXTU, match_opcode, 0}, | |
8254c3d2 CM |
2124 | {"th.ff0", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_FF0, MASK_TH_FF0, match_opcode, 0}, |
2125 | {"th.ff1", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_FF1, MASK_TH_FF1, match_opcode, 0}, | |
2126 | {"th.rev", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_REV, MASK_TH_REV, match_opcode, 0}, | |
2127 | {"th.revw", 64, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_REVW, MASK_TH_REVW, match_opcode, 0}, | |
2128 | {"th.tstnbz", 0, INSN_CLASS_XTHEADBB, "d,s", MATCH_TH_TSTNBZ, MASK_TH_TSTNBZ, match_opcode, 0}, | |
2129 | ||
2130 | /* Vendor-specific (T-Head) XTheadBs instructions. */ | |
6de11ff6 | 2131 | {"th.tst", 0, INSN_CLASS_XTHEADBS, "d,s,Xtu6@20", MATCH_TH_TST, MASK_TH_TST, match_opcode, 0}, |
8254c3d2 | 2132 | |
a9ba8bc2 CM |
2133 | /* Vendor-specific (T-Head) XTheadCmo instructions. */ |
2134 | {"th.dcache.call", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_CALL, MASK_TH_DCACHE_CALL, match_opcode, 0}, | |
2135 | {"th.dcache.ciall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_CIALL, MASK_TH_DCACHE_CIALL, match_opcode, 0}, | |
2136 | {"th.dcache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_DCACHE_IALL, MASK_TH_DCACHE_IALL, match_opcode, 0}, | |
2137 | {"th.dcache.cpa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CPA, MASK_TH_DCACHE_CPA, match_opcode, 0}, | |
2138 | {"th.dcache.cipa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CIPA, MASK_TH_DCACHE_CIPA, match_opcode, 0}, | |
2139 | {"th.dcache.ipa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_IPA, MASK_TH_DCACHE_IPA, match_opcode, 0}, | |
2140 | {"th.dcache.cva", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CVA, MASK_TH_DCACHE_CVA, match_opcode, 0}, | |
2141 | {"th.dcache.civa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CIVA, MASK_TH_DCACHE_CIVA, match_opcode, 0}, | |
2142 | {"th.dcache.iva", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_IVA, MASK_TH_DCACHE_IVA, match_opcode, 0}, | |
2143 | {"th.dcache.csw", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CSW, MASK_TH_DCACHE_CSW, match_opcode, 0}, | |
2144 | {"th.dcache.cisw", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CISW, MASK_TH_DCACHE_CISW, match_opcode, 0}, | |
2145 | {"th.dcache.isw", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_ISW, MASK_TH_DCACHE_ISW, match_opcode, 0}, | |
2146 | {"th.dcache.cpal1", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CPAL1, MASK_TH_DCACHE_CPAL1, match_opcode, 0}, | |
2147 | {"th.dcache.cval1", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_DCACHE_CVAL1, MASK_TH_DCACHE_CVAL1, match_opcode, 0}, | |
2148 | ||
2149 | {"th.icache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_ICACHE_IALL, MASK_TH_ICACHE_IALL, match_opcode, 0}, | |
2150 | {"th.icache.ialls", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_ICACHE_IALLS, MASK_TH_ICACHE_IALLS, match_opcode, 0}, | |
2151 | {"th.icache.ipa", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_ICACHE_IPA, MASK_TH_ICACHE_IPA, match_opcode, 0}, | |
2152 | {"th.icache.iva", 0, INSN_CLASS_XTHEADCMO, "s", MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA, match_opcode, 0}, | |
2153 | ||
2154 | {"th.l2cache.call", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL, match_opcode, 0}, | |
2155 | {"th.l2cache.ciall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL, match_opcode, 0}, | |
2156 | {"th.l2cache.iall", 0, INSN_CLASS_XTHEADCMO, "", MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL, match_opcode, 0}, | |
2157 | ||
73442230 CM |
2158 | /* Vendor-specific (T-Head) XTheadCondMov instructions. */ |
2159 | {"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVEQZ, MASK_TH_MVEQZ, match_opcode, 0}, | |
2160 | {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, | |
2161 | ||
f511f80f | 2162 | /* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ |
6de11ff6 NC |
2163 | {"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0}, |
2164 | {"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0}, | |
2165 | {"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0}, | |
2166 | {"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0}, | |
2167 | {"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0}, | |
2168 | {"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0}, | |
2169 | {"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, | |
2170 | {"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, | |
f511f80f | 2171 | |
4a3bc79b | 2172 | /* Vendor-specific (T-Head) XTheadFmv instructions. */ |
8cb16b68 | 2173 | {"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "D,s", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0}, |
4a3bc79b CM |
2174 | {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0}, |
2175 | ||
01804a09 CM |
2176 | /* Vendor-specific (T-Head) XTheadInt instructions. */ |
2177 | {"th.ipop", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPOP, MASK_TH_IPOP, match_opcode, 0}, | |
2178 | {"th.ipush", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPUSH, MASK_TH_IPUSH, match_opcode, 0}, | |
2179 | ||
27cfd142 | 2180 | /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ |
6de11ff6 NC |
2181 | {"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, |
2182 | {"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0}, | |
2183 | {"th.lwia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWIA, MASK_TH_LWIA, match_th_load_inc, 0}, | |
2184 | {"th.lwib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWIB, MASK_TH_LWIB, match_th_load_inc, 0}, | |
2185 | {"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWUIA, MASK_TH_LWUIA, match_th_load_inc, 0}, | |
2186 | {"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWUIB, MASK_TH_LWUIB, match_th_load_inc, 0}, | |
2187 | {"th.lhia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHIA, MASK_TH_LHIA, match_th_load_inc, 0}, | |
2188 | {"th.lhib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHIB, MASK_TH_LHIB, match_th_load_inc, 0}, | |
2189 | {"th.lhuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHUIA, MASK_TH_LHUIA, match_th_load_inc, 0}, | |
2190 | {"th.lhuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHUIB, MASK_TH_LHUIB, match_th_load_inc, 0}, | |
2191 | {"th.lbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBIA, MASK_TH_LBIA, match_th_load_inc, 0}, | |
2192 | {"th.lbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBIB, MASK_TH_LBIB, match_th_load_inc, 0}, | |
2193 | {"th.lbuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBUIA, MASK_TH_LBUIA, match_th_load_inc, 0}, | |
2194 | {"th.lbuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBUIB, MASK_TH_LBUIB, match_th_load_inc, 0}, | |
2195 | {"th.sdia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SDIA, MASK_TH_SDIA, match_opcode, 0}, | |
2196 | {"th.sdib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SDIB, MASK_TH_SDIB, match_opcode, 0}, | |
2197 | {"th.swia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SWIA, MASK_TH_SWIA, match_opcode, 0}, | |
2198 | {"th.swib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SWIB, MASK_TH_SWIB, match_opcode, 0}, | |
2199 | {"th.shia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SHIA, MASK_TH_SHIA, match_opcode, 0}, | |
2200 | {"th.shib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SHIB, MASK_TH_SHIB, match_opcode, 0}, | |
2201 | {"th.sbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SBIA, MASK_TH_SBIA, match_opcode, 0}, | |
2202 | {"th.sbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SBIB, MASK_TH_SBIB, match_opcode, 0}, | |
2203 | ||
2204 | {"th.lrd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRD, MASK_TH_LRD, match_opcode, 0}, | |
2205 | {"th.lrw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRW, MASK_TH_LRW, match_opcode, 0}, | |
2206 | {"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRWU, MASK_TH_LRWU, match_opcode, 0}, | |
2207 | {"th.lrh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRH, MASK_TH_LRH, match_opcode, 0}, | |
2208 | {"th.lrhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRHU, MASK_TH_LRHU, match_opcode, 0}, | |
2209 | {"th.lrb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRB, MASK_TH_LRB, match_opcode, 0}, | |
2210 | {"th.lrbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LRBU, MASK_TH_LRBU, match_opcode, 0}, | |
2211 | {"th.srd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRD, MASK_TH_SRD, match_opcode, 0}, | |
2212 | {"th.srw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRW, MASK_TH_SRW, match_opcode, 0}, | |
2213 | {"th.srh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRH, MASK_TH_SRH, match_opcode, 0}, | |
2214 | {"th.srb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SRB, MASK_TH_SRB, match_opcode, 0}, | |
2215 | ||
2216 | {"th.lurd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURD, MASK_TH_LURD, match_opcode, 0}, | |
2217 | {"th.lurw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURW, MASK_TH_LURW, match_opcode, 0}, | |
2218 | {"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURWU, MASK_TH_LURWU, match_opcode, 0}, | |
2219 | {"th.lurh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURH, MASK_TH_LURH, match_opcode, 0}, | |
2220 | {"th.lurhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURHU, MASK_TH_LURHU, match_opcode, 0}, | |
2221 | {"th.lurb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURB, MASK_TH_LURB, match_opcode, 0}, | |
2222 | {"th.lurbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_LURBU, MASK_TH_LURBU, match_opcode, 0}, | |
2223 | {"th.surd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURD, MASK_TH_SURD, match_opcode, 0}, | |
2224 | {"th.surw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURW, MASK_TH_SURW, match_opcode, 0}, | |
2225 | {"th.surh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURH, MASK_TH_SURH, match_opcode, 0}, | |
2226 | {"th.surb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xtu2@25", MATCH_TH_SURB, MASK_TH_SURB, match_opcode, 0}, | |
27cfd142 | 2227 | |
6e17ae62 | 2228 | /* Vendor-specific (T-Head) XTheadMemPair instructions. */ |
6de11ff6 NC |
2229 | {"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl4", MATCH_TH_LDD, MASK_TH_LDD, match_th_load_pair, 0}, |
2230 | {"th.lwd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_LWD, MASK_TH_LWD, match_th_load_pair, 0}, | |
2231 | {"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, 0}, | |
2232 | {"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl4", MATCH_TH_SDD, MASK_TH_SDD, match_opcode, 0}, | |
2233 | {"th.swd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_SWD, MASK_TH_SWD, match_opcode, 0}, | |
6e17ae62 | 2234 | |
4041e11d CM |
2235 | /* Vendor-specific (T-Head) XTheadMac instructions. */ |
2236 | {"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0}, | |
2237 | {"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0}, | |
2238 | {"th.mulaw", 64, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAW, MASK_TH_MULAW, match_opcode, 0}, | |
2239 | {"th.muls", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULS, MASK_TH_MULS, match_opcode, 0}, | |
2240 | {"th.mulsh", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULSH, MASK_TH_MULSH, match_opcode, 0}, | |
2241 | {"th.mulsw", 64, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULSW, MASK_TH_MULSW, match_opcode, 0}, | |
2242 | ||
547c18d9 CM |
2243 | /* Vendor-specific (T-Head) XTheadSync instructions. */ |
2244 | {"th.sfence.vmas", 0, INSN_CLASS_XTHEADSYNC, "s,t",MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS, match_opcode, 0}, | |
2245 | {"th.sync", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC, MASK_TH_SYNC, match_opcode, 0}, | |
2246 | {"th.sync.i", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_I, MASK_TH_SYNC_I, match_opcode, 0}, | |
2247 | {"th.sync.is", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS, match_opcode, 0}, | |
2248 | {"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, MASK_TH_SYNC_S, match_opcode, 0}, | |
2249 | ||
9aa5dde6 JM |
2250 | /* Vendor-specific (T-Head) XTheadVector instructions. */ |
2251 | {"th.vsetvl", 0, INSN_CLASS_XTHEADVECTOR, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0}, | |
6a95962e | 2252 | {"th.vsetvli", 0, INSN_CLASS_XTHEADVECTOR, "d,s,XtVc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0}, |
0bd0e652 JM |
2253 | {"th.vlb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLBV, MASK_TH_VLBV, match_opcode, INSN_DREF }, |
2254 | {"th.vlh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLHV, MASK_TH_VLHV, match_opcode, INSN_DREF }, | |
2255 | {"th.vlw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLWV, MASK_TH_VLWV, match_opcode, INSN_DREF }, | |
2256 | {"th.vlbu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF }, | |
2257 | {"th.vlhu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF }, | |
2258 | {"th.vlwu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF }, | |
2259 | {"th.vle.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF }, | |
2260 | {"th.vsb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF }, | |
2261 | {"th.vsh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF }, | |
2262 | {"th.vsw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF }, | |
2263 | {"th.vse.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF }, | |
2264 | {"th.vlsb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSBV, MASK_TH_VLSBV, match_opcode, INSN_DREF }, | |
2265 | {"th.vlsh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSHV, MASK_TH_VLSHV, match_opcode, INSN_DREF }, | |
2266 | {"th.vlsw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSWV, MASK_TH_VLSWV, match_opcode, INSN_DREF }, | |
2267 | {"th.vlsbu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF }, | |
2268 | {"th.vlshu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF }, | |
2269 | {"th.vlswu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF }, | |
2270 | {"th.vlse.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF }, | |
2271 | {"th.vssb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF }, | |
2272 | {"th.vssh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF }, | |
2273 | {"th.vssw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF }, | |
2274 | {"th.vsse.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF }, | |
2275 | {"th.vlxb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXBV, MASK_TH_VLXBV, match_opcode, INSN_DREF }, | |
2276 | {"th.vlxh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXHV, MASK_TH_VLXHV, match_opcode, INSN_DREF }, | |
2277 | {"th.vlxw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXWV, MASK_TH_VLXWV, match_opcode, INSN_DREF }, | |
2278 | {"th.vlxbu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_opcode, INSN_DREF }, | |
2279 | {"th.vlxhu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_opcode, INSN_DREF }, | |
2280 | {"th.vlxwu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_opcode, INSN_DREF }, | |
2281 | {"th.vlxe.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_opcode, INSN_DREF }, | |
2282 | {"th.vsxb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_opcode, INSN_DREF }, | |
2283 | {"th.vsxh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_opcode, INSN_DREF }, | |
2284 | {"th.vsxw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_opcode, INSN_DREF }, | |
2285 | {"th.vsxe.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_opcode, INSN_DREF }, | |
2286 | {"th.vsuxb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSUXBV, MASK_TH_VSUXBV, match_opcode, INSN_DREF }, | |
2287 | {"th.vsuxh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSUXHV, MASK_TH_VSUXHV, match_opcode, INSN_DREF }, | |
2288 | {"th.vsuxw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSUXWV, MASK_TH_VSUXWV, match_opcode, INSN_DREF }, | |
2289 | {"th.vsuxe.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSUXEV, MASK_TH_VSUXEV, match_opcode, INSN_DREF }, | |
2290 | {"th.vlbff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLBFFV, MASK_TH_VLBFFV, match_opcode, INSN_DREF }, | |
2291 | {"th.vlhff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLHFFV, MASK_TH_VLHFFV, match_opcode, INSN_DREF }, | |
2292 | {"th.vlwff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLWFFV, MASK_TH_VLWFFV, match_opcode, INSN_DREF }, | |
2293 | {"th.vlbuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF }, | |
2294 | {"th.vlhuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF }, | |
2295 | {"th.vlwuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF }, | |
2296 | {"th.vleff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF }, | |
763c4daa JM |
2297 | {"th.vlseg2b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG2BV, MASK_TH_VLSEG2BV, match_opcode, INSN_DREF }, |
2298 | {"th.vlseg2h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG2HV, MASK_TH_VLSEG2HV, match_opcode, INSN_DREF }, | |
2299 | {"th.vlseg2w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG2WV, MASK_TH_VLSEG2WV, match_opcode, INSN_DREF }, | |
2300 | {"th.vlseg2bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_opcode, INSN_DREF }, | |
2301 | {"th.vlseg2hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_opcode, INSN_DREF }, | |
2302 | {"th.vlseg2wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_opcode, INSN_DREF }, | |
2303 | {"th.vlseg2e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_opcode, INSN_DREF }, | |
2304 | {"th.vsseg2b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF }, | |
2305 | {"th.vsseg2h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_opcode, INSN_DREF }, | |
2306 | {"th.vsseg2w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_opcode, INSN_DREF }, | |
2307 | {"th.vsseg2e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF }, | |
2308 | {"th.vlseg3b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG3BV, MASK_TH_VLSEG3BV, match_opcode, INSN_DREF }, | |
2309 | {"th.vlseg3h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG3HV, MASK_TH_VLSEG3HV, match_opcode, INSN_DREF }, | |
2310 | {"th.vlseg3w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG3WV, MASK_TH_VLSEG3WV, match_opcode, INSN_DREF }, | |
2311 | {"th.vlseg3bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_opcode, INSN_DREF }, | |
2312 | {"th.vlseg3hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_opcode, INSN_DREF }, | |
2313 | {"th.vlseg3wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_opcode, INSN_DREF }, | |
2314 | {"th.vlseg3e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_opcode, INSN_DREF }, | |
2315 | {"th.vsseg3b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_opcode, INSN_DREF }, | |
2316 | {"th.vsseg3h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_opcode, INSN_DREF }, | |
2317 | {"th.vsseg3w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_opcode, INSN_DREF }, | |
2318 | {"th.vsseg3e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF }, | |
2319 | {"th.vlseg4b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG4BV, MASK_TH_VLSEG4BV, match_opcode, INSN_DREF }, | |
2320 | {"th.vlseg4h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG4HV, MASK_TH_VLSEG4HV, match_opcode, INSN_DREF }, | |
2321 | {"th.vlseg4w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG4WV, MASK_TH_VLSEG4WV, match_opcode, INSN_DREF }, | |
2322 | {"th.vlseg4bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_opcode, INSN_DREF }, | |
2323 | {"th.vlseg4hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_opcode, INSN_DREF }, | |
2324 | {"th.vlseg4wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_opcode, INSN_DREF }, | |
2325 | {"th.vlseg4e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_opcode, INSN_DREF }, | |
2326 | {"th.vsseg4b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_opcode, INSN_DREF }, | |
2327 | {"th.vsseg4h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_opcode, INSN_DREF }, | |
2328 | {"th.vsseg4w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_opcode, INSN_DREF }, | |
2329 | {"th.vsseg4e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF }, | |
2330 | {"th.vlseg5b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG5BV, MASK_TH_VLSEG5BV, match_opcode, INSN_DREF }, | |
2331 | {"th.vlseg5h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG5HV, MASK_TH_VLSEG5HV, match_opcode, INSN_DREF }, | |
2332 | {"th.vlseg5w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG5WV, MASK_TH_VLSEG5WV, match_opcode, INSN_DREF }, | |
2333 | {"th.vlseg5bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_opcode, INSN_DREF }, | |
2334 | {"th.vlseg5hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_opcode, INSN_DREF }, | |
2335 | {"th.vlseg5wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_opcode, INSN_DREF }, | |
2336 | {"th.vlseg5e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_opcode, INSN_DREF }, | |
2337 | {"th.vsseg5b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_opcode, INSN_DREF }, | |
2338 | {"th.vsseg5h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_opcode, INSN_DREF }, | |
2339 | {"th.vsseg5w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_opcode, INSN_DREF }, | |
2340 | {"th.vsseg5e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF }, | |
2341 | {"th.vlseg6b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG6BV, MASK_TH_VLSEG6BV, match_opcode, INSN_DREF }, | |
2342 | {"th.vlseg6h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG6HV, MASK_TH_VLSEG6HV, match_opcode, INSN_DREF }, | |
2343 | {"th.vlseg6w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG6WV, MASK_TH_VLSEG6WV, match_opcode, INSN_DREF }, | |
2344 | {"th.vlseg6bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_opcode, INSN_DREF }, | |
2345 | {"th.vlseg6hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_opcode, INSN_DREF }, | |
2346 | {"th.vlseg6wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_opcode, INSN_DREF }, | |
2347 | {"th.vlseg6e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_opcode, INSN_DREF }, | |
2348 | {"th.vsseg6b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_opcode, INSN_DREF }, | |
2349 | {"th.vsseg6h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_opcode, INSN_DREF }, | |
2350 | {"th.vsseg6w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_opcode, INSN_DREF }, | |
2351 | {"th.vsseg6e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF }, | |
2352 | {"th.vlseg7b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG7BV, MASK_TH_VLSEG7BV, match_opcode, INSN_DREF }, | |
2353 | {"th.vlseg7h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG7HV, MASK_TH_VLSEG7HV, match_opcode, INSN_DREF }, | |
2354 | {"th.vlseg7w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG7WV, MASK_TH_VLSEG7WV, match_opcode, INSN_DREF }, | |
2355 | {"th.vlseg7bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_opcode, INSN_DREF }, | |
2356 | {"th.vlseg7hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_opcode, INSN_DREF }, | |
2357 | {"th.vlseg7wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_opcode, INSN_DREF }, | |
2358 | {"th.vlseg7e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_opcode, INSN_DREF }, | |
2359 | {"th.vsseg7b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_opcode, INSN_DREF }, | |
2360 | {"th.vsseg7h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_opcode, INSN_DREF }, | |
2361 | {"th.vsseg7w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_opcode, INSN_DREF }, | |
2362 | {"th.vsseg7e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF }, | |
2363 | {"th.vlseg8b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG8BV, MASK_TH_VLSEG8BV, match_opcode, INSN_DREF }, | |
2364 | {"th.vlseg8h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG8HV, MASK_TH_VLSEG8HV, match_opcode, INSN_DREF }, | |
2365 | {"th.vlseg8w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG8WV, MASK_TH_VLSEG8WV, match_opcode, INSN_DREF }, | |
2366 | {"th.vlseg8bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_opcode, INSN_DREF }, | |
2367 | {"th.vlseg8hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_opcode, INSN_DREF }, | |
2368 | {"th.vlseg8wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_opcode, INSN_DREF }, | |
2369 | {"th.vlseg8e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_opcode, INSN_DREF }, | |
2370 | {"th.vsseg8b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_opcode, INSN_DREF }, | |
2371 | {"th.vsseg8h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_opcode, INSN_DREF }, | |
2372 | {"th.vsseg8w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF }, | |
2373 | {"th.vsseg8e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF }, | |
2374 | {"th.vlsseg2b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG2BV, MASK_TH_VLSSEG2BV, match_opcode, INSN_DREF }, | |
2375 | {"th.vlsseg2h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG2HV, MASK_TH_VLSSEG2HV, match_opcode, INSN_DREF }, | |
2376 | {"th.vlsseg2w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG2WV, MASK_TH_VLSSEG2WV, match_opcode, INSN_DREF }, | |
2377 | {"th.vlsseg2bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_opcode, INSN_DREF }, | |
2378 | {"th.vlsseg2hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_opcode, INSN_DREF }, | |
2379 | {"th.vlsseg2wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_opcode, INSN_DREF }, | |
2380 | {"th.vlsseg2e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_opcode, INSN_DREF }, | |
2381 | {"th.vssseg2b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF }, | |
2382 | {"th.vssseg2h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF }, | |
2383 | {"th.vssseg2w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF }, | |
2384 | {"th.vssseg2e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF }, | |
2385 | {"th.vlsseg3b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG3BV, MASK_TH_VLSSEG3BV, match_opcode, INSN_DREF }, | |
2386 | {"th.vlsseg3h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG3HV, MASK_TH_VLSSEG3HV, match_opcode, INSN_DREF }, | |
2387 | {"th.vlsseg3w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG3WV, MASK_TH_VLSSEG3WV, match_opcode, INSN_DREF }, | |
2388 | {"th.vlsseg3bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_opcode, INSN_DREF }, | |
2389 | {"th.vlsseg3hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_opcode, INSN_DREF }, | |
2390 | {"th.vlsseg3wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_opcode, INSN_DREF }, | |
2391 | {"th.vlsseg3e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_opcode, INSN_DREF }, | |
2392 | {"th.vssseg3b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_opcode, INSN_DREF }, | |
2393 | {"th.vssseg3h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_opcode, INSN_DREF }, | |
2394 | {"th.vssseg3w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_opcode, INSN_DREF }, | |
2395 | {"th.vssseg3e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF }, | |
2396 | {"th.vlsseg4b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG4BV, MASK_TH_VLSSEG4BV, match_opcode, INSN_DREF }, | |
2397 | {"th.vlsseg4h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG4HV, MASK_TH_VLSSEG4HV, match_opcode, INSN_DREF }, | |
2398 | {"th.vlsseg4w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG4WV, MASK_TH_VLSSEG4WV, match_opcode, INSN_DREF }, | |
2399 | {"th.vlsseg4bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_opcode, INSN_DREF }, | |
2400 | {"th.vlsseg4hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_opcode, INSN_DREF }, | |
2401 | {"th.vlsseg4wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_opcode, INSN_DREF }, | |
2402 | {"th.vlsseg4e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_opcode, INSN_DREF }, | |
2403 | {"th.vssseg4b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_opcode, INSN_DREF }, | |
2404 | {"th.vssseg4h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_opcode, INSN_DREF }, | |
2405 | {"th.vssseg4w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_opcode, INSN_DREF }, | |
2406 | {"th.vssseg4e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF }, | |
2407 | {"th.vlsseg5b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG5BV, MASK_TH_VLSSEG5BV, match_opcode, INSN_DREF }, | |
2408 | {"th.vlsseg5h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG5HV, MASK_TH_VLSSEG5HV, match_opcode, INSN_DREF }, | |
2409 | {"th.vlsseg5w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG5WV, MASK_TH_VLSSEG5WV, match_opcode, INSN_DREF }, | |
2410 | {"th.vlsseg5bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_opcode, INSN_DREF }, | |
2411 | {"th.vlsseg5hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_opcode, INSN_DREF }, | |
2412 | {"th.vlsseg5wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_opcode, INSN_DREF }, | |
2413 | {"th.vlsseg5e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_opcode, INSN_DREF }, | |
2414 | {"th.vssseg5b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_opcode, INSN_DREF }, | |
2415 | {"th.vssseg5h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_opcode, INSN_DREF }, | |
2416 | {"th.vssseg5w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_opcode, INSN_DREF }, | |
2417 | {"th.vssseg5e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF }, | |
2418 | {"th.vlsseg6b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG6BV, MASK_TH_VLSSEG6BV, match_opcode, INSN_DREF }, | |
2419 | {"th.vlsseg6h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG6HV, MASK_TH_VLSSEG6HV, match_opcode, INSN_DREF }, | |
2420 | {"th.vlsseg6w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG6WV, MASK_TH_VLSSEG6WV, match_opcode, INSN_DREF }, | |
2421 | {"th.vlsseg6bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_opcode, INSN_DREF }, | |
2422 | {"th.vlsseg6hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_opcode, INSN_DREF }, | |
2423 | {"th.vlsseg6wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_opcode, INSN_DREF }, | |
2424 | {"th.vlsseg6e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_opcode, INSN_DREF }, | |
2425 | {"th.vssseg6b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_opcode, INSN_DREF }, | |
2426 | {"th.vssseg6h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_opcode, INSN_DREF }, | |
2427 | {"th.vssseg6w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_opcode, INSN_DREF }, | |
2428 | {"th.vssseg6e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF }, | |
2429 | {"th.vlsseg7b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG7BV, MASK_TH_VLSSEG7BV, match_opcode, INSN_DREF }, | |
2430 | {"th.vlsseg7h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG7HV, MASK_TH_VLSSEG7HV, match_opcode, INSN_DREF }, | |
2431 | {"th.vlsseg7w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG7WV, MASK_TH_VLSSEG7WV, match_opcode, INSN_DREF }, | |
2432 | {"th.vlsseg7bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_opcode, INSN_DREF }, | |
2433 | {"th.vlsseg7hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_opcode, INSN_DREF }, | |
2434 | {"th.vlsseg7wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_opcode, INSN_DREF }, | |
2435 | {"th.vlsseg7e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_opcode, INSN_DREF }, | |
2436 | {"th.vssseg7b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_opcode, INSN_DREF }, | |
2437 | {"th.vssseg7h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_opcode, INSN_DREF }, | |
2438 | {"th.vssseg7w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_opcode, INSN_DREF }, | |
2439 | {"th.vssseg7e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF }, | |
2440 | {"th.vlsseg8b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG8BV, MASK_TH_VLSSEG8BV, match_opcode, INSN_DREF }, | |
2441 | {"th.vlsseg8h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG8HV, MASK_TH_VLSSEG8HV, match_opcode, INSN_DREF }, | |
2442 | {"th.vlsseg8w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSSEG8WV, MASK_TH_VLSSEG8WV, match_opcode, INSN_DREF }, | |
2443 | {"th.vlsseg8bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_opcode, INSN_DREF }, | |
2444 | {"th.vlsseg8hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_opcode, INSN_DREF }, | |
2445 | {"th.vlsseg8wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_opcode, INSN_DREF }, | |
2446 | {"th.vlsseg8e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_opcode, INSN_DREF }, | |
2447 | {"th.vssseg8b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_opcode, INSN_DREF }, | |
2448 | {"th.vssseg8h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_opcode, INSN_DREF }, | |
2449 | {"th.vssseg8w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF }, | |
2450 | {"th.vssseg8e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF }, | |
2451 | {"th.vlxseg2b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG2BV, MASK_TH_VLXSEG2BV, match_opcode, INSN_DREF }, | |
2452 | {"th.vlxseg2h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG2HV, MASK_TH_VLXSEG2HV, match_opcode, INSN_DREF }, | |
2453 | {"th.vlxseg2w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG2WV, MASK_TH_VLXSEG2WV, match_opcode, INSN_DREF }, | |
2454 | {"th.vlxseg2bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_opcode, INSN_DREF }, | |
2455 | {"th.vlxseg2hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_opcode, INSN_DREF }, | |
2456 | {"th.vlxseg2wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_opcode, INSN_DREF }, | |
2457 | {"th.vlxseg2e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_opcode, INSN_DREF }, | |
2458 | {"th.vsxseg2b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_opcode, INSN_DREF }, | |
2459 | {"th.vsxseg2h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_opcode, INSN_DREF }, | |
2460 | {"th.vsxseg2w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_opcode, INSN_DREF }, | |
2461 | {"th.vsxseg2e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_opcode, INSN_DREF }, | |
2462 | {"th.vlxseg3b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG3BV, MASK_TH_VLXSEG3BV, match_opcode, INSN_DREF }, | |
2463 | {"th.vlxseg3h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG3HV, MASK_TH_VLXSEG3HV, match_opcode, INSN_DREF }, | |
2464 | {"th.vlxseg3w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG3WV, MASK_TH_VLXSEG3WV, match_opcode, INSN_DREF }, | |
2465 | {"th.vlxseg3bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_opcode, INSN_DREF }, | |
2466 | {"th.vlxseg3hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_opcode, INSN_DREF }, | |
2467 | {"th.vlxseg3wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_opcode, INSN_DREF }, | |
2468 | {"th.vlxseg3e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_opcode, INSN_DREF }, | |
2469 | {"th.vsxseg3b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_opcode, INSN_DREF }, | |
2470 | {"th.vsxseg3h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_opcode, INSN_DREF }, | |
2471 | {"th.vsxseg3w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_opcode, INSN_DREF }, | |
2472 | {"th.vsxseg3e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_opcode, INSN_DREF }, | |
2473 | {"th.vlxseg4b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG4BV, MASK_TH_VLXSEG4BV, match_opcode, INSN_DREF }, | |
2474 | {"th.vlxseg4h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG4HV, MASK_TH_VLXSEG4HV, match_opcode, INSN_DREF }, | |
2475 | {"th.vlxseg4w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG4WV, MASK_TH_VLXSEG4WV, match_opcode, INSN_DREF }, | |
2476 | {"th.vlxseg4bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_opcode, INSN_DREF }, | |
2477 | {"th.vlxseg4hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_opcode, INSN_DREF }, | |
2478 | {"th.vlxseg4wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_opcode, INSN_DREF }, | |
2479 | {"th.vlxseg4e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_opcode, INSN_DREF }, | |
2480 | {"th.vsxseg4b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_opcode, INSN_DREF }, | |
2481 | {"th.vsxseg4h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_opcode, INSN_DREF }, | |
2482 | {"th.vsxseg4w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_opcode, INSN_DREF }, | |
2483 | {"th.vsxseg4e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_opcode, INSN_DREF }, | |
2484 | {"th.vlxseg5b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG5BV, MASK_TH_VLXSEG5BV, match_opcode, INSN_DREF }, | |
2485 | {"th.vlxseg5h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG5HV, MASK_TH_VLXSEG5HV, match_opcode, INSN_DREF }, | |
2486 | {"th.vlxseg5w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG5WV, MASK_TH_VLXSEG5WV, match_opcode, INSN_DREF }, | |
2487 | {"th.vlxseg5bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_opcode, INSN_DREF }, | |
2488 | {"th.vlxseg5hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_opcode, INSN_DREF }, | |
2489 | {"th.vlxseg5wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_opcode, INSN_DREF }, | |
2490 | {"th.vlxseg5e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_opcode, INSN_DREF }, | |
2491 | {"th.vsxseg5b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_opcode, INSN_DREF }, | |
2492 | {"th.vsxseg5h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_opcode, INSN_DREF }, | |
2493 | {"th.vsxseg5w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_opcode, INSN_DREF }, | |
2494 | {"th.vsxseg5e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_opcode, INSN_DREF }, | |
2495 | {"th.vlxseg6b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG6BV, MASK_TH_VLXSEG6BV, match_opcode, INSN_DREF }, | |
2496 | {"th.vlxseg6h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG6HV, MASK_TH_VLXSEG6HV, match_opcode, INSN_DREF }, | |
2497 | {"th.vlxseg6w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG6WV, MASK_TH_VLXSEG6WV, match_opcode, INSN_DREF }, | |
2498 | {"th.vlxseg6bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_opcode, INSN_DREF }, | |
2499 | {"th.vlxseg6hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_opcode, INSN_DREF }, | |
2500 | {"th.vlxseg6wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_opcode, INSN_DREF }, | |
2501 | {"th.vlxseg6e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_opcode, INSN_DREF }, | |
2502 | {"th.vsxseg6b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_opcode, INSN_DREF }, | |
2503 | {"th.vsxseg6h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_opcode, INSN_DREF }, | |
2504 | {"th.vsxseg6w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_opcode, INSN_DREF }, | |
2505 | {"th.vsxseg6e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_opcode, INSN_DREF }, | |
2506 | {"th.vlxseg7b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG7BV, MASK_TH_VLXSEG7BV, match_opcode, INSN_DREF }, | |
2507 | {"th.vlxseg7h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG7HV, MASK_TH_VLXSEG7HV, match_opcode, INSN_DREF }, | |
2508 | {"th.vlxseg7w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG7WV, MASK_TH_VLXSEG7WV, match_opcode, INSN_DREF }, | |
2509 | {"th.vlxseg7bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_opcode, INSN_DREF }, | |
2510 | {"th.vlxseg7hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_opcode, INSN_DREF }, | |
2511 | {"th.vlxseg7wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_opcode, INSN_DREF }, | |
2512 | {"th.vlxseg7e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_opcode, INSN_DREF }, | |
2513 | {"th.vsxseg7b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_opcode, INSN_DREF }, | |
2514 | {"th.vsxseg7h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_opcode, INSN_DREF }, | |
2515 | {"th.vsxseg7w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_opcode, INSN_DREF }, | |
2516 | {"th.vsxseg7e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_opcode, INSN_DREF }, | |
2517 | {"th.vlxseg8b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG8BV, MASK_TH_VLXSEG8BV, match_opcode, INSN_DREF }, | |
2518 | {"th.vlxseg8h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG8HV, MASK_TH_VLXSEG8HV, match_opcode, INSN_DREF }, | |
2519 | {"th.vlxseg8w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXSEG8WV, MASK_TH_VLXSEG8WV, match_opcode, INSN_DREF }, | |
2520 | {"th.vlxseg8bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_opcode, INSN_DREF }, | |
2521 | {"th.vlxseg8hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_opcode, INSN_DREF }, | |
2522 | {"th.vlxseg8wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_opcode, INSN_DREF }, | |
2523 | {"th.vlxseg8e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_opcode, INSN_DREF }, | |
2524 | {"th.vsxseg8b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_opcode, INSN_DREF }, | |
2525 | {"th.vsxseg8h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_opcode, INSN_DREF }, | |
2526 | {"th.vsxseg8w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_opcode, INSN_DREF }, | |
2527 | {"th.vsxseg8e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_opcode, INSN_DREF }, | |
2528 | {"th.vlseg2bff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG2BFFV, MASK_TH_VLSEG2BFFV, match_opcode, INSN_DREF }, | |
2529 | {"th.vlseg2hff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG2HFFV, MASK_TH_VLSEG2HFFV, match_opcode, INSN_DREF }, | |
2530 | {"th.vlseg2wff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG2WFFV, MASK_TH_VLSEG2WFFV, match_opcode, INSN_DREF }, | |
2531 | {"th.vlseg2buff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_opcode, INSN_DREF }, | |
2532 | {"th.vlseg2huff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_opcode, INSN_DREF }, | |
2533 | {"th.vlseg2wuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_opcode, INSN_DREF }, | |
2534 | {"th.vlseg2eff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_opcode, INSN_DREF }, | |
2535 | {"th.vlseg3bff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG3BFFV, MASK_TH_VLSEG3BFFV, match_opcode, INSN_DREF }, | |
2536 | {"th.vlseg3hff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG3HFFV, MASK_TH_VLSEG3HFFV, match_opcode, INSN_DREF }, | |
2537 | {"th.vlseg3wff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG3WFFV, MASK_TH_VLSEG3WFFV, match_opcode, INSN_DREF }, | |
2538 | {"th.vlseg3buff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_opcode, INSN_DREF }, | |
2539 | {"th.vlseg3huff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_opcode, INSN_DREF }, | |
2540 | {"th.vlseg3wuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_opcode, INSN_DREF }, | |
2541 | {"th.vlseg3eff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_opcode, INSN_DREF }, | |
2542 | {"th.vlseg4bff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG4BFFV, MASK_TH_VLSEG4BFFV, match_opcode, INSN_DREF }, | |
2543 | {"th.vlseg4hff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG4HFFV, MASK_TH_VLSEG4HFFV, match_opcode, INSN_DREF }, | |
2544 | {"th.vlseg4wff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG4WFFV, MASK_TH_VLSEG4WFFV, match_opcode, INSN_DREF }, | |
2545 | {"th.vlseg4buff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_opcode, INSN_DREF }, | |
2546 | {"th.vlseg4huff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_opcode, INSN_DREF }, | |
2547 | {"th.vlseg4wuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_opcode, INSN_DREF }, | |
2548 | {"th.vlseg4eff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_opcode, INSN_DREF }, | |
2549 | {"th.vlseg5bff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG5BFFV, MASK_TH_VLSEG5BFFV, match_opcode, INSN_DREF }, | |
2550 | {"th.vlseg5hff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG5HFFV, MASK_TH_VLSEG5HFFV, match_opcode, INSN_DREF }, | |
2551 | {"th.vlseg5wff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG5WFFV, MASK_TH_VLSEG5WFFV, match_opcode, INSN_DREF }, | |
2552 | {"th.vlseg5buff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_opcode, INSN_DREF }, | |
2553 | {"th.vlseg5huff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_opcode, INSN_DREF }, | |
2554 | {"th.vlseg5wuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_opcode, INSN_DREF }, | |
2555 | {"th.vlseg5eff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_opcode, INSN_DREF }, | |
2556 | {"th.vlseg6bff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG6BFFV, MASK_TH_VLSEG6BFFV, match_opcode, INSN_DREF }, | |
2557 | {"th.vlseg6hff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG6HFFV, MASK_TH_VLSEG6HFFV, match_opcode, INSN_DREF }, | |
2558 | {"th.vlseg6wff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG6WFFV, MASK_TH_VLSEG6WFFV, match_opcode, INSN_DREF }, | |
2559 | {"th.vlseg6buff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_opcode, INSN_DREF }, | |
2560 | {"th.vlseg6huff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_opcode, INSN_DREF }, | |
2561 | {"th.vlseg6wuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_opcode, INSN_DREF }, | |
2562 | {"th.vlseg6eff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_opcode, INSN_DREF }, | |
2563 | {"th.vlseg7bff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG7BFFV, MASK_TH_VLSEG7BFFV, match_opcode, INSN_DREF }, | |
2564 | {"th.vlseg7hff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG7HFFV, MASK_TH_VLSEG7HFFV, match_opcode, INSN_DREF }, | |
2565 | {"th.vlseg7wff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG7WFFV, MASK_TH_VLSEG7WFFV, match_opcode, INSN_DREF }, | |
2566 | {"th.vlseg7buff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_opcode, INSN_DREF }, | |
2567 | {"th.vlseg7huff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_opcode, INSN_DREF }, | |
2568 | {"th.vlseg7wuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_opcode, INSN_DREF }, | |
2569 | {"th.vlseg7eff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_opcode, INSN_DREF }, | |
2570 | {"th.vlseg8bff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG8BFFV, MASK_TH_VLSEG8BFFV, match_opcode, INSN_DREF }, | |
2571 | {"th.vlseg8hff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG8HFFV, MASK_TH_VLSEG8HFFV, match_opcode, INSN_DREF }, | |
2572 | {"th.vlseg8wff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG8WFFV, MASK_TH_VLSEG8WFFV, match_opcode, INSN_DREF }, | |
2573 | {"th.vlseg8buff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_opcode, INSN_DREF }, | |
2574 | {"th.vlseg8huff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_opcode, INSN_DREF }, | |
2575 | {"th.vlseg8wuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_opcode, INSN_DREF }, | |
2576 | {"th.vlseg8eff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_opcode, INSN_DREF }, | |
4d8f1ff3 JM |
2577 | {"th.vamoaddw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOADDWV, MASK_TH_VAMOADDWV, match_opcode, INSN_DREF}, |
2578 | {"th.vamoaddd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOADDDV, MASK_TH_VAMOADDDV, match_opcode, INSN_DREF}, | |
2579 | {"th.vamoswapw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOSWAPWV, MASK_TH_VAMOSWAPWV, match_opcode, INSN_DREF}, | |
2580 | {"th.vamoswapd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOSWAPDV, MASK_TH_VAMOSWAPDV, match_opcode, INSN_DREF}, | |
2581 | {"th.vamoxorw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOXORWV, MASK_TH_VAMOXORWV, match_opcode, INSN_DREF}, | |
2582 | {"th.vamoxord.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOXORDV, MASK_TH_VAMOXORDV, match_opcode, INSN_DREF}, | |
2583 | {"th.vamoandw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOANDWV, MASK_TH_VAMOANDWV, match_opcode, INSN_DREF}, | |
2584 | {"th.vamoandd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOANDDV, MASK_TH_VAMOANDDV, match_opcode, INSN_DREF}, | |
2585 | {"th.vamoorw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOORWV, MASK_TH_VAMOORWV, match_opcode, INSN_DREF}, | |
2586 | {"th.vamoord.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOORDV, MASK_TH_VAMOORDV, match_opcode, INSN_DREF}, | |
2587 | {"th.vamominw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINWV, MASK_TH_VAMOMINWV, match_opcode, INSN_DREF}, | |
2588 | {"th.vamomind.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINDV, MASK_TH_VAMOMINDV, match_opcode, INSN_DREF}, | |
2589 | {"th.vamomaxw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXWV, MASK_TH_VAMOMAXWV, match_opcode, INSN_DREF}, | |
2590 | {"th.vamomaxd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXDV, MASK_TH_VAMOMAXDV, match_opcode, INSN_DREF}, | |
2591 | {"th.vamominuw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUWV, MASK_TH_VAMOMINUWV, match_opcode, INSN_DREF}, | |
2592 | {"th.vamominud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUDV, MASK_TH_VAMOMINUDV, match_opcode, INSN_DREF}, | |
2593 | {"th.vamomaxuw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUWV, MASK_TH_VAMOMAXUWV, match_opcode, INSN_DREF}, | |
2594 | {"th.vamomaxud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUDV, MASK_TH_VAMOMAXUDV, match_opcode, INSN_DREF}, | |
77d242a0 | 2595 | {"th.vneg.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_opcode, INSN_ALIAS }, |
c63af675 JM |
2596 | {"th.vadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 }, |
2597 | {"th.vadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 }, | |
2598 | {"th.vadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 }, | |
2599 | {"th.vsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 }, | |
2600 | {"th.vsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 }, | |
2601 | {"th.vrsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 }, | |
2602 | {"th.vrsub.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 }, | |
2603 | {"th.vwcvt.x.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_opcode, INSN_ALIAS }, | |
2604 | {"th.vwcvtu.x.x.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_opcode, INSN_ALIAS }, | |
2605 | {"th.vwaddu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_opcode, 0 }, | |
2606 | {"th.vwaddu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_opcode, 0 }, | |
2607 | {"th.vwsubu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_opcode, 0 }, | |
2608 | {"th.vwsubu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_opcode, 0 }, | |
2609 | {"th.vwadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_opcode, 0 }, | |
2610 | {"th.vwadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_opcode, 0 }, | |
2611 | {"th.vwsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_opcode, 0 }, | |
2612 | {"th.vwsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_opcode, 0 }, | |
2613 | {"th.vwaddu.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_opcode, 0 }, | |
2614 | {"th.vwaddu.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_opcode, 0 }, | |
2615 | {"th.vwsubu.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_opcode, 0 }, | |
2616 | {"th.vwsubu.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_opcode, 0 }, | |
2617 | {"th.vwadd.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_opcode, 0 }, | |
2618 | {"th.vwadd.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_opcode, 0 }, | |
2619 | {"th.vwsub.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_opcode, 0 }, | |
2620 | {"th.vwsub.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_opcode, 0 }, | |
2621 | {"th.vadc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VADCVVM, MASK_TH_VADCVVM, match_opcode, 0 }, | |
2622 | {"th.vadc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VADCVXM, MASK_TH_VADCVXM, match_opcode, 0 }, | |
2623 | {"th.vadc.vim", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vi,V0", MATCH_TH_VADCVIM, MASK_TH_VADCVIM, match_opcode, 0 }, | |
2624 | {"th.vmadc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 }, | |
2625 | {"th.vmadc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 }, | |
2626 | {"th.vmadc.vim", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vi,V0", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 }, | |
2627 | {"th.vsbc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VSBCVVM, MASK_TH_VSBCVVM, match_opcode, 0 }, | |
2628 | {"th.vsbc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VSBCVXM, MASK_TH_VSBCVXM, match_opcode, 0 }, | |
2629 | {"th.vmsbc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 }, | |
2630 | {"th.vmsbc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 }, | |
2631 | {"th.vnot.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS }, | |
2632 | {"th.vand.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 }, | |
2633 | {"th.vand.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 }, | |
2634 | {"th.vand.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 }, | |
2635 | {"th.vor.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 }, | |
2636 | {"th.vor.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 }, | |
2637 | {"th.vor.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 }, | |
2638 | {"th.vxor.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 }, | |
2639 | {"th.vxor.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 }, | |
2640 | {"th.vxor.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 }, | |
2641 | {"th.vsll.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 }, | |
2642 | {"th.vsll.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 }, | |
2643 | {"th.vsll.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 }, | |
2644 | {"th.vsrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 }, | |
2645 | {"th.vsrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 }, | |
2646 | {"th.vsrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 }, | |
2647 | {"th.vsra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 }, | |
2648 | {"th.vsra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 }, | |
2649 | {"th.vsra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 }, | |
77d242a0 | 2650 | {"th.vncvt.x.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_opcode, INSN_ALIAS }, |
c63af675 JM |
2651 | {"th.vnsrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_opcode, 0 }, |
2652 | {"th.vnsrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_opcode, 0 }, | |
2653 | {"th.vnsrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_opcode, 0 }, | |
2654 | {"th.vnsra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_opcode, 0 }, | |
2655 | {"th.vnsra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_opcode, 0 }, | |
2656 | {"th.vnsra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_opcode, 0 }, | |
2657 | {"th.vmseq.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 }, | |
2658 | {"th.vmseq.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 }, | |
2659 | {"th.vmseq.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 }, | |
2660 | {"th.vmsne.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 }, | |
2661 | {"th.vmsne.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 }, | |
2662 | {"th.vmsne.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 }, | |
2663 | {"th.vmsltu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 }, | |
2664 | {"th.vmsltu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 }, | |
2665 | {"th.vmslt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 }, | |
2666 | {"th.vmslt.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 }, | |
2667 | {"th.vmsleu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 }, | |
2668 | {"th.vmsleu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 }, | |
2669 | {"th.vmsleu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 }, | |
2670 | {"th.vmsle.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 }, | |
2671 | {"th.vmsle.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 }, | |
2672 | {"th.vmsle.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 }, | |
2673 | {"th.vmsgtu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 }, | |
2674 | {"th.vmsgtu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 }, | |
2675 | {"th.vmsgt.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 }, | |
2676 | {"th.vmsgt.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 }, | |
2677 | {"th.vmsgt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS }, | |
2678 | {"th.vmsgtu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS }, | |
2679 | {"th.vmsge.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS }, | |
2680 | {"th.vmsgeu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS }, | |
2681 | {"th.vmslt.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS }, | |
2682 | {"th.vmsltu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS }, | |
2683 | {"th.vmsge.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS }, | |
2684 | {"th.vmsgeu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS }, | |
2ec31e54 JB |
2685 | {"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 0, (int) M_VMSGE, NULL, INSN_MACRO }, |
2686 | {"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, NULL, INSN_MACRO }, | |
2687 | {"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 1, (int) M_VMSGE, NULL, INSN_MACRO }, | |
2688 | {"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, NULL, INSN_MACRO }, | |
c63af675 JM |
2689 | {"th.vminu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0}, |
2690 | {"th.vminu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0}, | |
2691 | {"th.vmin.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0}, | |
2692 | {"th.vmin.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0}, | |
2693 | {"th.vmaxu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0}, | |
2694 | {"th.vmaxu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0}, | |
2695 | {"th.vmax.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0}, | |
2696 | {"th.vmax.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0}, | |
2697 | {"th.vmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 }, | |
2698 | {"th.vmul.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 }, | |
2699 | {"th.vmulh.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 }, | |
2700 | {"th.vmulh.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 }, | |
2701 | {"th.vmulhu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 }, | |
2702 | {"th.vmulhu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 }, | |
2703 | {"th.vmulhsu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 }, | |
2704 | {"th.vmulhsu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 }, | |
2705 | {"th.vwmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_opcode, 0 }, | |
2706 | {"th.vwmul.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_opcode, 0 }, | |
2707 | {"th.vwmulu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_opcode, 0 }, | |
2708 | {"th.vwmulu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_opcode, 0 }, | |
2709 | {"th.vwmulsu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_opcode, 0 }, | |
2710 | {"th.vwmulsu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_opcode, 0 }, | |
2711 | {"th.vmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0}, | |
2712 | {"th.vmacc.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0}, | |
2713 | {"th.vnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0}, | |
2714 | {"th.vnmsac.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0}, | |
2715 | {"th.vmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0}, | |
2716 | {"th.vmadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0}, | |
2717 | {"th.vnmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0}, | |
2718 | {"th.vnmsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0}, | |
2719 | {"th.vwmaccu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_opcode, 0}, | |
2720 | {"th.vwmaccu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_opcode, 0}, | |
2721 | {"th.vwmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_opcode, 0}, | |
2722 | {"th.vwmacc.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_opcode, 0}, | |
2723 | {"th.vwmaccsu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWMACCSUVV, MASK_TH_VWMACCSUVV, match_opcode, 0}, | |
2724 | {"th.vwmaccsu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_opcode, 0}, | |
2725 | {"th.vwmaccus.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_opcode, 0}, | |
2726 | {"th.vdivu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 }, | |
2727 | {"th.vdivu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 }, | |
2728 | {"th.vdiv.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 }, | |
2729 | {"th.vdiv.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 }, | |
2730 | {"th.vremu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 }, | |
2731 | {"th.vremu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 }, | |
2732 | {"th.vrem.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 }, | |
2733 | {"th.vrem.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 }, | |
2734 | {"th.vmerge.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 }, | |
2735 | {"th.vmerge.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 }, | |
2736 | {"th.vmerge.vim", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 }, | |
2737 | {"th.vmv.v.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 }, | |
2738 | {"th.vmv.v.x", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 }, | |
2739 | {"th.vmv.v.i", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 }, | |
9a51da26 JM |
2740 | {"th.vsaddu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 }, |
2741 | {"th.vsaddu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 }, | |
2742 | {"th.vsaddu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 }, | |
2743 | {"th.vsadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 }, | |
2744 | {"th.vsadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 }, | |
2745 | {"th.vsadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 }, | |
2746 | {"th.vssubu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 }, | |
2747 | {"th.vssubu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 }, | |
2748 | {"th.vssub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 }, | |
2749 | {"th.vssub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 }, | |
2750 | {"th.vaadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VAADDVV, MASK_TH_VAADDVV, match_opcode, 0 }, | |
2751 | {"th.vaadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VAADDVX, MASK_TH_VAADDVX, match_opcode, 0 }, | |
2752 | {"th.vaadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VAADDVI, MASK_TH_VAADDVI, match_opcode, 0 }, | |
2753 | {"th.vasub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VASUBVV, MASK_TH_VASUBVV, match_opcode, 0 }, | |
2754 | {"th.vasub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VASUBVX, MASK_TH_VASUBVX, match_opcode, 0 }, | |
2755 | {"th.vsmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 }, | |
2756 | {"th.vsmul.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 }, | |
2757 | {"th.vwsmaccu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VQMACCUVV, MASK_VQMACCUVV, match_opcode, 0 }, | |
2758 | {"th.vwsmaccu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VQMACCUVX, MASK_VQMACCUVX, match_opcode, 0 }, | |
2759 | {"th.vwsmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VQMACCVV, MASK_VQMACCVV, match_opcode, 0 }, | |
2760 | {"th.vwsmacc.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VQMACCVX, MASK_VQMACCVX, match_opcode, 0 }, | |
2761 | {"th.vwsmaccsu.vv",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWSMACCSUVV, MASK_TH_VWSMACCSUVV, match_opcode, 0 }, | |
2762 | {"th.vwsmaccsu.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VQMACCUSVX, MASK_VQMACCUSVX, match_opcode, 0 }, | |
2763 | {"th.vwsmaccus.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VQMACCSUVX, MASK_VQMACCSUVX, match_opcode, 0 }, | |
2764 | {"th.vssrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 }, | |
2765 | {"th.vssrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 }, | |
2766 | {"th.vssrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 }, | |
2767 | {"th.vssra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 }, | |
2768 | {"th.vssra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 }, | |
2769 | {"th.vssra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 }, | |
2770 | {"th.vnclipu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_opcode, 0 }, | |
2771 | {"th.vnclipu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_opcode, 0 }, | |
2772 | {"th.vnclipu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_opcode, 0 }, | |
2773 | {"th.vnclip.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_opcode, 0 }, | |
2774 | {"th.vnclip.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_opcode, 0 }, | |
2775 | {"th.vnclip.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_opcode, 0 }, | |
1ba39b6f JM |
2776 | {"th.vfadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0}, |
2777 | {"th.vfadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0}, | |
2778 | {"th.vfsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0}, | |
2779 | {"th.vfsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0}, | |
2780 | {"th.vfrsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0}, | |
2781 | {"th.vfwadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_opcode, 0}, | |
2782 | {"th.vfwadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_opcode, 0}, | |
2783 | {"th.vfwsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_opcode, 0}, | |
2784 | {"th.vfwsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_opcode, 0}, | |
2785 | {"th.vfwadd.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_opcode, 0}, | |
2786 | {"th.vfwsub.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_opcode, 0}, | |
2787 | {"th.vfwadd.wf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_opcode, 0}, | |
2788 | {"th.vfwsub.wf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_opcode, 0}, | |
2789 | {"th.vfmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0}, | |
2790 | {"th.vfmul.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0}, | |
2791 | {"th.vfdiv.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0}, | |
2792 | {"th.vfdiv.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0}, | |
2793 | {"th.vfrdiv.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0}, | |
2794 | {"th.vfwmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_opcode, 0}, | |
2795 | {"th.vfwmul.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_opcode, 0}, | |
2796 | {"th.vfmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0}, | |
2797 | {"th.vfmadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0}, | |
2798 | {"th.vfnmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0}, | |
2799 | {"th.vfnmadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0}, | |
2800 | {"th.vfmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0}, | |
2801 | {"th.vfmsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0}, | |
2802 | {"th.vfnmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0}, | |
2803 | {"th.vfnmsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0}, | |
2804 | {"th.vfmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0}, | |
2805 | {"th.vfmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0}, | |
2806 | {"th.vfnmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0}, | |
2807 | {"th.vfnmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0}, | |
2808 | {"th.vfmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0}, | |
2809 | {"th.vfmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0}, | |
2810 | {"th.vfnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0}, | |
2811 | {"th.vfnmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0}, | |
2812 | {"th.vfwmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_opcode, 0}, | |
2813 | {"th.vfwmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_opcode, 0}, | |
2814 | {"th.vfwnmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_opcode, 0}, | |
2815 | {"th.vfwnmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_opcode, 0}, | |
2816 | {"th.vfwmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_opcode, 0}, | |
2817 | {"th.vfwmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_opcode, 0}, | |
2818 | {"th.vfwnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_opcode, 0}, | |
2819 | {"th.vfwnmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_opcode, 0}, | |
2820 | {"th.vfsqrt.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFSQRTV, MASK_TH_VFSQRTV, match_opcode, 0}, | |
2821 | {"th.vfmin.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0}, | |
2822 | {"th.vfmin.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0}, | |
2823 | {"th.vfmax.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0}, | |
2824 | {"th.vfmax.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0}, | |
77d242a0 JM |
2825 | {"th.vfneg.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2, INSN_ALIAS }, |
2826 | {"th.vfabs.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VuVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vs1_eq_vs2, INSN_ALIAS }, | |
1ba39b6f JM |
2827 | {"th.vfsgnj.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0}, |
2828 | {"th.vfsgnj.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0}, | |
2829 | {"th.vfsgnjn.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0}, | |
2830 | {"th.vfsgnjn.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0}, | |
2831 | {"th.vfsgnjx.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0}, | |
2832 | {"th.vfsgnjx.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0}, | |
2833 | {"th.vmfeq.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0}, | |
2834 | {"th.vmfeq.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0}, | |
2835 | {"th.vmfne.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0}, | |
2836 | {"th.vmfne.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0}, | |
2837 | {"th.vmflt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0}, | |
2838 | {"th.vmflt.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0}, | |
2839 | {"th.vmfle.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0}, | |
2840 | {"th.vmfle.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0}, | |
2841 | {"th.vmfgt.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0}, | |
2842 | {"th.vmfge.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0}, | |
2843 | {"th.vmfgt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS}, | |
2844 | {"th.vmfge.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS}, | |
2845 | {"th.vmford.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFORDVV, MASK_TH_VMFORDVV, match_opcode, 0}, | |
2846 | {"th.vmford.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFORDVF, MASK_TH_VMFORDVF, match_opcode, 0}, | |
2847 | {"th.vfclass.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCLASSV, MASK_TH_VFCLASSV, match_opcode, 0}, | |
2848 | {"th.vfmerge.vfm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0}, | |
2849 | {"th.vfmv.v.f", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 }, | |
2850 | {"th.vfcvt.xu.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTXUFV, MASK_TH_VFCVTXUFV, match_opcode, 0}, | |
2851 | {"th.vfcvt.x.f.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTXFV, MASK_TH_VFCVTXFV, match_opcode, 0}, | |
2852 | {"th.vfcvt.f.xu.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTFXUV, MASK_TH_VFCVTFXUV, match_opcode, 0}, | |
2853 | {"th.vfcvt.f.x.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTFXV, MASK_TH_VFCVTFXV, match_opcode, 0}, | |
2854 | {"th.vfwcvt.xu.f.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTXUFV, MASK_TH_VFWCVTXUFV, match_opcode, 0}, | |
2855 | {"th.vfwcvt.x.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTXFV, MASK_TH_VFWCVTXFV, match_opcode, 0}, | |
2856 | {"th.vfwcvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFXUV, MASK_TH_VFWCVTFXUV, match_opcode, 0}, | |
2857 | {"th.vfwcvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFXV, MASK_TH_VFWCVTFXV, match_opcode, 0}, | |
2858 | {"th.vfwcvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFFV, MASK_TH_VFWCVTFFV, match_opcode, 0}, | |
2859 | {"th.vfncvt.xu.f.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTXUFV, MASK_TH_VFNCVTXUFV, match_opcode, 0}, | |
2860 | {"th.vfncvt.x.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTXFV, MASK_TH_VFNCVTXFV, match_opcode, 0}, | |
2861 | {"th.vfncvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXUV, MASK_TH_VFNCVTFXUV, match_opcode, 0}, | |
2862 | {"th.vfncvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXV, MASK_TH_VFNCVTFXV, match_opcode, 0}, | |
2863 | {"th.vfncvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFFV, MASK_TH_VFNCVTFFV, match_opcode, 0}, | |
b4cf88da JM |
2864 | {"th.vredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0}, |
2865 | {"th.vredmaxu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0}, | |
2866 | {"th.vredmax.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0}, | |
2867 | {"th.vredminu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0}, | |
2868 | {"th.vredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0}, | |
2869 | {"th.vredand.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0}, | |
2870 | {"th.vredor.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0}, | |
2871 | {"th.vredxor.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0}, | |
2872 | {"th.vwredsumu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0}, | |
2873 | {"th.vwredsum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0}, | |
2874 | {"th.vfredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0}, | |
2875 | {"th.vfredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, 0}, | |
2876 | {"th.vfredmax.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0}, | |
2877 | {"th.vfredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0}, | |
2878 | {"th.vfwredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0}, | |
2879 | {"th.vfwredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0}, | |
832cdeec | 2880 | {"th.vmcpy.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS}, |
77d242a0 | 2881 | {"th.vmmv.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS}, |
832cdeec JM |
2882 | {"th.vmclr.m", 0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS}, |
2883 | {"th.vmset.m", 0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS}, | |
2884 | {"th.vmnot.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS}, | |
2885 | {"th.vmand.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0}, | |
2886 | {"th.vmnand.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0}, | |
2887 | {"th.vmandnot.mm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, 0}, | |
2888 | {"th.vmxor.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0}, | |
2889 | {"th.vmor.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0}, | |
2890 | {"th.vmnor.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0}, | |
2891 | {"th.vmornot.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, 0}, | |
2892 | {"th.vmxnor.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0}, | |
2893 | {"th.vmpopc.m", 0, INSN_CLASS_XTHEADVECTOR, "d,VtVm", MATCH_TH_VMPOPCM, MASK_TH_VMPOPCM, match_opcode, 0}, | |
2894 | {"th.vmfirst.m", 0, INSN_CLASS_XTHEADVECTOR, "d,VtVm", MATCH_TH_VMFIRSTM, MASK_TH_VMFIRSTM, match_opcode, 0}, | |
2895 | {"th.vmsbf.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSBFM, MASK_TH_VMSBFM, match_opcode, 0}, | |
2896 | {"th.vmsif.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSIFM, MASK_TH_VMSIFM, match_opcode, 0}, | |
2897 | {"th.vmsof.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSOFM, MASK_TH_VMSOFM, match_opcode, 0}, | |
2898 | {"th.viota.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VIOTAM, MASK_TH_VIOTAM, match_opcode, 0}, | |
2899 | {"th.vid.v", 0, INSN_CLASS_XTHEADVECTOR, "VdVm", MATCH_TH_VIDV, MASK_TH_VIDV, match_opcode, 0}, | |
d95ba722 JM |
2900 | {"th.vmv.x.s", 0, INSN_CLASS_XTHEADVECTOR, "d,Vt", MATCH_TH_VMVXS, MASK_TH_VMVXS, match_opcode, INSN_ALIAS}, |
2901 | {"th.vext.x.v", 0, INSN_CLASS_XTHEADVECTOR, "d,Vt,s", MATCH_TH_VEXTXV, MASK_TH_VEXTXV, match_opcode, 0}, | |
2902 | {"th.vmv.s.x", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_TH_VMVSX, MASK_TH_VMVSX, match_opcode, 0}, | |
2903 | {"th.vfmv.f.s", 0, INSN_CLASS_XTHEADVECTOR, "D,Vt", MATCH_TH_VFMVFS, MASK_TH_VFMVFS, match_opcode, 0}, | |
2904 | {"th.vfmv.s.f", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_TH_VFMVSF, MASK_TH_VFMVSF, match_opcode, 0}, | |
2905 | {"th.vslideup.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_opcode, 0}, | |
2906 | {"th.vslideup.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_opcode, 0}, | |
2907 | {"th.vslidedown.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0}, | |
2908 | {"th.vslidedown.vi",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0}, | |
2909 | {"th.vslide1up.vx",0 ,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_opcode, 0}, | |
2910 | {"th.vslide1down.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0}, | |
2911 | {"th.vrgather.vv",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_opcode, 0}, | |
2912 | {"th.vrgather.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_opcode, 0}, | |
2913 | {"th.vrgather.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_opcode, 0}, | |
2914 | {"th.vcompress.vm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_opcode, 0}, | |
9aa5dde6 | 2915 | |
1656d3f8 | 2916 | /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ |
fe0f44a0 TO |
2917 | {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, |
2918 | {"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, | |
1656d3f8 | 2919 | |
248bf6de NC |
2920 | /* Vendor-specific (SiFive) vector coprocessor interface instructions. */ |
2921 | {"sf.vc.x", 0, INSN_CLASS_XSFVCP, "XsO2,Xst,Xsd,s", MATCH_SF_VC_X, MASK_SF_VC_X, match_opcode, 0 }, | |
2922 | {"sf.vc.v.x", 0, INSN_CLASS_XSFVCP, "XsO2,Xst,Vd,s", MATCH_SF_VC_V_X, MASK_SF_VC_V_X, match_opcode, 0 }, | |
2923 | {"sf.vc.i", 0, INSN_CLASS_XSFVCP, "XsO2,Xst,Xsd,Vi", MATCH_SF_VC_I, MASK_SF_VC_I, match_opcode, 0 }, | |
2924 | {"sf.vc.v.i", 0, INSN_CLASS_XSFVCP, "XsO2,Xst,Vd,Vi", MATCH_SF_VC_V_I, MASK_SF_VC_V_I, match_opcode, 0 }, | |
2925 | {"sf.vc.vv", 0, INSN_CLASS_XSFVCP, "XsO2,Xsd,Vt,Vs", MATCH_SF_VC_VV, MASK_SF_VC_VV, match_opcode, 0 }, | |
2926 | {"sf.vc.v.vv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_V_VV, MASK_SF_VC_V_VV, match_opcode, 0 }, | |
2927 | {"sf.vc.xv", 0, INSN_CLASS_XSFVCP, "XsO2,Xsd,Vt,s", MATCH_SF_VC_XV, MASK_SF_VC_XV, match_opcode, 0 }, | |
2928 | {"sf.vc.v.xv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s", MATCH_SF_VC_V_XV, MASK_SF_VC_V_XV, match_opcode, 0 }, | |
2929 | {"sf.vc.iv", 0, INSN_CLASS_XSFVCP, "XsO2,Xsd,Vt,Vi", MATCH_SF_VC_IV, MASK_SF_VC_IV, match_opcode, 0 }, | |
2930 | {"sf.vc.v.iv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_V_IV, MASK_SF_VC_V_IV, match_opcode, 0 }, | |
2931 | {"sf.vc.fv", 0, INSN_CLASS_XSFVCP, "XsO1,Xsd,Vt,S", MATCH_SF_VC_FV, MASK_SF_VC_FV, match_opcode, 0 }, | |
2932 | {"sf.vc.v.fv", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_V_FV, MASK_SF_VC_V_FV, match_opcode, 0 }, | |
2933 | {"sf.vc.vvv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_VVV, MASK_SF_VC_VVV, match_opcode, 0 }, | |
2934 | {"sf.vc.v.vvv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_V_VVV, MASK_SF_VC_V_VVV, match_opcode, 0 }, | |
2935 | {"sf.vc.xvv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s", MATCH_SF_VC_XVV, MASK_SF_VC_XVV, match_opcode, 0 }, | |
2936 | {"sf.vc.v.xvv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s", MATCH_SF_VC_V_XVV, MASK_SF_VC_V_XVV, match_opcode, 0 }, | |
2937 | {"sf.vc.ivv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_IVV, MASK_SF_VC_IVV, match_opcode, 0 }, | |
2938 | {"sf.vc.v.ivv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_V_IVV, MASK_SF_VC_V_IVV, match_opcode, 0 }, | |
2939 | {"sf.vc.fvv", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_FVV, MASK_SF_VC_FVV, match_opcode, 0 }, | |
2940 | {"sf.vc.v.fvv", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_V_FVV, MASK_SF_VC_V_FVV, match_opcode, 0 }, | |
2941 | {"sf.vc.vvw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_VVW, MASK_SF_VC_VVW, match_opcode, 0 }, | |
2942 | {"sf.vc.v.vvw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_V_VVW, MASK_SF_VC_V_VVW, match_opcode, 0 }, | |
2943 | {"sf.vc.xvw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s", MATCH_SF_VC_XVW, MASK_SF_VC_XVW, match_opcode, 0 }, | |
2944 | {"sf.vc.v.xvw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s", MATCH_SF_VC_V_XVW, MASK_SF_VC_V_XVW, match_opcode, 0 }, | |
2945 | {"sf.vc.ivw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_IVW, MASK_SF_VC_IVW, match_opcode, 0 }, | |
2946 | {"sf.vc.v.ivw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_V_IVW, MASK_SF_VC_V_IVW, match_opcode, 0 }, | |
2947 | {"sf.vc.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_FVW, MASK_SF_VC_FVW, match_opcode, 0 }, | |
2948 | {"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_V_FVW, MASK_SF_VC_V_FVW, match_opcode, 0 }, | |
2949 | ||
e23eba97 | 2950 | /* Terminate the list. */ |
7e9ad3a3 | 2951 | {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} |
e23eba97 | 2952 | }; |
0e35537d JW |
2953 | |
2954 | /* Instruction format for .insn directive. */ | |
2955 | const struct riscv_opcode riscv_insn_types[] = | |
2956 | { | |
dcd709e0 | 2957 | /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ |
1942a048 NC |
2958 | {"r", 0, INSN_CLASS_I, "O4,F3,F7,d,s,t", 0, 0, match_opcode, 0 }, |
2959 | {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,s,t", 0, 0, match_opcode, 0 }, | |
2960 | {"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,t", 0, 0, match_opcode, 0 }, | |
2961 | {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,t", 0, 0, match_opcode, 0 }, | |
2962 | {"r", 0, INSN_CLASS_F, "O4,F3,F7,d,s,T", 0, 0, match_opcode, 0 }, | |
2963 | {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,s,T", 0, 0, match_opcode, 0 }, | |
2964 | {"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,T", 0, 0, match_opcode, 0 }, | |
2965 | {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,T", 0, 0, match_opcode, 0 }, | |
2966 | {"r", 0, INSN_CLASS_I, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 }, | |
2967 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 }, | |
2968 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 }, | |
2969 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, 0 }, | |
2970 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, 0 }, | |
2971 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, 0 }, | |
2972 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, 0 }, | |
2973 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, 0 }, | |
2974 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, 0 }, | |
2975 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, 0 }, | |
2976 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, 0 }, | |
2977 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, 0 }, | |
2978 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, 0 }, | |
2979 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, 0 }, | |
2980 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 }, | |
2981 | {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 }, | |
2982 | ||
2983 | {"r4", 0, INSN_CLASS_I, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 }, | |
2984 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 }, | |
2985 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 }, | |
2986 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, 0 }, | |
2987 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, 0 }, | |
2988 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, 0 }, | |
2989 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, 0 }, | |
2990 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, 0 }, | |
2991 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, 0 }, | |
2992 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, 0 }, | |
2993 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, 0 }, | |
2994 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, 0 }, | |
2995 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, 0 }, | |
2996 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, 0 }, | |
2997 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 }, | |
2998 | {"r4", 0, INSN_CLASS_F, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 }, | |
2999 | ||
3000 | {"i", 0, INSN_CLASS_I, "O4,F3,d,s,j", 0, 0, match_opcode, 0 }, | |
3001 | {"i", 0, INSN_CLASS_F, "O4,F3,D,s,j", 0, 0, match_opcode, 0 }, | |
3002 | {"i", 0, INSN_CLASS_F, "O4,F3,d,S,j", 0, 0, match_opcode, 0 }, | |
3003 | {"i", 0, INSN_CLASS_F, "O4,F3,D,S,j", 0, 0, match_opcode, 0 }, | |
3004 | {"i", 0, INSN_CLASS_I, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 }, | |
3005 | {"i", 0, INSN_CLASS_F, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 }, | |
3006 | ||
3007 | {"s", 0, INSN_CLASS_I, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 }, | |
3008 | {"s", 0, INSN_CLASS_F, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 }, | |
3009 | ||
3010 | {"sb", 0, INSN_CLASS_I, "O4,F3,s,t,p", 0, 0, match_opcode, 0 }, | |
3011 | {"sb", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, 0 }, | |
3012 | {"sb", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, 0 }, | |
3013 | {"sb", 0, INSN_CLASS_F, "O4,F3,S,T,p", 0, 0, match_opcode, 0 }, | |
1942a048 NC |
3014 | {"b", 0, INSN_CLASS_I, "O4,F3,s,t,p", 0, 0, match_opcode, 0 }, |
3015 | {"b", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, 0 }, | |
3016 | {"b", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, 0 }, | |
3017 | {"b", 0, INSN_CLASS_F, "O4,F3,S,T,p", 0, 0, match_opcode, 0 }, | |
3018 | ||
3019 | {"u", 0, INSN_CLASS_I, "O4,d,u", 0, 0, match_opcode, 0 }, | |
3020 | {"u", 0, INSN_CLASS_F, "O4,D,u", 0, 0, match_opcode, 0 }, | |
3021 | ||
3022 | {"uj", 0, INSN_CLASS_I, "O4,d,a", 0, 0, match_opcode, 0 }, | |
3023 | {"uj", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, 0 }, | |
1942a048 NC |
3024 | {"j", 0, INSN_CLASS_I, "O4,d,a", 0, 0, match_opcode, 0 }, |
3025 | {"j", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, 0 }, | |
3026 | ||
3027 | {"cr", 0, INSN_CLASS_C, "O2,CF4,d,CV", 0, 0, match_opcode, 0 }, | |
3028 | {"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,D,CV", 0, 0, match_opcode, 0 }, | |
3029 | {"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,d,CT", 0, 0, match_opcode, 0 }, | |
3030 | {"cr", 0, INSN_CLASS_F_AND_C, "O2,CF4,D,CT", 0, 0, match_opcode, 0 }, | |
3031 | ||
3032 | {"ci", 0, INSN_CLASS_C, "O2,CF3,d,Co", 0, 0, match_opcode, 0 }, | |
3033 | {"ci", 0, INSN_CLASS_F_AND_C, "O2,CF3,D,Co", 0, 0, match_opcode, 0 }, | |
3034 | ||
3035 | {"ciw", 0, INSN_CLASS_C, "O2,CF3,Ct,C8", 0, 0, match_opcode, 0 }, | |
3036 | {"ciw", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C8", 0, 0, match_opcode, 0 }, | |
3037 | ||
5a9f5403 NC |
3038 | {"css", 0, INSN_CLASS_C, "O2,CF3,CV,C6", 0, 0, match_opcode, 0 }, |
3039 | {"css", 0, INSN_CLASS_F_AND_C, "O2,CF3,CT,C6", 0, 0, match_opcode, 0 }, | |
3040 | ||
3041 | {"cl", 0, INSN_CLASS_C, "O2,CF3,Ct,C5(Cs)", 0, 0, match_opcode, 0 }, | |
3042 | {"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode, 0 }, | |
3043 | {"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode, 0 }, | |
3044 | {"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode, 0 }, | |
3045 | ||
3046 | {"cs", 0, INSN_CLASS_C, "O2,CF3,Ct,C5(Cs)", 0, 0, match_opcode, 0 }, | |
3047 | {"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode, 0 }, | |
3048 | {"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode, 0 }, | |
3049 | {"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode, 0 }, | |
3050 | ||
1942a048 NC |
3051 | {"ca", 0, INSN_CLASS_C, "O2,CF6,CF2,Cs,Ct", 0, 0, match_opcode, 0 }, |
3052 | {"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,Ct", 0, 0, match_opcode, 0 }, | |
3053 | {"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,Cs,CD", 0, 0, match_opcode, 0 }, | |
3054 | {"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,CD", 0, 0, match_opcode, 0 }, | |
3055 | ||
3056 | {"cb", 0, INSN_CLASS_C, "O2,CF3,Cs,Cp", 0, 0, match_opcode, 0 }, | |
3057 | {"cb", 0, INSN_CLASS_F_AND_C, "O2,CF3,CS,Cp", 0, 0, match_opcode, 0 }, | |
3058 | ||
3059 | {"cj", 0, INSN_CLASS_C, "O2,CF3,Ca", 0, 0, match_opcode, 0 }, | |
dcd709e0 | 3060 | |
0e35537d | 3061 | /* Terminate the list. */ |
7e9ad3a3 | 3062 | {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} |
0e35537d | 3063 | }; |