[thirdparty/mdadm.git] / platform-intel.h

/*
 * Intel(R) Matrix Storage Manager hardware and firmware support routines
 *
 * Copyright (C) 2008 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 */
#include <asm/types.h>
#include <strings.h>

/* according to GUID format: "xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx" */
#define GUID_STR_MAX	37

/* The IMSM Capability (IMSM AHCI and ISCU OROM/EFI variable) Version Table definition */
struct imsm_orom {
	__u8 signature[4];
	#define IMSM_OROM_SIGNATURE "$VER"
	#define IMSM_NVME_OROM_COMPAT_SIGNATURE "$NVM"
	__u8 table_ver_major; /* Currently 2 (can change with future revs) */
	__u8 table_ver_minor; /* Currently 2 (can change with future revs) */
	__u16 major_ver; /* Example: 8 as in 8.6.0.1020 */
	__u16 minor_ver; /* Example: 6 as in 8.6.0.1020 */
	__u16 hotfix_ver; /* Example: 0 as in 8.6.0.1020 */
	__u16 build; /* Example: 1020 as in 8.6.0.1020 */
	__u8 len; /* number of bytes in this entire table */
	__u8 checksum; /* checksum of all the bytes in this table */
	__u16 rlc; /* RAID Level Capability */
	/* we assume the cpu is x86 as the orom should not be found
	 * anywhere else
	 */
	#define IMSM_OROM_RLC_RAID0 (1 << 0)
	#define IMSM_OROM_RLC_RAID1 (1 << 1)
	#define IMSM_OROM_RLC_RAID10 (1 << 2)
	#define IMSM_OROM_RLC_RAID1E (1 << 3)
	#define IMSM_OROM_RLC_RAID5 (1 << 4)
	#define IMSM_OROM_RLC_RAID_CNG (1 << 5)
	__u16 sss; /* Strip Size Supported */
	#define IMSM_OROM_SSS_2kB (1 << 0)
	#define IMSM_OROM_SSS_4kB (1 << 1)
	#define IMSM_OROM_SSS_8kB (1 << 2)
	#define IMSM_OROM_SSS_16kB (1 << 3)
	#define IMSM_OROM_SSS_32kB (1 << 4)
	#define IMSM_OROM_SSS_64kB (1 << 5)
	#define IMSM_OROM_SSS_128kB (1 << 6)
	#define IMSM_OROM_SSS_256kB (1 << 7)
	#define IMSM_OROM_SSS_512kB (1 << 8)
	#define IMSM_OROM_SSS_1MB (1 << 9)
	#define IMSM_OROM_SSS_2MB (1 << 10)
	#define IMSM_OROM_SSS_4MB (1 << 11)
	#define IMSM_OROM_SSS_8MB (1 << 12)
	#define IMSM_OROM_SSS_16MB (1 << 13)
	#define IMSM_OROM_SSS_32MB (1 << 14)
	#define IMSM_OROM_SSS_64MB (1 << 15)
	__u16 dpa; /* Disks Per Array supported */
	#define IMSM_OROM_DISKS_PER_ARRAY 6
	#define IMSM_OROM_DISKS_PER_ARRAY_NVME 12
	__u16 tds; /* Total Disks Supported */
	#define IMSM_OROM_TOTAL_DISKS 6
	#define IMSM_OROM_TOTAL_DISKS_NVME 12
	__u8 vpa; /* # Volumes Per Array supported */
	#define IMSM_OROM_VOLUMES_PER_ARRAY 2
	__u8 vphba; /* # Volumes Per Host Bus Adapter supported */
	#define IMSM_OROM_VOLUMES_PER_HBA 4
	#define IMSM_OROM_VOLUMES_PER_HBA_NVME 4
	/* Attributes supported. This should map to the
	 * attributes in the MPB. Also, lower 16 bits
	 * should match/duplicate RLC bits above.
	 */
	__u32 attr;
	#define IMSM_OROM_ATTR_RAID0 IMSM_OROM_RLC_RAID0
	#define IMSM_OROM_ATTR_RAID1 IMSM_OROM_RLC_RAID1
	#define IMSM_OROM_ATTR_RAID10 IMSM_OROM_RLC_RAID10
	#define IMSM_OROM_ATTR_RAID1E IMSM_OROM_RLC_RAID1E
	#define IMSM_OROM_ATTR_RAID5 IMSM_OROM_RLC_RAID5
	#define IMSM_OROM_ATTR_RAID_CNG IMSM_OROM_RLC_RAID_CNG
	#define IMSM_OROM_ATTR_2TB_DISK (1 << 26)
	#define IMSM_OROM_ATTR_2TB (1 << 29)
	#define IMSM_OROM_ATTR_PM (1 << 30)
	#define IMSM_OROM_ATTR_ChecksumVerify (1 << 31)
	__u32 capabilities;
	#define IMSM_OROM_CAPABILITIES_Ext_SATA (1 << 0)
	#define IMSM_OROM_CAPABILITIES_TurboMemory (1 << 1)
	#define IMSM_OROM_CAPABILITIES_HddPassword (1 << 2)
	#define IMSM_OROM_CAPABILITIES_DiskCoercion (1 << 3)
	__u32 driver_features;
	#define IMSM_OROM_CAPABILITIES_HDDUnlock (1 << 0)
	#define IMSM_OROM_CAPABILITIES_LEDLoc (1 << 1)
	#define IMSM_OROM_CAPABILITIES_EnterpriseSystem (1 << 2)
	#define IMSM_OROM_CAPABILITIES_Zpodd (1 << 3)
	#define IMSM_OROM_CAPABILITIES_LargeDramCache (1 << 4)
	#define IMSM_OROM_CAPABILITIES_Rohi (1 << 5)
	#define IMSM_OROM_CAPABILITIES_ReadPatrol (1 << 6)
	#define IMSM_OROM_CAPABILITIES_XorHw (1 << 7)
	#define IMSM_OROM_CAPABILITIES_SKUMode ((1 << 8)|(1 << 9))
	#define IMSM_OROM_CAPABILITIES_TPV (1 << 10)
} __attribute__((packed));

static inline int imsm_orom_has_raid0(const struct imsm_orom *orom)
{
	return !!(orom->rlc & IMSM_OROM_RLC_RAID0);
}
static inline int imsm_orom_has_raid1(const struct imsm_orom *orom)
{
	return !!(orom->rlc & IMSM_OROM_RLC_RAID1);
}
static inline int imsm_orom_has_raid1e(const struct imsm_orom *orom)
{
	return !!(orom->rlc & IMSM_OROM_RLC_RAID1E);
}
static inline int imsm_orom_has_raid10(const struct imsm_orom *orom)
{
	return !!(orom->rlc & IMSM_OROM_RLC_RAID10);
}
static inline int imsm_orom_has_raid5(const struct imsm_orom *orom)
{
	return !!(orom->rlc & IMSM_OROM_RLC_RAID5);
}

/**
 * imsm_orom_has_chunk - check if the orom supports the given chunk size
 * @orom: orom pointer from find_imsm_orom
 * @chunk: chunk size in kibibytes
 */
static inline int imsm_orom_has_chunk(const struct imsm_orom *orom, int chunk)
{
	int fs = ffs(chunk);
	if (!fs)
		return 0;
	fs--; /* bit num to bit index */
	if (chunk & (chunk-1))
		return 0; /* not a power of 2 */
	return !!(orom->sss & (1 << (fs - 1)));
}

/**
 * fls - find last (most-significant) bit set
 * @x: the word to search
 * The funciton is borrowed from Linux kernel code
 * include/asm-generic/bitops/fls.h
 */
static inline int fls(int x)
{
	int r = 32;

	if (!x)
		return 0;
	if (!(x & 0xffff0000u)) {
		x <<= 16;
		r -= 16;
	}
	if (!(x & 0xff000000u)) {
		x <<= 8;
		r -= 8;
	}
	if (!(x & 0xf0000000u)) {
		x <<= 4;
		r -= 4;
	}
	if (!(x & 0xc0000000u)) {
		x <<= 2;
		r -= 2;
	}
	if (!(x & 0x80000000u)) {
		r -= 1;
	}
	return r;
}

static inline int imsm_orom_is_enterprise(const struct imsm_orom *orom)
{
	return !!(orom->driver_features & IMSM_OROM_CAPABILITIES_EnterpriseSystem);
}

static inline int imsm_orom_is_nvme(const struct imsm_orom *orom)
{
	return memcmp(orom->signature, IMSM_NVME_OROM_COMPAT_SIGNATURE,
			sizeof(orom->signature)) == 0;
}

static inline int imsm_orom_has_tpv_support(const struct imsm_orom *orom)
{
	return !!(orom->driver_features & IMSM_OROM_CAPABILITIES_TPV);
}

enum sys_dev_type {
	SYS_DEV_UNKNOWN = 0,
	SYS_DEV_SAS,
	SYS_DEV_SATA,
	SYS_DEV_NVME,
	SYS_DEV_VMD,
	SYS_DEV_SATA_VMD,
	SYS_DEV_MAX
};

struct sys_dev {
	enum sys_dev_type type;
	char *path;
	char *pci_id;
	__u16  dev_id;
	__u32  class;
	struct sys_dev *next;
};

struct efi_guid {
	__u8 b[16];
};

struct devid_list {
	__u16 devid;
	struct devid_list *next;
};

struct orom_entry {
	struct imsm_orom orom;
	struct devid_list *devid_list;
	enum sys_dev_type type;
	struct orom_entry *next;
};

extern struct orom_entry *orom_entries;

static inline char *guid_str(char *buf, struct efi_guid guid)
{
	snprintf(buf, GUID_STR_MAX, "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x",
		 guid.b[3], guid.b[2], guid.b[1], guid.b[0],
		 guid.b[5], guid.b[4], guid.b[7], guid.b[6],
		 guid.b[8], guid.b[9], guid.b[10], guid.b[11],
		 guid.b[12], guid.b[13], guid.b[14], guid.b[15]);
	return buf;
}

char *get_nvme_multipath_dev_hw_path(const char *dev_path);
char *diskfd_to_devpath(int fd, int dev_level, char *buf);
int devpath_to_char(const char *dev_path, const char *entry, char *buf,
		    int len, int verbose);
__u16 devpath_to_vendor(const char *dev_path);
struct sys_dev *find_driver_devices(const char *bus, const char *driver);
struct sys_dev *find_intel_devices(void);
const struct imsm_orom *find_imsm_capability(struct sys_dev *hba);
const struct imsm_orom *find_imsm_orom(void);
int disk_attached_to_hba(int fd, const char *hba_path);
int devt_attached_to_hba(dev_t dev, const char *hba_path);
char *devt_to_devpath(dev_t dev, int dev_level, char *buf);
int path_attached_to_hba(const char *disk_path, const char *hba_path);
const char *get_sys_dev_type(enum sys_dev_type);
const struct orom_entry *get_orom_entry_by_device_id(__u16 dev_id);
const struct imsm_orom *get_orom_by_device_id(__u16 device_id);
struct sys_dev *device_by_id(__u16 device_id);
struct sys_dev *device_by_id_and_path(__u16 device_id, const char *path);
int is_multipath_nvme(int disk_fd);
int imsm_is_nvme_namespace_supported(int disk_fd, int verbose);
char *vmd_domain_to_controller(struct sys_dev *hba, char *buf);
Commit	Line	Data
b390f610 DW	1	/*
	2	* Intel(R) Matrix Storage Manager hardware and firmware support routines
	3	*
	4	* Copyright (C) 2008 Intel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program; if not, write to the Free Software Foundation, Inc.,
	17	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18	*/
	19	#include <asm/types.h>
88c32bb1	20	#include <strings.h>
b390f610	21
5ccd457b KT	22	/* according to GUID format: "xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx" */
	23	#define GUID_STR_MAX 37
	24
fc13853f	25	/* The IMSM Capability (IMSM AHCI and ISCU OROM/EFI variable) Version Table definition */
b390f610 DW	26	struct imsm_orom {
b390f610 DW	27	__u8 signature[4];
6b781d33	28	#define IMSM_OROM_SIGNATURE "$VER"
614902f6	29	#define IMSM_NVME_OROM_COMPAT_SIGNATURE "$NVM"
b390f610 DW	30	__u8 table_ver_major; /* Currently 2 (can change with future revs) */
	31	__u8 table_ver_minor; /* Currently 2 (can change with future revs) */
	32	__u16 major_ver; /* Example: 8 as in 8.6.0.1020 */
	33	__u16 minor_ver; /* Example: 6 as in 8.6.0.1020 */
	34	__u16 hotfix_ver; /* Example: 0 as in 8.6.0.1020 */
	35	__u16 build; /* Example: 1020 as in 8.6.0.1020 */
	36	__u8 len; /* number of bytes in this entire table */
	37	__u8 checksum; /* checksum of all the bytes in this table */
	38	__u16 rlc; /* RAID Level Capability */
	39	/* we assume the cpu is x86 as the orom should not be found
	40	* anywhere else
	41	*/
	42	#define IMSM_OROM_RLC_RAID0 (1 << 0)
	43	#define IMSM_OROM_RLC_RAID1 (1 << 1)
	44	#define IMSM_OROM_RLC_RAID10 (1 << 2)
	45	#define IMSM_OROM_RLC_RAID1E (1 << 3)
	46	#define IMSM_OROM_RLC_RAID5 (1 << 4)
	47	#define IMSM_OROM_RLC_RAID_CNG (1 << 5)
	48	__u16 sss; /* Strip Size Supported */
	49	#define IMSM_OROM_SSS_2kB (1 << 0)
	50	#define IMSM_OROM_SSS_4kB (1 << 1)
	51	#define IMSM_OROM_SSS_8kB (1 << 2)
	52	#define IMSM_OROM_SSS_16kB (1 << 3)
	53	#define IMSM_OROM_SSS_32kB (1 << 4)
	54	#define IMSM_OROM_SSS_64kB (1 << 5)
	55	#define IMSM_OROM_SSS_128kB (1 << 6)
	56	#define IMSM_OROM_SSS_256kB (1 << 7)
	57	#define IMSM_OROM_SSS_512kB (1 << 8)
	58	#define IMSM_OROM_SSS_1MB (1 << 9)
	59	#define IMSM_OROM_SSS_2MB (1 << 10)
	60	#define IMSM_OROM_SSS_4MB (1 << 11)
	61	#define IMSM_OROM_SSS_8MB (1 << 12)
	62	#define IMSM_OROM_SSS_16MB (1 << 13)
	63	#define IMSM_OROM_SSS_32MB (1 << 14)
	64	#define IMSM_OROM_SSS_64MB (1 << 15)
	65	__u16 dpa; /* Disks Per Array supported */
fc13853f	66	#define IMSM_OROM_DISKS_PER_ARRAY 6
614902f6	67	#define IMSM_OROM_DISKS_PER_ARRAY_NVME 12
b390f610	68	__u16 tds; /* Total Disks Supported */
fc13853f	69	#define IMSM_OROM_TOTAL_DISKS 6
614902f6	70	#define IMSM_OROM_TOTAL_DISKS_NVME 12
b390f610	71	__u8 vpa; /* # Volumes Per Array supported */
fc13853f	72	#define IMSM_OROM_VOLUMES_PER_ARRAY 2
b390f610	73	__u8 vphba; /* # Volumes Per Host Bus Adapter supported */
fc13853f	74	#define IMSM_OROM_VOLUMES_PER_HBA 4
614902f6	75	#define IMSM_OROM_VOLUMES_PER_HBA_NVME 4
b390f610 DW	76	/* Attributes supported. This should map to the
	77	* attributes in the MPB. Also, lower 16 bits
	78	* should match/duplicate RLC bits above.
	79	*/
	80	__u32 attr;
	81	#define IMSM_OROM_ATTR_RAID0 IMSM_OROM_RLC_RAID0
	82	#define IMSM_OROM_ATTR_RAID1 IMSM_OROM_RLC_RAID1
	83	#define IMSM_OROM_ATTR_RAID10 IMSM_OROM_RLC_RAID10
	84	#define IMSM_OROM_ATTR_RAID1E IMSM_OROM_RLC_RAID1E
	85	#define IMSM_OROM_ATTR_RAID5 IMSM_OROM_RLC_RAID5
	86	#define IMSM_OROM_ATTR_RAID_CNG IMSM_OROM_RLC_RAID_CNG
29cd0821	87	#define IMSM_OROM_ATTR_2TB_DISK (1 << 26)
b390f610 DW	88	#define IMSM_OROM_ATTR_2TB (1 << 29)
	89	#define IMSM_OROM_ATTR_PM (1 << 30)
	90	#define IMSM_OROM_ATTR_ChecksumVerify (1 << 31)
2a7e6de2 LM	91	__u32 capabilities;
	92	#define IMSM_OROM_CAPABILITIES_Ext_SATA (1 << 0)
	93	#define IMSM_OROM_CAPABILITIES_TurboMemory (1 << 1)
	94	#define IMSM_OROM_CAPABILITIES_HddPassword (1 << 2)
	95	#define IMSM_OROM_CAPABILITIES_DiskCoercion (1 << 3)
	96	__u32 driver_features;
	97	#define IMSM_OROM_CAPABILITIES_HDDUnlock (1 << 0)
	98	#define IMSM_OROM_CAPABILITIES_LEDLoc (1 << 1)
	99	#define IMSM_OROM_CAPABILITIES_EnterpriseSystem (1 << 2)
	100	#define IMSM_OROM_CAPABILITIES_Zpodd (1 << 3)
	101	#define IMSM_OROM_CAPABILITIES_LargeDramCache (1 << 4)
	102	#define IMSM_OROM_CAPABILITIES_Rohi (1 << 5)
	103	#define IMSM_OROM_CAPABILITIES_ReadPatrol (1 << 6)
	104	#define IMSM_OROM_CAPABILITIES_XorHw (1 << 7)
32716c51 PB	105	#define IMSM_OROM_CAPABILITIES_SKUMode ((1 << 8)\|(1 << 9))
32716c51 PB	106	#define IMSM_OROM_CAPABILITIES_TPV (1 << 10)
b390f610 DW	107	} __attribute__((packed));
b390f610 DW	108
88c32bb1 DW	109	static inline int imsm_orom_has_raid0(const struct imsm_orom *orom)
	110	{
	111	return !!(orom->rlc & IMSM_OROM_RLC_RAID0);
	112	}
	113	static inline int imsm_orom_has_raid1(const struct imsm_orom *orom)
	114	{
	115	return !!(orom->rlc & IMSM_OROM_RLC_RAID1);
	116	}
	117	static inline int imsm_orom_has_raid1e(const struct imsm_orom *orom)
	118	{
	119	return !!(orom->rlc & IMSM_OROM_RLC_RAID1E);
	120	}
	121	static inline int imsm_orom_has_raid10(const struct imsm_orom *orom)
	122	{
	123	return !!(orom->rlc & IMSM_OROM_RLC_RAID10);
	124	}
	125	static inline int imsm_orom_has_raid5(const struct imsm_orom *orom)
	126	{
	127	return !!(orom->rlc & IMSM_OROM_RLC_RAID5);
	128	}
	129
	130	/**
	131	* imsm_orom_has_chunk - check if the orom supports the given chunk size
	132	* @orom: orom pointer from find_imsm_orom
	133	* @chunk: chunk size in kibibytes
	134	*/
	135	static inline int imsm_orom_has_chunk(const struct imsm_orom *orom, int chunk)
	136	{
	137	int fs = ffs(chunk);
88c32bb1 DW	138	if (!fs)
	139	return 0;
	140	fs--; /* bit num to bit index */
70eb8219 HCP	141	if (chunk & (chunk-1))
	142	return 0; /* not a power of 2 */
	143	return !!(orom->sss & (1 << (fs - 1)));
88c32bb1 DW	144	}
88c32bb1 DW	145
0bd16cf2 DJ	146	/**
	147	* fls - find last (most-significant) bit set
	148	* @x: the word to search
	149	* The funciton is borrowed from Linux kernel code
	150	* include/asm-generic/bitops/fls.h
	151	*/
	152	static inline int fls(int x)
	153	{
	154	int r = 32;
	155
	156	if (!x)
	157	return 0;
	158	if (!(x & 0xffff0000u)) {
	159	x <<= 16;
	160	r -= 16;
	161	}
	162	if (!(x & 0xff000000u)) {
	163	x <<= 8;
	164	r -= 8;
	165	}
	166	if (!(x & 0xf0000000u)) {
	167	x <<= 4;
	168	r -= 4;
	169	}
	170	if (!(x & 0xc0000000u)) {
	171	x <<= 2;
	172	r -= 2;
	173	}
	174	if (!(x & 0x80000000u)) {
0bd16cf2 DJ	175	r -= 1;
	176	}
	177	return r;
	178	}
	179
0858eccf AP	180	static inline int imsm_orom_is_enterprise(const struct imsm_orom *orom)
	181	{
	182	return !!(orom->driver_features & IMSM_OROM_CAPABILITIES_EnterpriseSystem);
	183	}
	184
	185	static inline int imsm_orom_is_nvme(const struct imsm_orom *orom)
	186	{
	187	return memcmp(orom->signature, IMSM_NVME_OROM_COMPAT_SIGNATURE,
	188	sizeof(orom->signature)) == 0;
	189	}
	190
32716c51 PB	191	static inline int imsm_orom_has_tpv_support(const struct imsm_orom *orom)
	192	{
	193	return !!(orom->driver_features & IMSM_OROM_CAPABILITIES_TPV);
	194	}
	195
a8e5382a LM	196	enum sys_dev_type {
	197	SYS_DEV_UNKNOWN = 0,
	198	SYS_DEV_SAS,
	199	SYS_DEV_SATA,
614902f6	200	SYS_DEV_NVME,
60f0f54d	201	SYS_DEV_VMD,
75350d87	202	SYS_DEV_SATA_VMD,
a8e5382a LM	203	SYS_DEV_MAX
	204	};
	205
b390f610	206	struct sys_dev {
a8e5382a	207	enum sys_dev_type type;
b390f610	208	char *path;
a8e5382a	209	char *pci_id;
9c747fa0	210	__u16 dev_id;
6b781d33	211	__u32 class;
b390f610 DW	212	struct sys_dev *next;
	213	};
	214
1a901471 LM	215	struct efi_guid {
	216	__u8 b[16];
	217	};
	218
0858eccf AP	219	struct devid_list {
	220	__u16 devid;
	221	struct devid_list *next;
	222	};
	223
	224	struct orom_entry {
	225	struct imsm_orom orom;
	226	struct devid_list *devid_list;
60f0f54d	227	enum sys_dev_type type;
5e1d6128	228	struct orom_entry *next;
0858eccf AP	229	};
0858eccf AP	230
5e1d6128 AP	231	extern struct orom_entry *orom_entries;
5e1d6128 AP	232
1a901471 LM	233	static inline char guid_str(char buf, struct efi_guid guid)
1a901471 LM	234	{
5ccd457b	235	snprintf(buf, GUID_STR_MAX, "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x",
1a901471 LM	236	guid.b[3], guid.b[2], guid.b[1], guid.b[0],
	237	guid.b[5], guid.b[4], guid.b[7], guid.b[6],
	238	guid.b[8], guid.b[9], guid.b[10], guid.b[11],
	239	guid.b[12], guid.b[13], guid.b[14], guid.b[15]);
	240	return buf;
	241	}
	242
d835518b	243	char get_nvme_multipath_dev_hw_path(const char dev_path);
7c798f87	244	char diskfd_to_devpath(int fd, int dev_level, char buf);
fcebeb77 MT	245	int devpath_to_char(const char dev_path, const char entry, char *buf,
fcebeb77 MT	246	int len, int verbose);
60f0f54d	247	__u16 devpath_to_vendor(const char *dev_path);
b390f610	248	struct sys_dev find_driver_devices(const char bus, const char *driver);
a8e5382a	249	struct sys_dev *find_intel_devices(void);
6b781d33	250	const struct imsm_orom find_imsm_capability(struct sys_dev hba);
b390f610	251	const struct imsm_orom *find_imsm_orom(void);
25921536	252	int disk_attached_to_hba(int fd, const char *hba_path);
0c21b485	253	int devt_attached_to_hba(dev_t dev, const char *hba_path);
7c798f87	254	char devt_to_devpath(dev_t dev, int dev_level, char buf);
25921536	255	int path_attached_to_hba(const char disk_path, const char hba_path);
a8e5382a	256	const char *get_sys_dev_type(enum sys_dev_type);
72a45777	257	const struct orom_entry *get_orom_entry_by_device_id(__u16 dev_id);
6b781d33	258	const struct imsm_orom *get_orom_by_device_id(__u16 device_id);
0858eccf	259	struct sys_dev *device_by_id(__u16 device_id);
d3c11416	260	struct sys_dev device_by_id_and_path(__u16 device_id, const char path);
d835518b	261	int is_multipath_nvme(int disk_fd);
8662f92d	262	int imsm_is_nvme_namespace_supported(int disk_fd, int verbose);
60f0f54d	263	char vmd_domain_to_controller(struct sys_dev hba, char *buf);