projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 07490bf8 MF |
1 | 2021-06-19 Mike Frysinger <vapier@gentoo.org> |
| 2 | ||
| 3 | * configure: Regenerate. | |
| 4 | ||
| 47ce766a MF |
5 | 2021-06-18 Mike Frysinger <vapier@gentoo.org> |
| 6 | ||
| 7 | * aclocal.m4, configure: Regenerate. | |
| 8 | ||
| 982c3a65 MF |
9 | 2021-06-18 Mike Frysinger <vapier@gentoo.org> |
| 10 | ||
| 11 | * configure: Regenerate. | |
| 12 | ||
| 1fef66b0 MF |
13 | 2021-06-18 Mike Frysinger <vapier@gentoo.org> |
| 14 | ||
| 15 | * cpustate.c: Include sim-signal.h. | |
| 16 | * memory.c, simulator.c: Likewise. | |
| 17 | ||
| f9a4d543 MF |
18 | 2021-06-17 Mike Frysinger <vapier@gentoo.org> |
| 19 | ||
| 20 | * configure.ac: Delete SIM_AC_OPTION_ENDIAN call. | |
| 21 | * aclocal.m4, configure: Regenerate. | |
| 22 | ||
| a8a3d907 MF |
23 | 2021-06-16 Mike Frysinger <vapier@gentoo.org> |
| 24 | ||
| 25 | * configure: Regenerate. | |
| 26 | ||
| 52d37d2c MF |
27 | 2021-06-16 Mike Frysinger <vapier@gentoo.org> |
| 28 | ||
| 29 | * configure: Regenerate. | |
| 30 | * config.in: Removed. | |
| 31 | ||
| bcaa61f7 MF |
32 | 2021-06-15 Mike Frysinger <vapier@gentoo.org> |
| 33 | ||
| 34 | * config.in, configure: Regenerate. | |
| 35 | ||
| 82e6d6bf MF |
36 | 2021-06-14 Mike Frysinger <vapier@gentoo.org> |
| 37 | ||
| 38 | * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS. | |
| 39 | * configure: Regenerate. | |
| 40 | ||
| ba307cdd MF |
41 | 2021-06-12 Mike Frysinger <vapier@gentoo.org> |
| 42 | ||
| 43 | * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT. | |
| 44 | * interp.c (sim_open): Set current_alignment. | |
| 45 | ||
| dba333c1 MF |
46 | 2021-06-12 Mike Frysinger <vapier@gentoo.org> |
| 47 | ||
| 48 | * aclocal.m4, config.in, configure: Regenerate. | |
| 49 | ||
| b15c5d7a MF |
50 | 2021-06-12 Mike Frysinger <vapier@gentoo.org> |
| 51 | ||
| 52 | * config.in, configure: Regenerate. | |
| 53 | ||
| f4fdd845 MF |
54 | 2021-05-17 Mike Frysinger <vapier@gentoo.org> |
| 55 | ||
| 56 | * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete. | |
| 57 | ||
| 383861bd MF |
58 | 2021-05-17 Mike Frysinger <vapier@gentoo.org> |
| 59 | ||
| 60 | * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define. | |
| 61 | (struct sim_state): Delete. | |
| 62 | ||
| 6df01ab8 MF |
63 | 2021-05-16 Mike Frysinger <vapier@gentoo.org> |
| 64 | ||
| 65 | * cpustate.c: Include defs.h. | |
| 66 | * interp.c: Replace config.h include with defs.h. | |
| 67 | * memory.c, simulator.c: Likewise. | |
| 68 | * cpustate.h, simulator.h: Delete config.h include. | |
| 69 | ||
| 79633c12 MF |
70 | 2021-05-16 Mike Frysinger <vapier@gentoo.org> |
| 71 | ||
| 72 | * config.in, configure: Regenerate. | |
| 73 | ||
| df68e12b MF |
74 | 2021-05-14 Mike Frysinger <vapier@gentoo.org> |
| 75 | ||
| 76 | * cpustate.h: Update include path. | |
| 77 | * interp.c: Likewise. | |
| 78 | ||
| aa0fca16 MF |
79 | 2021-05-04 Mike Frysinger <vapier@gentoo.org> |
| 80 | ||
| 81 | * configure: Regenerate. | |
| 82 | ||
| fe348617 MF |
83 | 2021-05-01 Mike Frysinger <vapier@gentoo.org> |
| 84 | ||
| 85 | * config.in, configure: Regenerate. | |
| 86 | ||
| f1ca3215 MF |
87 | 2021-05-01 Mike Frysinger <vapier@gentoo.org> |
| 88 | ||
| 89 | * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64. | |
| 90 | (aarch64_set_FP_double, aarch64_set_FP_long_double, | |
| 91 | aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise. | |
| 92 | ||
| ce224813 MF |
93 | 2021-05-01 Mike Frysinger <vapier@gentoo.org> |
| 94 | ||
| 95 | * simulator.c (do_fcvtzu): Change UL to ULL. | |
| 96 | ||
| 66d055c7 MF |
97 | 2021-04-26 Mike Frysinger <vapier@gentoo.org> |
| 98 | ||
| 99 | * aclocal.m4, config.in, configure: Regenerate. | |
| 100 | ||
| 19f6a43c TT |
101 | 2021-04-22 Tom Tromey <tom@tromey.com> |
| 102 | ||
| 103 | * configure, config.in: Rebuild. | |
| 104 | ||
| efd82ac7 TT |
105 | 2021-04-22 Tom Tromey <tom@tromey.com> |
| 106 | ||
| 107 | * configure: Rebuild. | |
| 108 | ||
| 2662c237 MF |
109 | 2021-04-21 Mike Frysinger <vapier@gentoo.org> |
| 110 | ||
| 111 | * aclocal.m4: Regenerate. | |
| 112 | ||
| 1f195bc3 SM |
113 | 2021-04-21 Simon Marchi <simon.marchi@polymtl.ca> |
| 114 | ||
| 115 | * configure: Regenerate. | |
| 116 | ||
| 37e9f182 MF |
117 | 2021-04-18 Mike Frysinger <vapier@gentoo.org> |
| 118 | ||
| 119 | * configure: Regenerate. | |
| 120 | ||
| d5a71b11 MF |
121 | 2021-04-12 Mike Frysinger <vapier@gentoo.org> |
| 122 | ||
| 123 | * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all. | |
| 124 | ||
| 0592e80b JW |
125 | 2021-04-07 Jim Wilson <jimw@sifive.com> |
| 126 | ||
| 127 | PR sim/27483 | |
| 128 | * simulator.c (set_flags_for_add32): Compare uresult against | |
| 129 | itself. Compare sresult against itself. | |
| 130 | ||
| c2783492 MF |
131 | 2021-04-02 Mike Frysinger <vapier@gentoo.org> |
| 132 | ||
| 133 | * aclocal.m4, configure: Regenerate. | |
| 134 | ||
| ebe9564b MF |
135 | 2021-02-28 Mike Frysinger <vapier@gentoo.org> |
| 136 | ||
| 137 | * configure: Regenerate. | |
| 138 | ||
| 760b3e8b MF |
139 | 2021-02-21 Mike Frysinger <vapier@gentoo.org> |
| 140 | ||
| 141 | * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4. | |
| 142 | * aclocal.m4, configure: Regenerate. | |
| 143 | ||
| 136da8cd MF |
144 | 2021-02-13 Mike Frysinger <vapier@gentoo.org> |
| 145 | ||
| 146 | * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS. | |
| 147 | * aclocal.m4, configure: Regenerate. | |
| 148 | ||
| aa09469f MF |
149 | 2021-02-06 Mike Frysinger <vapier@gentoo.org> |
| 150 | ||
| 151 | * configure: Regenerate. | |
| 152 | ||
| 68ed2854 MF |
153 | 2021-01-11 Mike Frysinger <vapier@gentoo.org> |
| 154 | ||
| 155 | * config.in, configure: Regenerate. | |
| 156 | ||
| bf470982 MF |
157 | 2021-01-09 Mike Frysinger <vapier@gentoo.org> |
| 158 | ||
| 159 | * configure: Regenerate. | |
| 160 | ||
| 46f900c0 MF |
161 | 2021-01-08 Mike Frysinger <vapier@gentoo.org> |
| 162 | ||
| 163 | * configure: Regenerate. | |
| 164 | ||
| dfb856ba MF |
165 | 2021-01-04 Mike Frysinger <vapier@gentoo.org> |
| 166 | ||
| 167 | * configure: Regenerate. | |
| 168 | ||
| 69b1ffdb CB |
169 | 2020-02-06 Carlo Bramini <carlo_bramini@users.sourceforge.net> |
| 170 | ||
| 171 | PR sim/25318 | |
| 172 | * simulator.c (blr): Read destination register before calling | |
| 173 | aarch64_save_LR. | |
| 174 | ||
| cd5b6074 AB |
175 | 2019-03-28 Andrew Burgess <andrew.burgess@embecosm.com> |
| 176 | ||
| 177 | * cpustate.c: Add 'libiberty.h' include. | |
| 178 | * interp.c: Add 'sim-assert.h' include. | |
| 179 | ||
| 5c887dd5 JB |
180 | 2017-09-06 John Baldwin <jhb@FreeBSD.org> |
| 181 | ||
| 182 | * configure: Regenerate. | |
| 183 | ||
| bf155438 JW |
184 | 2017-04-22 Jim Wilson <jim.wilson@linaro.org> |
| 185 | ||
| 186 | * simulator.c (vec_load): Add M argument. Rewrite to iterate over | |
| 187 | registers based on structure size. | |
| 188 | (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load. | |
| 189 | (LD1_1): Replace with call to vec_load. | |
| 190 | (vec_store): Add new M argument. Rewrite to iterate over registers | |
| 191 | based on structure size. | |
| 192 | (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store. | |
| 193 | (ST1_1): Replace with call to vec_store. | |
| 194 | ||
| ae27d3fe JW |
195 | 2017-04-08 Jim Wilson <jim.wilson@linaro.org> |
| 196 | ||
| b630840c JW |
197 | * simulator.c (do_vec_FCVTL): New. |
| 198 | (do_vec_op1): Call do_vec_FCVTL. | |
| 199 | ||
| ae27d3fe JW |
200 | * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero, |
| 201 | do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New. | |
| 202 | (do_scalar_vec): Add calls to new functions. | |
| 203 | ||
| f1241682 JW |
204 | 2017-03-25 Jim Wilson <jim.wilson@linaro.org> |
| 205 | ||
| 206 | * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry | |
| 207 | flag check. | |
| 208 | ||
| 8ecbe595 JW |
209 | 2017-03-03 Jim Wilson <jim.wilson@linaro.org> |
| 210 | ||
| 211 | * simulator.c (mul64hi): Shift carry left by 32. | |
| 212 | (smulh): Change signum to negate. If negate, invert result, and add | |
| 213 | carry bit if low part of multiply result is zero. | |
| 214 | ||
| ac189e7b JW |
215 | 2017-02-25 Jim Wilson <jim.wilson@linaro.org> |
| 216 | ||
| 152e1e1b JW |
217 | * simulator.c (do_vec_SMOV_into_scalar): New. |
| 218 | (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar. | |
| 219 | Rewritten. | |
| 220 | (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted. | |
| 221 | (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call. Add | |
| 222 | do_vec_SMOV_into_scalar call. Delete do_vec_MOV_into_scalar and | |
| 223 | do_vec_UMOV calls. Add do_vec_UMOV_into_scalar call. | |
| 224 | ||
| ac189e7b JW |
225 | * simulator.c (popcount): New. |
| 226 | (do_vec_CNT): New. | |
| 227 | (do_vec_op1): Add do_vec_CNT call. | |
| 228 | ||
| 2e7e5e28 JW |
229 | 2017-02-19 Jim Wilson <jim.wilson@linaro.org> |
| 230 | ||
| 231 | * simulator.c (do_vec_ADDV): Mov val declaration inside each case, | |
| 232 | with type set to input type size. | |
| 233 | (do_vec_xtl): Change bias from 3 to 4 for byte case. | |
| 234 | ||
| e8f42b5e JW |
235 | 2017-02-14 Jim Wilson <jim.wilson@linaro.org> |
| 236 | ||
| 742e3a77 JW |
237 | * simulator.c (do_vec_MLA): Rewrite switch body. |
| 238 | ||
| bf25e9a0 JW |
239 | * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and |
| 240 | 2. Move test_false if inside loop. Fix logic for computing result | |
| 241 | stored to vd. | |
| 242 | ||
| e8f42b5e JW |
243 | * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. |
| 244 | (do_vec_LDn_single, do_vec_STn_single): New. | |
| 245 | (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with | |
| 246 | loop over nregs using new var n. Add n times size to address in loop. | |
| 247 | Add n to vd in loop. | |
| 248 | (do_vec_load_store): Add comment for instruction bit 24. New var | |
| 249 | single to hold instruction bit 24. Add new code to use single. Move | |
| 250 | ldnr support inside single if statements. Fix ldnr register counts | |
| 251 | inside post if statement. Change HALT_NYI calls to HALT_UNALLOC. | |
| 252 | ||
| fbf32f63 JW |
253 | 2017-01-23 Jim Wilson <jim.wilson@linaro.org> |
| 254 | ||
| 255 | * simulator.c (do_vec_compare): Add case 0x23 for CMTST. | |
| 256 | ||
| 05b3d79d JW |
257 | 2017-01-17 Jim Wilson <jim.wilson@linaro.org> |
| 258 | ||
| 259 | * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of | |
| 260 | aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In | |
| 261 | case 3, call HALT_UNALLOC unconditionally. | |
| 262 | (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to | |
| 263 | i + 2. Delete if on bias, change index to i + bias * X. | |
| 264 | ||
| a4fb5981 JW |
265 | 2017-01-09 Jim Wilson <jim.wilson@linaro.org> |
| 266 | ||
| 267 | * simulator.c (do_vec_UZP): Rewrite. | |
| 268 | ||
| c0386d4d JW |
269 | 2017-01-04 Jim Wilson <jim.wilson@linaro.org> |
| 270 | ||
| 271 | * cpustate.c: Include math.h. | |
| 272 | (aarch64_set_FP_float): Use signbit to check for signed zero. | |
| 273 | (aarch64_set_FP_double): Likewise. | |
| 274 | * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. | |
| 275 | (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth | |
| 276 | args same size as third arg. | |
| 277 | (fmaxnm): Use isnan instead of fpclassify. | |
| 278 | (fminnm, dmaxnm, dminnm): Likewise. | |
| 279 | (do_vec_MLS): Reverse order of subtraction operands. | |
| 280 | (dexSimpleFPCondSelect): Call aarch64_get_FP_double or | |
| 281 | aarch64_get_FP_float to get source register contents. | |
| 282 | (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN, | |
| 283 | DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN, | |
| 284 | DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New. | |
| 285 | (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in | |
| 286 | raise_exception calls. | |
| 287 | ||
| 87903eaf JW |
288 | 2016-12-21 Jim Wilson <jim.wilson@linaro.org> |
| 289 | ||
| 290 | * simulator.c (set_flags_for_float_compare): Add code to handle Inf. | |
| 291 | Add comment to document NaN issue. | |
| 292 | (set_flags_for_double_compare): Likewise. | |
| 293 | ||
| 963201cf JW |
294 | 2016-12-13 Jim Wilson <jim.wilson@linaro.org> |
| 295 | ||
| 296 | * simulator.c (NEG, POS): Move before set_flags_for_add64. | |
| 297 | (set_flags_for_add64): Replace with a modified copy of | |
| 298 | set_flags_for_sub64. | |
| 299 | ||
| 668650d5 JW |
300 | 2016-12-03 Jim Wilson <jim.wilson@linaro.org> |
| 301 | ||
| 302 | * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. | |
| 303 | (dexTestBranchImmediate): Shift high bit of pos by 5 not 4. | |
| 304 | ||
| 88ddd4a1 JW |
305 | 2016-12-01 Jim Wilson <jim.wilson@linaro.org> |
| 306 | ||
| 88256e71 | 307 | * simulator.c (fsturs): Switch use of rn and st variables. |
| 88ddd4a1 JW |
308 | (fsturd, fsturq): Likewise |
| 309 | ||
| 5357150c MF |
310 | 2016-08-15 Mike Frysinger <vapier@gentoo.org> |
| 311 | ||
| 312 | * interp.c: Include bfd.h. | |
| 313 | (symcount, symtab, aarch64_get_sym_value): Delete. | |
| 314 | (remove_useless_symbols): Change count type to long. | |
| 315 | (aarch64_get_func): Add SIM_DESC to arg list. Add symcount | |
| 316 | and symtab local variables. | |
| 317 | (sim_create_inferior): Delete storage. Replace symbol code | |
| 318 | with a call to trace_load_symbols. | |
| 319 | * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h | |
| 320 | includes. | |
| 321 | (aarch64_get_heap_start): Change aarch64_get_sym_value to | |
| 322 | trace_sym_value. | |
| 323 | * memory.h: Delete bfd.h include. | |
| 324 | (mem_add_blk): Delete unused prototype. | |
| 325 | * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func. | |
| 326 | * simulator.c (aarch64_get_func): Add SIM_DESC to arg list. | |
| 327 | (aarch64_get_sym_value): Delete. | |
| 328 | ||
| b14bdb3b NC |
329 | 2016-08-12 Nick Clifton <nickc@redhat.com> |
| 330 | ||
| 331 | * simulator.c (aarch64_step): Revert pervious delta. | |
| 332 | (aarch64_run): Call sim_events_tick after each | |
| 333 | instruction is simulated, and if necessary call | |
| 334 | sim_events_process. | |
| 335 | * simulator.h: Revert previous delta. | |
| 336 | ||
| 6a277579 NC |
337 | 2016-08-11 Nick Clifton <nickc@redhat.com> |
| 338 | ||
| 339 | * interp.c (sim_create_inferior): Allow for being called with a | |
| 340 | NULL abfd parameter. If a bfd is provided, initialise the sim | |
| 341 | with that start address. | |
| 342 | * simulator.c (HALT_NYI): Just print out the numeric value of the | |
| 343 | instruction when not tracing. | |
| b14bdb3b NC |
344 | (aarch64_step): Change from static to global. |
| 345 | * simulator.h: Add a prototype for aarch64_step(). | |
| 6a277579 | 346 | |
| 293acfae AM |
347 | 2016-07-27 Alan Modra <amodra@gmail.com> |
| 348 | ||
| 349 | * memory.c: Don't include libbfd.h. | |
| 350 | ||
| 0f118bc7 NC |
351 | 2016-07-21 Nick Clifton <nickc@redhat.com> |
| 352 | ||
| 0c66ea4c | 353 | * simulator.c (fsqrts): Use sqrtf rather than sqrt. |
| 0f118bc7 | 354 | |
| c7be4414 JW |
355 | 2016-06-30 Jim Wilson <jim.wilson@linaro.org> |
| 356 | ||
| 357 | * cpustate.h: Include config.h. | |
| 358 | (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code | |
| 359 | use anonymous structs to align members. | |
| 360 | * simulator.c (aarch64_step): Use sim_core_read_buffer and | |
| 361 | endian_le2h_4 to read instruction from pc. | |
| 362 | ||
| fd7ed446 NC |
363 | 2016-05-06 Nick Clifton <nickc@redhat.com> |
| 364 | ||
| 365 | * simulator.c (do_FMLA_by_element): New function. | |
| 366 | (do_vec_op2): Call it. | |
| 367 | ||
| 2cdad34c NC |
368 | 2016-04-27 Nick Clifton <nickc@redhat.com> |
| 369 | ||
| 370 | * simulator.c: Add TRACE_DECODE statements to all emulation | |
| 371 | functions. | |
| 372 | ||
| 7517e550 NC |
373 | 2016-03-30 Nick Clifton <nickc@redhat.com> |
| 374 | ||
| 375 | * cpustate.c (aarch64_set_reg_s32): New function. | |
| 376 | (aarch64_set_reg_u32): New function. | |
| 377 | (aarch64_get_FP_half): Place half precision value into the correct | |
| 378 | slot of the union. | |
| 379 | (aarch64_set_FP_half): Likewise. | |
| 380 | * cpustate.h: Add prototypes for aarch64_set_reg_s32 and | |
| 381 | aarch64_set_reg_u32. | |
| 382 | * memory.c (FETCH_FUNC): Cast the read value to the access type | |
| 383 | before converting it to the return type. Rename to FETCH_FUNC64. | |
| 384 | (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit | |
| 385 | accesses. Use for 32-bit memory access functions. | |
| 386 | * simulator.c (ldrsb_wb): Use sign extension not zero extension. | |
| 387 | (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. | |
| 388 | (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. | |
| 389 | (ldrsh_scale_ext, ldrsw_abs): Likewise. | |
| 390 | (ldrh32_abs): Store 32 bit value not 64-bits. | |
| 391 | (ldrh32_wb, ldrh32_scale_ext): Likewise. | |
| 392 | (do_vec_MOV_immediate): Fix computation of val. | |
| 393 | (do_vec_MVNI): Likewise. | |
| 394 | (DO_VEC_WIDENING_MUL): New macro. | |
| 395 | (do_vec_mull): Use new macro. | |
| 396 | (do_vec_mul): Use new macro. | |
| 397 | (do_vec_MLA): Read values before writing. | |
| 398 | (do_vec_xtl): Likewise. | |
| 399 | (do_vec_SSHL): Select correct shift value. | |
| 400 | (do_vec_USHL): Likewise. | |
| 401 | (do_scalar_UCVTF): New function. | |
| 402 | (do_scalar_vec): Call new function. | |
| 403 | (store_pair_u64): Treat reads of SP as reads of XZR. | |
| 404 | ||
| ef0d8ffc NC |
405 | 2016-03-29 Nick Clifton <nickc@redhat.com> |
| 406 | ||
| 407 | * cpustate.c: Remove space after asterisk in function parameters. | |
| 408 | * decode.h (greg): Delete unused function. | |
| 409 | (vreg, shift, extension, scaling, writeback, condcode): Likewise. | |
| 410 | * simulator.c: Use INSTR macro in more places. | |
| 411 | (HALT_NYI): Use sim_io_eprintf in place of fprintf. | |
| 412 | Remove extraneous whitespace. | |
| 413 | ||
| 5ab6d79e NC |
414 | 2016-03-23 Nick Clifton <nickc@redhat.com> |
| 415 | ||
| 416 | * cpustate.c (aarch64_get_FP_half): New function. Read a vector | |
| 417 | register as a half precision floating point number. | |
| 418 | (aarch64_set_FP_half): New function. Similar, but for setting | |
| 419 | a half precision register. | |
| 420 | (aarch64_get_thread_id): New function. Returns the value of the | |
| 421 | CPU's TPIDR register. | |
| 422 | (aarch64_get_FPCR): New function. Returns the value of the CPU's | |
| 423 | floating point control register. | |
| 424 | (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR | |
| 425 | register. | |
| 426 | * cpustate.h: Add prototypes for new functions. | |
| 427 | * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. | |
| 428 | * memory.c: Use unaligned core access functions for all memory | |
| 429 | reads and writes. | |
| 430 | * simulator.c (HALT_NYI): Generate an error message if tracing | |
| 431 | will not tell the user why the simulator is halting. | |
| 432 | (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. | |
| 433 | (INSTR): New time-saver macro. | |
| 434 | (fldrb_abs): New function. Loads an 8-bit value using a scaled | |
| 435 | offset. | |
| 436 | (fldrh_abs): New function. Likewise for 16-bit values. | |
| 437 | (do_vec_SSHL): Allow for negative shift values. | |
| 438 | (do_vec_USHL): Likewise. | |
| 439 | (do_vec_SHL): Correct computation of shift amount. | |
| 440 | (do_vec_SSHR_USHR): Correct decision of signed vs unsigned | |
| 441 | shifts and computation of shift value. | |
| 442 | (clz): New function. Counts leading zero bits. | |
| 443 | (do_vec_CLZ): New function. Implements CLZ (vector). | |
| 444 | (do_vec_MOV_element): Call do_vec_CLZ. | |
| 445 | (dexSimpleFPCondCompare): Implement. | |
| 446 | (do_FCVT_half_to_single): New function. Implements one of the | |
| 447 | FCVT operations. | |
| 448 | (do_FCVT_half_to_double): New function. Likewise. | |
| 449 | (do_FCVT_single_to_half): New function. Likewise. | |
| 450 | (do_FCVT_double_to_half): New function. Likewise. | |
| 451 | (dexSimpleFPDataProc1Source): Call new FCVT functions. | |
| 452 | (do_scalar_SHL): Handle negative shifts. | |
| 453 | (do_scalar_shift): Handle SSHR. | |
| 454 | (do_scalar_USHL): New function. | |
| 455 | (do_double_add): Simplify to just performing a double precision | |
| 456 | add operation. Move remaining code into... | |
| 457 | (do_scalar_vec): ... New function. | |
| 458 | (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs | |
| 459 | functions. | |
| 460 | (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR | |
| 461 | registers. | |
| 462 | (system_set): New function. | |
| 463 | (do_MSR_immediate): New function. Stub for now. | |
| 464 | (do_MSR_reg): New function. Likewise. Partially implements MSR | |
| 465 | instruction. | |
| 466 | (do_SYS): New function. Stub for now, | |
| 467 | (dexSystem): Call new functions. | |
| 468 | ||
| e101a78b NC |
469 | 2016-03-18 Nick Clifton <nickc@redhat.com> |
| 470 | ||
| 471 | * cpustate.c: Remove spurious spaces from TRACE strings. | |
| 472 | Print hex equivalents of floats and doubles. | |
| 473 | Check element number against array size when accessing vector | |
| 474 | registers. | |
| 4c0ca98e NC |
475 | (GET_VEC_ELEMENT): Fix off by one error checking for an invalid |
| 476 | element index. | |
| 477 | (SET_VEC_ELEMENT): Likewise. | |
| 87bba7a5 | 478 | (GET_VEC_ELEMENT): And fix thinko using macro arguments. |
| 4c0ca98e | 479 | |
| e101a78b NC |
480 | * memory.c: Trace memory reads when --trace-memory is enabled. |
| 481 | Remove float and double load and store functions. | |
| 482 | * memory.h (aarch64_get_mem_float): Delete prototype. | |
| 483 | (aarch64_get_mem_double): Likewise. | |
| 484 | (aarch64_set_mem_float): Likewise. | |
| 485 | (aarch64_set_mem_double): Likewise. | |
| 486 | * simulator (IS_SET): Always return either 0 or 1. | |
| 487 | (IS_CLEAR): Likewise. | |
| 488 | (fldrs_pcrel): Load and store floats using 32-bit memory accesses | |
| 489 | and doubles using 64-bit memory accesses. | |
| 490 | (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. | |
| 491 | (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. | |
| 492 | (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. | |
| 493 | (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. | |
| 494 | (store_pair_double, load_pair_float, load_pair_double): Likewise. | |
| 495 | (do_vec_MUL_by_element): New function. | |
| 496 | (do_vec_op2): Call do_vec_MUL_by_element. | |
| 497 | (do_scalar_NEG): New function. | |
| 498 | (do_double_add): Call do_scalar_NEG. | |
| 499 | ||
| 57aa1742 NC |
500 | 2016-03-03 Nick Clifton <nickc@redhat.com> |
| 501 | ||
| 502 | * simulator.c (set_flags_for_sub32): Correct type of signbit. | |
| 503 | (CondCompare): Swap interpretation of bit 30. | |
| 504 | (DO_ADDP): Delete macro. | |
| 505 | (do_vec_ADDP): Copy source registers before starting to update | |
| 506 | destination register. | |
| 507 | (do_vec_FADDP): Likewise. | |
| 508 | (do_vec_load_store): Fix computation of sizeof_operation. | |
| 509 | (rbit64): Fix type of constant. | |
| 510 | (aarch64_step): When displaying insn value, display all 32 bits. | |
| 511 | ||
| ce39bd38 MF |
512 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 513 | ||
| 514 | * config.in, configure: Regenerate. | |
| 515 | ||
| e19418e0 MF |
516 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 517 | ||
| 518 | * configure: Regenerate. | |
| 519 | ||
| 16f7876d MF |
520 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 521 | ||
| 522 | * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call. | |
| 523 | * configure: Regenerate. | |
| 524 | ||
| 99d8e879 MF |
525 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 526 | ||
| 527 | * configure: Regenerate. | |
| 35656e95 MF |
528 | |
| 529 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> | |
| 530 | ||
| 531 | * configure: Regenerate. | |
| 99d8e879 | 532 | |
| 347fe5bb MF |
533 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 534 | ||
| 535 | * configure.ac (SIM_AC_OPTION_INLINE): Delete call. | |
| 536 | * configure: Regenerate. | |
| 537 | ||
| 22be3fbe MF |
538 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 539 | ||
| 540 | * configure: Regenerate. | |
| 541 | ||
| 0dc73ef7 MF |
542 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| 543 | ||
| 544 | * configure: Regenerate. | |
| 545 | ||
| 936df756 MF |
546 | 2016-01-09 Mike Frysinger <vapier@gentoo.org> |
| 547 | ||
| 548 | * config.in, configure: Regenerate. | |
| 549 | ||
| 2e3d4f4d MF |
550 | 2016-01-06 Mike Frysinger <vapier@gentoo.org> |
| 551 | ||
| 552 | * interp.c (sim_create_inferior): Mark argv and env const. | |
| 553 | (sim_open): Mark argv const. | |
| 554 | ||
| 1a846c62 MF |
555 | 2016-01-05 Mike Frysinger <vapier@gentoo.org> |
| 556 | ||
| 557 | * interp.c: Delete dis-asm.h include. | |
| 558 | (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete. | |
| 559 | (sim_create_inferior): Delete disassemble init logic. | |
| 560 | (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete. | |
| 561 | (sim_open): Delete sim_add_option_table call. | |
| 562 | * memory.c (mem_error): Delete disas check. | |
| 563 | * simulator.c: Delete dis-asm.h include. | |
| 564 | (disas): Delete. | |
| 565 | (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM. | |
| 566 | (HALT_NYI): Likewise. | |
| 567 | (handle_halt): Delete disas call. | |
| 568 | (aarch64_step): Replace disas logic with TRACE_DISASM. | |
| 569 | * simulator.h: Delete dis-asm.h include. | |
| 570 | (aarch64_print_insn): Delete. | |
| 571 | ||
| bc273e17 MF |
572 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
| 573 | ||
| 574 | * simulator.c (MAX, MIN): Delete. | |
| 575 | (do_vec_maxv): Change MAX to max and MIN to min. | |
| 576 | (do_vec_fminmaxV): Likewise. | |
| 577 | ||
| ac8eefeb TG |
578 | 2016-01-04 Tristan Gingold <gingold@adacore.com> |
| 579 | ||
| 580 | * simulator.c: Remove syscall.h include. | |
| 581 | ||
| 9bbf6f91 MF |
582 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
| 583 | ||
| 584 | * configure: Regenerate. | |
| 585 | ||
| 0cb8d851 MF |
586 | 2016-01-03 Mike Frysinger <vapier@gentoo.org> |
| 587 | ||
| 588 | * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete. | |
| 589 | * configure: Regenerate. | |
| 590 | ||
| 1ac72f06 MF |
591 | 2016-01-02 Mike Frysinger <vapier@gentoo.org> |
| 592 | ||
| 593 | * configure: Regenerate. | |
| 594 | ||
| 5d015275 MF |
595 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
| 596 | ||
| 597 | * interp.c (sim_dis_read): Change private_data to application_data. | |
| 598 | (sim_create_inferior): Likewise. | |
| 599 | ||
| 5e744ef8 MF |
600 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
| 601 | ||
| 602 | * Makefile.in (SIM_OBJS): Delete sim-hload.o. | |
| 603 | ||
| 1b393626 MF |
604 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
| 605 | ||
| 606 | * config.in, configure: Regenerate. | |
| 607 | ||
| 0e967299 MF |
608 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
| 609 | ||
| 610 | * interp.c (sim_create_inferior): Update comment and argv check. | |
| 611 | ||
| f66affe9 MF |
612 | 2015-12-14 Nick Clifton <nickc@redhat.com> |
| 613 | ||
| 614 | * simulator.c (system_get): New function. Provides read | |
| 615 | access to the dczid system register. | |
| 616 | (do_mrs): New function - implements the MRS instruction. | |
| 617 | (dexSystem): Call do_mrs for the MRS instruction. Halt on | |
| 618 | unimplemented system instructions. | |
| 619 | ||
| 620 | 2015-11-24 Nick Clifton <nickc@redhat.com> | |
| 621 | ||
| 622 | * configure.ac: New configure template. | |
| 623 | * aclocal.m4: Generate. | |
| 624 | * config.in: Generate. | |
| 625 | * configure: Generate. | |
| 626 | * cpustate.c: New file - functions for accessing AArch64 registers. | |
| 627 | * cpustate.h: New header. | |
| 628 | * decode.h: New header. | |
| 629 | * interp.c: New file - interface between GDB and simulator. | |
| 630 | * Makefile.in: New makefile template. | |
| 631 | * memory.c: New file - functions for simulating aarch64 memory | |
| 632 | accesses. | |
| 633 | * memory.h: New header. | |
| 634 | * sim-main.h: New header. | |
| 635 | * simulator.c: New file - aarch64 simulator functions. | |
| 636 | * simulator.h: New header. |