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Commit | Line | Data |
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136da8cd MF |
1 | 2021-02-13 Mike Frysinger <vapier@gentoo.org> |
2 | ||
3 | * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS. | |
4 | * aclocal.m4, configure: Regenerate. | |
5 | ||
aa09469f MF |
6 | 2021-02-06 Mike Frysinger <vapier@gentoo.org> |
7 | ||
8 | * configure: Regenerate. | |
9 | ||
68ed2854 MF |
10 | 2021-01-11 Mike Frysinger <vapier@gentoo.org> |
11 | ||
12 | * config.in, configure: Regenerate. | |
13 | ||
bf470982 MF |
14 | 2021-01-09 Mike Frysinger <vapier@gentoo.org> |
15 | ||
16 | * configure: Regenerate. | |
17 | ||
46f900c0 MF |
18 | 2021-01-08 Mike Frysinger <vapier@gentoo.org> |
19 | ||
20 | * configure: Regenerate. | |
21 | ||
dfb856ba MF |
22 | 2021-01-04 Mike Frysinger <vapier@gentoo.org> |
23 | ||
24 | * configure: Regenerate. | |
25 | ||
69b1ffdb CB |
26 | 2020-02-06 Carlo Bramini <carlo_bramini@users.sourceforge.net> |
27 | ||
28 | PR sim/25318 | |
29 | * simulator.c (blr): Read destination register before calling | |
30 | aarch64_save_LR. | |
31 | ||
cd5b6074 AB |
32 | 2019-03-28 Andrew Burgess <andrew.burgess@embecosm.com> |
33 | ||
34 | * cpustate.c: Add 'libiberty.h' include. | |
35 | * interp.c: Add 'sim-assert.h' include. | |
36 | ||
5c887dd5 JB |
37 | 2017-09-06 John Baldwin <jhb@FreeBSD.org> |
38 | ||
39 | * configure: Regenerate. | |
40 | ||
bf155438 JW |
41 | 2017-04-22 Jim Wilson <jim.wilson@linaro.org> |
42 | ||
43 | * simulator.c (vec_load): Add M argument. Rewrite to iterate over | |
44 | registers based on structure size. | |
45 | (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load. | |
46 | (LD1_1): Replace with call to vec_load. | |
47 | (vec_store): Add new M argument. Rewrite to iterate over registers | |
48 | based on structure size. | |
49 | (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store. | |
50 | (ST1_1): Replace with call to vec_store. | |
51 | ||
ae27d3fe JW |
52 | 2017-04-08 Jim Wilson <jim.wilson@linaro.org> |
53 | ||
b630840c JW |
54 | * simulator.c (do_vec_FCVTL): New. |
55 | (do_vec_op1): Call do_vec_FCVTL. | |
56 | ||
ae27d3fe JW |
57 | * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero, |
58 | do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New. | |
59 | (do_scalar_vec): Add calls to new functions. | |
60 | ||
f1241682 JW |
61 | 2017-03-25 Jim Wilson <jim.wilson@linaro.org> |
62 | ||
63 | * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry | |
64 | flag check. | |
65 | ||
8ecbe595 JW |
66 | 2017-03-03 Jim Wilson <jim.wilson@linaro.org> |
67 | ||
68 | * simulator.c (mul64hi): Shift carry left by 32. | |
69 | (smulh): Change signum to negate. If negate, invert result, and add | |
70 | carry bit if low part of multiply result is zero. | |
71 | ||
ac189e7b JW |
72 | 2017-02-25 Jim Wilson <jim.wilson@linaro.org> |
73 | ||
152e1e1b JW |
74 | * simulator.c (do_vec_SMOV_into_scalar): New. |
75 | (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar. | |
76 | Rewritten. | |
77 | (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted. | |
78 | (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call. Add | |
79 | do_vec_SMOV_into_scalar call. Delete do_vec_MOV_into_scalar and | |
80 | do_vec_UMOV calls. Add do_vec_UMOV_into_scalar call. | |
81 | ||
ac189e7b JW |
82 | * simulator.c (popcount): New. |
83 | (do_vec_CNT): New. | |
84 | (do_vec_op1): Add do_vec_CNT call. | |
85 | ||
2e7e5e28 JW |
86 | 2017-02-19 Jim Wilson <jim.wilson@linaro.org> |
87 | ||
88 | * simulator.c (do_vec_ADDV): Mov val declaration inside each case, | |
89 | with type set to input type size. | |
90 | (do_vec_xtl): Change bias from 3 to 4 for byte case. | |
91 | ||
e8f42b5e JW |
92 | 2017-02-14 Jim Wilson <jim.wilson@linaro.org> |
93 | ||
742e3a77 JW |
94 | * simulator.c (do_vec_MLA): Rewrite switch body. |
95 | ||
bf25e9a0 JW |
96 | * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and |
97 | 2. Move test_false if inside loop. Fix logic for computing result | |
98 | stored to vd. | |
99 | ||
e8f42b5e JW |
100 | * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. |
101 | (do_vec_LDn_single, do_vec_STn_single): New. | |
102 | (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with | |
103 | loop over nregs using new var n. Add n times size to address in loop. | |
104 | Add n to vd in loop. | |
105 | (do_vec_load_store): Add comment for instruction bit 24. New var | |
106 | single to hold instruction bit 24. Add new code to use single. Move | |
107 | ldnr support inside single if statements. Fix ldnr register counts | |
108 | inside post if statement. Change HALT_NYI calls to HALT_UNALLOC. | |
109 | ||
fbf32f63 JW |
110 | 2017-01-23 Jim Wilson <jim.wilson@linaro.org> |
111 | ||
112 | * simulator.c (do_vec_compare): Add case 0x23 for CMTST. | |
113 | ||
05b3d79d JW |
114 | 2017-01-17 Jim Wilson <jim.wilson@linaro.org> |
115 | ||
116 | * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of | |
117 | aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In | |
118 | case 3, call HALT_UNALLOC unconditionally. | |
119 | (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to | |
120 | i + 2. Delete if on bias, change index to i + bias * X. | |
121 | ||
a4fb5981 JW |
122 | 2017-01-09 Jim Wilson <jim.wilson@linaro.org> |
123 | ||
124 | * simulator.c (do_vec_UZP): Rewrite. | |
125 | ||
c0386d4d JW |
126 | 2017-01-04 Jim Wilson <jim.wilson@linaro.org> |
127 | ||
128 | * cpustate.c: Include math.h. | |
129 | (aarch64_set_FP_float): Use signbit to check for signed zero. | |
130 | (aarch64_set_FP_double): Likewise. | |
131 | * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. | |
132 | (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth | |
133 | args same size as third arg. | |
134 | (fmaxnm): Use isnan instead of fpclassify. | |
135 | (fminnm, dmaxnm, dminnm): Likewise. | |
136 | (do_vec_MLS): Reverse order of subtraction operands. | |
137 | (dexSimpleFPCondSelect): Call aarch64_get_FP_double or | |
138 | aarch64_get_FP_float to get source register contents. | |
139 | (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN, | |
140 | DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN, | |
141 | DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New. | |
142 | (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in | |
143 | raise_exception calls. | |
144 | ||
87903eaf JW |
145 | 2016-12-21 Jim Wilson <jim.wilson@linaro.org> |
146 | ||
147 | * simulator.c (set_flags_for_float_compare): Add code to handle Inf. | |
148 | Add comment to document NaN issue. | |
149 | (set_flags_for_double_compare): Likewise. | |
150 | ||
963201cf JW |
151 | 2016-12-13 Jim Wilson <jim.wilson@linaro.org> |
152 | ||
153 | * simulator.c (NEG, POS): Move before set_flags_for_add64. | |
154 | (set_flags_for_add64): Replace with a modified copy of | |
155 | set_flags_for_sub64. | |
156 | ||
668650d5 JW |
157 | 2016-12-03 Jim Wilson <jim.wilson@linaro.org> |
158 | ||
159 | * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. | |
160 | (dexTestBranchImmediate): Shift high bit of pos by 5 not 4. | |
161 | ||
88ddd4a1 JW |
162 | 2016-12-01 Jim Wilson <jim.wilson@linaro.org> |
163 | ||
88256e71 | 164 | * simulator.c (fsturs): Switch use of rn and st variables. |
88ddd4a1 JW |
165 | (fsturd, fsturq): Likewise |
166 | ||
5357150c MF |
167 | 2016-08-15 Mike Frysinger <vapier@gentoo.org> |
168 | ||
169 | * interp.c: Include bfd.h. | |
170 | (symcount, symtab, aarch64_get_sym_value): Delete. | |
171 | (remove_useless_symbols): Change count type to long. | |
172 | (aarch64_get_func): Add SIM_DESC to arg list. Add symcount | |
173 | and symtab local variables. | |
174 | (sim_create_inferior): Delete storage. Replace symbol code | |
175 | with a call to trace_load_symbols. | |
176 | * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h | |
177 | includes. | |
178 | (aarch64_get_heap_start): Change aarch64_get_sym_value to | |
179 | trace_sym_value. | |
180 | * memory.h: Delete bfd.h include. | |
181 | (mem_add_blk): Delete unused prototype. | |
182 | * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func. | |
183 | * simulator.c (aarch64_get_func): Add SIM_DESC to arg list. | |
184 | (aarch64_get_sym_value): Delete. | |
185 | ||
b14bdb3b NC |
186 | 2016-08-12 Nick Clifton <nickc@redhat.com> |
187 | ||
188 | * simulator.c (aarch64_step): Revert pervious delta. | |
189 | (aarch64_run): Call sim_events_tick after each | |
190 | instruction is simulated, and if necessary call | |
191 | sim_events_process. | |
192 | * simulator.h: Revert previous delta. | |
193 | ||
6a277579 NC |
194 | 2016-08-11 Nick Clifton <nickc@redhat.com> |
195 | ||
196 | * interp.c (sim_create_inferior): Allow for being called with a | |
197 | NULL abfd parameter. If a bfd is provided, initialise the sim | |
198 | with that start address. | |
199 | * simulator.c (HALT_NYI): Just print out the numeric value of the | |
200 | instruction when not tracing. | |
b14bdb3b NC |
201 | (aarch64_step): Change from static to global. |
202 | * simulator.h: Add a prototype for aarch64_step(). | |
6a277579 | 203 | |
293acfae AM |
204 | 2016-07-27 Alan Modra <amodra@gmail.com> |
205 | ||
206 | * memory.c: Don't include libbfd.h. | |
207 | ||
0f118bc7 NC |
208 | 2016-07-21 Nick Clifton <nickc@redhat.com> |
209 | ||
0c66ea4c | 210 | * simulator.c (fsqrts): Use sqrtf rather than sqrt. |
0f118bc7 | 211 | |
c7be4414 JW |
212 | 2016-06-30 Jim Wilson <jim.wilson@linaro.org> |
213 | ||
214 | * cpustate.h: Include config.h. | |
215 | (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code | |
216 | use anonymous structs to align members. | |
217 | * simulator.c (aarch64_step): Use sim_core_read_buffer and | |
218 | endian_le2h_4 to read instruction from pc. | |
219 | ||
fd7ed446 NC |
220 | 2016-05-06 Nick Clifton <nickc@redhat.com> |
221 | ||
222 | * simulator.c (do_FMLA_by_element): New function. | |
223 | (do_vec_op2): Call it. | |
224 | ||
2cdad34c NC |
225 | 2016-04-27 Nick Clifton <nickc@redhat.com> |
226 | ||
227 | * simulator.c: Add TRACE_DECODE statements to all emulation | |
228 | functions. | |
229 | ||
7517e550 NC |
230 | 2016-03-30 Nick Clifton <nickc@redhat.com> |
231 | ||
232 | * cpustate.c (aarch64_set_reg_s32): New function. | |
233 | (aarch64_set_reg_u32): New function. | |
234 | (aarch64_get_FP_half): Place half precision value into the correct | |
235 | slot of the union. | |
236 | (aarch64_set_FP_half): Likewise. | |
237 | * cpustate.h: Add prototypes for aarch64_set_reg_s32 and | |
238 | aarch64_set_reg_u32. | |
239 | * memory.c (FETCH_FUNC): Cast the read value to the access type | |
240 | before converting it to the return type. Rename to FETCH_FUNC64. | |
241 | (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit | |
242 | accesses. Use for 32-bit memory access functions. | |
243 | * simulator.c (ldrsb_wb): Use sign extension not zero extension. | |
244 | (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. | |
245 | (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. | |
246 | (ldrsh_scale_ext, ldrsw_abs): Likewise. | |
247 | (ldrh32_abs): Store 32 bit value not 64-bits. | |
248 | (ldrh32_wb, ldrh32_scale_ext): Likewise. | |
249 | (do_vec_MOV_immediate): Fix computation of val. | |
250 | (do_vec_MVNI): Likewise. | |
251 | (DO_VEC_WIDENING_MUL): New macro. | |
252 | (do_vec_mull): Use new macro. | |
253 | (do_vec_mul): Use new macro. | |
254 | (do_vec_MLA): Read values before writing. | |
255 | (do_vec_xtl): Likewise. | |
256 | (do_vec_SSHL): Select correct shift value. | |
257 | (do_vec_USHL): Likewise. | |
258 | (do_scalar_UCVTF): New function. | |
259 | (do_scalar_vec): Call new function. | |
260 | (store_pair_u64): Treat reads of SP as reads of XZR. | |
261 | ||
ef0d8ffc NC |
262 | 2016-03-29 Nick Clifton <nickc@redhat.com> |
263 | ||
264 | * cpustate.c: Remove space after asterisk in function parameters. | |
265 | * decode.h (greg): Delete unused function. | |
266 | (vreg, shift, extension, scaling, writeback, condcode): Likewise. | |
267 | * simulator.c: Use INSTR macro in more places. | |
268 | (HALT_NYI): Use sim_io_eprintf in place of fprintf. | |
269 | Remove extraneous whitespace. | |
270 | ||
5ab6d79e NC |
271 | 2016-03-23 Nick Clifton <nickc@redhat.com> |
272 | ||
273 | * cpustate.c (aarch64_get_FP_half): New function. Read a vector | |
274 | register as a half precision floating point number. | |
275 | (aarch64_set_FP_half): New function. Similar, but for setting | |
276 | a half precision register. | |
277 | (aarch64_get_thread_id): New function. Returns the value of the | |
278 | CPU's TPIDR register. | |
279 | (aarch64_get_FPCR): New function. Returns the value of the CPU's | |
280 | floating point control register. | |
281 | (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR | |
282 | register. | |
283 | * cpustate.h: Add prototypes for new functions. | |
284 | * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. | |
285 | * memory.c: Use unaligned core access functions for all memory | |
286 | reads and writes. | |
287 | * simulator.c (HALT_NYI): Generate an error message if tracing | |
288 | will not tell the user why the simulator is halting. | |
289 | (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. | |
290 | (INSTR): New time-saver macro. | |
291 | (fldrb_abs): New function. Loads an 8-bit value using a scaled | |
292 | offset. | |
293 | (fldrh_abs): New function. Likewise for 16-bit values. | |
294 | (do_vec_SSHL): Allow for negative shift values. | |
295 | (do_vec_USHL): Likewise. | |
296 | (do_vec_SHL): Correct computation of shift amount. | |
297 | (do_vec_SSHR_USHR): Correct decision of signed vs unsigned | |
298 | shifts and computation of shift value. | |
299 | (clz): New function. Counts leading zero bits. | |
300 | (do_vec_CLZ): New function. Implements CLZ (vector). | |
301 | (do_vec_MOV_element): Call do_vec_CLZ. | |
302 | (dexSimpleFPCondCompare): Implement. | |
303 | (do_FCVT_half_to_single): New function. Implements one of the | |
304 | FCVT operations. | |
305 | (do_FCVT_half_to_double): New function. Likewise. | |
306 | (do_FCVT_single_to_half): New function. Likewise. | |
307 | (do_FCVT_double_to_half): New function. Likewise. | |
308 | (dexSimpleFPDataProc1Source): Call new FCVT functions. | |
309 | (do_scalar_SHL): Handle negative shifts. | |
310 | (do_scalar_shift): Handle SSHR. | |
311 | (do_scalar_USHL): New function. | |
312 | (do_double_add): Simplify to just performing a double precision | |
313 | add operation. Move remaining code into... | |
314 | (do_scalar_vec): ... New function. | |
315 | (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs | |
316 | functions. | |
317 | (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR | |
318 | registers. | |
319 | (system_set): New function. | |
320 | (do_MSR_immediate): New function. Stub for now. | |
321 | (do_MSR_reg): New function. Likewise. Partially implements MSR | |
322 | instruction. | |
323 | (do_SYS): New function. Stub for now, | |
324 | (dexSystem): Call new functions. | |
325 | ||
e101a78b NC |
326 | 2016-03-18 Nick Clifton <nickc@redhat.com> |
327 | ||
328 | * cpustate.c: Remove spurious spaces from TRACE strings. | |
329 | Print hex equivalents of floats and doubles. | |
330 | Check element number against array size when accessing vector | |
331 | registers. | |
4c0ca98e NC |
332 | (GET_VEC_ELEMENT): Fix off by one error checking for an invalid |
333 | element index. | |
334 | (SET_VEC_ELEMENT): Likewise. | |
87bba7a5 | 335 | (GET_VEC_ELEMENT): And fix thinko using macro arguments. |
4c0ca98e | 336 | |
e101a78b NC |
337 | * memory.c: Trace memory reads when --trace-memory is enabled. |
338 | Remove float and double load and store functions. | |
339 | * memory.h (aarch64_get_mem_float): Delete prototype. | |
340 | (aarch64_get_mem_double): Likewise. | |
341 | (aarch64_set_mem_float): Likewise. | |
342 | (aarch64_set_mem_double): Likewise. | |
343 | * simulator (IS_SET): Always return either 0 or 1. | |
344 | (IS_CLEAR): Likewise. | |
345 | (fldrs_pcrel): Load and store floats using 32-bit memory accesses | |
346 | and doubles using 64-bit memory accesses. | |
347 | (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. | |
348 | (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. | |
349 | (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. | |
350 | (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. | |
351 | (store_pair_double, load_pair_float, load_pair_double): Likewise. | |
352 | (do_vec_MUL_by_element): New function. | |
353 | (do_vec_op2): Call do_vec_MUL_by_element. | |
354 | (do_scalar_NEG): New function. | |
355 | (do_double_add): Call do_scalar_NEG. | |
356 | ||
57aa1742 NC |
357 | 2016-03-03 Nick Clifton <nickc@redhat.com> |
358 | ||
359 | * simulator.c (set_flags_for_sub32): Correct type of signbit. | |
360 | (CondCompare): Swap interpretation of bit 30. | |
361 | (DO_ADDP): Delete macro. | |
362 | (do_vec_ADDP): Copy source registers before starting to update | |
363 | destination register. | |
364 | (do_vec_FADDP): Likewise. | |
365 | (do_vec_load_store): Fix computation of sizeof_operation. | |
366 | (rbit64): Fix type of constant. | |
367 | (aarch64_step): When displaying insn value, display all 32 bits. | |
368 | ||
ce39bd38 MF |
369 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
370 | ||
371 | * config.in, configure: Regenerate. | |
372 | ||
e19418e0 MF |
373 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
374 | ||
375 | * configure: Regenerate. | |
376 | ||
16f7876d MF |
377 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
378 | ||
379 | * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call. | |
380 | * configure: Regenerate. | |
381 | ||
99d8e879 MF |
382 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
383 | ||
384 | * configure: Regenerate. | |
35656e95 MF |
385 | |
386 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> | |
387 | ||
388 | * configure: Regenerate. | |
99d8e879 | 389 | |
347fe5bb MF |
390 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
391 | ||
392 | * configure.ac (SIM_AC_OPTION_INLINE): Delete call. | |
393 | * configure: Regenerate. | |
394 | ||
22be3fbe MF |
395 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
396 | ||
397 | * configure: Regenerate. | |
398 | ||
0dc73ef7 MF |
399 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
400 | ||
401 | * configure: Regenerate. | |
402 | ||
936df756 MF |
403 | 2016-01-09 Mike Frysinger <vapier@gentoo.org> |
404 | ||
405 | * config.in, configure: Regenerate. | |
406 | ||
2e3d4f4d MF |
407 | 2016-01-06 Mike Frysinger <vapier@gentoo.org> |
408 | ||
409 | * interp.c (sim_create_inferior): Mark argv and env const. | |
410 | (sim_open): Mark argv const. | |
411 | ||
1a846c62 MF |
412 | 2016-01-05 Mike Frysinger <vapier@gentoo.org> |
413 | ||
414 | * interp.c: Delete dis-asm.h include. | |
415 | (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete. | |
416 | (sim_create_inferior): Delete disassemble init logic. | |
417 | (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete. | |
418 | (sim_open): Delete sim_add_option_table call. | |
419 | * memory.c (mem_error): Delete disas check. | |
420 | * simulator.c: Delete dis-asm.h include. | |
421 | (disas): Delete. | |
422 | (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM. | |
423 | (HALT_NYI): Likewise. | |
424 | (handle_halt): Delete disas call. | |
425 | (aarch64_step): Replace disas logic with TRACE_DISASM. | |
426 | * simulator.h: Delete dis-asm.h include. | |
427 | (aarch64_print_insn): Delete. | |
428 | ||
bc273e17 MF |
429 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
430 | ||
431 | * simulator.c (MAX, MIN): Delete. | |
432 | (do_vec_maxv): Change MAX to max and MIN to min. | |
433 | (do_vec_fminmaxV): Likewise. | |
434 | ||
ac8eefeb TG |
435 | 2016-01-04 Tristan Gingold <gingold@adacore.com> |
436 | ||
437 | * simulator.c: Remove syscall.h include. | |
438 | ||
9bbf6f91 MF |
439 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
440 | ||
441 | * configure: Regenerate. | |
442 | ||
0cb8d851 MF |
443 | 2016-01-03 Mike Frysinger <vapier@gentoo.org> |
444 | ||
445 | * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete. | |
446 | * configure: Regenerate. | |
447 | ||
1ac72f06 MF |
448 | 2016-01-02 Mike Frysinger <vapier@gentoo.org> |
449 | ||
450 | * configure: Regenerate. | |
451 | ||
5d015275 MF |
452 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
453 | ||
454 | * interp.c (sim_dis_read): Change private_data to application_data. | |
455 | (sim_create_inferior): Likewise. | |
456 | ||
5e744ef8 MF |
457 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
458 | ||
459 | * Makefile.in (SIM_OBJS): Delete sim-hload.o. | |
460 | ||
1b393626 MF |
461 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
462 | ||
463 | * config.in, configure: Regenerate. | |
464 | ||
0e967299 MF |
465 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
466 | ||
467 | * interp.c (sim_create_inferior): Update comment and argv check. | |
468 | ||
f66affe9 MF |
469 | 2015-12-14 Nick Clifton <nickc@redhat.com> |
470 | ||
471 | * simulator.c (system_get): New function. Provides read | |
472 | access to the dczid system register. | |
473 | (do_mrs): New function - implements the MRS instruction. | |
474 | (dexSystem): Call do_mrs for the MRS instruction. Halt on | |
475 | unimplemented system instructions. | |
476 | ||
477 | 2015-11-24 Nick Clifton <nickc@redhat.com> | |
478 | ||
479 | * configure.ac: New configure template. | |
480 | * aclocal.m4: Generate. | |
481 | * config.in: Generate. | |
482 | * configure: Generate. | |
483 | * cpustate.c: New file - functions for accessing AArch64 registers. | |
484 | * cpustate.h: New header. | |
485 | * decode.h: New header. | |
486 | * interp.c: New file - interface between GDB and simulator. | |
487 | * Makefile.in: New makefile template. | |
488 | * memory.c: New file - functions for simulating aarch64 memory | |
489 | accesses. | |
490 | * memory.h: New header. | |
491 | * sim-main.h: New header. | |
492 | * simulator.c: New file - aarch64 simulator functions. | |
493 | * simulator.h: New header. |