[thirdparty/binutils-gdb.git] / sim / arm / armdefs.h

/*  armdefs.h -- ARMulator common definitions:  ARM6 Instruction Emulator.
    Copyright (C) 1994 Advanced RISC Machines Ltd.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */

#include <stdio.h>
#include <stdlib.h>

#define FALSE 0
#define TRUE 1
#define LOW 0
#define HIGH 1
#define LOWHIGH 1
#define HIGHLOW 2

#ifndef __STDC__
typedef char *VoidStar;
#endif

typedef unsigned long ARMword;	/* must be 32 bits wide */
typedef unsigned long long ARMdword;	/* Must be at least 64 bits wide.  */
typedef struct ARMul_State ARMul_State;

typedef unsigned ARMul_CPInits (ARMul_State * state);
typedef unsigned ARMul_CPExits (ARMul_State * state);
typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
			     ARMword instr, ARMword value);
typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
			     ARMword instr, ARMword * value);
typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
			     ARMword instr, ARMword * value);
typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
			     ARMword instr, ARMword value);
typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
			     ARMword instr);
typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
				ARMword * value);
typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
				 ARMword value);

struct ARMul_State
{
  ARMword Emulate;		/* to start and stop emulation */
  unsigned EndCondition;	/* reason for stopping */
  unsigned ErrorCode;		/* type of illegal instruction */
  ARMword Reg[16];		/* the current register file */
  ARMword RegBank[7][16];	/* all the registers */
  /* 40 bit accumulator.  We always keep this 64 bits wide,
     and move only 40 bits out of it in an MRA insn.  */
  ARMdword Accumulator;
  ARMword Cpsr;			/* the current psr */
  ARMword Spsr[7];		/* the exception psr's */
  ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags;	/* dummy flags for speed */
  ARMword SFlag;
#ifdef MODET
  ARMword TFlag;		/* Thumb state */
#endif
  ARMword Bank;			/* the current register bank */
  ARMword Mode;			/* the current mode */
  ARMword instr, pc, temp;	/* saved register state */
  ARMword loaded, decoded;	/* saved pipeline state */
  unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles;	/* emulated cycles used */
  unsigned long NumInstrs;	/* the number of instructions executed */
  unsigned NextInstr;
  unsigned VectorCatch;		/* caught exception mask */
  unsigned CallDebug;		/* set to call the debugger */
  unsigned CanWatch;		/* set by memory interface if its willing to suffer the
				   overhead of checking for watchpoints on each memory
				   access */
  unsigned MemReadDebug, MemWriteDebug;
  unsigned long StopHandle;

  unsigned char *MemDataPtr;	/* admin data */
  unsigned char *MemInPtr;	/* the Data In bus */
  unsigned char *MemOutPtr;	/* the Data Out bus (which you may not need */
  unsigned char *MemSparePtr;	/* extra space */
  ARMword MemSize;

  unsigned char *OSptr;		/* OS Handle */
  char *CommandLine;		/* Command Line from ARMsd */

  ARMul_CPInits *CPInit[16];	/* coprocessor initialisers */
  ARMul_CPExits *CPExit[16];	/* coprocessor finalisers */
  ARMul_LDCs *LDC[16];		/* LDC instruction */
  ARMul_STCs *STC[16];		/* STC instruction */
  ARMul_MRCs *MRC[16];		/* MRC instruction */
  ARMul_MCRs *MCR[16];		/* MCR instruction */
  ARMul_CDPs *CDP[16];		/* CDP instruction */
  ARMul_CPReads *CPRead[16];	/* Read CP register */
  ARMul_CPWrites *CPWrite[16];	/* Write CP register */
  unsigned char *CPData[16];	/* Coprocessor data */
  unsigned char const *CPRegWords[16];	/* map of coprocessor register sizes */
  unsigned long LastTime;	/* Value of last call to ARMul_Time() */
  ARMword CP14R0_CCD;		/* used to count 64 clock cycles with CP14 R0 bit
				   3 set */

  unsigned EventSet;		/* the number of events in the queue */
  unsigned long Now;		/* time to the nearest cycle */
  struct EventNode **EventPtr;	/* the event list */

  unsigned Exception;		/* enable the next four values */
  unsigned Debug;		/* show instructions as they are executed */
  unsigned NresetSig;		/* reset the processor */
  unsigned NfiqSig;
  unsigned NirqSig;

  unsigned abortSig;
  unsigned NtransSig;
  unsigned bigendSig;
  unsigned prog32Sig;
  unsigned data32Sig;
  unsigned lateabtSig;
  ARMword Vector;		/* synthesize aborts in cycle modes */
  ARMword Aborted;		/* sticky flag for aborts */
  ARMword Reseted;		/* sticky flag for Reset */
  ARMword Inted, LastInted;	/* sticky flags for interrupts */
  ARMword Base;			/* extra hand for base writeback */
  ARMword AbortAddr;		/* to keep track of Prefetch aborts */

  const struct Dbg_HostosInterface *hostif;

  unsigned is_v4;		/* Are we emulating a v4 architecture (or higher) ?  */
  unsigned is_v5;		/* Are we emulating a v5 architecture ?  */
  unsigned is_v5e;		/* Are we emulating a v5e architecture ?  */
  unsigned is_XScale;		/* Are we emulating an XScale architecture ?  */
  unsigned is_ep9312;		/* Are we emulating a Cirrus Maverick co-processor ?  */
  unsigned verbose;		/* Print various messages like the banner */
};

#define ResetPin NresetSig
#define FIQPin NfiqSig
#define IRQPin NirqSig
#define AbortPin abortSig
#define TransPin NtransSig
#define BigEndPin bigendSig
#define Prog32Pin prog32Sig
#define Data32Pin data32Sig
#define LateAbortPin lateabtSig

/***************************************************************************\
*                        Properties of ARM we know about                    *
\***************************************************************************/

/* The bitflags */
#define ARM_Fix26_Prop   0x01
#define ARM_Nexec_Prop   0x02
#define ARM_Debug_Prop   0x10
#define ARM_Isync_Prop   ARM_Debug_Prop
#define ARM_Lock_Prop    0x20
#define ARM_v4_Prop      0x40
#define ARM_v5_Prop      0x80
#define ARM_v5e_Prop     0x100
#define ARM_XScale_Prop  0x200
#define ARM_ep9312_Prop  0x400

/***************************************************************************\
*                   Macros to extract instruction fields                    *
\***************************************************************************/

#define BIT(n) ( (ARMword)(instr>>(n))&1)	/* bit n of instruction */
#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) )	/* bits m to n of instr */
#define TOPBITS(n) (instr >> (n))	/* bits 31 to n of instr */

/***************************************************************************\
*                      The hardware vector addresses                        *
\***************************************************************************/

#define ARMResetV 0L
#define ARMUndefinedInstrV 4L
#define ARMSWIV 8L
#define ARMPrefetchAbortV 12L
#define ARMDataAbortV 16L
#define ARMAddrExceptnV 20L
#define ARMIRQV 24L
#define ARMFIQV 28L
#define ARMErrorV 32L		/* This is an offset, not an address ! */

#define ARMul_ResetV ARMResetV
#define ARMul_UndefinedInstrV ARMUndefinedInstrV
#define ARMul_SWIV ARMSWIV
#define ARMul_PrefetchAbortV ARMPrefetchAbortV
#define ARMul_DataAbortV ARMDataAbortV
#define ARMul_AddrExceptnV ARMAddrExceptnV
#define ARMul_IRQV ARMIRQV
#define ARMul_FIQV ARMFIQV

/***************************************************************************\
*                          Mode and Bank Constants                          *
\***************************************************************************/

#define USER26MODE   0L
#define FIQ26MODE    1L
#define IRQ26MODE    2L
#define SVC26MODE    3L
#define USER32MODE  16L
#define FIQ32MODE   17L
#define IRQ32MODE   18L
#define SVC32MODE   19L
#define ABORT32MODE 23L
#define UNDEF32MODE 27L
#define SYSTEMMODE  31L

#define ARM32BITMODE (state->Mode > 3)
#define ARM26BITMODE (state->Mode <= 3)
#define ARMMODE (state->Mode)
#define ARMul_MODEBITS 0x1fL
#define ARMul_MODE32BIT ARM32BITMODE
#define ARMul_MODE26BIT ARM26BITMODE

#define USERBANK 0
#define FIQBANK 1
#define IRQBANK 2
#define SVCBANK 3
#define ABORTBANK 4
#define UNDEFBANK 5
#define DUMMYBANK 6
#define SYSTEMBANK USERBANK

#define BANK_CAN_ACCESS_SPSR(bank)  \
  ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)

/***************************************************************************\
*                  Definitons of things in the emulator                     *
\***************************************************************************/

extern void ARMul_EmulateInit (void);
extern ARMul_State *ARMul_NewState (void);
extern void ARMul_Reset (ARMul_State * state);
extern ARMword ARMul_DoProg (ARMul_State * state);
extern ARMword ARMul_DoInstr (ARMul_State * state);

/***************************************************************************\
*                Definitons of things for event handling                    *
\***************************************************************************/

extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
				 unsigned (*func) ());
extern void ARMul_EnvokeEvent (ARMul_State * state);
extern unsigned long ARMul_Time (ARMul_State * state);

/***************************************************************************\
*                          Useful support routines                          *
\***************************************************************************/

extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
			     unsigned reg);
extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
			  ARMword value);
extern ARMword ARMul_GetPC (ARMul_State * state);
extern ARMword ARMul_GetNextPC (ARMul_State * state);
extern void ARMul_SetPC (ARMul_State * state, ARMword value);
extern ARMword ARMul_GetR15 (ARMul_State * state);
extern void ARMul_SetR15 (ARMul_State * state, ARMword value);

extern ARMword ARMul_GetCPSR (ARMul_State * state);
extern void ARMul_SetCPSR (ARMul_State * state, ARMword value);
extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);

/***************************************************************************\
*                  Definitons of things to handle aborts                    *
\***************************************************************************/

extern void ARMul_Abort (ARMul_State * state, ARMword address);
#define ARMul_ABORTWORD 0xefffffff	/* SWI -1 */
#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
                                        state->AbortAddr = (address & ~3L)
#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
                                 state->Aborted = ARMul_DataAbortV ;
#define ARMul_CLEARABORT state->abortSig = LOW

/***************************************************************************\
*              Definitons of things in the memory interface                 *
\***************************************************************************/

extern unsigned ARMul_MemoryInit (ARMul_State * state,
				  unsigned long initmemsize);
extern void ARMul_MemoryExit (ARMul_State * state);

extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
				 ARMword isize);
extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
				 ARMword isize);
extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
				  ARMword isize);

extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);

extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
			      ARMword data);
extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
			      ARMword data);
extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
				 ARMword data);
extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
			     ARMword data);

extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
			       ARMword data);
extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
			       ARMword data);

extern void ARMul_Icycles (ARMul_State * state, unsigned number,
			   ARMword address);
extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
			   ARMword address);

extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
extern ARMword ARMul_SafeReadByte (ARMul_State * state, ARMword address);
extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
			     ARMword data);
extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
			     ARMword data);
extern void ARMul_SafeWriteByte (ARMul_State * state, ARMword address,
			     ARMword data);

extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
				ARMword, ARMword, ARMword, ARMword, ARMword,
				ARMword, ARMword, ARMword);

/***************************************************************************\
*            Definitons of things in the co-processor interface             *
\***************************************************************************/

#define ARMul_FIRST 0
#define ARMul_TRANSFER 1
#define ARMul_BUSY 2
#define ARMul_DATA 3
#define ARMul_INTERRUPT 4
#define ARMul_DONE 0
#define ARMul_CANT 1
#define ARMul_INC 3

#define ARMul_CP13_R0_FIQ	0x1
#define ARMul_CP13_R0_IRQ	0x2
#define ARMul_CP13_R8_PMUS	0x1

#define ARMul_CP14_R0_ENABLE	0x0001
#define ARMul_CP14_R0_CLKRST	0x0004
#define ARMul_CP14_R0_CCD	0x0008
#define ARMul_CP14_R0_INTEN0	0x0010
#define ARMul_CP14_R0_INTEN1	0x0020
#define ARMul_CP14_R0_INTEN2	0x0040
#define ARMul_CP14_R0_FLAG0	0x0100
#define ARMul_CP14_R0_FLAG1	0x0200
#define ARMul_CP14_R0_FLAG2	0x0400
#define ARMul_CP14_R10_MOE_IB	0x0004
#define ARMul_CP14_R10_MOE_DB	0x0008
#define ARMul_CP14_R10_MOE_BT	0x000c
#define ARMul_CP15_R1_ENDIAN	0x0080
#define ARMul_CP15_R1_ALIGN	0x0002
#define ARMul_CP15_R5_X		0x0400
#define ARMul_CP15_R5_ST_ALIGN	0x0001
#define ARMul_CP15_R5_IMPRE	0x0406
#define ARMul_CP15_R5_MMU_EXCPT	0x0400
#define ARMul_CP15_DBCON_M	0x0100
#define ARMul_CP15_DBCON_E1	0x000c
#define ARMul_CP15_DBCON_E0	0x0003

extern unsigned ARMul_CoProInit (ARMul_State * state);
extern void ARMul_CoProExit (ARMul_State * state);
extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
			       ARMul_CPInits * init, ARMul_CPExits * exit,
			       ARMul_LDCs * ldc, ARMul_STCs * stc,
			       ARMul_MRCs * mrc, ARMul_MCRs * mcr,
			       ARMul_CDPs * cdp,
			       ARMul_CPReads * read, ARMul_CPWrites * write);
extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
extern void XScale_check_memacc (ARMul_State * state, ARMword * address,
				 int store);
extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far);
extern int XScale_debug_moe (ARMul_State * state, int moe);

/***************************************************************************\
*               Definitons of things in the host environment                *
\***************************************************************************/

extern unsigned ARMul_OSInit (ARMul_State * state);
extern void ARMul_OSExit (ARMul_State * state);
extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
extern ARMword ARMul_OSLastErrorP (ARMul_State * state);

extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
				   ARMword pc);
extern int rdi_log;

/***************************************************************************\
*                            Host-dependent stuff                           *
\***************************************************************************/

#ifdef macintosh
pascal void SpinCursor (short increment);	/* copied from CursorCtl.h */
# define HOURGLASS           SpinCursor( 1 )
# define HOURGLASS_RATE      1023	/* 2^n - 1 */
#endif

extern void ARMul_UndefInstr      (ARMul_State *, ARMword);
extern void ARMul_FixCPSR         (ARMul_State *, ARMword, ARMword);
extern void ARMul_FixSPSR         (ARMul_State *, ARMword, ARMword);
extern void ARMul_ConsolePrint    (ARMul_State *, const char *, ...);
extern void ARMul_SelectProcessor (ARMul_State *, unsigned);
Commit	Line	Data
c906108c SS	1	/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.
	2	Copyright (C) 1994 Advanced RISC Machines Ltd.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
	16	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	17
	18	#include <stdio.h>
	19	#include <stdlib.h>
	20
	21	#define FALSE 0
	22	#define TRUE 1
	23	#define LOW 0
	24	#define HIGH 1
	25	#define LOWHIGH 1
	26	#define HIGHLOW 2
	27
	28	#ifndef __STDC__
dfcd3bfb	29	typedef char *VoidStar;
c906108c SS	30	#endif
c906108c SS	31
dfcd3bfb	32	typedef unsigned long ARMword; /* must be 32 bits wide */
f1129fb8	33	typedef unsigned long long ARMdword; /* Must be at least 64 bits wide. */
dfcd3bfb JM	34	typedef struct ARMul_State ARMul_State;
	35
	36	typedef unsigned ARMul_CPInits (ARMul_State * state);
	37	typedef unsigned ARMul_CPExits (ARMul_State * state);
	38	typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
	39	ARMword instr, ARMword value);
	40	typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
	41	ARMword instr, ARMword * value);
	42	typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
	43	ARMword instr, ARMword * value);
	44	typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
	45	ARMword instr, ARMword value);
	46	typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
	47	ARMword instr);
	48	typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
	49	ARMword * value);
	50	typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
	51	ARMword value);
	52
	53	struct ARMul_State
	54	{
	55	ARMword Emulate; /* to start and stop emulation */
	56	unsigned EndCondition; /* reason for stopping */
	57	unsigned ErrorCode; /* type of illegal instruction */
	58	ARMword Reg[16]; /* the current register file */
	59	ARMword RegBank[7][16]; /* all the registers */
f1129fb8 NC	60	/* 40 bit accumulator. We always keep this 64 bits wide,
	61	and move only 40 bits out of it in an MRA insn. */
	62	ARMdword Accumulator;
dfcd3bfb JM	63	ARMword Cpsr; /* the current psr */
	64	ARMword Spsr[7]; /* the exception psr's */
	65	ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
f1129fb8	66	ARMword SFlag;
c906108c	67	#ifdef MODET
dfcd3bfb	68	ARMword TFlag; /* Thumb state */
c906108c	69	#endif
dfcd3bfb JM	70	ARMword Bank; /* the current register bank */
	71	ARMword Mode; /* the current mode */
	72	ARMword instr, pc, temp; /* saved register state */
	73	ARMword loaded, decoded; /* saved pipeline state */
	74	unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
	75	unsigned long NumInstrs; /* the number of instructions executed */
	76	unsigned NextInstr;
	77	unsigned VectorCatch; /* caught exception mask */
	78	unsigned CallDebug; /* set to call the debugger */
	79	unsigned CanWatch; /* set by memory interface if its willing to suffer the
	80	overhead of checking for watchpoints on each memory
	81	access */
	82	unsigned MemReadDebug, MemWriteDebug;
	83	unsigned long StopHandle;
	84
	85	unsigned char MemDataPtr; / admin data */
	86	unsigned char MemInPtr; / the Data In bus */
	87	unsigned char MemOutPtr; / the Data Out bus (which you may not need */
	88	unsigned char MemSparePtr; / extra space */
	89	ARMword MemSize;
	90
	91	unsigned char OSptr; / OS Handle */
	92	char CommandLine; / Command Line from ARMsd */
	93
	94	ARMul_CPInits CPInit[16]; / coprocessor initialisers */
	95	ARMul_CPExits CPExit[16]; / coprocessor finalisers */
	96	ARMul_LDCs LDC[16]; / LDC instruction */
	97	ARMul_STCs STC[16]; / STC instruction */
	98	ARMul_MRCs MRC[16]; / MRC instruction */
	99	ARMul_MCRs MCR[16]; / MCR instruction */
	100	ARMul_CDPs CDP[16]; / CDP instruction */
	101	ARMul_CPReads CPRead[16]; / Read CP register */
	102	ARMul_CPWrites CPWrite[16]; / Write CP register */
	103	unsigned char CPData[16]; / Coprocessor data */
	104	unsigned char const CPRegWords[16]; / map of coprocessor register sizes */
c3ae2f98 MG	105	unsigned long LastTime; /* Value of last call to ARMul_Time() */
	106	ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit
	107	3 set */
dfcd3bfb JM	108
	109	unsigned EventSet; /* the number of events in the queue */
	110	unsigned long Now; /* time to the nearest cycle */
	111	struct EventNode *EventPtr; / the event list */
	112
	113	unsigned Exception; /* enable the next four values */
	114	unsigned Debug; /* show instructions as they are executed */
	115	unsigned NresetSig; /* reset the processor */
	116	unsigned NfiqSig;
	117	unsigned NirqSig;
	118
	119	unsigned abortSig;
	120	unsigned NtransSig;
	121	unsigned bigendSig;
	122	unsigned prog32Sig;
	123	unsigned data32Sig;
	124	unsigned lateabtSig;
	125	ARMword Vector; /* synthesize aborts in cycle modes */
	126	ARMword Aborted; /* sticky flag for aborts */
	127	ARMword Reseted; /* sticky flag for Reset */
	128	ARMword Inted, LastInted; /* sticky flags for interrupts */
	129	ARMword Base; /* extra hand for base writeback */
	130	ARMword AbortAddr; /* to keep track of Prefetch aborts */
	131
	132	const struct Dbg_HostosInterface *hostif;
	133
3943c96b NC	134	unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
3943c96b NC	135	unsigned is_v5; /* Are we emulating a v5 architecture ? */
f1129fb8 NC	136	unsigned is_v5e; /* Are we emulating a v5e architecture ? */
f1129fb8 NC	137	unsigned is_XScale; /* Are we emulating an XScale architecture ? */
f603c8fe	138	unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
3943c96b	139	unsigned verbose; /* Print various messages like the banner */
dfcd3bfb	140	};
c906108c SS	141
	142	#define ResetPin NresetSig
	143	#define FIQPin NfiqSig
	144	#define IRQPin NirqSig
	145	#define AbortPin abortSig
	146	#define TransPin NtransSig
	147	#define BigEndPin bigendSig
	148	#define Prog32Pin prog32Sig
	149	#define Data32Pin data32Sig
	150	#define LateAbortPin lateabtSig
	151
	152	/***************************************************************************\
3943c96b	153	* Properties of ARM we know about *
c906108c	154	\***************************************************************************/
dfcd3bfb	155
c906108c SS	156	/* The bitflags */
	157	#define ARM_Fix26_Prop 0x01
	158	#define ARM_Nexec_Prop 0x02
	159	#define ARM_Debug_Prop 0x10
	160	#define ARM_Isync_Prop ARM_Debug_Prop
	161	#define ARM_Lock_Prop 0x20
3943c96b NC	162	#define ARM_v4_Prop 0x40
3943c96b NC	163	#define ARM_v5_Prop 0x80
f1129fb8 NC	164	#define ARM_v5e_Prop 0x100
f1129fb8 NC	165	#define ARM_XScale_Prop 0x200
f603c8fe	166	#define ARM_ep9312_Prop 0x400
c906108c SS	167
	168	/***************************************************************************\
	169	* Macros to extract instruction fields *
	170	\***************************************************************************/
	171
dfcd3bfb JM	172	#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
	173	#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
	174	#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
c906108c SS	175
	176	/***************************************************************************\
	177	* The hardware vector addresses *
	178	\***************************************************************************/
	179
	180	#define ARMResetV 0L
	181	#define ARMUndefinedInstrV 4L
	182	#define ARMSWIV 8L
	183	#define ARMPrefetchAbortV 12L
	184	#define ARMDataAbortV 16L
	185	#define ARMAddrExceptnV 20L
	186	#define ARMIRQV 24L
	187	#define ARMFIQV 28L
dfcd3bfb	188	#define ARMErrorV 32L /* This is an offset, not an address ! */
c906108c SS	189
	190	#define ARMul_ResetV ARMResetV
	191	#define ARMul_UndefinedInstrV ARMUndefinedInstrV
	192	#define ARMul_SWIV ARMSWIV
	193	#define ARMul_PrefetchAbortV ARMPrefetchAbortV
	194	#define ARMul_DataAbortV ARMDataAbortV
	195	#define ARMul_AddrExceptnV ARMAddrExceptnV
	196	#define ARMul_IRQV ARMIRQV
	197	#define ARMul_FIQV ARMFIQV
	198
	199	/***************************************************************************\
	200	* Mode and Bank Constants *
	201	\***************************************************************************/
	202
c1a72ffd NC	203	#define USER26MODE 0L
	204	#define FIQ26MODE 1L
	205	#define IRQ26MODE 2L
	206	#define SVC26MODE 3L
	207	#define USER32MODE 16L
	208	#define FIQ32MODE 17L
	209	#define IRQ32MODE 18L
	210	#define SVC32MODE 19L
c906108c SS	211	#define ABORT32MODE 23L
c906108c SS	212	#define UNDEF32MODE 27L
c1a72ffd	213	#define SYSTEMMODE 31L
c906108c SS	214
	215	#define ARM32BITMODE (state->Mode > 3)
	216	#define ARM26BITMODE (state->Mode <= 3)
	217	#define ARMMODE (state->Mode)
	218	#define ARMul_MODEBITS 0x1fL
	219	#define ARMul_MODE32BIT ARM32BITMODE
	220	#define ARMul_MODE26BIT ARM26BITMODE
	221
	222	#define USERBANK 0
	223	#define FIQBANK 1
	224	#define IRQBANK 2
	225	#define SVCBANK 3
	226	#define ABORTBANK 4
	227	#define UNDEFBANK 5
	228	#define DUMMYBANK 6
b0eae074	229	#define SYSTEMBANK USERBANK
c1a72ffd NC	230
	231	#define BANK_CAN_ACCESS_SPSR(bank) \
	232	((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
c906108c SS	233
	234	/***************************************************************************\
	235	* Definitons of things in the emulator *
	236	\***************************************************************************/
	237
dfcd3bfb JM	238	extern void ARMul_EmulateInit (void);
	239	extern ARMul_State *ARMul_NewState (void);
	240	extern void ARMul_Reset (ARMul_State * state);
	241	extern ARMword ARMul_DoProg (ARMul_State * state);
	242	extern ARMword ARMul_DoInstr (ARMul_State * state);
c906108c SS	243
	244	/***************************************************************************\
	245	* Definitons of things for event handling *
	246	\***************************************************************************/
	247
dfcd3bfb JM	248	extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
	249	unsigned (*func) ());
	250	extern void ARMul_EnvokeEvent (ARMul_State * state);
	251	extern unsigned long ARMul_Time (ARMul_State * state);
c906108c SS	252
	253	/***************************************************************************\
	254	* Useful support routines *
	255	\***************************************************************************/
	256
dfcd3bfb JM	257	extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
	258	unsigned reg);
	259	extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
	260	ARMword value);
	261	extern ARMword ARMul_GetPC (ARMul_State * state);
	262	extern ARMword ARMul_GetNextPC (ARMul_State * state);
	263	extern void ARMul_SetPC (ARMul_State * state, ARMword value);
	264	extern ARMword ARMul_GetR15 (ARMul_State * state);
	265	extern void ARMul_SetR15 (ARMul_State * state, ARMword value);
	266
	267	extern ARMword ARMul_GetCPSR (ARMul_State * state);
	268	extern void ARMul_SetCPSR (ARMul_State * state, ARMword value);
	269	extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
	270	extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
c906108c SS	271
	272	/***************************************************************************\
	273	* Definitons of things to handle aborts *
	274	\***************************************************************************/
	275
dfcd3bfb JM	276	extern void ARMul_Abort (ARMul_State * state, ARMword address);
dfcd3bfb JM	277	#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
c906108c SS	278	#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
	279	state->AbortAddr = (address & ~3L)
	280	#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
	281	state->Aborted = ARMul_DataAbortV ;
	282	#define ARMul_CLEARABORT state->abortSig = LOW
	283
	284	/***************************************************************************\
	285	* Definitons of things in the memory interface *
	286	\***************************************************************************/
	287
dfcd3bfb JM	288	extern unsigned ARMul_MemoryInit (ARMul_State * state,
	289	unsigned long initmemsize);
	290	extern void ARMul_MemoryExit (ARMul_State * state);
	291
	292	extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
	293	ARMword isize);
	294	extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
	295	ARMword isize);
	296	extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
	297	ARMword isize);
	298
	299	extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
	300	extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
	301	extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
	302	extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
	303
	304	extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
	305	ARMword data);
	306	extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
	307	ARMword data);
	308	extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
	309	ARMword data);
	310	extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
	311	ARMword data);
	312
	313	extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
	314	ARMword data);
	315	extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
	316	ARMword data);
	317
	318	extern void ARMul_Icycles (ARMul_State * state, unsigned number,
	319	ARMword address);
	320	extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
	321	ARMword address);
	322
	323	extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
	324	extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
917bca4f	325	extern ARMword ARMul_SafeReadByte (ARMul_State * state, ARMword address);
dfcd3bfb JM	326	extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
	327	ARMword data);
	328	extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
	329	ARMword data);
917bca4f NC	330	extern void ARMul_SafeWriteByte (ARMul_State * state, ARMword address,
917bca4f NC	331	ARMword data);
dfcd3bfb JM	332
	333	extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
	334	ARMword, ARMword, ARMword, ARMword, ARMword,
	335	ARMword, ARMword, ARMword);
c906108c SS	336
	337	/***************************************************************************\
	338	* Definitons of things in the co-processor interface *
	339	\***************************************************************************/
	340
	341	#define ARMul_FIRST 0
	342	#define ARMul_TRANSFER 1
	343	#define ARMul_BUSY 2
	344	#define ARMul_DATA 3
	345	#define ARMul_INTERRUPT 4
	346	#define ARMul_DONE 0
	347	#define ARMul_CANT 1
	348	#define ARMul_INC 3
	349
c3ae2f98 MG	350	#define ARMul_CP13_R0_FIQ 0x1
	351	#define ARMul_CP13_R0_IRQ 0x2
	352	#define ARMul_CP13_R8_PMUS 0x1
	353
	354	#define ARMul_CP14_R0_ENABLE 0x0001
	355	#define ARMul_CP14_R0_CLKRST 0x0004
	356	#define ARMul_CP14_R0_CCD 0x0008
	357	#define ARMul_CP14_R0_INTEN0 0x0010
	358	#define ARMul_CP14_R0_INTEN1 0x0020
	359	#define ARMul_CP14_R0_INTEN2 0x0040
	360	#define ARMul_CP14_R0_FLAG0 0x0100
	361	#define ARMul_CP14_R0_FLAG1 0x0200
	362	#define ARMul_CP14_R0_FLAG2 0x0400
	363	#define ARMul_CP14_R10_MOE_IB 0x0004
	364	#define ARMul_CP14_R10_MOE_DB 0x0008
	365	#define ARMul_CP14_R10_MOE_BT 0x000c
	366	#define ARMul_CP15_R1_ENDIAN 0x0080
	367	#define ARMul_CP15_R1_ALIGN 0x0002
	368	#define ARMul_CP15_R5_X 0x0400
	369	#define ARMul_CP15_R5_ST_ALIGN 0x0001
	370	#define ARMul_CP15_R5_IMPRE 0x0406
	371	#define ARMul_CP15_R5_MMU_EXCPT 0x0400
	372	#define ARMul_CP15_DBCON_M 0x0100
	373	#define ARMul_CP15_DBCON_E1 0x000c
	374	#define ARMul_CP15_DBCON_E0 0x0003
	375
dfcd3bfb JM	376	extern unsigned ARMul_CoProInit (ARMul_State * state);
	377	extern void ARMul_CoProExit (ARMul_State * state);
	378	extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
	379	ARMul_CPInits * init, ARMul_CPExits * exit,
	380	ARMul_LDCs * ldc, ARMul_STCs * stc,
	381	ARMul_MRCs * mrc, ARMul_MCRs * mcr,
	382	ARMul_CDPs * cdp,
	383	ARMul_CPReads * read, ARMul_CPWrites * write);
	384	extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
c3ae2f98 MG	385	extern void XScale_check_memacc (ARMul_State * state, ARMword * address,
	386	int store);
	387	extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far);
	388	extern int XScale_debug_moe (ARMul_State * state, int moe);
c906108c SS	389
	390	/***************************************************************************\
	391	* Definitons of things in the host environment *
	392	\***************************************************************************/
	393
dfcd3bfb JM	394	extern unsigned ARMul_OSInit (ARMul_State * state);
	395	extern void ARMul_OSExit (ARMul_State * state);
	396	extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
	397	extern ARMword ARMul_OSLastErrorP (ARMul_State * state);
c906108c	398
dfcd3bfb JM	399	extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
	400	extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
	401	ARMword pc);
	402	extern int rdi_log;
c906108c SS	403
	404	/***************************************************************************\
	405	* Host-dependent stuff *
	406	\***************************************************************************/
	407
	408	#ifdef macintosh
dfcd3bfb	409	pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
c906108c	410	# define HOURGLASS SpinCursor( 1 )
dfcd3bfb	411	# define HOURGLASS_RATE 1023 /* 2^n - 1 */
c906108c	412	#endif
6d358e86 NC	413
	414	extern void ARMul_UndefInstr (ARMul_State *, ARMword);
	415	extern void ARMul_FixCPSR (ARMul_State *, ARMword, ARMword);
	416	extern void ARMul_FixSPSR (ARMul_State *, ARMword, ARMword);
	417	extern void ARMul_ConsolePrint (ARMul_State , const char , ...);
	418	extern void ARMul_SelectProcessor (ARMul_State *, unsigned);