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d4f3574e SS |
1 | /* Simulator parallel routines for CGEN simulators (and maybe others). |
2 | Copyright (C) 1999 Free Software Foundation, Inc. | |
3 | Contributed by Cygnus Solutions. | |
4 | ||
5 | This file is part of the GNU instruction set simulator. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include "sim-main.h" | |
22 | #include "cgen-mem.h" | |
23 | #include "cgen-par.h" | |
24 | ||
25 | /* Functions required by the cgen interface. These functions add various | |
26 | kinds of writes to the write queue. */ | |
c2c6d25f JM |
27 | void sim_queue_bi_write (SIM_CPU *cpu, BI *target, BI value) |
28 | { | |
29 | CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); | |
30 | CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); | |
31 | element->kind = CGEN_BI_WRITE; | |
32 | element->kinds.bi_write.target = target; | |
33 | element->kinds.bi_write.value = value; | |
34 | } | |
35 | ||
d4f3574e SS |
36 | void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value) |
37 | { | |
38 | CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); | |
39 | CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); | |
40 | element->kind = CGEN_QI_WRITE; | |
41 | element->kinds.qi_write.target = target; | |
42 | element->kinds.qi_write.value = value; | |
43 | } | |
44 | ||
45 | void sim_queue_si_write (SIM_CPU *cpu, SI *target, SI value) | |
46 | { | |
47 | CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); | |
48 | CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); | |
49 | element->kind = CGEN_SI_WRITE; | |
50 | element->kinds.si_write.target = target; | |
51 | element->kinds.si_write.value = value; | |
52 | } | |
53 | ||
54 | void sim_queue_sf_write (SIM_CPU *cpu, SI *target, SF value) | |
55 | { | |
56 | CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); | |
57 | CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); | |
58 | element->kind = CGEN_SF_WRITE; | |
59 | element->kinds.sf_write.target = target; | |
60 | element->kinds.sf_write.value = value; | |
61 | } | |
62 | ||
63 | void sim_queue_pc_write (SIM_CPU *cpu, USI value) | |
64 | { | |
65 | CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); | |
66 | CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); | |
67 | element->kind = CGEN_PC_WRITE; | |
68 | element->kinds.pc_write.value = value; | |
69 | } | |
70 | ||
71 | void sim_queue_fn_si_write ( | |
72 | SIM_CPU *cpu, | |
73 | void (*write_function)(SIM_CPU *cpu, UINT, USI), | |
74 | UINT regno, | |
75 | SI value | |
76 | ) | |
77 | { | |
78 | CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); | |
79 | CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); | |
80 | element->kind = CGEN_FN_SI_WRITE; | |
81 | element->kinds.fn_si_write.function = write_function; | |
82 | element->kinds.fn_si_write.regno = regno; | |
83 | element->kinds.fn_si_write.value = value; | |
84 | } | |
85 | ||
86 | void sim_queue_fn_di_write ( | |
87 | SIM_CPU *cpu, | |
88 | void (*write_function)(SIM_CPU *cpu, UINT, DI), | |
89 | UINT regno, | |
90 | DI value | |
91 | ) | |
92 | { | |
93 | CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); | |
94 | CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); | |
95 | element->kind = CGEN_FN_DI_WRITE; | |
96 | element->kinds.fn_di_write.function = write_function; | |
97 | element->kinds.fn_di_write.regno = regno; | |
98 | element->kinds.fn_di_write.value = value; | |
99 | } | |
100 | ||
101 | void sim_queue_fn_df_write ( | |
102 | SIM_CPU *cpu, | |
103 | void (*write_function)(SIM_CPU *cpu, UINT, DI), | |
104 | UINT regno, | |
105 | DF value | |
106 | ) | |
107 | { | |
108 | CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); | |
109 | CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); | |
110 | element->kind = CGEN_FN_DF_WRITE; | |
111 | element->kinds.fn_df_write.function = write_function; | |
112 | element->kinds.fn_df_write.regno = regno; | |
113 | element->kinds.fn_df_write.value = value; | |
114 | } | |
115 | ||
116 | void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value) | |
117 | { | |
118 | CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); | |
119 | CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); | |
120 | element->kind = CGEN_MEM_QI_WRITE; | |
121 | element->kinds.mem_qi_write.address = address; | |
122 | element->kinds.mem_qi_write.value = value; | |
123 | } | |
124 | ||
125 | void sim_queue_mem_hi_write (SIM_CPU *cpu, SI address, HI value) | |
126 | { | |
127 | CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); | |
128 | CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); | |
129 | element->kind = CGEN_MEM_HI_WRITE; | |
130 | element->kinds.mem_hi_write.address = address; | |
131 | element->kinds.mem_hi_write.value = value; | |
132 | } | |
133 | ||
134 | void sim_queue_mem_si_write (SIM_CPU *cpu, SI address, SI value) | |
135 | { | |
136 | CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); | |
137 | CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); | |
138 | element->kind = CGEN_MEM_SI_WRITE; | |
139 | element->kinds.mem_si_write.address = address; | |
140 | element->kinds.mem_si_write.value = value; | |
141 | } | |
142 | ||
143 | /* Execute a write stored on the write queue. */ | |
144 | void | |
145 | cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item) | |
146 | { | |
147 | IADDR pc; | |
148 | switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item)) | |
149 | { | |
c2c6d25f JM |
150 | case CGEN_BI_WRITE: |
151 | *item->kinds.bi_write.target = item->kinds.bi_write.value; | |
152 | break; | |
d4f3574e SS |
153 | case CGEN_QI_WRITE: |
154 | *item->kinds.qi_write.target = item->kinds.qi_write.value; | |
155 | break; | |
156 | case CGEN_SI_WRITE: | |
157 | *item->kinds.si_write.target = item->kinds.si_write.value; | |
158 | break; | |
159 | case CGEN_SF_WRITE: | |
160 | *item->kinds.sf_write.target = item->kinds.sf_write.value; | |
161 | break; | |
162 | case CGEN_PC_WRITE: | |
163 | CPU_PC_SET (cpu, item->kinds.pc_write.value); | |
164 | break; | |
165 | case CGEN_FN_SI_WRITE: | |
166 | item->kinds.fn_si_write.function (cpu, | |
167 | item->kinds.fn_si_write.regno, | |
168 | item->kinds.fn_si_write.value); | |
169 | break; | |
170 | case CGEN_FN_DI_WRITE: | |
171 | item->kinds.fn_di_write.function (cpu, | |
172 | item->kinds.fn_di_write.regno, | |
173 | item->kinds.fn_di_write.value); | |
174 | break; | |
175 | case CGEN_FN_DF_WRITE: | |
176 | item->kinds.fn_df_write.function (cpu, | |
177 | item->kinds.fn_df_write.regno, | |
178 | item->kinds.fn_df_write.value); | |
179 | break; | |
180 | case CGEN_MEM_QI_WRITE: | |
181 | pc = CPU_PC_GET (cpu); | |
182 | SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address, | |
183 | item->kinds.mem_qi_write.value); | |
184 | break; | |
185 | case CGEN_MEM_HI_WRITE: | |
186 | pc = CPU_PC_GET (cpu); | |
187 | SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address, | |
188 | item->kinds.mem_hi_write.value); | |
189 | break; | |
190 | case CGEN_MEM_SI_WRITE: | |
191 | pc = CPU_PC_GET (cpu); | |
192 | SETMEMSI (cpu, pc, item->kinds.mem_si_write.address, | |
193 | item->kinds.mem_si_write.value); | |
194 | break; | |
195 | default: | |
196 | break; /* FIXME: for now....print message later. */ | |
197 | } | |
198 | } | |
199 | ||
200 | /* Utilities for the write queue. */ | |
201 | CGEN_WRITE_QUEUE_ELEMENT * | |
202 | cgen_write_queue_overflow (CGEN_WRITE_QUEUE *q) | |
203 | { | |
204 | abort (); /* FIXME: for now....print message later. */ | |
205 | return 0; | |
206 | } |