[thirdparty/binutils-gdb.git] / sim / common / cgen-par.h

/* Simulator header for cgen parallel support.
   Copyright (C) 1999 Free Software Foundation, Inc.
   Contributed by Cygnus Solutions.

This file is part of the GNU instruction set simulator.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#ifndef CGEN_PAR_H
#define CGEN_PAR_H

/* Kinds of writes stored on the write queue.  */
enum cgen_write_queue_kind {
  CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
  CGEN_PC_WRITE,
  CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
  CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE,
  CGEN_NUM_WRITE_KINDS
};

/* Element of the write queue.  */
typedef struct {
  enum cgen_write_queue_kind kind; /* Used to select union member below.  */
  union {
    struct {
      BI  *target;
      BI   value;
    } bi_write;
    struct {
      UQI *target;
      QI   value;
    } qi_write;
    struct {
      SI *target;
      SI  value;
    } si_write;
    struct {
      SI *target;
      SF  value;
    } sf_write;
    struct {
      USI value;
    } pc_write;
    struct {
      UINT regno;
      UHI   value;
      void (*function)(SIM_CPU *, UINT, UHI);
    } fn_hi_write;
    struct {
      UINT regno;
      SI   value;
      void (*function)(SIM_CPU *, UINT, USI);
    } fn_si_write;
    struct {
      UINT regno;
      DI   value;
      void (*function)(SIM_CPU *, UINT, DI);
    } fn_di_write;
    struct {
      UINT regno;
      DI   value;
      void (*function)(SIM_CPU *, UINT, DI);
    } fn_df_write;
    struct {
      SI   address;
      QI   value;
    } mem_qi_write;
    struct {
      SI   address;
      HI   value;
    } mem_hi_write;
    struct {
      SI   address;
      SI   value;
    } mem_si_write;
  } kinds;
} CGEN_WRITE_QUEUE_ELEMENT;

#define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)

extern void cgen_write_queue_element_execute (
  SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *
);

/* Instance of the queue for parallel write-after support.  */
/* FIXME: Should be dynamic?  */
#define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now.  */

typedef struct {
  int index;
  CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
} CGEN_WRITE_QUEUE;

#define CGEN_WRITE_QUEUE_CLEAR(queue)       ((queue)->index = 0)
#define CGEN_WRITE_QUEUE_INDEX(queue)       ((queue)->index)
#define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])

#define CGEN_WRITE_QUEUE_NEXT(queue) (   \
  (queue)->index < CGEN_WRITE_QUEUE_SIZE \
    ? &(queue)->q[(queue)->index++]      \
    : cgen_write_queue_overflow (queue)  \
)

extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *);

/* Functions for queuing writes.  Used by semantic code.  */
extern void sim_queue_bi_write (SIM_CPU *, BI *, BI);
extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI);
extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);

extern void sim_queue_pc_write (SIM_CPU *, USI);

extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI);
extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI);
extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DF);

extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);

#endif /* CGEN_PAR_H */
Commit	Line	Data
d4f3574e SS	1	/* Simulator header for cgen parallel support.
	2	Copyright (C) 1999 Free Software Foundation, Inc.
	3	Contributed by Cygnus Solutions.
	4
	5	This file is part of the GNU instruction set simulator.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License along
	18	with this program; if not, write to the Free Software Foundation, Inc.,
	19	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21	#ifndef CGEN_PAR_H
	22	#define CGEN_PAR_H
	23
	24	/* Kinds of writes stored on the write queue. */
	25	enum cgen_write_queue_kind {
c2c6d25f	26	CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
d4f3574e	27	CGEN_PC_WRITE,
2df3850c	28	CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
d4f3574e SS	29	CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE,
	30	CGEN_NUM_WRITE_KINDS
	31	};
	32
	33	/* Element of the write queue. */
	34	typedef struct {
	35	enum cgen_write_queue_kind kind; /* Used to select union member below. */
	36	union {
c2c6d25f JM	37	struct {
	38	BI *target;
	39	BI value;
	40	} bi_write;
d4f3574e SS	41	struct {
	42	UQI *target;
	43	QI value;
	44	} qi_write;
	45	struct {
	46	SI *target;
	47	SI value;
	48	} si_write;
	49	struct {
	50	SI *target;
	51	SF value;
	52	} sf_write;
	53	struct {
	54	USI value;
	55	} pc_write;
2df3850c JM	56	struct {
	57	UINT regno;
	58	UHI value;
	59	void (function)(SIM_CPU , UINT, UHI);
	60	} fn_hi_write;
d4f3574e SS	61	struct {
	62	UINT regno;
	63	SI value;
	64	void (function)(SIM_CPU , UINT, USI);
	65	} fn_si_write;
	66	struct {
	67	UINT regno;
	68	DI value;
	69	void (function)(SIM_CPU , UINT, DI);
	70	} fn_di_write;
	71	struct {
	72	UINT regno;
	73	DI value;
	74	void (function)(SIM_CPU , UINT, DI);
	75	} fn_df_write;
	76	struct {
	77	SI address;
	78	QI value;
	79	} mem_qi_write;
	80	struct {
	81	SI address;
	82	HI value;
	83	} mem_hi_write;
	84	struct {
	85	SI address;
	86	SI value;
	87	} mem_si_write;
	88	} kinds;
	89	} CGEN_WRITE_QUEUE_ELEMENT;
	90
	91	#define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
	92
	93	extern void cgen_write_queue_element_execute (
	94	SIM_CPU , CGEN_WRITE_QUEUE_ELEMENT
	95	);
	96
	97	/* Instance of the queue for parallel write-after support. */
	98	/* FIXME: Should be dynamic? */
	99	#define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now. */
	100
	101	typedef struct {
	102	int index;
	103	CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
	104	} CGEN_WRITE_QUEUE;
	105
	106	#define CGEN_WRITE_QUEUE_CLEAR(queue) ((queue)->index = 0)
	107	#define CGEN_WRITE_QUEUE_INDEX(queue) ((queue)->index)
	108	#define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
	109
	110	#define CGEN_WRITE_QUEUE_NEXT(queue) ( \
	111	(queue)->index < CGEN_WRITE_QUEUE_SIZE \
	112	? &(queue)->q[(queue)->index++] \
	113	: cgen_write_queue_overflow (queue) \
	114	)
	115
	116	extern CGEN_WRITE_QUEUE_ELEMENT cgen_write_queue_overflow (CGEN_WRITE_QUEUE );
	117
	118	/* Functions for queuing writes. Used by semantic code. */
c2c6d25f	119	extern void sim_queue_bi_write (SIM_CPU , BI , BI);
d4f3574e SS	120	extern void sim_queue_qi_write (SIM_CPU , UQI , UQI);
	121	extern void sim_queue_si_write (SIM_CPU , SI , SI);
	122	extern void sim_queue_sf_write (SIM_CPU , SI , SF);
	123
	124	extern void sim_queue_pc_write (SIM_CPU *, USI);
	125
2df3850c	126	extern void sim_queue_fn_hi_write (SIM_CPU , void ()(SIM_CPU *, UINT, UHI), UINT, UHI);
d4f3574e SS	127	extern void sim_queue_fn_si_write (SIM_CPU , void ()(SIM_CPU *, UINT, USI), UINT, SI);
	128	extern void sim_queue_fn_di_write (SIM_CPU , void ()(SIM_CPU *, UINT, DI), UINT, DI);
	129	extern void sim_queue_fn_df_write (SIM_CPU , void ()(SIM_CPU *, UINT, DI), UINT, DF);
	130
	131	extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
	132	extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
	133	extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
	134
	135	#endif /* CGEN_PAR_H */