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e77fd269 DE |
1 | /* Simulator pseudo baseclass. |
2 | Copyright (C) 1997 Free Software Foundation, Inc. | |
3 | Contributed by Cygnus Support. | |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
e6a43446 DE |
21 | |
22 | /* Simulator state pseudo baseclass. | |
23 | ||
4b2a6aed AC |
24 | Each simulator is required to have the file ``sim-main.h''. That |
25 | file includes ``sim-basics.h'', defines the base type ``sim_cia'' | |
26 | (the data type that contains complete current instruction address | |
27 | information), include ``sim-base.h'': | |
e6a43446 DE |
28 | |
29 | #include "sim-basics.h" | |
30 | typedef address_word sim_cia; | |
31 | #include "sim-base.h" | |
32 | ||
4b2a6aed AC |
33 | finally, two data types ``struct _sim_cpu' and ``struct sim_state' |
34 | are defined: | |
e6a43446 DE |
35 | |
36 | struct _sim_cpu { | |
37 | ... simulator specific members ... | |
38 | sim_cpu_base base; | |
39 | }; | |
40 | ||
e6a43446 DE |
41 | struct sim_state { |
42 | sim_cpu cpu[MAX_NR_PROCESSORS]; | |
43 | #if (WITH_SMP) | |
44 | #define STATE_CPU(sd,n) (&(sd)->cpu[n]) | |
45 | #else | |
46 | #define STATE_CPU(sd,n) (&(sd)->cpu[0]) | |
47 | #endif | |
48 | ... simulator specific members ... | |
49 | sim_state_base base; | |
50 | }; | |
51 | ||
52 | Note that `base' appears last. This makes `base.magic' appear last | |
53 | in the entire struct and helps catch miscompilation errors. */ | |
54 | ||
e77fd269 DE |
55 | |
56 | #ifndef SIM_BASE_H | |
57 | #define SIM_BASE_H | |
58 | ||
e6a43446 DE |
59 | /* Pre-declare certain types. */ |
60 | ||
61 | /* typedef <target-dependant> sim_cia; */ | |
62 | #ifndef NULL_CIA | |
63 | #define NULL_CIA ((sim_cia) 0) | |
64 | #endif | |
e5ce1670 DE |
65 | /* Return the current instruction address as a number. |
66 | Some targets treat the current instruction address as a struct | |
67 | (e.g. for delay slot handling). */ | |
68 | #ifndef CIA_ADDR | |
69 | #define CIA_ADDR(cia) (cia) | |
70 | #endif | |
4b2a6aed AC |
71 | #ifndef INVALID_INSTRUCTION_ADDRESS |
72 | #define INVALID_INSTRUCTION_ADDRESS ((address_word)0 - 1) | |
73 | #endif | |
e5ce1670 | 74 | |
e6a43446 DE |
75 | typedef struct _sim_cpu sim_cpu; |
76 | ||
77 | #include "sim-module.h" | |
18c319ae | 78 | |
e6a43446 | 79 | #include "sim-trace.h" |
e6a43446 DE |
80 | #include "sim-core.h" |
81 | #include "sim-events.h" | |
4ca7d6d2 AC |
82 | #include "sim-profile.h" |
83 | #ifdef SIM_HAVE_MODEL | |
84 | #include "sim-model.h" | |
85 | #endif | |
e6a43446 | 86 | #include "sim-io.h" |
18c319ae AC |
87 | #include "sim-engine.h" |
88 | #include "sim-watch.h" | |
a34abff8 | 89 | #include "sim-memopt.h" |
e5ce1670 DE |
90 | #ifdef SIM_HAVE_BREAKPOINTS |
91 | #include "sim-break.h" | |
92 | #endif | |
e6a43446 | 93 | |
e77fd269 DE |
94 | /* Global pointer to current state while sim_resume is running. |
95 | On a machine with lots of registers, it might be possible to reserve | |
96 | one of them for current_state. However on a machine with few registers | |
97 | current_state can't permanently live in one and indirecting through it | |
98 | will be slower [in which case one can have sim_resume set globals from | |
99 | current_state for faster access]. | |
100 | If CURRENT_STATE_REG is defined, it means current_state is living in | |
101 | a global register. */ | |
102 | ||
e6a43446 | 103 | |
e77fd269 DE |
104 | #ifdef CURRENT_STATE_REG |
105 | /* FIXME: wip */ | |
106 | #else | |
107 | extern struct sim_state *current_state; | |
108 | #endif | |
109 | ||
e6a43446 | 110 | |
0f2811d1 DE |
111 | /* The simulator may provide different (and faster) definition. */ |
112 | #ifndef CURRENT_STATE | |
113 | #define CURRENT_STATE current_state | |
114 | #endif | |
115 | ||
0f2811d1 DE |
116 | |
117 | typedef struct { | |
e6a43446 | 118 | |
e77fd269 DE |
119 | /* Simulator's argv[0]. */ |
120 | const char *my_name; | |
121 | #define STATE_MY_NAME(sd) ((sd)->base.my_name) | |
122 | ||
123 | /* Who opened the simulator. */ | |
124 | SIM_OPEN_KIND open_kind; | |
125 | #define STATE_OPEN_KIND(sd) ((sd)->base.open_kind) | |
126 | ||
127 | /* The host callbacks. */ | |
128 | struct host_callback_struct *callback; | |
129 | #define STATE_CALLBACK(sd) ((sd)->base.callback) | |
130 | ||
131 | #if 0 /* FIXME: Not ready yet. */ | |
132 | /* Stuff defined in sim-config.h. */ | |
133 | struct sim_config config; | |
134 | #define STATE_CONFIG(sd) ((sd)->base.config) | |
135 | #endif | |
0f2811d1 | 136 | |
c967f187 DE |
137 | /* List of installed module `init' handlers. */ |
138 | MODULE_INIT_LIST *init_list; | |
139 | #define STATE_INIT_LIST(sd) ((sd)->base.init_list) | |
140 | /* List of installed module `uninstall' handlers. */ | |
141 | MODULE_UNINSTALL_LIST *uninstall_list; | |
142 | #define STATE_UNINSTALL_LIST(sd) ((sd)->base.uninstall_list) | |
fdd64f95 AC |
143 | /* List of installed module `resume' handlers. */ |
144 | MODULE_RESUME_LIST *resume_list; | |
145 | #define STATE_RESUME_LIST(sd) ((sd)->base.resume_list) | |
146 | /* List of installed module `suspend' handlers. */ | |
147 | MODULE_SUSPEND_LIST *suspend_list; | |
148 | #define STATE_SUSPEND_LIST(sd) ((sd)->base.suspend_list) | |
c967f187 | 149 | |
4ca7d6d2 | 150 | #ifdef SIM_HAVE_MODEL |
c967f187 DE |
151 | /* ??? This might be more appropriate in sim_cpu. */ |
152 | /* Machine tables for this cpu. See sim-model.h. */ | |
153 | const MODEL *model; | |
154 | #define STATE_MODEL(sd) ((sd)->base.model) | |
4ca7d6d2 | 155 | #endif |
c967f187 | 156 | |
0f2811d1 DE |
157 | /* Supported options. */ |
158 | struct option_list *options; | |
159 | #define STATE_OPTIONS(sd) ((sd)->base.options) | |
160 | ||
161 | /* Non-zero if -v specified. */ | |
162 | int verbose_p; | |
163 | #define STATE_VERBOSE_P(sd) ((sd)->base.verbose_p) | |
164 | ||
e5ce1670 DE |
165 | /* Non cpu-specific trace data. See sim-trace.h. */ |
166 | TRACE_DATA trace_data; | |
167 | #define STATE_TRACE_DATA(sd) (& (sd)->base.trace_data) | |
168 | ||
18c319ae AC |
169 | /* If non NULL, the BFD architecture specified on the command line */ |
170 | const struct bfd_arch_info *architecture; | |
171 | #define STATE_ARCHITECTURE(sd) ((sd)->base.architecture) | |
172 | ||
173 | /* If non NULL, the bfd target specified on the command line */ | |
174 | const char *target; | |
175 | #define STATE_TARGET(sd) ((sd)->base.target) | |
176 | ||
0f2811d1 DE |
177 | /* In standalone simulator, this is the program's arguments passed |
178 | on the command line. */ | |
179 | char **prog_argv; | |
180 | #define STATE_PROG_ARGV(sd) ((sd)->base.prog_argv) | |
181 | ||
182 | /* The program's bfd. */ | |
183 | struct _bfd *prog_bfd; | |
184 | #define STATE_PROG_BFD(sd) ((sd)->base.prog_bfd) | |
185 | ||
186 | /* The program's text section. */ | |
187 | struct sec *text_section; | |
188 | /* Starting and ending text section addresses from the bfd. */ | |
189 | SIM_ADDR text_start, text_end; | |
190 | #define STATE_TEXT_SECTION(sd) ((sd)->base.text_section) | |
191 | #define STATE_TEXT_START(sd) ((sd)->base.text_start) | |
192 | #define STATE_TEXT_END(sd) ((sd)->base.text_end) | |
193 | ||
194 | /* Start address, set when the program is loaded from the bfd. */ | |
195 | SIM_ADDR start_addr; | |
196 | #define STATE_START_ADDR(sd) ((sd)->base.start_addr) | |
197 | ||
c967f187 | 198 | #if WITH_SCACHE |
0f2811d1 DE |
199 | /* Size of the simulator's cache, if any. |
200 | This is not the target's cache. It is the cache the simulator uses | |
201 | to process instructions. */ | |
c967f187 DE |
202 | unsigned int scache_size; |
203 | #define STATE_SCACHE_SIZE(sd) ((sd)->base.scache_size) | |
204 | #endif | |
0f2811d1 DE |
205 | |
206 | /* FIXME: Move to top level sim_state struct (as some struct)? */ | |
207 | #ifdef SIM_HAVE_FLATMEM | |
208 | unsigned int mem_size; | |
209 | #define STATE_MEM_SIZE(sd) ((sd)->base.mem_size) | |
18c319ae AC |
210 | unsigned int mem_base; |
211 | #define STATE_MEM_BASE(sd) ((sd)->base.mem_base) | |
0f2811d1 DE |
212 | unsigned char *memory; |
213 | #define STATE_MEMORY(sd) ((sd)->base.memory) | |
214 | #endif | |
215 | ||
e6a43446 DE |
216 | /* core memory bus */ |
217 | #define STATE_CORE(sd) (&(sd)->base.core) | |
218 | sim_core core; | |
219 | ||
a34abff8 AC |
220 | /* memory-options for managing the core */ |
221 | #define STATE_MEMOPT(sd) ((sd)->base.memopt) | |
a34abff8 AC |
222 | sim_memopt *memopt; |
223 | ||
e6a43446 DE |
224 | /* event handler */ |
225 | #define STATE_EVENTS(sd) (&(sd)->base.events) | |
226 | sim_events events; | |
227 | ||
18c319ae AC |
228 | /* generic halt/resume engine */ |
229 | sim_engine engine; | |
230 | #define STATE_ENGINE(sd) (&(sd)->base.engine) | |
231 | ||
232 | /* generic watchpoint support */ | |
233 | sim_watchpoints watchpoints; | |
234 | #define STATE_WATCHPOINTS(sd) (&(sd)->base.watchpoints) | |
235 | ||
e5ce1670 DE |
236 | /* Pointer to list of breakpoints */ |
237 | struct sim_breakpoint *breakpoints; | |
238 | #define STATE_BREAKPOINTS(sd) ((sd)->base.breakpoints) | |
239 | ||
0f2811d1 DE |
240 | /* Marker for those wanting to do sanity checks. |
241 | This should remain the last member of this struct to help catch | |
242 | miscompilation errors. */ | |
243 | int magic; | |
244 | #define SIM_MAGIC_NUMBER 0x4242 | |
245 | #define STATE_MAGIC(sd) ((sd)->base.magic) | |
246 | } sim_state_base; | |
247 | ||
e6a43446 | 248 | |
0f2811d1 DE |
249 | /* Pseudo baseclass for each cpu. */ |
250 | ||
251 | typedef struct { | |
e6a43446 | 252 | |
0f2811d1 | 253 | /* Backlink to main state struct. */ |
c967f187 DE |
254 | SIM_DESC state; |
255 | #define CPU_STATE(cpu) ((cpu)->base.state) | |
0f2811d1 | 256 | |
7a418800 | 257 | /* Processor specific core data */ |
7a418800 | 258 | sim_cpu_core core; |
18c319ae | 259 | #define CPU_CORE(cpu) (& (cpu)->base.core) |
7a418800 | 260 | |
c967f187 DE |
261 | /* Trace data. See sim-trace.h. */ |
262 | TRACE_DATA trace_data; | |
263 | #define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data) | |
0f2811d1 DE |
264 | |
265 | /* Maximum number of debuggable entities. | |
266 | This debugging is not intended for normal use. | |
267 | It is only enabled when the simulator is configured with --with-debug | |
268 | which shouldn't normally be specified. */ | |
269 | #ifndef MAX_DEBUG_VALUES | |
270 | #define MAX_DEBUG_VALUES 4 | |
271 | #endif | |
272 | ||
273 | /* Boolean array of specified debugging flags. */ | |
274 | char debug_flags[MAX_DEBUG_VALUES]; | |
275 | #define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags) | |
276 | /* Standard values. */ | |
277 | #define DEBUG_INSN_IDX 0 | |
278 | #define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */ | |
279 | ||
280 | /* Debugging output goes to this or stderr if NULL. | |
281 | We can't store `stderr' here as stderr goes through a callback. */ | |
282 | FILE *debug_file; | |
5bfbd725 | 283 | #define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file) |
0f2811d1 | 284 | |
c967f187 DE |
285 | /* Profile data. See sim-profile.h. */ |
286 | PROFILE_DATA profile_data; | |
287 | #define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data) | |
e6a43446 | 288 | |
0f2811d1 | 289 | } sim_cpu_base; |
e77fd269 | 290 | |
e6a43446 | 291 | |
e77fd269 | 292 | /* Functions for allocating/freeing a sim_state. */ |
4b2a6aed | 293 | SIM_DESC sim_state_alloc PARAMS ((SIM_OPEN_KIND kind, host_callback *callback)); |
e77fd269 DE |
294 | void sim_state_free PARAMS ((SIM_DESC)); |
295 | ||
e6a43446 | 296 | |
e77fd269 | 297 | #endif /* SIM_BASE_H */ |