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c906108c SS |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | ||
19 | */ | |
20 | ||
21 | ||
22 | #ifndef N | |
23 | #error "N must be #defined" | |
24 | #endif | |
25 | #ifndef M | |
26 | #define M N | |
27 | #endif | |
28 | ||
29 | /* N: The number of bytes of data to transfer. | |
30 | M: The number of bytes in the type used to transfer the data */ | |
31 | ||
32 | #if (N > M) | |
33 | #error "N (nr bytes of data) must be <= M (nr of bytes in data type)" | |
34 | #endif | |
35 | ||
36 | ||
37 | #include "symcat.h" | |
38 | ||
39 | /* NOTE: see end of file for #undef of these macros */ | |
40 | ||
41 | #define unsigned_M XCONCAT2(unsigned_,M) | |
42 | ||
43 | #define T2H_M XCONCAT2(T2H_,M) | |
44 | #define H2T_M XCONCAT2(H2T_,M) | |
45 | #define SWAP_M XCONCAT2(SWAP_,M) | |
46 | ||
47 | #define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N) | |
48 | #define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N) | |
49 | #define sim_core_read_misaligned_N XCONCAT2(sim_core_read_misaligned_,N) | |
50 | #define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N) | |
51 | #define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N) | |
52 | #define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N) | |
53 | #define sim_core_trace_M XCONCAT2(sim_core_trace_,M) | |
54 | #define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M) | |
55 | ||
56 | ||
57 | #if (M == N && N > 1) | |
58 | /* dummy variable used as a return value when nothing else is | |
59 | available and the compiler is complaining */ | |
60 | static unsigned_M sim_core_dummy_M; | |
61 | #endif | |
62 | ||
63 | ||
64 | /* TAGS: sim_core_trace_1 sim_core_trace_2 */ | |
65 | /* TAGS: sim_core_trace_4 sim_core_trace_8 */ | |
66 | /* TAGS: sim_core_trace_16 */ | |
67 | ||
68 | #if (M == N) | |
69 | STATIC_SIM_CORE(void) | |
70 | sim_core_trace_M (sim_cpu *cpu, | |
71 | sim_cia cia, | |
72 | int line_nr, | |
73 | transfer_type type, | |
74 | unsigned map, | |
75 | address_word addr, | |
76 | unsigned_M val, | |
77 | int nr_bytes) | |
78 | { | |
79 | const char *transfer = (type == read_transfer ? "read" : "write"); | |
80 | const char *direction = (type == read_transfer ? "->" : "<-"); | |
81 | ||
82 | if (TRACE_DEBUG_P (cpu)) | |
83 | trace_printf (CPU_STATE (cpu), cpu, "sim-n-core.h:%d: ", line_nr); | |
84 | ||
85 | #if (M == 16) | |
86 | trace_printf (CPU_STATE (cpu), cpu, | |
87 | "%s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx\n", | |
88 | transfer, nr_bytes, | |
89 | map_to_str (map), | |
90 | (unsigned long) addr, | |
91 | direction, | |
92 | (unsigned long) V4_16 (val, 0), | |
93 | (unsigned long) V4_16 (val, 1), | |
94 | (unsigned long) V4_16 (val, 2), | |
95 | (unsigned long) V4_16 (val, 3)); | |
96 | #endif | |
97 | #if (M == 8) | |
98 | trace_printf (CPU_STATE (cpu), cpu, | |
99 | "%s-%d %s:0x%08lx %s 0x%08lx%08lx\n", | |
100 | transfer, nr_bytes, | |
101 | map_to_str (map), | |
102 | (unsigned long) addr, | |
103 | direction, | |
104 | (unsigned long) V4_8 (val, 0), | |
105 | (unsigned long) V4_8 (val, 1)); | |
106 | #endif | |
107 | #if (M == 4) | |
108 | trace_printf (CPU_STATE (cpu), cpu, | |
109 | "%s-%d %s:0x%08lx %s 0x%08lx\n", | |
110 | transfer, | |
111 | nr_bytes, | |
112 | map_to_str (map), | |
113 | (unsigned long) addr, | |
114 | direction, | |
115 | (unsigned long) val); | |
116 | #endif | |
117 | #if (M == 2) | |
118 | trace_printf (CPU_STATE (cpu), cpu, | |
119 | "%s-%d %s:0x%08lx %s 0x%04lx\n", | |
120 | transfer, | |
121 | nr_bytes, | |
122 | map_to_str (map), | |
123 | (unsigned long) addr, | |
124 | direction, | |
125 | (unsigned long) val); | |
126 | #endif | |
127 | #if (M == 1) | |
128 | trace_printf (CPU_STATE (cpu), cpu, | |
129 | "%s-%d %s:0x%08lx %s 0x%02lx\n", | |
130 | transfer, | |
131 | nr_bytes, | |
132 | map_to_str (map), | |
133 | (unsigned long) addr, | |
134 | direction, | |
135 | (unsigned long) val); | |
136 | #endif | |
137 | } | |
138 | #endif | |
139 | ||
140 | ||
141 | /* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */ | |
142 | /* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */ | |
143 | /* TAGS: sim_core_read_aligned_16 */ | |
144 | ||
145 | #if (M == N) | |
146 | INLINE_SIM_CORE(unsigned_M) | |
147 | sim_core_read_aligned_N(sim_cpu *cpu, | |
148 | sim_cia cia, | |
149 | unsigned map, | |
150 | address_word xaddr) | |
151 | { | |
152 | sim_cpu_core *cpu_core = CPU_CORE (cpu); | |
153 | sim_core_common *core = &cpu_core->common; | |
154 | unsigned_M val; | |
155 | sim_core_mapping *mapping; | |
156 | address_word addr; | |
157 | #if WITH_XOR_ENDIAN != 0 | |
158 | if (WITH_XOR_ENDIAN) | |
159 | addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN]; | |
160 | else | |
161 | #endif | |
162 | addr = xaddr; | |
163 | mapping = sim_core_find_mapping (core, map, addr, N, read_transfer, 1 /*abort*/, cpu, cia); | |
164 | do | |
165 | { | |
166 | #if (WITH_DEVICES) | |
167 | if (WITH_CALLBACK_MEMORY && mapping->device != NULL) | |
168 | { | |
169 | unsigned_M data; | |
170 | if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N) | |
171 | device_error (mapping->device, "internal error - %s - io_read_buffer should not fail", | |
172 | XSTRING (sim_core_read_aligned_N)); | |
173 | val = T2H_M (data); | |
174 | break; | |
175 | } | |
176 | #endif | |
177 | #if (WITH_HW) | |
178 | if (WITH_CALLBACK_MEMORY && mapping->device != NULL) | |
179 | { | |
180 | unsigned_M data; | |
181 | sim_cpu_hw_io_read_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N); | |
182 | val = T2H_M (data); | |
183 | break; | |
184 | } | |
185 | #endif | |
186 | val = T2H_M (*(unsigned_M*) sim_core_translate (mapping, addr)); | |
187 | } | |
188 | while (0); | |
189 | PROFILE_COUNT_CORE (cpu, addr, N, map); | |
190 | if (TRACE_P (cpu, TRACE_CORE_IDX)) | |
191 | sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N); | |
192 | return val; | |
193 | } | |
194 | #endif | |
195 | ||
196 | /* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */ | |
197 | /* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */ | |
198 | /* TAGS: sim_core_read_unaligned_16 */ | |
199 | ||
200 | #if (M == N && N > 1) | |
201 | INLINE_SIM_CORE(unsigned_M) | |
202 | sim_core_read_unaligned_N(sim_cpu *cpu, | |
203 | sim_cia cia, | |
204 | unsigned map, | |
205 | address_word addr) | |
206 | { | |
207 | int alignment = N - 1; | |
208 | /* if hardwired to forced alignment just do it */ | |
209 | if (WITH_ALIGNMENT == FORCED_ALIGNMENT) | |
210 | return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment); | |
211 | else if ((addr & alignment) == 0) | |
212 | return sim_core_read_aligned_N (cpu, cia, map, addr); | |
213 | else | |
214 | switch (CURRENT_ALIGNMENT) | |
215 | { | |
216 | case STRICT_ALIGNMENT: | |
217 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr, | |
218 | read_transfer, sim_core_unaligned_signal); | |
219 | case NONSTRICT_ALIGNMENT: | |
220 | { | |
221 | unsigned_M val; | |
222 | if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N) | |
223 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr, | |
224 | read_transfer, sim_core_unaligned_signal); | |
225 | val = T2H_M(val); | |
226 | PROFILE_COUNT_CORE (cpu, addr, N, map); | |
227 | if (TRACE_P (cpu, TRACE_CORE_IDX)) | |
228 | sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N); | |
229 | return val; | |
230 | } | |
231 | case FORCED_ALIGNMENT: | |
232 | return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment); | |
233 | case MIXED_ALIGNMENT: | |
234 | sim_engine_abort (CPU_STATE (cpu), cpu, cia, | |
235 | "internal error - %s - mixed alignment", | |
236 | XSTRING (sim_core_read_unaligned_N)); | |
237 | default: | |
238 | sim_engine_abort (CPU_STATE (cpu), cpu, cia, | |
239 | "internal error - %s - bad switch", | |
240 | XSTRING (sim_core_read_unaligned_N)); | |
241 | /* to keep some compilers happy, we return a dummy */ | |
242 | return sim_core_dummy_M; | |
243 | } | |
244 | } | |
245 | #endif | |
246 | ||
247 | /* TAGS: sim_core_read_misaligned_3 sim_core_read_misaligned_5 */ | |
248 | /* TAGS: sim_core_read_misaligned_6 sim_core_read_misaligned_7 */ | |
249 | ||
250 | #if (M != N) | |
251 | INLINE_SIM_CORE(unsigned_M) | |
252 | sim_core_read_misaligned_N(sim_cpu *cpu, | |
253 | sim_cia cia, | |
254 | unsigned map, | |
255 | address_word addr) | |
256 | { | |
257 | unsigned_M val = 0; | |
258 | if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N) | |
259 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr, | |
260 | read_transfer, sim_core_unaligned_signal); | |
261 | if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER) | |
262 | val = SWAP_M (val); | |
263 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) | |
264 | val >>= (M - N) * 8; | |
265 | PROFILE_COUNT_CORE (cpu, addr, N, map); | |
266 | if (TRACE_P (cpu, TRACE_CORE_IDX)) | |
267 | sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N); | |
268 | return val; | |
269 | } | |
270 | #endif | |
271 | ||
272 | /* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */ | |
273 | /* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */ | |
274 | /* TAGS: sim_core_write_aligned_16 */ | |
275 | ||
276 | #if (M == N) | |
277 | INLINE_SIM_CORE(void) | |
278 | sim_core_write_aligned_N(sim_cpu *cpu, | |
279 | sim_cia cia, | |
280 | unsigned map, | |
281 | address_word xaddr, | |
282 | unsigned_M val) | |
283 | { | |
284 | sim_cpu_core *cpu_core = CPU_CORE (cpu); | |
285 | sim_core_common *core = &cpu_core->common; | |
286 | sim_core_mapping *mapping; | |
287 | address_word addr; | |
288 | #if WITH_XOR_ENDIAN != 0 | |
289 | if (WITH_XOR_ENDIAN) | |
290 | addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN]; | |
291 | else | |
292 | #endif | |
293 | addr = xaddr; | |
294 | mapping = sim_core_find_mapping (core, map, addr, N, write_transfer, 1 /*abort*/, cpu, cia); | |
295 | do | |
296 | { | |
297 | #if (WITH_DEVICES) | |
298 | if (WITH_CALLBACK_MEMORY && mapping->device != NULL) | |
299 | { | |
300 | unsigned_M data = H2T_M (val); | |
301 | if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N) | |
302 | device_error (mapping->device, "internal error - %s - io_write_buffer should not fail", | |
303 | XSTRING (sim_core_write_aligned_N)); | |
304 | break; | |
305 | } | |
306 | #endif | |
307 | #if (WITH_HW) | |
308 | if (WITH_CALLBACK_MEMORY && mapping->device != NULL) | |
309 | { | |
310 | unsigned_M data = H2T_M (val); | |
311 | sim_cpu_hw_io_write_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N); | |
312 | break; | |
313 | } | |
314 | #endif | |
315 | *(unsigned_M*) sim_core_translate (mapping, addr) = H2T_M (val); | |
316 | } | |
317 | while (0); | |
318 | PROFILE_COUNT_CORE (cpu, addr, N, map); | |
319 | if (TRACE_P (cpu, TRACE_CORE_IDX)) | |
320 | sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N); | |
321 | } | |
322 | #endif | |
323 | ||
324 | /* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */ | |
325 | /* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */ | |
326 | /* TAGS: sim_core_write_unaligned_16 */ | |
327 | ||
328 | #if (M == N && N > 1) | |
329 | INLINE_SIM_CORE(void) | |
330 | sim_core_write_unaligned_N(sim_cpu *cpu, | |
331 | sim_cia cia, | |
332 | unsigned map, | |
333 | address_word addr, | |
334 | unsigned_M val) | |
335 | { | |
336 | int alignment = N - 1; | |
337 | /* if hardwired to forced alignment just do it */ | |
338 | if (WITH_ALIGNMENT == FORCED_ALIGNMENT) | |
339 | sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val); | |
340 | else if ((addr & alignment) == 0) | |
341 | sim_core_write_aligned_N (cpu, cia, map, addr, val); | |
342 | else | |
343 | switch (CURRENT_ALIGNMENT) | |
344 | { | |
345 | case STRICT_ALIGNMENT: | |
346 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr, | |
347 | write_transfer, sim_core_unaligned_signal); | |
348 | break; | |
349 | case NONSTRICT_ALIGNMENT: | |
350 | { | |
351 | unsigned_M data = H2T_M (val); | |
352 | if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N) | |
353 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr, | |
354 | write_transfer, sim_core_unaligned_signal); | |
355 | PROFILE_COUNT_CORE (cpu, addr, N, map); | |
356 | if (TRACE_P (cpu, TRACE_CORE_IDX)) | |
357 | sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N); | |
358 | break; | |
359 | } | |
360 | case FORCED_ALIGNMENT: | |
361 | sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val); | |
362 | break; | |
363 | case MIXED_ALIGNMENT: | |
364 | sim_engine_abort (CPU_STATE (cpu), cpu, cia, | |
365 | "internal error - %s - mixed alignment", | |
366 | XSTRING (sim_core_write_unaligned_N)); | |
367 | break; | |
368 | default: | |
369 | sim_engine_abort (CPU_STATE (cpu), cpu, cia, | |
370 | "internal error - %s - bad switch", | |
371 | XSTRING (sim_core_write_unaligned_N)); | |
372 | break; | |
373 | } | |
374 | } | |
375 | #endif | |
376 | ||
377 | /* TAGS: sim_core_write_misaligned_3 sim_core_write_misaligned_5 */ | |
378 | /* TAGS: sim_core_write_misaligned_6 sim_core_write_misaligned_7 */ | |
379 | ||
380 | #if (M != N) | |
381 | INLINE_SIM_CORE(void) | |
382 | sim_core_write_misaligned_N(sim_cpu *cpu, | |
383 | sim_cia cia, | |
384 | unsigned map, | |
385 | address_word addr, | |
386 | unsigned_M val) | |
387 | { | |
388 | unsigned_M data = val; | |
389 | if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) | |
390 | data <<= (M - N) * 8; | |
391 | if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER) | |
392 | data = SWAP_M (data); | |
393 | if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N) | |
394 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr, | |
395 | write_transfer, sim_core_unaligned_signal); | |
396 | PROFILE_COUNT_CORE (cpu, addr, N, map); | |
397 | if (TRACE_P (cpu, TRACE_CORE_IDX)) | |
398 | sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N); | |
399 | } | |
400 | #endif | |
401 | ||
402 | ||
403 | /* NOTE: see start of file for #define of these macros */ | |
404 | #undef unsigned_M | |
405 | #undef T2H_M | |
406 | #undef H2T_M | |
407 | #undef SWAP_M | |
408 | #undef sim_core_read_aligned_N | |
409 | #undef sim_core_read_unaligned_N | |
410 | #undef sim_core_read_misaligned_N | |
411 | #undef sim_core_write_aligned_N | |
412 | #undef sim_core_write_unaligned_N | |
413 | #undef sim_core_write_misaligned_N | |
414 | #undef sim_core_trace_M | |
415 | #undef sim_core_dummy_M | |
416 | #undef M | |
417 | #undef N |