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fee8ec00 | 1 | /* Simulation code for the CR16 processor. |
3666a048 | 2 | Copyright (C) 2008-2021 Free Software Foundation, Inc. |
fee8ec00 SR |
3 | Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com> |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
dc3cf14f | 9 | the Free Software Foundation; either version 3, or (at your option) |
fee8ec00 SR |
10 | any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
8e26b0f4 SR |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
fee8ec00 | 20 | |
fee8ec00 SR |
21 | #include <stdio.h> |
22 | #include <ctype.h> | |
23 | #include <limits.h> | |
24 | #include "ansidecl.h" | |
df68e12b | 25 | #include "sim/callback.h" |
fee8ec00 SR |
26 | #include "opcode/cr16.h" |
27 | #include "bfd.h" | |
28 | ||
29 | #define DEBUG_TRACE 0x00000001 | |
30 | #define DEBUG_VALUES 0x00000002 | |
31 | #define DEBUG_LINE_NUMBER 0x00000004 | |
32 | #define DEBUG_MEMSIZE 0x00000008 | |
33 | #define DEBUG_INSTRUCTION 0x00000010 | |
34 | #define DEBUG_TRAP 0x00000020 | |
35 | #define DEBUG_MEMORY 0x00000040 | |
36 | ||
37 | #ifndef DEBUG | |
38 | #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER) | |
39 | #endif | |
40 | ||
41 | extern int cr16_debug; | |
42 | ||
df68e12b | 43 | #include "sim/sim.h" |
fee8ec00 SR |
44 | #include "sim-config.h" |
45 | #include "sim-types.h" | |
46 | ||
47 | typedef unsigned8 uint8; | |
48 | typedef signed8 int8; | |
49 | typedef unsigned16 uint16; | |
50 | typedef signed16 int16; | |
51 | typedef unsigned32 uint32; | |
52 | typedef signed32 int32; | |
53 | typedef unsigned64 uint64; | |
54 | typedef signed64 int64; | |
55 | ||
56 | /* FIXME: CR16 defines */ | |
57 | typedef uint16 reg_t; | |
58 | typedef uint32 creg_t; | |
59 | ||
60 | struct simops | |
61 | { | |
8e26b0f4 SR |
62 | char mnimonic[12]; |
63 | uint32 size; | |
64 | uint32 mask; | |
65 | uint32 opcode; | |
fee8ec00 | 66 | int format; |
8e26b0f4 | 67 | char fname[12]; |
267b3b8e | 68 | void (*func)(SIM_DESC, SIM_CPU *); |
fee8ec00 | 69 | int numops; |
8e26b0f4 | 70 | operand_desc operands[4]; |
fee8ec00 SR |
71 | }; |
72 | ||
73 | enum _ins_type | |
74 | { | |
75 | INS_UNKNOWN, /* unknown instruction */ | |
76 | INS_NO_TYPE_INS, | |
77 | INS_ARITH_INS, | |
78 | INS_LD_STOR_INS, | |
79 | INS_BRANCH_INS, | |
80 | INS_ARITH_BYTE_INS, | |
81 | INS_SHIFT_INS, | |
82 | INS_BRANCH_NEQ_INS, | |
83 | INS_STOR_IMM_INS, | |
84 | INS_CSTBIT_INS, | |
85 | INS_MAX | |
86 | }; | |
87 | ||
88 | extern unsigned long ins_type_counters[ (int)INS_MAX ]; | |
89 | ||
90 | enum { | |
91 | SP_IDX = 15, | |
92 | }; | |
93 | ||
94 | /* Write-back slots */ | |
95 | union slot_data { | |
96 | unsigned_1 _1; | |
97 | unsigned_2 _2; | |
98 | unsigned_4 _4; | |
99 | }; | |
100 | struct slot { | |
101 | void *dest; | |
102 | int size; | |
103 | union slot_data data; | |
104 | union slot_data mask; | |
105 | }; | |
106 | enum { | |
107 | NR_SLOTS = 16 | |
108 | }; | |
109 | #define SLOT (State.slot) | |
110 | #define SLOT_NR (State.slot_nr) | |
111 | #define SLOT_PEND_MASK(DEST, MSK, VAL) \ | |
112 | do \ | |
113 | { \ | |
114 | SLOT[SLOT_NR].dest = &(DEST); \ | |
115 | SLOT[SLOT_NR].size = sizeof (DEST); \ | |
116 | switch (sizeof (DEST)) \ | |
117 | { \ | |
118 | case 1: \ | |
119 | SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \ | |
120 | SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \ | |
121 | break; \ | |
122 | case 2: \ | |
123 | SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \ | |
124 | SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \ | |
125 | break; \ | |
126 | case 4: \ | |
127 | SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \ | |
128 | SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \ | |
129 | break; \ | |
130 | } \ | |
131 | SLOT_NR = (SLOT_NR + 1); \ | |
132 | } \ | |
133 | while (0) | |
134 | #define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL) | |
135 | #define SLOT_DISCARD() (SLOT_NR = 0) | |
136 | #define SLOT_FLUSH() \ | |
137 | do \ | |
138 | { \ | |
139 | int i; \ | |
140 | for (i = 0; i < SLOT_NR; i++) \ | |
141 | { \ | |
142 | switch (SLOT[i].size) \ | |
143 | { \ | |
144 | case 1: \ | |
145 | *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \ | |
146 | *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \ | |
147 | break; \ | |
148 | case 2: \ | |
149 | *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \ | |
150 | *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \ | |
151 | break; \ | |
152 | case 4: \ | |
153 | *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \ | |
154 | *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \ | |
155 | break; \ | |
156 | } \ | |
157 | } \ | |
158 | SLOT_NR = 0; \ | |
159 | } \ | |
160 | while (0) | |
161 | #define SLOT_DUMP() \ | |
162 | do \ | |
163 | { \ | |
164 | int i; \ | |
165 | for (i = 0; i < SLOT_NR; i++) \ | |
166 | { \ | |
167 | switch (SLOT[i].size) \ | |
168 | { \ | |
169 | case 1: \ | |
170 | printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \ | |
171 | (long) SLOT[i].dest, \ | |
172 | (unsigned) SLOT[i].mask._1, \ | |
173 | (unsigned) SLOT[i].data._1); \ | |
174 | break; \ | |
175 | case 2: \ | |
176 | printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \ | |
177 | (long) SLOT[i].dest, \ | |
178 | (unsigned) SLOT[i].mask._2, \ | |
179 | (unsigned) SLOT[i].data._2); \ | |
180 | break; \ | |
181 | case 4: \ | |
182 | printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \ | |
183 | (long) SLOT[i].dest, \ | |
184 | (unsigned) SLOT[i].mask._4, \ | |
185 | (unsigned) SLOT[i].data._4); \ | |
186 | break; \ | |
187 | case 8: \ | |
188 | printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \ | |
189 | (long) SLOT[i].dest, \ | |
190 | (unsigned) (SLOT[i].mask._8 >> 32), \ | |
191 | (unsigned) SLOT[i].mask._8, \ | |
192 | (unsigned) (SLOT[i].data._8 >> 32), \ | |
193 | (unsigned) SLOT[i].data._8); \ | |
194 | break; \ | |
195 | } \ | |
196 | } \ | |
197 | } \ | |
198 | while (0) | |
199 | ||
fee8ec00 SR |
200 | struct _state |
201 | { | |
202 | creg_t regs[16]; /* general-purpose registers */ | |
203 | #define GPR(N) (State.regs[(N)] + 0) | |
204 | #define SET_GPR(N,VAL) (State.regs[(N)] = (VAL)) | |
205 | ||
206 | #define GPR32(N) \ | |
207 | (N < 12) ? \ | |
208 | ((((uint16) State.regs[(N) + 1]) << 16) | (uint16) State.regs[(N)]) \ | |
209 | : GPR (N) | |
210 | ||
211 | #define SET_GPR32(N,VAL) do { \ | |
212 | if (N < 11) \ | |
213 | { SET_GPR (N + 1, (VAL) >> 16); SET_GPR (N, ((VAL) & 0xffff));} \ | |
214 | else { if ( N == 11) \ | |
215 | { SET_GPR (N + 1, ((GPR32 (12)) & 0xffff0000)|((VAL) >> 16)); \ | |
216 | SET_GPR (N, ((VAL) & 0xffff));} \ | |
217 | else SET_GPR (N, (VAL));} \ | |
218 | } while (0) | |
219 | ||
220 | creg_t cregs[16]; /* control registers */ | |
221 | #define CREG(N) (State.cregs[(N)] + 0) | |
267b3b8e MF |
222 | #define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0) |
223 | #define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1) | |
fee8ec00 SR |
224 | |
225 | reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */ | |
226 | #define HELD_SP(N) (State.sp[(N)] + 0) | |
227 | #define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL)) | |
228 | ||
229 | /* writeback info */ | |
230 | struct slot slot[NR_SLOTS]; | |
231 | int slot_nr; | |
232 | ||
233 | /* trace data */ | |
234 | struct { | |
235 | uint16 psw; | |
236 | } trace; | |
237 | ||
fee8ec00 SR |
238 | int pc_changed; |
239 | ||
240 | /* NOTE: everything below this line is not reset by | |
241 | sim_create_inferior() */ | |
242 | ||
fee8ec00 SR |
243 | enum _ins_type ins_type; |
244 | ||
7eb99e5e MF |
245 | }; |
246 | ||
247 | extern struct _state State; | |
fee8ec00 SR |
248 | |
249 | ||
fee8ec00 SR |
250 | extern uint32 OP[4]; |
251 | extern uint32 sign_flag; | |
252 | extern struct simops Simops[]; | |
fee8ec00 SR |
253 | |
254 | enum | |
255 | { | |
256 | PC_CR = 0, | |
257 | BDS_CR = 1, | |
258 | BSR_CR = 2, | |
259 | DCR_CR = 3, | |
260 | CAR0_CR = 5, | |
261 | CAR1_CR = 7, | |
262 | CFG_CR = 9, | |
263 | PSR_CR = 10, | |
264 | INTBASE_CR = 11, | |
265 | ISP_CR = 13, | |
266 | USP_CR = 15 | |
267 | }; | |
268 | ||
269 | enum | |
270 | { | |
271 | PSR_I_BIT = 0x0800, | |
272 | PSR_P_BIT = 0x0400, | |
273 | PSR_E_BIT = 0x0200, | |
8e26b0f4 | 274 | PSR_N_BIT = 0x0080, |
fee8ec00 SR |
275 | PSR_Z_BIT = 0x0040, |
276 | PSR_F_BIT = 0x0020, | |
8e26b0f4 | 277 | PSR_U_BIT = 0x0008, |
fee8ec00 SR |
278 | PSR_L_BIT = 0x0004, |
279 | PSR_T_BIT = 0x0002, | |
8e26b0f4 | 280 | PSR_C_BIT = 0x0001 |
fee8ec00 SR |
281 | }; |
282 | ||
283 | #define PSR CREG (PSR_CR) | |
284 | #define SET_PSR(VAL) SET_CREG (PSR_CR, (VAL)) | |
285 | #define SET_HW_PSR(VAL) SET_HW_CREG (PSR_CR, (VAL)) | |
267b3b8e | 286 | #define SET_PSR_BIT(MASK,VAL) move_to_cr (sd, cpu, PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1) |
fee8ec00 SR |
287 | |
288 | #define PSR_SM ((PSR & PSR_SM_BIT) != 0) | |
289 | #define SET_PSR_SM(VAL) SET_PSR_BIT (PSR_SM_BIT, (VAL)) | |
290 | ||
291 | #define PSR_I ((PSR & PSR_I_BIT) != 0) | |
292 | #define SET_PSR_I(VAL) SET_PSR_BIT (PSR_I_BIT, (VAL)) | |
293 | ||
294 | #define PSR_DB ((PSR & PSR_DB_BIT) != 0) | |
295 | #define SET_PSR_DB(VAL) SET_PSR_BIT (PSR_DB_BIT, (VAL)) | |
296 | ||
297 | #define PSR_P ((PSR & PSR_P_BIT) != 0) | |
298 | #define SET_PSR_P(VAL) SET_PSR_BIT (PSR_P_BIT, (VAL)) | |
299 | ||
300 | #define PSR_E ((PSR & PSR_E_BIT) != 0) | |
301 | #define SET_PSR_E(VAL) SET_PSR_BIT (PSR_E_BIT, (VAL)) | |
302 | ||
303 | #define PSR_N ((PSR & PSR_N_BIT) != 0) | |
304 | #define SET_PSR_N(VAL) SET_PSR_BIT (PSR_N_BIT, (VAL)) | |
305 | ||
306 | #define PSR_Z ((PSR & PSR_Z_BIT) != 0) | |
307 | #define SET_PSR_Z(VAL) SET_PSR_BIT (PSR_Z_BIT, (VAL)) | |
308 | ||
309 | #define PSR_F ((PSR & PSR_F_BIT) != 0) | |
310 | #define SET_PSR_F(VAL) SET_PSR_BIT (PSR_F_BIT, (VAL)) | |
311 | ||
312 | #define PSR_U ((PSR & PSR_U_BIT) != 0) | |
313 | #define SET_PSR_U(VAL) SET_PSR_BIT (PSR_U_BIT, (VAL)) | |
314 | ||
315 | #define PSR_L ((PSR & PSR_L_BIT) != 0) | |
316 | #define SET_PSR_L(VAL) SET_PSR_BIT (PSR_L_BIT, (VAL)) | |
317 | ||
318 | #define PSR_T ((PSR & PSR_T_BIT) != 0) | |
319 | #define SET_PSR_T(VAL) SET_PSR_BIT (PSR_T_BIT, (VAL)) | |
320 | ||
321 | #define PSR_C ((PSR & PSR_C_BIT) != 0) | |
322 | #define SET_PSR_C(VAL) SET_PSR_BIT (PSR_C_BIT, (VAL)) | |
323 | ||
324 | /* See simopsc.:move_to_cr() for registers that can not be read-from | |
325 | or assigned-to directly */ | |
326 | ||
327 | #define PC CREG (PC_CR) | |
328 | #define SET_PC(VAL) SET_CREG (PC_CR, (VAL)) | |
329 | //#define SET_PC(VAL) (State.cregs[PC_CR] = (VAL)) | |
330 | ||
331 | #define BPSR CREG (BPSR_CR) | |
332 | #define SET_BPSR(VAL) SET_CREG (BPSR_CR, (VAL)) | |
333 | ||
334 | #define BPC CREG (BPC_CR) | |
335 | #define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL)) | |
336 | ||
337 | #define DPSR CREG (DPSR_CR) | |
338 | #define SET_DPSR(VAL) SET_CREG (DPSR_CR, (VAL)) | |
339 | ||
340 | #define DPC CREG (DPC_CR) | |
341 | #define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL)) | |
342 | ||
343 | #define RPT_C CREG (RPT_C_CR) | |
344 | #define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL)) | |
345 | ||
346 | #define RPT_S CREG (RPT_S_CR) | |
347 | #define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL)) | |
348 | ||
349 | #define RPT_E CREG (RPT_E_CR) | |
350 | #define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL)) | |
351 | ||
352 | #define MOD_S CREG (MOD_S_CR) | |
353 | #define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL)) | |
354 | ||
355 | #define MOD_E CREG (MOD_E_CR) | |
356 | #define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL)) | |
357 | ||
358 | #define IBA CREG (IBA_CR) | |
359 | #define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL)) | |
360 | ||
361 | ||
362 | #define SIG_CR16_STOP -1 | |
363 | #define SIG_CR16_EXIT -2 | |
364 | #define SIG_CR16_BUS -3 | |
365 | #define SIG_CR16_IAD -4 | |
366 | ||
247ac9ee MF |
367 | /* TODO: Resolve conflicts with common headers. */ |
368 | #undef SEXT8 | |
369 | #undef SEXT16 | |
370 | #undef SEXT32 | |
371 | ||
fee8ec00 SR |
372 | #define SEXT3(x) ((((x)&0x7)^(~3))+4) |
373 | ||
374 | /* sign-extend a 4-bit number */ | |
375 | #define SEXT4(x) ((((x)&0xf)^(~7))+8) | |
376 | ||
377 | /* sign-extend an 8-bit number */ | |
378 | #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80) | |
379 | ||
380 | /* sign-extend a 16-bit number */ | |
381 | #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000) | |
382 | ||
383 | /* sign-extend a 24-bit number */ | |
384 | #define SEXT24(x) ((((x)&0xffffff)^(~0x7fffff))+0x800000) | |
385 | ||
386 | /* sign-extend a 32-bit number */ | |
387 | #define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000) | |
388 | ||
761e171a MF |
389 | #define SB(addr, data) sim_core_write_1 (cpu, PC, read_map, addr, data) |
390 | #define RB(addr) sim_core_read_1 (cpu, PC, read_map, addr) | |
391 | #define SW(addr, data) sim_core_write_unaligned_2 (cpu, PC, read_map, addr, data) | |
392 | #define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr) | |
393 | #define SLW(addr, data) sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data) | |
fee8ec00 | 394 | |
761e171a MF |
395 | /* Yes, this is as whacked as it looks. The sim currently reads little endian |
396 | for 16 bits, but then merge them like big endian to get 32 bits. */ | |
397 | static inline uint32 get_longword (SIM_CPU *cpu, address_word addr) | |
398 | { | |
399 | return (RW (addr) << 16) | RW (addr + 2); | |
400 | } | |
401 | #define RLW(addr) get_longword (cpu, addr) | |
fee8ec00 SR |
402 | |
403 | #define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0) | |
404 | ||
405 | #define RIE_VECTOR_START 0xffc2 | |
406 | #define AE_VECTOR_START 0xffc3 | |
407 | #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */ | |
408 | #define DBT_VECTOR_START 0xffd4 | |
409 | #define SDBT_VECTOR_START 0xffd5 | |
410 | ||
411 | #define INT_VECTOR_START 0xFFFE00 /*maskable interrupt - mapped to ICU */ | |
412 | #define NMI_VECTOR_START 0xFFFF00 /*non-maskable interrupt;for observability*/ | |
413 | #define ISE_VECTOR_START 0xFFFC00 /*in-system emulation trap */ | |
414 | #define ADBG_VECTOR_START 0xFFFC02 /*alternate debug trap */ | |
415 | #define ATRC_VECTOR_START 0xFFFC0C /*alternate trace trap */ | |
416 | #define ABPT_VECTOR_START 0xFFFC0E /*alternate break point trap */ | |
417 | ||
418 | ||
419 | /* Scedule a store of VAL into cr[CR]. MASK indicates the bits in | |
420 | cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) | | |
421 | (VAL & ~MASK)). In addition, unless PSR_HW_P, a VAL intended for | |
422 | PSR is masked for zero bits. */ | |
423 | ||
267b3b8e | 424 | extern creg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, creg_t mask, creg_t val, int psw_hw_p); |
5a06d7c4 MF |
425 | |
426 | #ifndef SIGTRAP | |
427 | #define SIGTRAP 5 | |
428 | #endif | |
429 | /* Special purpose trap */ | |
430 | #define TRAP_BREAKPOINT 8 |