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b34f6357 DB |
1 | /* frv simulator fr500 dependent profiling code. |
2 | ||
3666a048 | 3 | Copyright (C) 1998-2021 Free Software Foundation, Inc. |
b34f6357 DB |
4 | Contributed by Red Hat |
5 | ||
6 | This file is part of the GNU simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
10 | the Free Software Foundation; either version 3 of the License, or |
11 | (at your option) any later version. | |
b34f6357 DB |
12 | |
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
4744ac1b | 18 | You should have received a copy of the GNU General Public License |
6df01ab8 MF |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
20 | ||
21 | /* This must come before any other includes. */ | |
22 | #include "defs.h" | |
b34f6357 | 23 | |
b34f6357 DB |
24 | #define WANT_CPU |
25 | #define WANT_CPU_FRVBF | |
26 | ||
27 | #include "sim-main.h" | |
28 | #include "bfd.h" | |
29 | ||
30 | #if WITH_PROFILE_MODEL_P | |
31 | ||
32 | #include "profile.h" | |
33 | #include "profile-fr500.h" | |
34 | ||
35 | /* Initialize cycle counting for an insn. | |
36 | FIRST_P is non-zero if this is the first insn in a set of parallel | |
37 | insns. */ | |
38 | void | |
39 | fr500_model_insn_before (SIM_CPU *cpu, int first_p) | |
40 | { | |
41 | if (first_p) | |
42 | { | |
43 | MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); | |
44 | FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); | |
45 | ps->cur_gr_complex = ps->prev_gr_complex; | |
46 | d->cur_fpop = d->prev_fpop; | |
47 | d->cur_media = d->prev_media; | |
48 | d->cur_cc_complex = d->prev_cc_complex; | |
49 | } | |
50 | } | |
51 | ||
52 | /* Record the cycles computed for an insn. | |
53 | LAST_P is non-zero if this is the last insn in a set of parallel insns, | |
54 | and we update the total cycle count. | |
55 | CYCLES is the cycle count of the insn. */ | |
56 | void | |
57 | fr500_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) | |
58 | { | |
59 | if (last_p) | |
60 | { | |
61 | MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); | |
62 | FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); | |
63 | ps->prev_gr_complex = ps->cur_gr_complex; | |
64 | d->prev_fpop = d->cur_fpop; | |
65 | d->prev_media = d->cur_media; | |
66 | d->prev_cc_complex = d->cur_cc_complex; | |
67 | } | |
68 | } | |
69 | ||
70 | static void | |
71 | set_use_is_fpop (SIM_CPU *cpu, INT fr) | |
72 | { | |
73 | MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); | |
74 | fr500_reset_fr_flags (cpu, (fr)); | |
75 | d->cur_fpop |= (((DI)1) << (fr)); | |
76 | } | |
77 | ||
78 | static void | |
79 | set_use_not_fpop (SIM_CPU *cpu, INT fr) | |
80 | { | |
81 | MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); | |
82 | d->cur_fpop &= ~(((DI)1) << (fr)); | |
83 | } | |
84 | ||
85 | static int | |
86 | use_is_fpop (SIM_CPU *cpu, INT fr) | |
87 | { | |
88 | MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); | |
89 | return d->prev_fpop & (((DI)1) << (fr)); | |
90 | } | |
91 | ||
92 | static void | |
93 | set_use_is_media ( SIM_CPU *cpu, INT fr) | |
94 | { | |
95 | MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); | |
96 | fr500_reset_fr_flags (cpu, (fr)); | |
97 | d->cur_media |= (((DI)1) << (fr)); | |
98 | } | |
99 | ||
100 | static void | |
101 | set_use_not_media (SIM_CPU *cpu, INT fr) | |
102 | { | |
103 | MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); | |
104 | d->cur_media &= ~(((DI)1) << (fr)); | |
105 | } | |
106 | ||
107 | static int | |
108 | use_is_media (SIM_CPU *cpu, INT fr) | |
109 | { | |
110 | MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); | |
111 | return d->prev_media & (((DI)1) << (fr)); | |
112 | } | |
113 | ||
114 | static void | |
115 | set_use_is_cc_complex (SIM_CPU *cpu, INT cc) | |
116 | { | |
117 | MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); | |
118 | fr500_reset_cc_flags (cpu, cc); | |
119 | d->cur_cc_complex |= (((DI)1) << (cc)); | |
120 | } | |
121 | ||
122 | static void | |
123 | set_use_not_cc_complex (SIM_CPU *cpu, INT cc) | |
124 | { | |
125 | MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); | |
126 | d->cur_cc_complex &= ~(((DI)1) << (cc)); | |
127 | } | |
128 | ||
129 | static int | |
130 | use_is_cc_complex (SIM_CPU *cpu, INT cc) | |
131 | { | |
132 | MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); | |
133 | return d->prev_cc_complex & (((DI)1) << (cc)); | |
134 | } | |
135 | ||
136 | void | |
137 | fr500_reset_fr_flags (SIM_CPU *cpu, INT fr) | |
138 | { | |
139 | set_use_not_fpop (cpu, fr); | |
140 | set_use_not_media (cpu, fr); | |
141 | } | |
142 | ||
143 | void | |
144 | fr500_reset_cc_flags (SIM_CPU *cpu, INT cc) | |
145 | { | |
146 | set_use_not_cc_complex (cpu, cc); | |
147 | } | |
148 | ||
149 | /* Latency of floating point registers may be less than recorded when followed | |
150 | by another floating point insn. */ | |
151 | static void | |
152 | adjust_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, | |
153 | int cycles) | |
154 | { | |
155 | /* If the registers were previously used in a floating point op, | |
156 | then their latency will be less than previously recorded. | |
157 | See Table 13-13 in the LSI. */ | |
158 | if (in_FRi >= 0) | |
159 | if (use_is_fpop (cpu, in_FRi)) | |
160 | decrease_FR_busy (cpu, in_FRi, cycles); | |
161 | else | |
162 | enforce_full_fr_latency (cpu, in_FRi); | |
163 | ||
164 | if (in_FRj >= 0 && in_FRj != in_FRi) | |
165 | if (use_is_fpop (cpu, in_FRj)) | |
166 | decrease_FR_busy (cpu, in_FRj, cycles); | |
167 | else | |
168 | enforce_full_fr_latency (cpu, in_FRj); | |
169 | ||
170 | if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj) | |
171 | if (use_is_fpop (cpu, out_FRk)) | |
172 | decrease_FR_busy (cpu, out_FRk, cycles); | |
173 | else | |
174 | enforce_full_fr_latency (cpu, out_FRk); | |
175 | } | |
176 | ||
177 | /* Latency of floating point registers may be less than recorded when followed | |
178 | by another floating point insn. */ | |
179 | static void | |
180 | adjust_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, | |
181 | int cycles) | |
182 | { | |
183 | /* If the registers were previously used in a floating point op, | |
184 | then their latency will be less than previously recorded. | |
185 | See Table 13-13 in the LSI. */ | |
186 | adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); | |
187 | if (in_FRi >= 0) ++in_FRi; | |
188 | if (in_FRj >= 0) ++in_FRj; | |
189 | if (out_FRk >= 0) ++out_FRk; | |
190 | adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); | |
191 | } | |
192 | ||
193 | /* Latency of floating point registers is less than recorded when followed | |
194 | by another floating point insn. */ | |
195 | static void | |
196 | restore_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, | |
197 | int cycles) | |
198 | { | |
199 | /* If the registers were previously used in a floating point op, | |
200 | then their latency will be less than previously recorded. | |
201 | See Table 13-13 in the LSI. */ | |
202 | if (in_FRi >= 0 && use_is_fpop (cpu, in_FRi)) | |
203 | increase_FR_busy (cpu, in_FRi, cycles); | |
204 | if (in_FRj != in_FRi && use_is_fpop (cpu, in_FRj)) | |
205 | increase_FR_busy (cpu, in_FRj, cycles); | |
206 | if (out_FRk != in_FRi && out_FRk != in_FRj && use_is_fpop (cpu, out_FRk)) | |
207 | increase_FR_busy (cpu, out_FRk, cycles); | |
208 | } | |
209 | ||
210 | /* Latency of floating point registers is less than recorded when followed | |
211 | by another floating point insn. */ | |
212 | static void | |
213 | restore_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, | |
214 | int cycles) | |
215 | { | |
216 | /* If the registers were previously used in a floating point op, | |
217 | then their latency will be less than previously recorded. | |
218 | See Table 13-13 in the LSI. */ | |
219 | restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); | |
220 | if (in_FRi >= 0) ++in_FRi; | |
221 | if (in_FRj >= 0) ++in_FRj; | |
222 | if (out_FRk >= 0) ++out_FRk; | |
223 | restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); | |
224 | } | |
225 | ||
226 | int | |
227 | frvbf_model_fr500_u_exec (SIM_CPU *cpu, const IDESC *idesc, | |
228 | int unit_num, int referenced) | |
229 | { | |
230 | return idesc->timing->units[unit_num].done; | |
231 | } | |
232 | ||
233 | int | |
234 | frvbf_model_fr500_u_integer (SIM_CPU *cpu, const IDESC *idesc, | |
235 | int unit_num, int referenced, | |
236 | INT in_GRi, INT in_GRj, INT out_GRk, | |
237 | INT out_ICCi_1) | |
238 | { | |
239 | int cycles; | |
240 | ||
241 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
242 | { | |
243 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
244 | if (out_ICCi_1 >= 0) | |
245 | out_ICCi_1 += 4; | |
246 | ||
247 | /* The entire VLIW insn must wait if there is a dependency on a register | |
248 | which is not ready yet. | |
249 | The latency of the registers may be less than previously recorded, | |
250 | depending on how they were used previously. | |
251 | See Table 13-8 in the LSI. */ | |
252 | if (in_GRi != out_GRk && in_GRi >= 0) | |
253 | { | |
254 | if (use_is_gr_complex (cpu, in_GRi)) | |
255 | decrease_GR_busy (cpu, in_GRi, 1); | |
256 | } | |
257 | if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) | |
258 | { | |
259 | if (use_is_gr_complex (cpu, in_GRj)) | |
260 | decrease_GR_busy (cpu, in_GRj, 1); | |
261 | } | |
262 | vliw_wait_for_GR (cpu, in_GRi); | |
263 | vliw_wait_for_GR (cpu, in_GRj); | |
264 | vliw_wait_for_GR (cpu, out_GRk); | |
265 | vliw_wait_for_CCR (cpu, out_ICCi_1); | |
266 | handle_resource_wait (cpu); | |
267 | load_wait_for_GR (cpu, in_GRi); | |
268 | load_wait_for_GR (cpu, in_GRj); | |
269 | load_wait_for_GR (cpu, out_GRk); | |
270 | trace_vliw_wait_cycles (cpu); | |
271 | return 0; | |
272 | } | |
273 | ||
274 | /* GRk is available immediately to the next VLIW insn as is ICCi_1. */ | |
275 | cycles = idesc->timing->units[unit_num].done; | |
276 | return cycles; | |
277 | } | |
278 | ||
279 | int | |
280 | frvbf_model_fr500_u_imul (SIM_CPU *cpu, const IDESC *idesc, | |
281 | int unit_num, int referenced, | |
282 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
283 | { | |
284 | int cycles; | |
285 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
286 | if (out_ICCi_1 >= 0) | |
287 | out_ICCi_1 += 4; | |
288 | ||
289 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
290 | { | |
291 | /* The entire VLIW insn must wait if there is a dependency on a register | |
292 | which is not ready yet. | |
293 | The latency of the registers may be less than previously recorded, | |
294 | depending on how they were used previously. | |
295 | See Table 13-8 in the LSI. */ | |
296 | if (in_GRi != out_GRk && in_GRi >= 0) | |
297 | { | |
298 | if (use_is_gr_complex (cpu, in_GRi)) | |
299 | decrease_GR_busy (cpu, in_GRi, 1); | |
300 | } | |
301 | if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) | |
302 | { | |
303 | if (use_is_gr_complex (cpu, in_GRj)) | |
304 | decrease_GR_busy (cpu, in_GRj, 1); | |
305 | } | |
306 | vliw_wait_for_GR (cpu, in_GRi); | |
307 | vliw_wait_for_GR (cpu, in_GRj); | |
308 | vliw_wait_for_GRdouble (cpu, out_GRk); | |
309 | vliw_wait_for_CCR (cpu, out_ICCi_1); | |
310 | handle_resource_wait (cpu); | |
311 | load_wait_for_GR (cpu, in_GRi); | |
312 | load_wait_for_GR (cpu, in_GRj); | |
313 | load_wait_for_GRdouble (cpu, out_GRk); | |
314 | trace_vliw_wait_cycles (cpu); | |
315 | return 0; | |
316 | } | |
317 | ||
318 | /* GRk has a latency of 2 cycles. */ | |
319 | cycles = idesc->timing->units[unit_num].done; | |
320 | update_GRdouble_latency (cpu, out_GRk, cycles + 2); | |
321 | set_use_is_gr_complex (cpu, out_GRk); | |
322 | set_use_is_gr_complex (cpu, out_GRk + 1); | |
323 | ||
324 | /* ICCi_1 has a latency of 1 cycle. */ | |
325 | update_CCR_latency (cpu, out_ICCi_1, cycles + 1); | |
326 | ||
327 | return cycles; | |
328 | } | |
329 | ||
330 | int | |
331 | frvbf_model_fr500_u_idiv (SIM_CPU *cpu, const IDESC *idesc, | |
332 | int unit_num, int referenced, | |
333 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
334 | { | |
335 | int cycles; | |
336 | FRV_VLIW *vliw; | |
337 | int slot; | |
338 | ||
339 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
340 | if (out_ICCi_1 >= 0) | |
341 | out_ICCi_1 += 4; | |
342 | ||
343 | vliw = CPU_VLIW (cpu); | |
344 | slot = vliw->next_slot - 1; | |
345 | slot = (*vliw->current_vliw)[slot] - UNIT_I0; | |
346 | ||
347 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
348 | { | |
349 | /* The entire VLIW insn must wait if there is a dependency on a register | |
350 | which is not ready yet. | |
351 | The latency of the registers may be less than previously recorded, | |
352 | depending on how they were used previously. | |
353 | See Table 13-8 in the LSI. */ | |
354 | if (in_GRi != out_GRk && in_GRi >= 0) | |
355 | { | |
356 | if (use_is_gr_complex (cpu, in_GRi)) | |
357 | decrease_GR_busy (cpu, in_GRi, 1); | |
358 | } | |
359 | if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) | |
360 | { | |
361 | if (use_is_gr_complex (cpu, in_GRj)) | |
362 | decrease_GR_busy (cpu, in_GRj, 1); | |
363 | } | |
364 | vliw_wait_for_GR (cpu, in_GRi); | |
365 | vliw_wait_for_GR (cpu, in_GRj); | |
366 | vliw_wait_for_GR (cpu, out_GRk); | |
367 | vliw_wait_for_CCR (cpu, out_ICCi_1); | |
368 | vliw_wait_for_idiv_resource (cpu, slot); | |
369 | handle_resource_wait (cpu); | |
370 | load_wait_for_GR (cpu, in_GRi); | |
371 | load_wait_for_GR (cpu, in_GRj); | |
372 | load_wait_for_GR (cpu, out_GRk); | |
373 | trace_vliw_wait_cycles (cpu); | |
374 | return 0; | |
375 | } | |
376 | ||
377 | /* GRk has a latency of 19 cycles! */ | |
378 | cycles = idesc->timing->units[unit_num].done; | |
379 | update_GR_latency (cpu, out_GRk, cycles + 19); | |
380 | set_use_is_gr_complex (cpu, out_GRk); | |
381 | ||
382 | /* ICCi_1 has a latency of 19 cycles. */ | |
383 | update_CCR_latency (cpu, out_ICCi_1, cycles + 19); | |
384 | set_use_is_cc_complex (cpu, out_ICCi_1); | |
385 | ||
153431d6 DB |
386 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
387 | { | |
388 | /* GNER has a latency of 18 cycles. */ | |
389 | update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 18); | |
390 | } | |
391 | ||
b34f6357 DB |
392 | /* the idiv resource has a latency of 18 cycles! */ |
393 | update_idiv_resource_latency (cpu, slot, cycles + 18); | |
394 | ||
395 | return cycles; | |
396 | } | |
397 | ||
398 | int | |
399 | frvbf_model_fr500_u_branch (SIM_CPU *cpu, const IDESC *idesc, | |
400 | int unit_num, int referenced, | |
401 | INT in_GRi, INT in_GRj, | |
402 | INT in_ICCi_2, INT in_FCCi_2) | |
403 | { | |
404 | int cycles; | |
405 | FRV_PROFILE_STATE *ps; | |
406 | ||
407 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
408 | { | |
409 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
410 | if (in_ICCi_2 >= 0) | |
411 | in_ICCi_2 += 4; | |
412 | ||
413 | /* The entire VLIW insn must wait if there is a dependency on a register | |
414 | which is not ready yet. | |
415 | The latency of the registers may be less than previously recorded, | |
416 | depending on how they were used previously. | |
417 | See Table 13-8 in the LSI. */ | |
418 | if (in_GRi >= 0) | |
419 | { | |
420 | if (use_is_gr_complex (cpu, in_GRi)) | |
421 | decrease_GR_busy (cpu, in_GRi, 1); | |
422 | } | |
423 | if (in_GRj != in_GRi && in_GRj >= 0) | |
424 | { | |
425 | if (use_is_gr_complex (cpu, in_GRj)) | |
426 | decrease_GR_busy (cpu, in_GRj, 1); | |
427 | } | |
428 | vliw_wait_for_GR (cpu, in_GRi); | |
429 | vliw_wait_for_GR (cpu, in_GRj); | |
430 | vliw_wait_for_CCR (cpu, in_ICCi_2); | |
431 | vliw_wait_for_CCR (cpu, in_FCCi_2); | |
432 | handle_resource_wait (cpu); | |
433 | load_wait_for_GR (cpu, in_GRi); | |
434 | load_wait_for_GR (cpu, in_GRj); | |
435 | trace_vliw_wait_cycles (cpu); | |
436 | return 0; | |
437 | } | |
438 | ||
439 | /* When counting branches taken or not taken, don't consider branches after | |
440 | the first taken branch in a vliw insn. */ | |
441 | ps = CPU_PROFILE_STATE (cpu); | |
442 | if (! ps->vliw_branch_taken) | |
443 | { | |
444 | /* (1 << 4): The pc is the 5th element in inputs, outputs. | |
445 | ??? can be cleaned up */ | |
446 | PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); | |
447 | int taken = (referenced & (1 << 4)) != 0; | |
448 | if (taken) | |
449 | { | |
450 | ++PROFILE_MODEL_TAKEN_COUNT (p); | |
451 | ps->vliw_branch_taken = 1; | |
452 | } | |
453 | else | |
454 | ++PROFILE_MODEL_UNTAKEN_COUNT (p); | |
455 | } | |
456 | ||
457 | cycles = idesc->timing->units[unit_num].done; | |
458 | return cycles; | |
459 | } | |
460 | ||
461 | int | |
462 | frvbf_model_fr500_u_trap (SIM_CPU *cpu, const IDESC *idesc, | |
463 | int unit_num, int referenced, | |
464 | INT in_GRi, INT in_GRj, | |
465 | INT in_ICCi_2, INT in_FCCi_2) | |
466 | { | |
467 | int cycles; | |
b34f6357 DB |
468 | |
469 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
470 | { | |
471 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
472 | if (in_ICCi_2 >= 0) | |
473 | in_ICCi_2 += 4; | |
474 | ||
475 | /* The entire VLIW insn must wait if there is a dependency on a register | |
476 | which is not ready yet. | |
477 | The latency of the registers may be less than previously recorded, | |
478 | depending on how they were used previously. | |
479 | See Table 13-8 in the LSI. */ | |
480 | if (in_GRi >= 0) | |
481 | { | |
482 | if (use_is_gr_complex (cpu, in_GRi)) | |
483 | decrease_GR_busy (cpu, in_GRi, 1); | |
484 | } | |
485 | if (in_GRj != in_GRi && in_GRj >= 0) | |
486 | { | |
487 | if (use_is_gr_complex (cpu, in_GRj)) | |
488 | decrease_GR_busy (cpu, in_GRj, 1); | |
489 | } | |
490 | vliw_wait_for_GR (cpu, in_GRi); | |
491 | vliw_wait_for_GR (cpu, in_GRj); | |
492 | vliw_wait_for_CCR (cpu, in_ICCi_2); | |
493 | vliw_wait_for_CCR (cpu, in_FCCi_2); | |
494 | handle_resource_wait (cpu); | |
495 | load_wait_for_GR (cpu, in_GRi); | |
496 | load_wait_for_GR (cpu, in_GRj); | |
497 | trace_vliw_wait_cycles (cpu); | |
498 | return 0; | |
499 | } | |
500 | ||
501 | cycles = idesc->timing->units[unit_num].done; | |
502 | return cycles; | |
503 | } | |
504 | ||
505 | int | |
506 | frvbf_model_fr500_u_check (SIM_CPU *cpu, const IDESC *idesc, | |
507 | int unit_num, int referenced, | |
508 | INT in_ICCi_3, INT in_FCCi_3) | |
509 | { | |
510 | int cycles; | |
b34f6357 DB |
511 | |
512 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
513 | { | |
514 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
515 | if (in_ICCi_3 >= 0) | |
516 | in_ICCi_3 += 4; | |
517 | ||
518 | /* The entire VLIW insn must wait if there is a dependency on a register | |
519 | which is not ready yet. */ | |
520 | vliw_wait_for_CCR (cpu, in_ICCi_3); | |
521 | vliw_wait_for_CCR (cpu, in_FCCi_3); | |
522 | handle_resource_wait (cpu); | |
523 | trace_vliw_wait_cycles (cpu); | |
524 | return 0; | |
525 | } | |
526 | ||
527 | cycles = idesc->timing->units[unit_num].done; | |
528 | return cycles; | |
529 | } | |
530 | ||
153431d6 DB |
531 | int |
532 | frvbf_model_fr500_u_clrgr (SIM_CPU *cpu, const IDESC *idesc, | |
533 | int unit_num, int referenced, | |
534 | INT in_GRk) | |
535 | { | |
536 | int cycles; | |
537 | ||
538 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
539 | { | |
540 | /* Wait for both GNER registers or just the one specified. */ | |
541 | if (in_GRk == -1) | |
542 | { | |
543 | vliw_wait_for_SPR (cpu, H_SPR_GNER0); | |
544 | vliw_wait_for_SPR (cpu, H_SPR_GNER1); | |
545 | } | |
546 | else | |
547 | vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk)); | |
548 | handle_resource_wait (cpu); | |
549 | trace_vliw_wait_cycles (cpu); | |
550 | return 0; | |
551 | } | |
552 | ||
553 | cycles = idesc->timing->units[unit_num].done; | |
554 | return cycles; | |
555 | } | |
556 | ||
557 | int | |
558 | frvbf_model_fr500_u_clrfr (SIM_CPU *cpu, const IDESC *idesc, | |
559 | int unit_num, int referenced, | |
560 | INT in_FRk) | |
561 | { | |
562 | int cycles; | |
563 | ||
564 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
565 | { | |
566 | /* Wait for both GNER registers or just the one specified. */ | |
567 | if (in_FRk == -1) | |
568 | { | |
569 | vliw_wait_for_SPR (cpu, H_SPR_FNER0); | |
570 | vliw_wait_for_SPR (cpu, H_SPR_FNER1); | |
571 | } | |
572 | else | |
573 | vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk)); | |
574 | handle_resource_wait (cpu); | |
575 | trace_vliw_wait_cycles (cpu); | |
576 | return 0; | |
577 | } | |
578 | ||
579 | cycles = idesc->timing->units[unit_num].done; | |
580 | return cycles; | |
581 | } | |
582 | ||
1c453cd6 DB |
583 | int |
584 | frvbf_model_fr500_u_commit (SIM_CPU *cpu, const IDESC *idesc, | |
585 | int unit_num, int referenced, | |
586 | INT in_GRk, INT in_FRk) | |
587 | { | |
588 | int cycles; | |
589 | ||
590 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
591 | { | |
592 | /* If GR is specified, then FR is not and vice-versa. If neither is | |
593 | then it's a commitga or commitfa. Check the insn attribute to | |
594 | figure out which. */ | |
595 | if (in_GRk != -1) | |
596 | vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk)); | |
597 | else if (in_FRk != -1) | |
598 | vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk)); | |
599 | else if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_FR_ACCESS)) | |
600 | { | |
601 | vliw_wait_for_SPR (cpu, H_SPR_FNER0); | |
602 | vliw_wait_for_SPR (cpu, H_SPR_FNER1); | |
603 | } | |
604 | else | |
605 | { | |
606 | vliw_wait_for_SPR (cpu, H_SPR_GNER0); | |
607 | vliw_wait_for_SPR (cpu, H_SPR_GNER1); | |
608 | } | |
609 | handle_resource_wait (cpu); | |
610 | trace_vliw_wait_cycles (cpu); | |
611 | return 0; | |
612 | } | |
613 | ||
614 | cycles = idesc->timing->units[unit_num].done; | |
615 | return cycles; | |
616 | } | |
617 | ||
b34f6357 DB |
618 | int |
619 | frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, | |
620 | int unit_num, int referenced, | |
621 | INT out_GRkhi, INT out_GRklo) | |
622 | { | |
623 | int cycles; | |
624 | ||
625 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
626 | { | |
627 | /* The entire VLIW insn must wait if there is a dependency on a GR | |
628 | which is not ready yet. */ | |
629 | vliw_wait_for_GR (cpu, out_GRkhi); | |
630 | vliw_wait_for_GR (cpu, out_GRklo); | |
631 | handle_resource_wait (cpu); | |
632 | load_wait_for_GR (cpu, out_GRkhi); | |
633 | load_wait_for_GR (cpu, out_GRklo); | |
634 | trace_vliw_wait_cycles (cpu); | |
635 | return 0; | |
636 | } | |
637 | ||
638 | /* GRk is available immediately to the next VLIW insn. */ | |
639 | cycles = idesc->timing->units[unit_num].done; | |
640 | ||
641 | set_use_not_gr_complex (cpu, out_GRkhi); | |
642 | set_use_not_gr_complex (cpu, out_GRklo); | |
643 | ||
644 | return cycles; | |
645 | } | |
646 | ||
647 | int | |
648 | frvbf_model_fr500_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, | |
649 | int unit_num, int referenced, | |
650 | INT in_GRi, INT in_GRj, | |
651 | INT out_GRk, INT out_GRdoublek) | |
652 | { | |
653 | int cycles; | |
654 | ||
655 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
656 | { | |
657 | /* The entire VLIW insn must wait if there is a dependency on a register | |
658 | which is not ready yet. | |
659 | The latency of the registers may be less than previously recorded, | |
660 | depending on how they were used previously. | |
661 | See Table 13-8 in the LSI. */ | |
662 | if (in_GRi != out_GRk && in_GRi != out_GRdoublek | |
663 | && in_GRi != out_GRdoublek + 1 && in_GRi >= 0) | |
664 | { | |
665 | if (use_is_gr_complex (cpu, in_GRi)) | |
666 | decrease_GR_busy (cpu, in_GRi, 1); | |
667 | } | |
668 | if (in_GRj != in_GRi && in_GRj != out_GRk && in_GRj != out_GRdoublek | |
669 | && in_GRj != out_GRdoublek + 1 && in_GRj >= 0) | |
670 | ||
671 | { | |
672 | if (use_is_gr_complex (cpu, in_GRj)) | |
673 | decrease_GR_busy (cpu, in_GRj, 1); | |
674 | } | |
675 | vliw_wait_for_GR (cpu, in_GRi); | |
676 | vliw_wait_for_GR (cpu, in_GRj); | |
677 | vliw_wait_for_GR (cpu, out_GRk); | |
678 | vliw_wait_for_GRdouble (cpu, out_GRdoublek); | |
679 | handle_resource_wait (cpu); | |
680 | load_wait_for_GR (cpu, in_GRi); | |
681 | load_wait_for_GR (cpu, in_GRj); | |
682 | load_wait_for_GR (cpu, out_GRk); | |
683 | load_wait_for_GRdouble (cpu, out_GRdoublek); | |
684 | trace_vliw_wait_cycles (cpu); | |
685 | return 0; | |
686 | } | |
687 | ||
688 | cycles = idesc->timing->units[unit_num].done; | |
689 | ||
690 | /* The latency of GRk for a load will depend on how long it takes to retrieve | |
691 | the the data from the cache or memory. */ | |
692 | update_GR_latency_for_load (cpu, out_GRk, cycles); | |
693 | update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles); | |
694 | ||
1c453cd6 DB |
695 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
696 | { | |
697 | /* GNER has a latency of 2 cycles. */ | |
698 | update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2); | |
699 | update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2); | |
700 | } | |
701 | ||
702 | if (out_GRk >= 0) | |
703 | set_use_is_gr_complex (cpu, out_GRk); | |
704 | if (out_GRdoublek != -1) | |
705 | { | |
706 | set_use_is_gr_complex (cpu, out_GRdoublek); | |
707 | set_use_is_gr_complex (cpu, out_GRdoublek + 1); | |
708 | } | |
b34f6357 DB |
709 | |
710 | return cycles; | |
711 | } | |
712 | ||
713 | int | |
714 | frvbf_model_fr500_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, | |
715 | int unit_num, int referenced, | |
716 | INT in_GRi, INT in_GRj, | |
717 | INT in_GRk, INT in_GRdoublek) | |
718 | { | |
719 | int cycles; | |
720 | ||
721 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
722 | { | |
723 | /* The entire VLIW insn must wait if there is a dependency on a register | |
724 | which is not ready yet. | |
725 | The latency of the registers may be less than previously recorded, | |
726 | depending on how they were used previously. | |
727 | See Table 13-8 in the LSI. */ | |
728 | if (in_GRi >= 0) | |
729 | { | |
730 | if (use_is_gr_complex (cpu, in_GRi)) | |
731 | decrease_GR_busy (cpu, in_GRi, 1); | |
732 | } | |
733 | if (in_GRj != in_GRi && in_GRj >= 0) | |
734 | { | |
735 | if (use_is_gr_complex (cpu, in_GRj)) | |
736 | decrease_GR_busy (cpu, in_GRj, 1); | |
737 | } | |
738 | if (in_GRk != in_GRi && in_GRk != in_GRj && in_GRk >= 0) | |
739 | { | |
740 | if (use_is_gr_complex (cpu, in_GRk)) | |
741 | decrease_GR_busy (cpu, in_GRk, 1); | |
742 | } | |
743 | if (in_GRdoublek != in_GRi && in_GRdoublek != in_GRj | |
744 | && in_GRdoublek + 1 != in_GRi && in_GRdoublek + 1 != in_GRj | |
745 | && in_GRdoublek >= 0) | |
746 | { | |
747 | if (use_is_gr_complex (cpu, in_GRdoublek)) | |
748 | decrease_GR_busy (cpu, in_GRdoublek, 1); | |
749 | if (use_is_gr_complex (cpu, in_GRdoublek + 1)) | |
750 | decrease_GR_busy (cpu, in_GRdoublek + 1, 1); | |
751 | } | |
752 | vliw_wait_for_GR (cpu, in_GRi); | |
753 | vliw_wait_for_GR (cpu, in_GRj); | |
754 | vliw_wait_for_GR (cpu, in_GRk); | |
755 | vliw_wait_for_GRdouble (cpu, in_GRdoublek); | |
756 | handle_resource_wait (cpu); | |
757 | load_wait_for_GR (cpu, in_GRi); | |
758 | load_wait_for_GR (cpu, in_GRj); | |
759 | load_wait_for_GR (cpu, in_GRk); | |
760 | load_wait_for_GRdouble (cpu, in_GRdoublek); | |
761 | trace_vliw_wait_cycles (cpu); | |
762 | return 0; | |
763 | } | |
764 | ||
765 | cycles = idesc->timing->units[unit_num].done; | |
766 | ||
767 | return cycles; | |
768 | } | |
769 | ||
770 | int | |
771 | frvbf_model_fr500_u_gr_r_store (SIM_CPU *cpu, const IDESC *idesc, | |
772 | int unit_num, int referenced, | |
773 | INT in_GRi, INT in_GRj, | |
774 | INT in_GRk, INT in_GRdoublek) | |
775 | { | |
776 | int cycles = frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced, | |
777 | in_GRi, in_GRj, in_GRk, | |
778 | in_GRdoublek); | |
779 | ||
780 | if (model_insn == FRV_INSN_MODEL_PASS_2) | |
781 | { | |
782 | if (CPU_RSTR_INVALIDATE(cpu)) | |
783 | request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles); | |
784 | } | |
785 | ||
786 | return cycles; | |
787 | } | |
788 | ||
789 | int | |
790 | frvbf_model_fr500_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, | |
791 | int unit_num, int referenced, | |
792 | INT in_GRi, INT in_GRj, | |
793 | INT out_FRk, INT out_FRdoublek) | |
794 | { | |
795 | int cycles; | |
796 | ||
797 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
798 | { | |
799 | /* The entire VLIW insn must wait if there is a dependency on a register | |
800 | which is not ready yet. | |
801 | The latency of the registers may be less than previously recorded, | |
802 | depending on how they were used previously. | |
803 | See Table 13-8 in the LSI. */ | |
804 | if (in_GRi >= 0) | |
805 | { | |
806 | if (use_is_gr_complex (cpu, in_GRi)) | |
807 | decrease_GR_busy (cpu, in_GRi, 1); | |
808 | } | |
809 | if (in_GRj != in_GRi && in_GRj >= 0) | |
810 | { | |
811 | if (use_is_gr_complex (cpu, in_GRj)) | |
812 | decrease_GR_busy (cpu, in_GRj, 1); | |
813 | } | |
814 | if (out_FRk >= 0) | |
815 | { | |
816 | if (use_is_media (cpu, out_FRk)) | |
817 | decrease_FR_busy (cpu, out_FRk, 1); | |
818 | else | |
819 | adjust_float_register_busy (cpu, -1, -1, out_FRk, 1); | |
820 | } | |
821 | if (out_FRdoublek >= 0) | |
822 | { | |
823 | if (use_is_media (cpu, out_FRdoublek)) | |
824 | decrease_FR_busy (cpu, out_FRdoublek, 1); | |
825 | else | |
826 | adjust_float_register_busy (cpu, -1, -1, out_FRdoublek, 1); | |
827 | if (use_is_media (cpu, out_FRdoublek + 1)) | |
828 | decrease_FR_busy (cpu, out_FRdoublek + 1, 1); | |
829 | else | |
830 | adjust_float_register_busy (cpu, -1, -1, out_FRdoublek + 1, 1); | |
831 | } | |
832 | vliw_wait_for_GR (cpu, in_GRi); | |
833 | vliw_wait_for_GR (cpu, in_GRj); | |
834 | vliw_wait_for_FR (cpu, out_FRk); | |
835 | vliw_wait_for_FRdouble (cpu, out_FRdoublek); | |
1c453cd6 DB |
836 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
837 | { | |
838 | vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
839 | vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); | |
840 | } | |
b34f6357 DB |
841 | handle_resource_wait (cpu); |
842 | load_wait_for_GR (cpu, in_GRi); | |
843 | load_wait_for_GR (cpu, in_GRj); | |
844 | load_wait_for_FR (cpu, out_FRk); | |
845 | load_wait_for_FRdouble (cpu, out_FRdoublek); | |
846 | trace_vliw_wait_cycles (cpu); | |
847 | return 0; | |
848 | } | |
849 | ||
850 | cycles = idesc->timing->units[unit_num].done; | |
851 | ||
852 | /* The latency of FRk for a load will depend on how long it takes to retrieve | |
853 | the the data from the cache or memory. */ | |
854 | update_FR_latency_for_load (cpu, out_FRk, cycles); | |
855 | update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles); | |
856 | ||
1c453cd6 DB |
857 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
858 | { | |
859 | /* FNER has a latency of 3 cycles. */ | |
860 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), cycles + 3); | |
861 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), cycles + 3); | |
862 | } | |
863 | ||
b34f6357 DB |
864 | fr500_reset_fr_flags (cpu, out_FRk); |
865 | ||
866 | return cycles; | |
867 | } | |
868 | ||
869 | int | |
870 | frvbf_model_fr500_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, | |
871 | int unit_num, int referenced, | |
872 | INT in_GRi, INT in_GRj, | |
873 | INT in_FRk, INT in_FRdoublek) | |
874 | { | |
875 | int cycles; | |
876 | ||
877 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
878 | { | |
879 | /* The entire VLIW insn must wait if there is a dependency on a register | |
880 | which is not ready yet. | |
881 | The latency of the registers may be less than previously recorded, | |
882 | depending on how they were used previously. | |
883 | See Table 13-8 in the LSI. */ | |
884 | if (in_GRi >= 0) | |
885 | { | |
886 | if (use_is_gr_complex (cpu, in_GRi)) | |
887 | decrease_GR_busy (cpu, in_GRi, 1); | |
888 | } | |
889 | if (in_GRj != in_GRi && in_GRj >= 0) | |
890 | { | |
891 | if (use_is_gr_complex (cpu, in_GRj)) | |
892 | decrease_GR_busy (cpu, in_GRj, 1); | |
893 | } | |
894 | if (in_FRk >= 0) | |
895 | { | |
896 | if (use_is_media (cpu, in_FRk)) | |
897 | decrease_FR_busy (cpu, in_FRk, 1); | |
898 | else | |
899 | adjust_float_register_busy (cpu, -1, -1, in_FRk, 1); | |
900 | } | |
901 | if (in_FRdoublek >= 0) | |
902 | { | |
903 | if (use_is_media (cpu, in_FRdoublek)) | |
904 | decrease_FR_busy (cpu, in_FRdoublek, 1); | |
905 | else | |
906 | adjust_float_register_busy (cpu, -1, -1, in_FRdoublek, 1); | |
907 | if (use_is_media (cpu, in_FRdoublek + 1)) | |
908 | decrease_FR_busy (cpu, in_FRdoublek + 1, 1); | |
909 | else | |
910 | adjust_float_register_busy (cpu, -1, -1, in_FRdoublek + 1, 1); | |
911 | } | |
912 | vliw_wait_for_GR (cpu, in_GRi); | |
913 | vliw_wait_for_GR (cpu, in_GRj); | |
914 | vliw_wait_for_FR (cpu, in_FRk); | |
915 | vliw_wait_for_FRdouble (cpu, in_FRdoublek); | |
916 | handle_resource_wait (cpu); | |
917 | load_wait_for_GR (cpu, in_GRi); | |
918 | load_wait_for_GR (cpu, in_GRj); | |
919 | load_wait_for_FR (cpu, in_FRk); | |
920 | load_wait_for_FRdouble (cpu, in_FRdoublek); | |
921 | trace_vliw_wait_cycles (cpu); | |
922 | return 0; | |
923 | } | |
924 | ||
925 | cycles = idesc->timing->units[unit_num].done; | |
926 | ||
927 | return cycles; | |
928 | } | |
929 | ||
930 | int | |
931 | frvbf_model_fr500_u_fr_r_store (SIM_CPU *cpu, const IDESC *idesc, | |
932 | int unit_num, int referenced, | |
933 | INT in_GRi, INT in_GRj, | |
934 | INT in_FRk, INT in_FRdoublek) | |
935 | { | |
936 | int cycles = frvbf_model_fr500_u_fr_store (cpu, idesc, unit_num, referenced, | |
937 | in_GRi, in_GRj, in_FRk, | |
938 | in_FRdoublek); | |
939 | ||
940 | if (model_insn == FRV_INSN_MODEL_PASS_2) | |
941 | { | |
942 | if (CPU_RSTR_INVALIDATE(cpu)) | |
943 | request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles); | |
944 | } | |
945 | ||
946 | return cycles; | |
947 | } | |
948 | ||
949 | int | |
950 | frvbf_model_fr500_u_swap (SIM_CPU *cpu, const IDESC *idesc, | |
951 | int unit_num, int referenced, | |
952 | INT in_GRi, INT in_GRj, INT out_GRk) | |
953 | { | |
954 | int cycles; | |
955 | ||
956 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
957 | { | |
958 | /* The entire VLIW insn must wait if there is a dependency on a register | |
959 | which is not ready yet. | |
960 | The latency of the registers may be less than previously recorded, | |
961 | depending on how they were used previously. | |
962 | See Table 13-8 in the LSI. */ | |
963 | if (in_GRi != out_GRk && in_GRi >= 0) | |
964 | { | |
965 | if (use_is_gr_complex (cpu, in_GRi)) | |
966 | decrease_GR_busy (cpu, in_GRi, 1); | |
967 | } | |
968 | if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) | |
969 | { | |
970 | if (use_is_gr_complex (cpu, in_GRj)) | |
971 | decrease_GR_busy (cpu, in_GRj, 1); | |
972 | } | |
973 | vliw_wait_for_GR (cpu, in_GRi); | |
974 | vliw_wait_for_GR (cpu, in_GRj); | |
975 | vliw_wait_for_GR (cpu, out_GRk); | |
976 | handle_resource_wait (cpu); | |
977 | load_wait_for_GR (cpu, in_GRi); | |
978 | load_wait_for_GR (cpu, in_GRj); | |
979 | load_wait_for_GR (cpu, out_GRk); | |
980 | trace_vliw_wait_cycles (cpu); | |
981 | return 0; | |
982 | } | |
983 | ||
984 | cycles = idesc->timing->units[unit_num].done; | |
985 | ||
986 | /* The latency of GRk will depend on how long it takes to swap | |
987 | the the data from the cache or memory. */ | |
988 | update_GR_latency_for_swap (cpu, out_GRk, cycles); | |
989 | set_use_is_gr_complex (cpu, out_GRk); | |
990 | ||
991 | return cycles; | |
992 | } | |
993 | ||
994 | int | |
995 | frvbf_model_fr500_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc, | |
996 | int unit_num, int referenced, | |
997 | INT in_FRj, INT out_FRk) | |
998 | { | |
999 | int cycles; | |
1000 | ||
1001 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1002 | { | |
1003 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1004 | which is not ready yet. */ | |
1005 | if (in_FRj >= 0) | |
1006 | { | |
1007 | if (use_is_media (cpu, in_FRj)) | |
1008 | decrease_FR_busy (cpu, in_FRj, 1); | |
1009 | else | |
1010 | adjust_float_register_busy (cpu, -1, in_FRj, -1, 1); | |
1011 | } | |
1012 | if (out_FRk >= 0 && out_FRk != in_FRj) | |
1013 | { | |
1014 | if (use_is_media (cpu, out_FRk)) | |
1015 | decrease_FR_busy (cpu, out_FRk, 1); | |
1016 | else | |
1017 | adjust_float_register_busy (cpu, -1, -1, out_FRk, 1); | |
1018 | } | |
1019 | vliw_wait_for_FR (cpu, in_FRj); | |
1020 | vliw_wait_for_FR (cpu, out_FRk); | |
1021 | handle_resource_wait (cpu); | |
1022 | load_wait_for_FR (cpu, in_FRj); | |
1023 | load_wait_for_FR (cpu, out_FRk); | |
1024 | trace_vliw_wait_cycles (cpu); | |
1025 | return 0; | |
1026 | } | |
1027 | ||
1028 | /* The latency of FRj is 3 cycles. */ | |
1029 | cycles = idesc->timing->units[unit_num].done; | |
1030 | update_FR_latency (cpu, out_FRk, cycles + 3); | |
1031 | ||
1032 | return cycles; | |
1033 | } | |
1034 | ||
1035 | int | |
1036 | frvbf_model_fr500_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
1037 | int unit_num, int referenced, | |
1038 | INT in_FRk, INT out_GRj) | |
1039 | { | |
1040 | int cycles; | |
1041 | ||
1042 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1043 | { | |
1044 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1045 | which is not ready yet. */ | |
1046 | if (in_FRk >= 0) | |
1047 | { | |
1048 | if (use_is_media (cpu, in_FRk)) | |
1049 | decrease_FR_busy (cpu, in_FRk, 1); | |
1050 | else | |
1051 | adjust_float_register_busy (cpu, -1, in_FRk, -1, 1); | |
1052 | } | |
1053 | vliw_wait_for_FR (cpu, in_FRk); | |
1054 | vliw_wait_for_GR (cpu, out_GRj); | |
1055 | handle_resource_wait (cpu); | |
1056 | load_wait_for_FR (cpu, in_FRk); | |
1057 | load_wait_for_GR (cpu, out_GRj); | |
1058 | trace_vliw_wait_cycles (cpu); | |
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | /* The latency of GRj is 2 cycles. */ | |
1063 | cycles = idesc->timing->units[unit_num].done; | |
1064 | update_GR_latency (cpu, out_GRj, cycles + 2); | |
1065 | set_use_is_gr_complex (cpu, out_GRj); | |
1066 | ||
1067 | return cycles; | |
1068 | } | |
1069 | ||
1070 | int | |
1071 | frvbf_model_fr500_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
1072 | int unit_num, int referenced, | |
1073 | INT in_spr, INT out_GRj) | |
1074 | { | |
1075 | int cycles; | |
1076 | ||
1077 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1078 | { | |
1079 | /* The entire VLIW insn must wait if there is a dependency on a register | |
153431d6 DB |
1080 | which is not ready yet. */ |
1081 | vliw_wait_for_SPR (cpu, in_spr); | |
b34f6357 DB |
1082 | vliw_wait_for_GR (cpu, out_GRj); |
1083 | handle_resource_wait (cpu); | |
1084 | load_wait_for_GR (cpu, out_GRj); | |
1085 | trace_vliw_wait_cycles (cpu); | |
1086 | return 0; | |
1087 | } | |
1088 | ||
1089 | cycles = idesc->timing->units[unit_num].done; | |
1090 | ||
1091 | #if 0 /* no latency? */ | |
1092 | /* The latency of GRj is 2 cycles. */ | |
1093 | update_GR_latency (cpu, out_GRj, cycles + 2); | |
1094 | #endif | |
1095 | ||
1096 | return cycles; | |
1097 | } | |
1098 | ||
1099 | int | |
1100 | frvbf_model_fr500_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, | |
1101 | int unit_num, int referenced, | |
1102 | INT in_GRj, INT out_FRk) | |
1103 | { | |
1104 | int cycles; | |
1105 | ||
1106 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1107 | { | |
1108 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1109 | which is not ready yet. | |
1110 | The latency of the registers may be less than previously recorded, | |
1111 | depending on how they were used previously. | |
1112 | See Table 13-8 in the LSI. */ | |
1113 | if (in_GRj >= 0) | |
1114 | { | |
1115 | if (use_is_gr_complex (cpu, in_GRj)) | |
1116 | decrease_GR_busy (cpu, in_GRj, 1); | |
1117 | } | |
1118 | if (out_FRk >= 0) | |
1119 | { | |
1120 | if (use_is_media (cpu, out_FRk)) | |
1121 | decrease_FR_busy (cpu, out_FRk, 1); | |
1122 | else | |
1c453cd6 | 1123 | adjust_float_register_busy (cpu, -1, -1, out_FRk, 1); |
b34f6357 DB |
1124 | } |
1125 | vliw_wait_for_GR (cpu, in_GRj); | |
1126 | vliw_wait_for_FR (cpu, out_FRk); | |
1127 | handle_resource_wait (cpu); | |
1128 | load_wait_for_GR (cpu, in_GRj); | |
1129 | load_wait_for_FR (cpu, out_FRk); | |
1130 | trace_vliw_wait_cycles (cpu); | |
1131 | return 0; | |
1132 | } | |
1133 | ||
1134 | /* The latency of FRk is 2 cycles. */ | |
1135 | cycles = idesc->timing->units[unit_num].done; | |
1136 | update_FR_latency (cpu, out_FRk, cycles + 2); | |
1137 | ||
1138 | /* Mark this use of the register as NOT a floating point op. */ | |
1139 | fr500_reset_fr_flags (cpu, out_FRk); | |
1140 | ||
1141 | return cycles; | |
1142 | } | |
1143 | ||
1144 | int | |
1145 | frvbf_model_fr500_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, | |
1146 | int unit_num, int referenced, | |
1147 | INT in_GRj, INT out_spr) | |
1148 | { | |
1149 | int cycles; | |
1150 | ||
1151 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1152 | { | |
1153 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1154 | which is not ready yet. | |
1155 | The latency of the registers may be less than previously recorded, | |
1156 | depending on how they were used previously. | |
1157 | See Table 13-8 in the LSI. */ | |
1158 | if (in_GRj >= 0) | |
1159 | { | |
1160 | if (use_is_gr_complex (cpu, in_GRj)) | |
1161 | decrease_GR_busy (cpu, in_GRj, 1); | |
1162 | } | |
1163 | vliw_wait_for_GR (cpu, in_GRj); | |
153431d6 | 1164 | vliw_wait_for_SPR (cpu, out_spr); |
b34f6357 DB |
1165 | handle_resource_wait (cpu); |
1166 | load_wait_for_GR (cpu, in_GRj); | |
1167 | trace_vliw_wait_cycles (cpu); | |
1168 | return 0; | |
1169 | } | |
1170 | ||
1171 | cycles = idesc->timing->units[unit_num].done; | |
1172 | ||
1173 | #if 0 | |
1174 | /* The latency of spr is ? cycles. */ | |
1175 | update_SPR_latency (cpu, out_spr, cycles + ?); | |
1176 | #endif | |
1177 | ||
1178 | return cycles; | |
1179 | } | |
1180 | ||
1181 | int | |
1182 | frvbf_model_fr500_u_ici (SIM_CPU *cpu, const IDESC *idesc, | |
1183 | int unit_num, int referenced, | |
1184 | INT in_GRi, INT in_GRj) | |
1185 | { | |
1186 | int cycles; | |
1187 | ||
1188 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1189 | { | |
1190 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1191 | which is not ready yet. | |
1192 | The latency of the registers may be less than previously recorded, | |
1193 | depending on how they were used previously. | |
1194 | See Table 13-8 in the LSI. */ | |
1195 | if (in_GRi >= 0) | |
1196 | { | |
1197 | if (use_is_gr_complex (cpu, in_GRi)) | |
1198 | decrease_GR_busy (cpu, in_GRi, 1); | |
1199 | } | |
1200 | if (in_GRj != in_GRi && in_GRj >= 0) | |
1201 | { | |
1202 | if (use_is_gr_complex (cpu, in_GRj)) | |
1203 | decrease_GR_busy (cpu, in_GRj, 1); | |
1204 | } | |
1205 | vliw_wait_for_GR (cpu, in_GRi); | |
1206 | vliw_wait_for_GR (cpu, in_GRj); | |
1207 | handle_resource_wait (cpu); | |
1208 | load_wait_for_GR (cpu, in_GRi); | |
1209 | load_wait_for_GR (cpu, in_GRj); | |
1210 | trace_vliw_wait_cycles (cpu); | |
1211 | return 0; | |
1212 | } | |
1213 | ||
1214 | cycles = idesc->timing->units[unit_num].done; | |
1215 | request_cache_invalidate (cpu, CPU_INSN_CACHE (cpu), cycles); | |
1216 | return cycles; | |
1217 | } | |
1218 | ||
1219 | int | |
1220 | frvbf_model_fr500_u_dci (SIM_CPU *cpu, const IDESC *idesc, | |
1221 | int unit_num, int referenced, | |
1222 | INT in_GRi, INT in_GRj) | |
1223 | { | |
1224 | int cycles; | |
1225 | ||
1226 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1227 | { | |
1228 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1229 | which is not ready yet. | |
1230 | The latency of the registers may be less than previously recorded, | |
1231 | depending on how they were used previously. | |
1232 | See Table 13-8 in the LSI. */ | |
1233 | if (in_GRi >= 0) | |
1234 | { | |
1235 | if (use_is_gr_complex (cpu, in_GRi)) | |
1236 | decrease_GR_busy (cpu, in_GRi, 1); | |
1237 | } | |
1238 | if (in_GRj != in_GRi && in_GRj >= 0) | |
1239 | { | |
1240 | if (use_is_gr_complex (cpu, in_GRj)) | |
1241 | decrease_GR_busy (cpu, in_GRj, 1); | |
1242 | } | |
1243 | vliw_wait_for_GR (cpu, in_GRi); | |
1244 | vliw_wait_for_GR (cpu, in_GRj); | |
1245 | handle_resource_wait (cpu); | |
1246 | load_wait_for_GR (cpu, in_GRi); | |
1247 | load_wait_for_GR (cpu, in_GRj); | |
1248 | trace_vliw_wait_cycles (cpu); | |
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | cycles = idesc->timing->units[unit_num].done; | |
1253 | request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles); | |
1254 | return cycles; | |
1255 | } | |
1256 | ||
1257 | int | |
1258 | frvbf_model_fr500_u_dcf (SIM_CPU *cpu, const IDESC *idesc, | |
1259 | int unit_num, int referenced, | |
1260 | INT in_GRi, INT in_GRj) | |
1261 | { | |
1262 | int cycles; | |
1263 | ||
1264 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1265 | { | |
1266 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1267 | which is not ready yet. | |
1268 | The latency of the registers may be less than previously recorded, | |
1269 | depending on how they were used previously. | |
1270 | See Table 13-8 in the LSI. */ | |
1271 | if (in_GRi >= 0) | |
1272 | { | |
1273 | if (use_is_gr_complex (cpu, in_GRi)) | |
1274 | decrease_GR_busy (cpu, in_GRi, 1); | |
1275 | } | |
1276 | if (in_GRj != in_GRi && in_GRj >= 0) | |
1277 | { | |
1278 | if (use_is_gr_complex (cpu, in_GRj)) | |
1279 | decrease_GR_busy (cpu, in_GRj, 1); | |
1280 | } | |
1281 | vliw_wait_for_GR (cpu, in_GRi); | |
1282 | vliw_wait_for_GR (cpu, in_GRj); | |
1283 | handle_resource_wait (cpu); | |
1284 | load_wait_for_GR (cpu, in_GRi); | |
1285 | load_wait_for_GR (cpu, in_GRj); | |
1286 | trace_vliw_wait_cycles (cpu); | |
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | cycles = idesc->timing->units[unit_num].done; | |
1291 | request_cache_flush (cpu, CPU_DATA_CACHE (cpu), cycles); | |
1292 | return cycles; | |
1293 | } | |
1294 | ||
1295 | int | |
1296 | frvbf_model_fr500_u_icpl (SIM_CPU *cpu, const IDESC *idesc, | |
1297 | int unit_num, int referenced, | |
1298 | INT in_GRi, INT in_GRj) | |
1299 | { | |
1300 | int cycles; | |
1301 | ||
1302 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1303 | { | |
1304 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1305 | which is not ready yet. | |
1306 | The latency of the registers may be less than previously recorded, | |
1307 | depending on how they were used previously. | |
1308 | See Table 13-8 in the LSI. */ | |
1309 | if (in_GRi >= 0) | |
1310 | { | |
1311 | if (use_is_gr_complex (cpu, in_GRi)) | |
1312 | decrease_GR_busy (cpu, in_GRi, 1); | |
1313 | } | |
1314 | if (in_GRj != in_GRi && in_GRj >= 0) | |
1315 | { | |
1316 | if (use_is_gr_complex (cpu, in_GRj)) | |
1317 | decrease_GR_busy (cpu, in_GRj, 1); | |
1318 | } | |
1319 | vliw_wait_for_GR (cpu, in_GRi); | |
1320 | vliw_wait_for_GR (cpu, in_GRj); | |
1321 | handle_resource_wait (cpu); | |
1322 | load_wait_for_GR (cpu, in_GRi); | |
1323 | load_wait_for_GR (cpu, in_GRj); | |
1324 | trace_vliw_wait_cycles (cpu); | |
1325 | return 0; | |
1326 | } | |
1327 | ||
1328 | cycles = idesc->timing->units[unit_num].done; | |
1329 | request_cache_preload (cpu, CPU_INSN_CACHE (cpu), cycles); | |
1330 | return cycles; | |
1331 | } | |
1332 | ||
1333 | int | |
1334 | frvbf_model_fr500_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, | |
1335 | int unit_num, int referenced, | |
1336 | INT in_GRi, INT in_GRj) | |
1337 | { | |
1338 | int cycles; | |
1339 | ||
1340 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1341 | { | |
1342 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1343 | which is not ready yet. | |
1344 | The latency of the registers may be less than previously recorded, | |
1345 | depending on how they were used previously. | |
1346 | See Table 13-8 in the LSI. */ | |
1347 | if (in_GRi >= 0) | |
1348 | { | |
1349 | if (use_is_gr_complex (cpu, in_GRi)) | |
1350 | decrease_GR_busy (cpu, in_GRi, 1); | |
1351 | } | |
1352 | if (in_GRj != in_GRi && in_GRj >= 0) | |
1353 | { | |
1354 | if (use_is_gr_complex (cpu, in_GRj)) | |
1355 | decrease_GR_busy (cpu, in_GRj, 1); | |
1356 | } | |
1357 | vliw_wait_for_GR (cpu, in_GRi); | |
1358 | vliw_wait_for_GR (cpu, in_GRj); | |
1359 | handle_resource_wait (cpu); | |
1360 | load_wait_for_GR (cpu, in_GRi); | |
1361 | load_wait_for_GR (cpu, in_GRj); | |
1362 | trace_vliw_wait_cycles (cpu); | |
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | cycles = idesc->timing->units[unit_num].done; | |
1367 | request_cache_preload (cpu, CPU_DATA_CACHE (cpu), cycles); | |
1368 | return cycles; | |
1369 | } | |
1370 | ||
1371 | int | |
1372 | frvbf_model_fr500_u_icul (SIM_CPU *cpu, const IDESC *idesc, | |
1373 | int unit_num, int referenced, | |
1374 | INT in_GRi, INT in_GRj) | |
1375 | { | |
1376 | int cycles; | |
1377 | ||
1378 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1379 | { | |
1380 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1381 | which is not ready yet. | |
1382 | The latency of the registers may be less than previously recorded, | |
1383 | depending on how they were used previously. | |
1384 | See Table 13-8 in the LSI. */ | |
1385 | if (in_GRi >= 0) | |
1386 | { | |
1387 | if (use_is_gr_complex (cpu, in_GRi)) | |
1388 | decrease_GR_busy (cpu, in_GRi, 1); | |
1389 | } | |
1390 | if (in_GRj != in_GRi && in_GRj >= 0) | |
1391 | { | |
1392 | if (use_is_gr_complex (cpu, in_GRj)) | |
1393 | decrease_GR_busy (cpu, in_GRj, 1); | |
1394 | } | |
1395 | vliw_wait_for_GR (cpu, in_GRi); | |
1396 | vliw_wait_for_GR (cpu, in_GRj); | |
1397 | handle_resource_wait (cpu); | |
1398 | load_wait_for_GR (cpu, in_GRi); | |
1399 | load_wait_for_GR (cpu, in_GRj); | |
1400 | trace_vliw_wait_cycles (cpu); | |
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | cycles = idesc->timing->units[unit_num].done; | |
1405 | request_cache_unlock (cpu, CPU_INSN_CACHE (cpu), cycles); | |
1406 | return cycles; | |
1407 | } | |
1408 | ||
1409 | int | |
1410 | frvbf_model_fr500_u_dcul (SIM_CPU *cpu, const IDESC *idesc, | |
1411 | int unit_num, int referenced, | |
1412 | INT in_GRi, INT in_GRj) | |
1413 | { | |
1414 | int cycles; | |
1415 | ||
1416 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1417 | { | |
1418 | /* The entire VLIW insn must wait if there is a dependency on a register | |
1419 | which is not ready yet. | |
1420 | The latency of the registers may be less than previously recorded, | |
1421 | depending on how they were used previously. | |
1422 | See Table 13-8 in the LSI. */ | |
1423 | if (in_GRi >= 0) | |
1424 | { | |
1425 | if (use_is_gr_complex (cpu, in_GRi)) | |
1426 | decrease_GR_busy (cpu, in_GRi, 1); | |
1427 | } | |
1428 | if (in_GRj != in_GRi && in_GRj >= 0) | |
1429 | { | |
1430 | if (use_is_gr_complex (cpu, in_GRj)) | |
1431 | decrease_GR_busy (cpu, in_GRj, 1); | |
1432 | } | |
1433 | vliw_wait_for_GR (cpu, in_GRi); | |
1434 | vliw_wait_for_GR (cpu, in_GRj); | |
1435 | handle_resource_wait (cpu); | |
1436 | load_wait_for_GR (cpu, in_GRi); | |
1437 | load_wait_for_GR (cpu, in_GRj); | |
1438 | trace_vliw_wait_cycles (cpu); | |
1439 | return 0; | |
1440 | } | |
1441 | ||
1442 | cycles = idesc->timing->units[unit_num].done; | |
1443 | request_cache_unlock (cpu, CPU_DATA_CACHE (cpu), cycles); | |
1444 | return cycles; | |
1445 | } | |
1446 | ||
b34f6357 DB |
1447 | int |
1448 | frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc, | |
1449 | int unit_num, int referenced, | |
1450 | INT in_FRi, INT in_FRj, | |
1451 | INT in_FRdoublei, INT in_FRdoublej, | |
1452 | INT out_FRk, INT out_FRdoublek) | |
1453 | { | |
1454 | int cycles; | |
1455 | FRV_PROFILE_STATE *ps; | |
1456 | ||
1457 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1458 | return 0; | |
1459 | ||
1460 | /* The preprocessing can execute right away. */ | |
1461 | cycles = idesc->timing->units[unit_num].done; | |
1462 | ||
1463 | /* The post processing must wait if there is a dependency on a FR | |
1464 | which is not ready yet. */ | |
1465 | adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); | |
1466 | adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, | |
1467 | 1); | |
1468 | ps = CPU_PROFILE_STATE (cpu); | |
1469 | ps->post_wait = cycles; | |
1470 | post_wait_for_FR (cpu, in_FRi); | |
1471 | post_wait_for_FR (cpu, in_FRj); | |
1472 | post_wait_for_FR (cpu, out_FRk); | |
1473 | post_wait_for_FRdouble (cpu, in_FRdoublei); | |
1474 | post_wait_for_FRdouble (cpu, in_FRdoublej); | |
1475 | post_wait_for_FRdouble (cpu, out_FRdoublek); | |
1c453cd6 DB |
1476 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1477 | { | |
1478 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
1479 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); | |
1480 | } | |
b34f6357 DB |
1481 | restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); |
1482 | restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, | |
1483 | 1); | |
1484 | ||
1485 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
1486 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1487 | update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); | |
1488 | ||
1c453cd6 DB |
1489 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1490 | { | |
1491 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); | |
1492 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); | |
1493 | } | |
1494 | ||
b34f6357 DB |
1495 | /* Once initiated, post-processing will take 3 cycles. */ |
1496 | update_FR_ptime (cpu, out_FRk, 3); | |
1497 | update_FRdouble_ptime (cpu, out_FRdoublek, 3); | |
1498 | ||
1c453cd6 DB |
1499 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1500 | { | |
1501 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); | |
1502 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); | |
1503 | } | |
1504 | ||
b34f6357 DB |
1505 | /* Mark this use of the register as a floating point op. */ |
1506 | if (out_FRk >= 0) | |
1507 | set_use_is_fpop (cpu, out_FRk); | |
1508 | if (out_FRdoublek >= 0) | |
1509 | { | |
1510 | set_use_is_fpop (cpu, out_FRdoublek); | |
1511 | if (out_FRdoublek < 63) | |
1512 | set_use_is_fpop (cpu, out_FRdoublek + 1); | |
1513 | } | |
1514 | ||
1515 | return cycles; | |
1516 | } | |
1517 | ||
1518 | int | |
1519 | frvbf_model_fr500_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc, | |
1520 | int unit_num, int referenced, | |
1521 | INT in_FRi, INT in_FRj, | |
1522 | INT in_FRdoublei, INT in_FRdoublej, | |
1523 | INT out_FRk, INT out_FRdoublek) | |
1524 | { | |
1525 | int cycles; | |
1526 | INT dual_FRi; | |
1527 | INT dual_FRj; | |
1528 | INT dual_FRk; | |
1529 | INT dual_FRdoublei; | |
1530 | INT dual_FRdoublej; | |
1531 | INT dual_FRdoublek; | |
1532 | FRV_PROFILE_STATE *ps; | |
1533 | ||
1534 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1535 | return 0; | |
1536 | ||
1537 | /* The preprocessing can execute right away. */ | |
1538 | cycles = idesc->timing->units[unit_num].done; | |
1539 | ||
1540 | /* The post processing must wait if there is a dependency on a FR | |
1541 | which is not ready yet. */ | |
1542 | dual_FRi = DUAL_REG (in_FRi); | |
1543 | dual_FRj = DUAL_REG (in_FRj); | |
1544 | dual_FRk = DUAL_REG (out_FRk); | |
1545 | dual_FRdoublei = DUAL_DOUBLE (in_FRdoublei); | |
1546 | dual_FRdoublej = DUAL_DOUBLE (in_FRdoublej); | |
1547 | dual_FRdoublek = DUAL_DOUBLE (out_FRdoublek); | |
1548 | ||
1549 | adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); | |
1550 | adjust_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1); | |
1551 | adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, | |
1552 | 1); | |
1553 | adjust_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej, | |
1554 | dual_FRdoublek, 1); | |
1555 | ps = CPU_PROFILE_STATE (cpu); | |
1556 | ps->post_wait = cycles; | |
1557 | post_wait_for_FR (cpu, in_FRi); | |
1558 | post_wait_for_FR (cpu, in_FRj); | |
1559 | post_wait_for_FR (cpu, out_FRk); | |
1560 | post_wait_for_FR (cpu, dual_FRi); | |
1561 | post_wait_for_FR (cpu, dual_FRj); | |
1562 | post_wait_for_FR (cpu, dual_FRk); | |
1563 | post_wait_for_FRdouble (cpu, in_FRdoublei); | |
1564 | post_wait_for_FRdouble (cpu, in_FRdoublej); | |
1565 | post_wait_for_FRdouble (cpu, out_FRdoublek); | |
1566 | post_wait_for_FRdouble (cpu, dual_FRdoublei); | |
1567 | post_wait_for_FRdouble (cpu, dual_FRdoublej); | |
1568 | post_wait_for_FRdouble (cpu, dual_FRdoublek); | |
1c453cd6 DB |
1569 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1570 | { | |
1571 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
1572 | post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRk)); | |
1573 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); | |
1574 | post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRdoublek)); | |
1575 | } | |
b34f6357 DB |
1576 | restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); |
1577 | restore_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1); | |
1578 | restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, | |
1579 | 1); | |
1580 | restore_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej, | |
1581 | dual_FRdoublek, 1); | |
1582 | ||
1583 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
1584 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1585 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
1586 | update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); | |
1587 | update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait); | |
1588 | ||
1c453cd6 DB |
1589 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1590 | { | |
1591 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); | |
1592 | update_SPR_latency (cpu, FNER_FOR_FR (dual_FRk), ps->post_wait); | |
1593 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); | |
1594 | update_SPR_latency (cpu, FNER_FOR_FR (dual_FRdoublek), ps->post_wait); | |
1595 | } | |
1596 | ||
b34f6357 DB |
1597 | /* Once initiated, post-processing will take 3 cycles. */ |
1598 | update_FR_ptime (cpu, out_FRk, 3); | |
1599 | update_FR_ptime (cpu, dual_FRk, 3); | |
1600 | update_FRdouble_ptime (cpu, out_FRdoublek, 3); | |
1601 | update_FRdouble_ptime (cpu, dual_FRdoublek, 3); | |
1602 | ||
1c453cd6 DB |
1603 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1604 | { | |
1605 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); | |
1606 | update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRk), 3); | |
1607 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); | |
1608 | update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRdoublek), 3); | |
1609 | } | |
1610 | ||
b34f6357 DB |
1611 | /* Mark this use of the register as a floating point op. */ |
1612 | if (out_FRk >= 0) | |
1613 | set_use_is_fpop (cpu, out_FRk); | |
1614 | if (dual_FRk >= 0) | |
1615 | set_use_is_fpop (cpu, dual_FRk); | |
1616 | if (out_FRdoublek >= 0) | |
1617 | { | |
1618 | set_use_is_fpop (cpu, out_FRdoublek); | |
1619 | if (out_FRdoublek < 63) | |
1620 | set_use_is_fpop (cpu, out_FRdoublek + 1); | |
1621 | } | |
1622 | if (dual_FRdoublek >= 0) | |
1623 | { | |
1624 | set_use_is_fpop (cpu, dual_FRdoublek); | |
1625 | if (dual_FRdoublek < 63) | |
1626 | set_use_is_fpop (cpu, dual_FRdoublek + 1); | |
1627 | } | |
1628 | ||
1629 | return cycles; | |
1630 | } | |
1631 | ||
1632 | int | |
1633 | frvbf_model_fr500_u_float_div (SIM_CPU *cpu, const IDESC *idesc, | |
1634 | int unit_num, int referenced, | |
1635 | INT in_FRi, INT in_FRj, INT out_FRk) | |
1636 | { | |
1637 | int cycles; | |
1638 | FRV_VLIW *vliw; | |
1639 | int slot; | |
1640 | FRV_PROFILE_STATE *ps; | |
1641 | ||
1642 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1643 | return 0; | |
1644 | ||
1645 | cycles = idesc->timing->units[unit_num].done; | |
1646 | ||
1647 | /* The post processing must wait if there is a dependency on a FR | |
1648 | which is not ready yet. */ | |
1649 | adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); | |
1650 | ps = CPU_PROFILE_STATE (cpu); | |
1651 | ps->post_wait = cycles; | |
1652 | post_wait_for_FR (cpu, in_FRi); | |
1653 | post_wait_for_FR (cpu, in_FRj); | |
1654 | post_wait_for_FR (cpu, out_FRk); | |
1c453cd6 DB |
1655 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1656 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
b34f6357 DB |
1657 | vliw = CPU_VLIW (cpu); |
1658 | slot = vliw->next_slot - 1; | |
1659 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1660 | post_wait_for_fdiv (cpu, slot); | |
1661 | restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); | |
1662 | ||
1663 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
1664 | /* Once initiated, post-processing will take 10 cycles. */ | |
1665 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1666 | update_FR_ptime (cpu, out_FRk, 10); | |
1667 | ||
1c453cd6 DB |
1668 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1669 | { | |
1670 | /* FNER has a latency of 10 cycles. */ | |
1671 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); | |
1672 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 10); | |
1673 | } | |
1674 | ||
b34f6357 DB |
1675 | /* The latency of the fdiv unit will be at least the latency of the other |
1676 | inputs. Once initiated, post-processing will take 9 cycles. */ | |
1677 | update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9); | |
1678 | ||
1679 | /* Mark this use of the register as a floating point op. */ | |
1680 | set_use_is_fpop (cpu, out_FRk); | |
1681 | ||
1682 | return cycles; | |
1683 | } | |
1684 | ||
1685 | int | |
1686 | frvbf_model_fr500_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc, | |
1687 | int unit_num, int referenced, | |
1688 | INT in_FRj, INT in_FRdoublej, | |
1689 | INT out_FRk, INT out_FRdoublek) | |
1690 | { | |
1691 | int cycles; | |
1692 | FRV_VLIW *vliw; | |
1693 | int slot; | |
1694 | FRV_PROFILE_STATE *ps; | |
1695 | ||
1696 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1697 | return 0; | |
1698 | ||
1699 | cycles = idesc->timing->units[unit_num].done; | |
1700 | ||
1701 | /* The post processing must wait if there is a dependency on a FR | |
1702 | which is not ready yet. */ | |
1703 | adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); | |
1704 | adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); | |
1705 | ps = CPU_PROFILE_STATE (cpu); | |
1706 | ps->post_wait = cycles; | |
1707 | post_wait_for_FR (cpu, in_FRj); | |
1708 | post_wait_for_FR (cpu, out_FRk); | |
1709 | post_wait_for_FRdouble (cpu, in_FRdoublej); | |
1710 | post_wait_for_FRdouble (cpu, out_FRdoublek); | |
1c453cd6 DB |
1711 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1712 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
b34f6357 DB |
1713 | vliw = CPU_VLIW (cpu); |
1714 | slot = vliw->next_slot - 1; | |
1715 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1716 | post_wait_for_fsqrt (cpu, slot); | |
1717 | restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); | |
1718 | restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); | |
1719 | ||
1720 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
1721 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1722 | update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); | |
1c453cd6 DB |
1723 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1724 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); | |
b34f6357 DB |
1725 | |
1726 | /* Once initiated, post-processing will take 15 cycles. */ | |
1727 | update_FR_ptime (cpu, out_FRk, 15); | |
1728 | update_FRdouble_ptime (cpu, out_FRdoublek, 15); | |
1729 | ||
1c453cd6 DB |
1730 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1731 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 15); | |
1732 | ||
b34f6357 DB |
1733 | /* The latency of the sqrt unit will be the latency of the other |
1734 | inputs plus 14 cycles. */ | |
1735 | update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14); | |
1736 | ||
1737 | /* Mark this use of the register as a floating point op. */ | |
1738 | if (out_FRk >= 0) | |
1739 | set_use_is_fpop (cpu, out_FRk); | |
1740 | if (out_FRdoublek >= 0) | |
1741 | { | |
1742 | set_use_is_fpop (cpu, out_FRdoublek); | |
1743 | if (out_FRdoublek < 63) | |
1744 | set_use_is_fpop (cpu, out_FRdoublek + 1); | |
1745 | } | |
1746 | ||
1747 | return cycles; | |
1748 | } | |
1749 | ||
1750 | int | |
1751 | frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU *cpu, const IDESC *idesc, | |
1752 | int unit_num, int referenced, | |
1753 | INT in_FRj, INT out_FRk) | |
1754 | { | |
1755 | int cycles; | |
1756 | FRV_VLIW *vliw; | |
1757 | int slot; | |
1758 | INT dual_FRj; | |
1759 | INT dual_FRk; | |
1760 | FRV_PROFILE_STATE *ps; | |
1761 | ||
1762 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1763 | return 0; | |
1764 | ||
1765 | cycles = idesc->timing->units[unit_num].done; | |
1766 | ||
1767 | /* The post processing must wait if there is a dependency on a FR | |
1768 | which is not ready yet. */ | |
1769 | dual_FRj = DUAL_REG (in_FRj); | |
1770 | dual_FRk = DUAL_REG (out_FRk); | |
1771 | adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); | |
1772 | adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); | |
1773 | ps = CPU_PROFILE_STATE (cpu); | |
1774 | ps->post_wait = cycles; | |
1775 | post_wait_for_FR (cpu, in_FRj); | |
1776 | post_wait_for_FR (cpu, out_FRk); | |
1777 | post_wait_for_FR (cpu, dual_FRj); | |
1778 | post_wait_for_FR (cpu, dual_FRk); | |
1779 | ||
1780 | vliw = CPU_VLIW (cpu); | |
1781 | slot = vliw->next_slot - 1; | |
1782 | slot = (*vliw->current_vliw)[slot] - UNIT_FM0; | |
1783 | post_wait_for_fsqrt (cpu, slot); | |
1784 | restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); | |
1785 | restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); | |
1786 | ||
1787 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
1788 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1789 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
1790 | ||
1791 | /* Once initiated, post-processing will take 15 cycles. */ | |
1792 | update_FR_ptime (cpu, out_FRk, 15); | |
1793 | update_FR_ptime (cpu, dual_FRk, 15); | |
1794 | ||
1795 | /* The latency of the sqrt unit will be at least the latency of the other | |
1796 | inputs. */ | |
1797 | update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14); | |
1798 | ||
1799 | /* Mark this use of the register as a floating point op. */ | |
1800 | if (out_FRk >= 0) | |
1801 | set_use_is_fpop (cpu, out_FRk); | |
1802 | if (dual_FRk >= 0) | |
1803 | set_use_is_fpop (cpu, dual_FRk); | |
1804 | ||
1805 | return cycles; | |
1806 | } | |
1807 | ||
1808 | int | |
1809 | frvbf_model_fr500_u_float_compare (SIM_CPU *cpu, const IDESC *idesc, | |
1810 | int unit_num, int referenced, | |
1811 | INT in_FRi, INT in_FRj, | |
1812 | INT in_FRdoublei, INT in_FRdoublej, | |
1813 | INT out_FCCi_2) | |
1814 | { | |
1815 | int cycles; | |
1816 | FRV_PROFILE_STATE *ps; | |
1817 | ||
1818 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1819 | return 0; | |
1820 | ||
1821 | /* The preprocessing can execute right away. */ | |
1822 | cycles = idesc->timing->units[unit_num].done; | |
1823 | ||
1824 | /* The post processing must wait if there is a dependency on a FR | |
1825 | which is not ready yet. */ | |
1826 | adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1); | |
1827 | ps = CPU_PROFILE_STATE (cpu); | |
1828 | ps->post_wait = cycles; | |
1829 | post_wait_for_FR (cpu, in_FRi); | |
1830 | post_wait_for_FR (cpu, in_FRj); | |
1831 | post_wait_for_FRdouble (cpu, in_FRdoublei); | |
1832 | post_wait_for_FRdouble (cpu, in_FRdoublej); | |
1833 | post_wait_for_CCR (cpu, out_FCCi_2); | |
1834 | restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1); | |
1835 | ||
1836 | /* The latency of FCCi_2 will be the latency of the other inputs plus 3 | |
1837 | cycles. */ | |
1838 | update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3); | |
1839 | ||
1840 | return cycles; | |
1841 | } | |
1842 | ||
1843 | int | |
1844 | frvbf_model_fr500_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc, | |
1845 | int unit_num, int referenced, | |
1846 | INT in_FRi, INT in_FRj, | |
1847 | INT out_FCCi_2) | |
1848 | { | |
1849 | int cycles; | |
1850 | INT dual_FRi; | |
1851 | INT dual_FRj; | |
1852 | INT dual_FCCi_2; | |
1853 | FRV_PROFILE_STATE *ps; | |
1854 | ||
1855 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1856 | return 0; | |
1857 | ||
1858 | /* The preprocessing can execute right away. */ | |
1859 | cycles = idesc->timing->units[unit_num].done; | |
1860 | ||
1861 | /* The post processing must wait if there is a dependency on a FR | |
1862 | which is not ready yet. */ | |
1863 | ps = CPU_PROFILE_STATE (cpu); | |
1864 | ps->post_wait = cycles; | |
1865 | dual_FRi = DUAL_REG (in_FRi); | |
1866 | dual_FRj = DUAL_REG (in_FRj); | |
1867 | dual_FCCi_2 = out_FCCi_2 + 1; | |
1868 | adjust_float_register_busy (cpu, in_FRi, in_FRj, -1, 1); | |
1869 | adjust_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1); | |
1870 | post_wait_for_FR (cpu, in_FRi); | |
1871 | post_wait_for_FR (cpu, in_FRj); | |
1872 | post_wait_for_FR (cpu, dual_FRi); | |
1873 | post_wait_for_FR (cpu, dual_FRj); | |
1874 | post_wait_for_CCR (cpu, out_FCCi_2); | |
1875 | post_wait_for_CCR (cpu, dual_FCCi_2); | |
1876 | restore_float_register_busy (cpu, in_FRi, in_FRj, -1, 1); | |
1877 | restore_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1); | |
1878 | ||
1879 | /* The latency of FCCi_2 will be the latency of the other inputs plus 3 | |
1880 | cycles. */ | |
1881 | update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3); | |
1882 | update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3); | |
1883 | ||
1884 | return cycles; | |
1885 | } | |
1886 | ||
1887 | int | |
1888 | frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc, | |
1889 | int unit_num, int referenced, | |
1890 | INT in_FRj, INT in_FRintj, INT in_FRdoublej, | |
1891 | INT out_FRk, INT out_FRintk, | |
1892 | INT out_FRdoublek) | |
1893 | { | |
1894 | int cycles; | |
1895 | FRV_PROFILE_STATE *ps; | |
1896 | ||
1897 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1898 | return 0; | |
1899 | ||
1900 | /* The preprocessing can execute right away. */ | |
1901 | cycles = idesc->timing->units[unit_num].done; | |
1902 | ||
1903 | /* The post processing must wait if there is a dependency on a FR | |
1904 | which is not ready yet. */ | |
1905 | ps = CPU_PROFILE_STATE (cpu); | |
1906 | ps->post_wait = cycles; | |
1907 | adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); | |
1908 | adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); | |
1909 | adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); | |
1910 | post_wait_for_FR (cpu, in_FRj); | |
1911 | post_wait_for_FR (cpu, in_FRintj); | |
1912 | post_wait_for_FRdouble (cpu, in_FRdoublej); | |
1913 | post_wait_for_FR (cpu, out_FRk); | |
1914 | post_wait_for_FR (cpu, out_FRintk); | |
1915 | post_wait_for_FRdouble (cpu, out_FRdoublek); | |
1c453cd6 DB |
1916 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1917 | { | |
1918 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); | |
1919 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRintk)); | |
1920 | post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); | |
1921 | } | |
b34f6357 DB |
1922 | restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); |
1923 | restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); | |
1924 | restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); | |
1925 | ||
1926 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
1927 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1928 | update_FR_latency (cpu, out_FRintk, ps->post_wait); | |
1929 | update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); | |
1930 | ||
1c453cd6 DB |
1931 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1932 | { | |
1933 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); | |
1934 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRintk), ps->post_wait); | |
1935 | update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); | |
1936 | } | |
1937 | ||
b34f6357 DB |
1938 | /* Once initiated, post-processing will take 3 cycles. */ |
1939 | update_FR_ptime (cpu, out_FRk, 3); | |
1940 | update_FR_ptime (cpu, out_FRintk, 3); | |
1941 | update_FRdouble_ptime (cpu, out_FRdoublek, 3); | |
1942 | ||
1c453cd6 DB |
1943 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) |
1944 | { | |
1945 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); | |
1946 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRintk), 3); | |
1947 | update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); | |
1948 | } | |
1949 | ||
b34f6357 DB |
1950 | /* Mark this use of the register as a floating point op. */ |
1951 | if (out_FRk >= 0) | |
1952 | set_use_is_fpop (cpu, out_FRk); | |
1953 | if (out_FRintk >= 0) | |
1954 | set_use_is_fpop (cpu, out_FRintk); | |
1955 | if (out_FRdoublek >= 0) | |
1956 | { | |
1957 | set_use_is_fpop (cpu, out_FRdoublek); | |
1958 | set_use_is_fpop (cpu, out_FRdoublek + 1); | |
1959 | } | |
1960 | ||
1961 | return cycles; | |
1962 | } | |
1963 | ||
1964 | int | |
1965 | frvbf_model_fr500_u_float_dual_convert (SIM_CPU *cpu, const IDESC *idesc, | |
1966 | int unit_num, int referenced, | |
1967 | INT in_FRj, INT in_FRintj, | |
1968 | INT out_FRk, INT out_FRintk) | |
1969 | { | |
1970 | int cycles; | |
1971 | INT dual_FRj; | |
1972 | INT dual_FRintj; | |
1973 | INT dual_FRk; | |
1974 | INT dual_FRintk; | |
1975 | FRV_PROFILE_STATE *ps; | |
1976 | ||
1977 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1978 | return 0; | |
1979 | ||
1980 | /* The preprocessing can execute right away. */ | |
1981 | cycles = idesc->timing->units[unit_num].done; | |
1982 | ||
1983 | /* The post processing must wait if there is a dependency on a FR | |
1984 | which is not ready yet. */ | |
1985 | ps = CPU_PROFILE_STATE (cpu); | |
1986 | ps->post_wait = cycles; | |
1987 | dual_FRj = DUAL_REG (in_FRj); | |
1988 | dual_FRintj = DUAL_REG (in_FRintj); | |
1989 | dual_FRk = DUAL_REG (out_FRk); | |
1990 | dual_FRintk = DUAL_REG (out_FRintk); | |
1991 | adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); | |
1992 | adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); | |
1993 | adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); | |
1994 | adjust_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1); | |
1995 | post_wait_for_FR (cpu, in_FRj); | |
1996 | post_wait_for_FR (cpu, in_FRintj); | |
1997 | post_wait_for_FR (cpu, out_FRk); | |
1998 | post_wait_for_FR (cpu, out_FRintk); | |
1999 | post_wait_for_FR (cpu, dual_FRj); | |
2000 | post_wait_for_FR (cpu, dual_FRintj); | |
2001 | post_wait_for_FR (cpu, dual_FRk); | |
2002 | post_wait_for_FR (cpu, dual_FRintk); | |
2003 | restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); | |
2004 | restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); | |
2005 | restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); | |
2006 | restore_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1); | |
2007 | ||
2008 | /* The latency of FRk will be at least the latency of the other inputs. */ | |
2009 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
2010 | update_FR_latency (cpu, out_FRintk, ps->post_wait); | |
2011 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
2012 | update_FR_latency (cpu, dual_FRintk, ps->post_wait); | |
2013 | ||
2014 | /* Once initiated, post-processing will take 3 cycles. */ | |
2015 | update_FR_ptime (cpu, out_FRk, 3); | |
2016 | update_FR_ptime (cpu, out_FRintk, 3); | |
2017 | update_FR_ptime (cpu, dual_FRk, 3); | |
2018 | update_FR_ptime (cpu, dual_FRintk, 3); | |
2019 | ||
2020 | /* Mark this use of the register as a floating point op. */ | |
2021 | if (out_FRk >= 0) | |
2022 | set_use_is_fpop (cpu, out_FRk); | |
2023 | if (out_FRintk >= 0) | |
2024 | set_use_is_fpop (cpu, out_FRintk); | |
2025 | ||
2026 | return cycles; | |
2027 | } | |
2028 | ||
2029 | int | |
2030 | frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc, | |
2031 | int unit_num, int referenced, | |
2032 | INT in_FRi, INT in_FRj, INT in_ACC40Si, INT in_ACCGi, | |
2033 | INT out_FRk, | |
2034 | INT out_ACC40Sk, INT out_ACC40Uk, INT out_ACCGk) | |
2035 | { | |
2036 | int cycles; | |
2037 | FRV_PROFILE_STATE *ps; | |
2038 | const CGEN_INSN *insn; | |
2039 | int is_media_s1; | |
2040 | int is_media_s2; | |
2041 | int busy_adjustment[] = {0, 0, 0}; | |
2042 | int *fr; | |
2043 | int *acc; | |
2044 | ||
2045 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2046 | return 0; | |
2047 | ||
2048 | /* The preprocessing can execute right away. */ | |
2049 | cycles = idesc->timing->units[unit_num].done; | |
2050 | ||
2051 | ps = CPU_PROFILE_STATE (cpu); | |
2052 | insn = idesc->idata; | |
2053 | ||
2054 | /* If the previous use of the registers was a media op, | |
2055 | then their latency will be less than previously recorded. | |
2056 | See Table 13-13 in the LSI. */ | |
2057 | if (in_FRi >= 0) | |
2058 | { | |
2059 | if (use_is_media (cpu, in_FRi)) | |
2060 | { | |
2061 | busy_adjustment[0] = 2; | |
2062 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
2063 | } | |
2064 | else | |
2065 | enforce_full_fr_latency (cpu, in_FRi); | |
2066 | } | |
2067 | if (in_FRj >= 0 && in_FRj != in_FRi) | |
2068 | { | |
2069 | if (use_is_media (cpu, in_FRj)) | |
2070 | { | |
2071 | busy_adjustment[1] = 2; | |
2072 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); | |
2073 | } | |
2074 | else | |
2075 | enforce_full_fr_latency (cpu, in_FRj); | |
2076 | } | |
2077 | if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj) | |
2078 | { | |
2079 | if (use_is_media (cpu, out_FRk)) | |
2080 | { | |
2081 | busy_adjustment[2] = 2; | |
2082 | decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]); | |
2083 | } | |
2084 | else | |
2085 | enforce_full_fr_latency (cpu, out_FRk); | |
2086 | } | |
2087 | ||
2088 | /* The post processing must wait if there is a dependency on a FR | |
2089 | which is not ready yet. */ | |
2090 | ps->post_wait = cycles; | |
2091 | post_wait_for_FR (cpu, in_FRi); | |
2092 | post_wait_for_FR (cpu, in_FRj); | |
2093 | post_wait_for_FR (cpu, out_FRk); | |
2094 | post_wait_for_ACC (cpu, in_ACC40Si); | |
2095 | post_wait_for_ACC (cpu, in_ACCGi); | |
2096 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
2097 | post_wait_for_ACC (cpu, out_ACC40Uk); | |
2098 | post_wait_for_ACC (cpu, out_ACCGk); | |
2099 | ||
2100 | /* Restore the busy cycles of the registers we used. */ | |
2101 | fr = ps->fr_busy; | |
2102 | if (in_FRi >= 0) | |
2103 | fr[in_FRi] += busy_adjustment[0]; | |
2104 | if (in_FRj >= 0) | |
2105 | fr[in_FRj] += busy_adjustment[1]; | |
2106 | if (out_FRk >= 0) | |
2107 | fr[out_FRk] += busy_adjustment[2]; | |
2108 | ||
2109 | /* The latency of tht output register will be at least the latency of the | |
2110 | other inputs. Once initiated, post-processing will take 3 cycles. */ | |
2111 | if (out_FRk >= 0) | |
2112 | { | |
2113 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
2114 | update_FR_ptime (cpu, out_FRk, 3); | |
2115 | /* Mark this use of the register as a media op. */ | |
2116 | set_use_is_media (cpu, out_FRk); | |
2117 | } | |
2118 | /* The latency of tht output accumulator will be at least the latency of the | |
2119 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2120 | if (out_ACC40Sk >= 0) | |
2121 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
2122 | if (out_ACC40Uk >= 0) | |
2123 | update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); | |
2124 | if (out_ACCGk >= 0) | |
2125 | update_ACC_latency (cpu, out_ACCGk, ps->post_wait + 1); | |
2126 | ||
2127 | return cycles; | |
2128 | } | |
2129 | ||
2130 | int | |
2131 | frvbf_model_fr500_u_media_quad_arith (SIM_CPU *cpu, const IDESC *idesc, | |
2132 | int unit_num, int referenced, | |
2133 | INT in_FRi, INT in_FRj, | |
2134 | INT out_FRk) | |
2135 | { | |
2136 | int cycles; | |
2137 | INT dual_FRi; | |
2138 | INT dual_FRj; | |
2139 | INT dual_FRk; | |
2140 | FRV_PROFILE_STATE *ps; | |
2141 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; | |
2142 | int *fr; | |
2143 | ||
2144 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2145 | return 0; | |
2146 | ||
2147 | /* The preprocessing can execute right away. */ | |
2148 | cycles = idesc->timing->units[unit_num].done; | |
2149 | ||
2150 | ps = CPU_PROFILE_STATE (cpu); | |
2151 | dual_FRi = DUAL_REG (in_FRi); | |
2152 | dual_FRj = DUAL_REG (in_FRj); | |
2153 | dual_FRk = DUAL_REG (out_FRk); | |
2154 | ||
2155 | /* If the previous use of the registers was a media op, | |
2156 | then their latency will be less than previously recorded. | |
2157 | See Table 13-13 in the LSI. */ | |
2158 | if (use_is_media (cpu, in_FRi)) | |
2159 | { | |
2160 | busy_adjustment[0] = 2; | |
2161 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
2162 | } | |
2163 | else | |
2164 | enforce_full_fr_latency (cpu, in_FRi); | |
2165 | if (dual_FRi >= 0 && use_is_media (cpu, dual_FRi)) | |
2166 | { | |
2167 | busy_adjustment[1] = 2; | |
2168 | decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); | |
2169 | } | |
2170 | else | |
2171 | enforce_full_fr_latency (cpu, dual_FRi); | |
2172 | if (in_FRj != in_FRi) | |
2173 | { | |
2174 | if (use_is_media (cpu, in_FRj)) | |
2175 | { | |
2176 | busy_adjustment[2] = 2; | |
2177 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); | |
2178 | } | |
2179 | else | |
2180 | enforce_full_fr_latency (cpu, in_FRj); | |
2181 | if (dual_FRj >= 0 && use_is_media (cpu, dual_FRj)) | |
2182 | { | |
2183 | busy_adjustment[3] = 2; | |
2184 | decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); | |
2185 | } | |
2186 | else | |
2187 | enforce_full_fr_latency (cpu, dual_FRj + 1); | |
2188 | } | |
2189 | if (out_FRk != in_FRi && out_FRk != in_FRj) | |
2190 | { | |
2191 | if (use_is_media (cpu, out_FRk)) | |
2192 | { | |
2193 | busy_adjustment[4] = 2; | |
2194 | decrease_FR_busy (cpu, out_FRk, busy_adjustment[4]); | |
2195 | } | |
2196 | else | |
2197 | enforce_full_fr_latency (cpu, out_FRk); | |
2198 | if (dual_FRk >= 0 && use_is_media (cpu, dual_FRk)) | |
2199 | { | |
2200 | busy_adjustment[5] = 2; | |
2201 | decrease_FR_busy (cpu, dual_FRk, busy_adjustment[5]); | |
2202 | } | |
2203 | else | |
2204 | enforce_full_fr_latency (cpu, dual_FRk); | |
2205 | } | |
2206 | ||
2207 | /* The post processing must wait if there is a dependency on a FR | |
2208 | which is not ready yet. */ | |
2209 | ps->post_wait = cycles; | |
2210 | post_wait_for_FR (cpu, in_FRi); | |
2211 | post_wait_for_FR (cpu, dual_FRi); | |
2212 | post_wait_for_FR (cpu, in_FRj); | |
2213 | post_wait_for_FR (cpu, dual_FRj); | |
2214 | post_wait_for_FR (cpu, out_FRk); | |
2215 | post_wait_for_FR (cpu, dual_FRk); | |
2216 | ||
2217 | /* Restore the busy cycles of the registers we used. */ | |
2218 | fr = ps->fr_busy; | |
2219 | fr[in_FRi] += busy_adjustment[0]; | |
2220 | if (dual_FRi >= 0) | |
2221 | fr[dual_FRi] += busy_adjustment[1]; | |
2222 | fr[in_FRj] += busy_adjustment[2]; | |
2223 | if (dual_FRj >= 0) | |
2224 | fr[dual_FRj] += busy_adjustment[3]; | |
2225 | fr[out_FRk] += busy_adjustment[4]; | |
2226 | if (dual_FRk >= 0) | |
2227 | fr[dual_FRk] += busy_adjustment[5]; | |
2228 | ||
2229 | /* The latency of tht output register will be at least the latency of the | |
2230 | other inputs. */ | |
2231 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
2232 | ||
2233 | /* Once initiated, post-processing will take 3 cycles. */ | |
2234 | update_FR_ptime (cpu, out_FRk, 3); | |
2235 | ||
2236 | /* Mark this use of the register as a media op. */ | |
2237 | set_use_is_media (cpu, out_FRk); | |
2238 | if (dual_FRk >= 0) | |
2239 | { | |
2240 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
2241 | update_FR_ptime (cpu, dual_FRk, 3); | |
2242 | /* Mark this use of the register as a media op. */ | |
2243 | set_use_is_media (cpu, dual_FRk); | |
2244 | } | |
2245 | ||
2246 | return cycles; | |
2247 | } | |
2248 | ||
2249 | int | |
2250 | frvbf_model_fr500_u_media_dual_mul (SIM_CPU *cpu, const IDESC *idesc, | |
2251 | int unit_num, int referenced, | |
2252 | INT in_FRi, INT in_FRj, | |
2253 | INT out_ACC40Sk, INT out_ACC40Uk) | |
2254 | { | |
2255 | int cycles; | |
2256 | INT dual_ACC40Sk; | |
2257 | INT dual_ACC40Uk; | |
2258 | FRV_PROFILE_STATE *ps; | |
2259 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; | |
2260 | int *fr; | |
2261 | int *acc; | |
2262 | ||
2263 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2264 | return 0; | |
2265 | ||
2266 | /* The preprocessing can execute right away. */ | |
2267 | cycles = idesc->timing->units[unit_num].done; | |
2268 | ||
2269 | ps = CPU_PROFILE_STATE (cpu); | |
2270 | dual_ACC40Sk = DUAL_REG (out_ACC40Sk); | |
2271 | dual_ACC40Uk = DUAL_REG (out_ACC40Uk); | |
2272 | ||
2273 | /* If the previous use of the registers was a media op, | |
2274 | then their latency will be less than previously recorded. | |
2275 | See Table 13-13 in the LSI. */ | |
2276 | if (use_is_media (cpu, in_FRi)) | |
2277 | { | |
2278 | busy_adjustment[0] = 2; | |
2279 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
2280 | } | |
2281 | else | |
2282 | enforce_full_fr_latency (cpu, in_FRi); | |
2283 | if (in_FRj != in_FRi) | |
2284 | { | |
2285 | if (use_is_media (cpu, in_FRj)) | |
2286 | { | |
2287 | busy_adjustment[1] = 2; | |
2288 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); | |
2289 | } | |
2290 | else | |
2291 | enforce_full_fr_latency (cpu, in_FRj); | |
2292 | } | |
2293 | if (out_ACC40Sk >= 0) | |
2294 | { | |
2295 | busy_adjustment[2] = 1; | |
2296 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); | |
2297 | } | |
2298 | if (dual_ACC40Sk >= 0) | |
2299 | { | |
2300 | busy_adjustment[3] = 1; | |
2301 | decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]); | |
2302 | } | |
2303 | if (out_ACC40Uk >= 0) | |
2304 | { | |
2305 | busy_adjustment[4] = 1; | |
2306 | decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); | |
2307 | } | |
2308 | if (dual_ACC40Uk >= 0) | |
2309 | { | |
2310 | busy_adjustment[5] = 1; | |
2311 | decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]); | |
2312 | } | |
2313 | ||
2314 | /* The post processing must wait if there is a dependency on a FR | |
2315 | which is not ready yet. */ | |
2316 | ps->post_wait = cycles; | |
2317 | post_wait_for_FR (cpu, in_FRi); | |
2318 | post_wait_for_FR (cpu, in_FRj); | |
2319 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
2320 | post_wait_for_ACC (cpu, dual_ACC40Sk); | |
2321 | post_wait_for_ACC (cpu, out_ACC40Uk); | |
2322 | post_wait_for_ACC (cpu, dual_ACC40Uk); | |
2323 | ||
2324 | /* Restore the busy cycles of the registers we used. */ | |
2325 | fr = ps->fr_busy; | |
2326 | acc = ps->acc_busy; | |
2327 | fr[in_FRi] += busy_adjustment[0]; | |
2328 | fr[in_FRj] += busy_adjustment[1]; | |
2329 | if (out_ACC40Sk >= 0) | |
2330 | acc[out_ACC40Sk] += busy_adjustment[2]; | |
2331 | if (dual_ACC40Sk >= 0) | |
2332 | acc[dual_ACC40Sk] += busy_adjustment[3]; | |
2333 | if (out_ACC40Uk >= 0) | |
2334 | acc[out_ACC40Uk] += busy_adjustment[4]; | |
2335 | if (dual_ACC40Uk >= 0) | |
2336 | acc[dual_ACC40Uk] += busy_adjustment[5]; | |
2337 | ||
2338 | /* The latency of tht output register will be at least the latency of the | |
2339 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2340 | if (out_ACC40Sk >= 0) | |
2341 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
2342 | if (dual_ACC40Sk >= 0) | |
2343 | update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1); | |
2344 | if (out_ACC40Uk >= 0) | |
2345 | update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); | |
2346 | if (dual_ACC40Uk >= 0) | |
2347 | update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1); | |
2348 | ||
2349 | return cycles; | |
2350 | } | |
2351 | ||
2352 | int | |
2353 | frvbf_model_fr500_u_media_quad_mul (SIM_CPU *cpu, const IDESC *idesc, | |
2354 | int unit_num, int referenced, | |
2355 | INT in_FRi, INT in_FRj, | |
2356 | INT out_ACC40Sk, INT out_ACC40Uk) | |
2357 | { | |
2358 | int cycles; | |
2359 | INT FRi_1; | |
2360 | INT FRj_1; | |
2361 | INT ACC40Sk_1; | |
2362 | INT ACC40Sk_2; | |
2363 | INT ACC40Sk_3; | |
2364 | INT ACC40Uk_1; | |
2365 | INT ACC40Uk_2; | |
2366 | INT ACC40Uk_3; | |
2367 | FRV_PROFILE_STATE *ps; | |
2368 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0}; | |
2369 | int *fr; | |
2370 | int *acc; | |
2371 | ||
2372 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2373 | return 0; | |
2374 | ||
2375 | /* The preprocessing can execute right away. */ | |
2376 | cycles = idesc->timing->units[unit_num].done; | |
2377 | ||
2378 | FRi_1 = DUAL_REG (in_FRi); | |
2379 | FRj_1 = DUAL_REG (in_FRj); | |
2380 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
2381 | ACC40Sk_2 = DUAL_REG (ACC40Sk_1); | |
2382 | ACC40Sk_3 = DUAL_REG (ACC40Sk_2); | |
2383 | ACC40Uk_1 = DUAL_REG (out_ACC40Uk); | |
2384 | ACC40Uk_2 = DUAL_REG (ACC40Uk_1); | |
2385 | ACC40Uk_3 = DUAL_REG (ACC40Uk_2); | |
2386 | ||
2387 | /* If the previous use of the registers was a media op, | |
2388 | then their latency will be less than previously recorded. | |
2389 | See Table 13-13 in the LSI. */ | |
2390 | ps = CPU_PROFILE_STATE (cpu); | |
2391 | if (use_is_media (cpu, in_FRi)) | |
2392 | { | |
2393 | busy_adjustment[0] = 2; | |
2394 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
2395 | } | |
2396 | else | |
2397 | enforce_full_fr_latency (cpu, in_FRi); | |
2398 | if (FRi_1 >= 0) | |
2399 | { | |
2400 | if (use_is_media (cpu, FRi_1)) | |
2401 | { | |
2402 | busy_adjustment[1] = 2; | |
2403 | decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]); | |
2404 | } | |
2405 | else | |
2406 | enforce_full_fr_latency (cpu, FRi_1); | |
2407 | } | |
2408 | if (in_FRj != in_FRi) | |
2409 | { | |
2410 | if (use_is_media (cpu, in_FRj)) | |
2411 | { | |
2412 | busy_adjustment[2] = 2; | |
2413 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); | |
2414 | } | |
2415 | else | |
2416 | enforce_full_fr_latency (cpu, in_FRj); | |
2417 | if (FRj_1 >= 0) | |
2418 | { | |
2419 | if (use_is_media (cpu, FRj_1)) | |
2420 | { | |
2421 | busy_adjustment[3] = 2; | |
2422 | decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]); | |
2423 | } | |
2424 | else | |
2425 | enforce_full_fr_latency (cpu, FRj_1); | |
2426 | } | |
2427 | } | |
2428 | if (out_ACC40Sk >= 0) | |
2429 | { | |
2430 | busy_adjustment[4] = 1; | |
2431 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); | |
2432 | ||
2433 | if (ACC40Sk_1 >= 0) | |
2434 | { | |
2435 | busy_adjustment[5] = 1; | |
2436 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); | |
2437 | } | |
2438 | if (ACC40Sk_2 >= 0) | |
2439 | { | |
2440 | busy_adjustment[6] = 1; | |
2441 | decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); | |
2442 | } | |
2443 | if (ACC40Sk_3 >= 0) | |
2444 | { | |
2445 | busy_adjustment[7] = 1; | |
2446 | decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); | |
2447 | } | |
2448 | } | |
2449 | else if (out_ACC40Uk >= 0) | |
2450 | { | |
2451 | busy_adjustment[4] = 1; | |
2452 | decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); | |
2453 | ||
2454 | if (ACC40Uk_1 >= 0) | |
2455 | { | |
2456 | busy_adjustment[5] = 1; | |
2457 | decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]); | |
2458 | } | |
2459 | if (ACC40Uk_2 >= 0) | |
2460 | { | |
2461 | busy_adjustment[6] = 1; | |
2462 | decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]); | |
2463 | } | |
2464 | if (ACC40Uk_3 >= 0) | |
2465 | { | |
2466 | busy_adjustment[7] = 1; | |
2467 | decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]); | |
2468 | } | |
2469 | } | |
2470 | ||
2471 | /* The post processing must wait if there is a dependency on a FR | |
2472 | which is not ready yet. */ | |
2473 | ps->post_wait = cycles; | |
2474 | post_wait_for_FR (cpu, in_FRi); | |
2475 | post_wait_for_FR (cpu, FRi_1); | |
2476 | post_wait_for_FR (cpu, in_FRj); | |
2477 | post_wait_for_FR (cpu, FRj_1); | |
2478 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
2479 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
2480 | post_wait_for_ACC (cpu, ACC40Sk_2); | |
2481 | post_wait_for_ACC (cpu, ACC40Sk_3); | |
2482 | post_wait_for_ACC (cpu, out_ACC40Uk); | |
2483 | post_wait_for_ACC (cpu, ACC40Uk_1); | |
2484 | post_wait_for_ACC (cpu, ACC40Uk_2); | |
2485 | post_wait_for_ACC (cpu, ACC40Uk_3); | |
2486 | ||
2487 | /* Restore the busy cycles of the registers we used. */ | |
2488 | fr = ps->fr_busy; | |
2489 | acc = ps->acc_busy; | |
2490 | fr[in_FRi] += busy_adjustment[0]; | |
2491 | if (FRi_1 >= 0) | |
2492 | fr[FRi_1] += busy_adjustment[1]; | |
2493 | fr[in_FRj] += busy_adjustment[2]; | |
2494 | if (FRj_1 > 0) | |
2495 | fr[FRj_1] += busy_adjustment[3]; | |
2496 | if (out_ACC40Sk >= 0) | |
2497 | { | |
2498 | acc[out_ACC40Sk] += busy_adjustment[4]; | |
2499 | if (ACC40Sk_1 >= 0) | |
2500 | acc[ACC40Sk_1] += busy_adjustment[5]; | |
2501 | if (ACC40Sk_2 >= 0) | |
2502 | acc[ACC40Sk_2] += busy_adjustment[6]; | |
2503 | if (ACC40Sk_3 >= 0) | |
2504 | acc[ACC40Sk_3] += busy_adjustment[7]; | |
2505 | } | |
2506 | else if (out_ACC40Uk >= 0) | |
2507 | { | |
2508 | acc[out_ACC40Uk] += busy_adjustment[4]; | |
2509 | if (ACC40Uk_1 >= 0) | |
2510 | acc[ACC40Uk_1] += busy_adjustment[5]; | |
2511 | if (ACC40Uk_2 >= 0) | |
2512 | acc[ACC40Uk_2] += busy_adjustment[6]; | |
2513 | if (ACC40Uk_3 >= 0) | |
2514 | acc[ACC40Uk_3] += busy_adjustment[7]; | |
2515 | } | |
2516 | ||
2517 | /* The latency of tht output register will be at least the latency of the | |
2518 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2519 | if (out_ACC40Sk >= 0) | |
2520 | { | |
2521 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
2522 | if (ACC40Sk_1 >= 0) | |
2523 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
2524 | if (ACC40Sk_2 >= 0) | |
2525 | update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); | |
2526 | if (ACC40Sk_3 >= 0) | |
2527 | update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); | |
2528 | } | |
2529 | else if (out_ACC40Uk >= 0) | |
2530 | { | |
2531 | update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); | |
2532 | if (ACC40Uk_1 >= 0) | |
2533 | update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1); | |
2534 | if (ACC40Uk_2 >= 0) | |
2535 | update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1); | |
2536 | if (ACC40Uk_3 >= 0) | |
2537 | update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1); | |
2538 | } | |
2539 | ||
2540 | return cycles; | |
2541 | } | |
2542 | ||
2543 | int | |
2544 | frvbf_model_fr500_u_media_quad_complex (SIM_CPU *cpu, const IDESC *idesc, | |
2545 | int unit_num, int referenced, | |
2546 | INT in_FRi, INT in_FRj, | |
2547 | INT out_ACC40Sk) | |
2548 | { | |
2549 | int cycles; | |
2550 | INT FRi_1; | |
2551 | INT FRj_1; | |
2552 | INT ACC40Sk_1; | |
2553 | FRV_PROFILE_STATE *ps; | |
2554 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; | |
2555 | int *fr; | |
2556 | int *acc; | |
2557 | ||
2558 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2559 | return 0; | |
2560 | ||
2561 | /* The preprocessing can execute right away. */ | |
2562 | cycles = idesc->timing->units[unit_num].done; | |
2563 | ||
2564 | FRi_1 = DUAL_REG (in_FRi); | |
2565 | FRj_1 = DUAL_REG (in_FRj); | |
2566 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
2567 | ||
2568 | /* If the previous use of the registers was a media op, | |
2569 | then their latency will be less than previously recorded. | |
2570 | See Table 13-13 in the LSI. */ | |
2571 | ps = CPU_PROFILE_STATE (cpu); | |
2572 | if (use_is_media (cpu, in_FRi)) | |
2573 | { | |
2574 | busy_adjustment[0] = 2; | |
2575 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
2576 | } | |
2577 | else | |
2578 | enforce_full_fr_latency (cpu, in_FRi); | |
2579 | if (FRi_1 >= 0) | |
2580 | { | |
2581 | if (use_is_media (cpu, FRi_1)) | |
2582 | { | |
2583 | busy_adjustment[1] = 2; | |
2584 | decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]); | |
2585 | } | |
2586 | else | |
2587 | enforce_full_fr_latency (cpu, FRi_1); | |
2588 | } | |
2589 | if (in_FRj != in_FRi) | |
2590 | { | |
2591 | if (use_is_media (cpu, in_FRj)) | |
2592 | { | |
2593 | busy_adjustment[2] = 2; | |
2594 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); | |
2595 | } | |
2596 | else | |
2597 | enforce_full_fr_latency (cpu, in_FRj); | |
2598 | if (FRj_1 >= 0) | |
2599 | { | |
2600 | if (use_is_media (cpu, FRj_1)) | |
2601 | { | |
2602 | busy_adjustment[3] = 2; | |
2603 | decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]); | |
2604 | } | |
2605 | else | |
2606 | enforce_full_fr_latency (cpu, FRj_1); | |
2607 | } | |
2608 | } | |
2609 | if (out_ACC40Sk >= 0) | |
2610 | { | |
2611 | busy_adjustment[4] = 1; | |
2612 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); | |
2613 | ||
2614 | if (ACC40Sk_1 >= 0) | |
2615 | { | |
2616 | busy_adjustment[5] = 1; | |
2617 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); | |
2618 | } | |
2619 | } | |
2620 | ||
2621 | /* The post processing must wait if there is a dependency on a FR | |
2622 | which is not ready yet. */ | |
2623 | ps->post_wait = cycles; | |
2624 | post_wait_for_FR (cpu, in_FRi); | |
2625 | post_wait_for_FR (cpu, FRi_1); | |
2626 | post_wait_for_FR (cpu, in_FRj); | |
2627 | post_wait_for_FR (cpu, FRj_1); | |
2628 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
2629 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
2630 | ||
2631 | /* Restore the busy cycles of the registers we used. */ | |
2632 | fr = ps->fr_busy; | |
2633 | acc = ps->acc_busy; | |
2634 | fr[in_FRi] += busy_adjustment[0]; | |
2635 | if (FRi_1 >= 0) | |
2636 | fr[FRi_1] += busy_adjustment[1]; | |
2637 | fr[in_FRj] += busy_adjustment[2]; | |
2638 | if (FRj_1 > 0) | |
2639 | fr[FRj_1] += busy_adjustment[3]; | |
2640 | if (out_ACC40Sk >= 0) | |
2641 | { | |
2642 | acc[out_ACC40Sk] += busy_adjustment[4]; | |
2643 | if (ACC40Sk_1 >= 0) | |
2644 | acc[ACC40Sk_1] += busy_adjustment[5]; | |
2645 | } | |
2646 | ||
2647 | /* The latency of tht output register will be at least the latency of the | |
2648 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
2649 | if (out_ACC40Sk >= 0) | |
2650 | { | |
2651 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
2652 | if (ACC40Sk_1 >= 0) | |
2653 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
2654 | } | |
2655 | ||
2656 | return cycles; | |
2657 | } | |
2658 | ||
2659 | int | |
2660 | frvbf_model_fr500_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, | |
2661 | int unit_num, int referenced, | |
2662 | INT in_FRi, | |
2663 | INT out_FRk) | |
2664 | { | |
2665 | int cycles; | |
2666 | INT dual_FRk; | |
2667 | FRV_PROFILE_STATE *ps; | |
2668 | int busy_adjustment[] = {0, 0, 0}; | |
2669 | int *fr; | |
2670 | ||
2671 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2672 | return 0; | |
2673 | ||
2674 | /* The preprocessing can execute right away. */ | |
2675 | cycles = idesc->timing->units[unit_num].done; | |
2676 | ||
2677 | /* If the previous use of the registers was a media op, | |
2678 | then their latency will be less than previously recorded. | |
2679 | See Table 13-13 in the LSI. */ | |
2680 | dual_FRk = DUAL_REG (out_FRk); | |
2681 | ps = CPU_PROFILE_STATE (cpu); | |
2682 | if (use_is_media (cpu, in_FRi)) | |
2683 | { | |
2684 | busy_adjustment[0] = 2; | |
2685 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
2686 | } | |
2687 | else | |
2688 | enforce_full_fr_latency (cpu, in_FRi); | |
2689 | if (out_FRk != in_FRi) | |
2690 | { | |
2691 | if (use_is_media (cpu, out_FRk)) | |
2692 | { | |
2693 | busy_adjustment[1] = 2; | |
2694 | decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]); | |
2695 | } | |
2696 | else | |
2697 | enforce_full_fr_latency (cpu, out_FRk); | |
2698 | } | |
2699 | if (dual_FRk >= 0 && dual_FRk != in_FRi) | |
2700 | { | |
2701 | if (use_is_media (cpu, dual_FRk)) | |
2702 | { | |
2703 | busy_adjustment[2] = 2; | |
2704 | decrease_FR_busy (cpu, dual_FRk, busy_adjustment[2]); | |
2705 | } | |
2706 | else | |
2707 | enforce_full_fr_latency (cpu, dual_FRk); | |
2708 | } | |
2709 | ||
2710 | /* The post processing must wait if there is a dependency on a FR | |
2711 | which is not ready yet. */ | |
2712 | ps->post_wait = cycles; | |
2713 | post_wait_for_FR (cpu, in_FRi); | |
2714 | post_wait_for_FR (cpu, out_FRk); | |
2715 | post_wait_for_FR (cpu, dual_FRk); | |
2716 | ||
2717 | /* Restore the busy cycles of the registers we used. */ | |
2718 | fr = ps->fr_busy; | |
2719 | fr[in_FRi] += busy_adjustment[0]; | |
2720 | fr[out_FRk] += busy_adjustment[1]; | |
2721 | if (dual_FRk >= 0) | |
2722 | fr[dual_FRk] += busy_adjustment[2]; | |
2723 | ||
1c453cd6 | 2724 | /* The latency of the output register will be at least the latency of the |
b34f6357 DB |
2725 | other inputs. Once initiated, post-processing will take 3 cycles. */ |
2726 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
2727 | update_FR_ptime (cpu, out_FRk, 3); | |
2728 | ||
2729 | /* Mark this use of the register as a media op. */ | |
2730 | set_use_is_media (cpu, out_FRk); | |
2731 | if (dual_FRk >= 0) | |
2732 | { | |
2733 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
2734 | update_FR_ptime (cpu, dual_FRk, 3); | |
2735 | ||
2736 | /* Mark this use of the register as a media op. */ | |
2737 | set_use_is_media (cpu, dual_FRk); | |
2738 | } | |
2739 | ||
2740 | return cycles; | |
2741 | } | |
2742 | ||
2743 | int | |
2744 | frvbf_model_fr500_u_media_dual_unpack (SIM_CPU *cpu, const IDESC *idesc, | |
2745 | int unit_num, int referenced, | |
2746 | INT in_FRi, | |
2747 | INT out_FRk) | |
2748 | { | |
2749 | int cycles; | |
2750 | INT FRi_1; | |
2751 | INT FRk_1; | |
2752 | INT FRk_2; | |
2753 | INT FRk_3; | |
2754 | FRV_PROFILE_STATE *ps; | |
2755 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; | |
2756 | int *fr; | |
2757 | ||
2758 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2759 | return 0; | |
2760 | ||
2761 | /* The preprocessing can execute right away. */ | |
2762 | cycles = idesc->timing->units[unit_num].done; | |
2763 | ||
2764 | FRi_1 = DUAL_REG (in_FRi); | |
2765 | FRk_1 = DUAL_REG (out_FRk); | |
2766 | FRk_2 = DUAL_REG (FRk_1); | |
2767 | FRk_3 = DUAL_REG (FRk_2); | |
2768 | ||
2769 | /* If the previous use of the registers was a media op, | |
2770 | then their latency will be less than previously recorded. | |
2771 | See Table 13-13 in the LSI. */ | |
2772 | ps = CPU_PROFILE_STATE (cpu); | |
2773 | if (use_is_media (cpu, in_FRi)) | |
2774 | { | |
2775 | busy_adjustment[0] = 2; | |
2776 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
2777 | } | |
2778 | else | |
2779 | enforce_full_fr_latency (cpu, in_FRi); | |
2780 | if (FRi_1 >= 0 && use_is_media (cpu, FRi_1)) | |
2781 | { | |
2782 | busy_adjustment[1] = 2; | |
2783 | decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]); | |
2784 | } | |
2785 | else | |
2786 | enforce_full_fr_latency (cpu, FRi_1); | |
2787 | if (out_FRk != in_FRi) | |
2788 | { | |
2789 | if (use_is_media (cpu, out_FRk)) | |
2790 | { | |
2791 | busy_adjustment[2] = 2; | |
2792 | decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]); | |
2793 | } | |
2794 | else | |
2795 | enforce_full_fr_latency (cpu, out_FRk); | |
2796 | if (FRk_1 >= 0 && FRk_1 != in_FRi) | |
2797 | { | |
2798 | if (use_is_media (cpu, FRk_1)) | |
2799 | { | |
2800 | busy_adjustment[3] = 2; | |
2801 | decrease_FR_busy (cpu, FRk_1, busy_adjustment[3]); | |
2802 | } | |
2803 | else | |
2804 | enforce_full_fr_latency (cpu, FRk_1); | |
2805 | } | |
2806 | if (FRk_2 >= 0 && FRk_2 != in_FRi) | |
2807 | { | |
2808 | if (use_is_media (cpu, FRk_2)) | |
2809 | { | |
2810 | busy_adjustment[4] = 2; | |
2811 | decrease_FR_busy (cpu, FRk_2, busy_adjustment[4]); | |
2812 | } | |
2813 | else | |
2814 | enforce_full_fr_latency (cpu, FRk_2); | |
2815 | } | |
2816 | if (FRk_3 >= 0 && FRk_3 != in_FRi) | |
2817 | { | |
2818 | if (use_is_media (cpu, FRk_3)) | |
2819 | { | |
2820 | busy_adjustment[5] = 2; | |
2821 | decrease_FR_busy (cpu, FRk_3, busy_adjustment[5]); | |
2822 | } | |
2823 | else | |
2824 | enforce_full_fr_latency (cpu, FRk_3); | |
2825 | } | |
2826 | } | |
2827 | ||
2828 | /* The post processing must wait if there is a dependency on a FR | |
2829 | which is not ready yet. */ | |
2830 | ps->post_wait = cycles; | |
2831 | post_wait_for_FR (cpu, in_FRi); | |
2832 | post_wait_for_FR (cpu, FRi_1); | |
2833 | post_wait_for_FR (cpu, out_FRk); | |
2834 | post_wait_for_FR (cpu, FRk_1); | |
2835 | post_wait_for_FR (cpu, FRk_2); | |
2836 | post_wait_for_FR (cpu, FRk_3); | |
2837 | ||
2838 | /* Restore the busy cycles of the registers we used. */ | |
2839 | fr = ps->fr_busy; | |
2840 | fr[in_FRi] += busy_adjustment[0]; | |
2841 | if (FRi_1 >= 0) | |
2842 | fr[FRi_1] += busy_adjustment[1]; | |
2843 | fr[out_FRk] += busy_adjustment[2]; | |
2844 | if (FRk_1 >= 0) | |
2845 | fr[FRk_1] += busy_adjustment[3]; | |
2846 | if (FRk_2 >= 0) | |
2847 | fr[FRk_2] += busy_adjustment[4]; | |
2848 | if (FRk_3 >= 0) | |
2849 | fr[FRk_3] += busy_adjustment[5]; | |
2850 | ||
2851 | /* The latency of tht output register will be at least the latency of the | |
2852 | other inputs. Once initiated, post-processing will take 3 cycles. */ | |
2853 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
2854 | update_FR_ptime (cpu, out_FRk, 3); | |
2855 | ||
2856 | /* Mark this use of the register as a media op. */ | |
2857 | set_use_is_media (cpu, out_FRk); | |
2858 | if (FRk_1 >= 0) | |
2859 | { | |
2860 | update_FR_latency (cpu, FRk_1, ps->post_wait); | |
2861 | update_FR_ptime (cpu, FRk_1, 3); | |
2862 | ||
2863 | /* Mark this use of the register as a media op. */ | |
2864 | set_use_is_media (cpu, FRk_1); | |
2865 | } | |
2866 | if (FRk_2 >= 0) | |
2867 | { | |
2868 | update_FR_latency (cpu, FRk_2, ps->post_wait); | |
2869 | update_FR_ptime (cpu, FRk_2, 3); | |
2870 | ||
2871 | /* Mark this use of the register as a media op. */ | |
2872 | set_use_is_media (cpu, FRk_2); | |
2873 | } | |
2874 | if (FRk_3 >= 0) | |
2875 | { | |
2876 | update_FR_latency (cpu, FRk_3, ps->post_wait); | |
2877 | update_FR_ptime (cpu, FRk_3, 3); | |
2878 | ||
2879 | /* Mark this use of the register as a media op. */ | |
2880 | set_use_is_media (cpu, FRk_3); | |
2881 | } | |
2882 | ||
2883 | return cycles; | |
2884 | } | |
2885 | ||
2886 | int | |
2887 | frvbf_model_fr500_u_media_dual_btoh (SIM_CPU *cpu, const IDESC *idesc, | |
2888 | int unit_num, int referenced, | |
2889 | INT in_FRj, | |
2890 | INT out_FRk) | |
2891 | { | |
2892 | return frvbf_model_fr500_u_media_dual_expand (cpu, idesc, unit_num, | |
2893 | referenced, in_FRj, out_FRk); | |
2894 | } | |
2895 | ||
2896 | int | |
2897 | frvbf_model_fr500_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, | |
2898 | int unit_num, int referenced, | |
2899 | INT in_FRj, | |
2900 | INT out_FRk) | |
2901 | { | |
2902 | int cycles; | |
2903 | INT dual_FRj; | |
2904 | FRV_PROFILE_STATE *ps; | |
2905 | int busy_adjustment[] = {0, 0, 0}; | |
2906 | int *fr; | |
2907 | ||
2908 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2909 | return 0; | |
2910 | ||
2911 | /* The preprocessing can execute right away. */ | |
2912 | cycles = idesc->timing->units[unit_num].done; | |
2913 | ||
2914 | /* If the previous use of the registers was a media op, | |
2915 | then their latency will be less than previously recorded. | |
2916 | See Table 13-13 in the LSI. */ | |
2917 | dual_FRj = DUAL_REG (in_FRj); | |
2918 | ps = CPU_PROFILE_STATE (cpu); | |
2919 | if (use_is_media (cpu, in_FRj)) | |
2920 | { | |
2921 | busy_adjustment[0] = 2; | |
2922 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); | |
2923 | } | |
2924 | else | |
2925 | enforce_full_fr_latency (cpu, in_FRj); | |
2926 | if (dual_FRj >= 0) | |
2927 | { | |
2928 | if (use_is_media (cpu, dual_FRj)) | |
2929 | { | |
2930 | busy_adjustment[1] = 2; | |
2931 | decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]); | |
2932 | } | |
2933 | else | |
2934 | enforce_full_fr_latency (cpu, dual_FRj); | |
2935 | } | |
2936 | if (out_FRk != in_FRj) | |
2937 | { | |
2938 | if (use_is_media (cpu, out_FRk)) | |
2939 | { | |
2940 | busy_adjustment[2] = 2; | |
2941 | decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]); | |
2942 | } | |
2943 | else | |
2944 | enforce_full_fr_latency (cpu, out_FRk); | |
2945 | } | |
2946 | ||
2947 | /* The post processing must wait if there is a dependency on a FR | |
2948 | which is not ready yet. */ | |
2949 | ps->post_wait = cycles; | |
2950 | post_wait_for_FR (cpu, in_FRj); | |
2951 | post_wait_for_FR (cpu, dual_FRj); | |
2952 | post_wait_for_FR (cpu, out_FRk); | |
2953 | ||
2954 | /* Restore the busy cycles of the registers we used. */ | |
2955 | fr = ps->fr_busy; | |
2956 | fr[in_FRj] += busy_adjustment[0]; | |
2957 | if (dual_FRj >= 0) | |
2958 | fr[dual_FRj] += busy_adjustment[1]; | |
2959 | fr[out_FRk] += busy_adjustment[2]; | |
2960 | ||
2961 | /* The latency of tht output register will be at least the latency of the | |
2962 | other inputs. */ | |
2963 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
2964 | ||
2965 | /* Once initiated, post-processing will take 3 cycles. */ | |
2966 | update_FR_ptime (cpu, out_FRk, 3); | |
2967 | ||
2968 | /* Mark this use of the register as a media op. */ | |
2969 | set_use_is_media (cpu, out_FRk); | |
2970 | ||
2971 | return cycles; | |
2972 | } | |
2973 | ||
2974 | int | |
2975 | frvbf_model_fr500_u_media_dual_btohe (SIM_CPU *cpu, const IDESC *idesc, | |
2976 | int unit_num, int referenced, | |
2977 | INT in_FRj, | |
2978 | INT out_FRk) | |
2979 | { | |
2980 | int cycles; | |
2981 | INT FRk_1; | |
2982 | INT FRk_2; | |
2983 | INT FRk_3; | |
2984 | FRV_PROFILE_STATE *ps; | |
2985 | int busy_adjustment[] = {0, 0, 0, 0, 0}; | |
2986 | int *fr; | |
2987 | ||
2988 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
2989 | return 0; | |
2990 | ||
2991 | /* The preprocessing can execute right away. */ | |
2992 | cycles = idesc->timing->units[unit_num].done; | |
2993 | ||
2994 | FRk_1 = DUAL_REG (out_FRk); | |
2995 | FRk_2 = DUAL_REG (FRk_1); | |
2996 | FRk_3 = DUAL_REG (FRk_2); | |
2997 | ||
2998 | /* If the previous use of the registers was a media op, | |
2999 | then their latency will be less than previously recorded. | |
3000 | See Table 13-13 in the LSI. */ | |
3001 | ps = CPU_PROFILE_STATE (cpu); | |
3002 | if (use_is_media (cpu, in_FRj)) | |
3003 | { | |
3004 | busy_adjustment[0] = 2; | |
3005 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); | |
3006 | } | |
3007 | else | |
3008 | enforce_full_fr_latency (cpu, in_FRj); | |
3009 | if (out_FRk != in_FRj) | |
3010 | { | |
3011 | if (use_is_media (cpu, out_FRk)) | |
3012 | { | |
3013 | busy_adjustment[1] = 2; | |
3014 | decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]); | |
3015 | } | |
3016 | else | |
3017 | enforce_full_fr_latency (cpu, out_FRk); | |
3018 | if (FRk_1 >= 0 && FRk_1 != in_FRj) | |
3019 | { | |
3020 | if (use_is_media (cpu, FRk_1)) | |
3021 | { | |
3022 | busy_adjustment[2] = 2; | |
3023 | decrease_FR_busy (cpu, FRk_1, busy_adjustment[2]); | |
3024 | } | |
3025 | else | |
3026 | enforce_full_fr_latency (cpu, FRk_1); | |
3027 | } | |
3028 | if (FRk_2 >= 0 && FRk_2 != in_FRj) | |
3029 | { | |
3030 | if (use_is_media (cpu, FRk_2)) | |
3031 | { | |
3032 | busy_adjustment[3] = 2; | |
3033 | decrease_FR_busy (cpu, FRk_2, busy_adjustment[3]); | |
3034 | } | |
3035 | else | |
3036 | enforce_full_fr_latency (cpu, FRk_2); | |
3037 | } | |
3038 | if (FRk_3 >= 0 && FRk_3 != in_FRj) | |
3039 | { | |
3040 | if (use_is_media (cpu, FRk_3)) | |
3041 | { | |
3042 | busy_adjustment[4] = 2; | |
3043 | decrease_FR_busy (cpu, FRk_3, busy_adjustment[4]); | |
3044 | } | |
3045 | else | |
3046 | enforce_full_fr_latency (cpu, FRk_3); | |
3047 | } | |
3048 | } | |
3049 | ||
3050 | /* The post processing must wait if there is a dependency on a FR | |
3051 | which is not ready yet. */ | |
3052 | ps->post_wait = cycles; | |
3053 | post_wait_for_FR (cpu, in_FRj); | |
3054 | post_wait_for_FR (cpu, out_FRk); | |
3055 | post_wait_for_FR (cpu, FRk_1); | |
3056 | post_wait_for_FR (cpu, FRk_2); | |
3057 | post_wait_for_FR (cpu, FRk_3); | |
3058 | ||
3059 | /* Restore the busy cycles of the registers we used. */ | |
3060 | fr = ps->fr_busy; | |
3061 | fr[in_FRj] += busy_adjustment[0]; | |
3062 | fr[out_FRk] += busy_adjustment[1]; | |
3063 | if (FRk_1 >= 0) | |
3064 | fr[FRk_1] += busy_adjustment[2]; | |
3065 | if (FRk_2 >= 0) | |
3066 | fr[FRk_2] += busy_adjustment[3]; | |
3067 | if (FRk_3 >= 0) | |
3068 | fr[FRk_3] += busy_adjustment[4]; | |
3069 | ||
3070 | /* The latency of tht output register will be at least the latency of the | |
3071 | other inputs. Once initiated, post-processing will take 3 cycles. */ | |
3072 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
3073 | update_FR_ptime (cpu, out_FRk, 3); | |
3074 | ||
3075 | /* Mark this use of the register as a media op. */ | |
3076 | set_use_is_media (cpu, out_FRk); | |
3077 | if (FRk_1 >= 0) | |
3078 | { | |
3079 | update_FR_latency (cpu, FRk_1, ps->post_wait); | |
3080 | update_FR_ptime (cpu, FRk_1, 3); | |
3081 | ||
3082 | /* Mark this use of the register as a media op. */ | |
3083 | set_use_is_media (cpu, FRk_1); | |
3084 | } | |
3085 | if (FRk_2 >= 0) | |
3086 | { | |
3087 | update_FR_latency (cpu, FRk_2, ps->post_wait); | |
3088 | update_FR_ptime (cpu, FRk_2, 3); | |
3089 | ||
3090 | /* Mark this use of the register as a media op. */ | |
3091 | set_use_is_media (cpu, FRk_2); | |
3092 | } | |
3093 | if (FRk_3 >= 0) | |
3094 | { | |
3095 | update_FR_latency (cpu, FRk_3, ps->post_wait); | |
3096 | update_FR_ptime (cpu, FRk_3, 3); | |
3097 | ||
3098 | /* Mark this use of the register as a media op. */ | |
3099 | set_use_is_media (cpu, FRk_3); | |
3100 | } | |
3101 | ||
3102 | return cycles; | |
3103 | } | |
3104 | ||
3105 | int | |
3106 | frvbf_model_fr500_u_barrier (SIM_CPU *cpu, const IDESC *idesc, | |
3107 | int unit_num, int referenced) | |
3108 | { | |
3109 | int cycles; | |
3110 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
3111 | { | |
3112 | int i; | |
3113 | /* Wait for ALL resources. */ | |
3114 | for (i = 0; i < 64; ++i) | |
3115 | { | |
3116 | enforce_full_fr_latency (cpu, i); | |
3117 | vliw_wait_for_GR (cpu, i); | |
3118 | vliw_wait_for_FR (cpu, i); | |
3119 | vliw_wait_for_ACC (cpu, i); | |
3120 | } | |
3121 | for (i = 0; i < 8; ++i) | |
3122 | vliw_wait_for_CCR (cpu, i); | |
3123 | for (i = 0; i < 2; ++i) | |
3124 | { | |
3125 | vliw_wait_for_idiv_resource (cpu, i); | |
3126 | vliw_wait_for_fdiv_resource (cpu, i); | |
3127 | vliw_wait_for_fsqrt_resource (cpu, i); | |
3128 | } | |
3129 | handle_resource_wait (cpu); | |
3130 | for (i = 0; i < 64; ++i) | |
3131 | { | |
3132 | load_wait_for_GR (cpu, i); | |
3133 | load_wait_for_FR (cpu, i); | |
3134 | } | |
3135 | trace_vliw_wait_cycles (cpu); | |
3136 | return 0; | |
3137 | } | |
3138 | ||
3139 | cycles = idesc->timing->units[unit_num].done; | |
3140 | return cycles; | |
3141 | } | |
3142 | ||
3143 | int | |
3144 | frvbf_model_fr500_u_membar (SIM_CPU *cpu, const IDESC *idesc, | |
3145 | int unit_num, int referenced) | |
3146 | { | |
3147 | int cycles; | |
3148 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
3149 | { | |
3150 | int i; | |
3151 | /* Wait for ALL resources, except GR and ICC. */ | |
3152 | for (i = 0; i < 64; ++i) | |
3153 | { | |
3154 | enforce_full_fr_latency (cpu, i); | |
3155 | vliw_wait_for_FR (cpu, i); | |
3156 | vliw_wait_for_ACC (cpu, i); | |
3157 | } | |
3158 | for (i = 0; i < 4; ++i) | |
3159 | vliw_wait_for_CCR (cpu, i); | |
3160 | for (i = 0; i < 2; ++i) | |
3161 | { | |
3162 | vliw_wait_for_idiv_resource (cpu, i); | |
3163 | vliw_wait_for_fdiv_resource (cpu, i); | |
3164 | vliw_wait_for_fsqrt_resource (cpu, i); | |
3165 | } | |
3166 | handle_resource_wait (cpu); | |
3167 | for (i = 0; i < 64; ++i) | |
3168 | { | |
3169 | load_wait_for_FR (cpu, i); | |
3170 | } | |
3171 | trace_vliw_wait_cycles (cpu); | |
3172 | return 0; | |
3173 | } | |
3174 | ||
3175 | cycles = idesc->timing->units[unit_num].done; | |
3176 | return cycles; | |
3177 | } | |
3178 | ||
3179 | /* The frv machine is a fictional implementation of the fr500 which implements | |
3180 | all frv architectural features. */ | |
3181 | int | |
3182 | frvbf_model_frv_u_exec (SIM_CPU *cpu, const IDESC *idesc, | |
3183 | int unit_num, int referenced) | |
3184 | { | |
3185 | return idesc->timing->units[unit_num].done; | |
3186 | } | |
3187 | ||
3188 | /* The simple machine is a fictional implementation of the fr500 which | |
3189 | implements limited frv architectural features. */ | |
3190 | int | |
3191 | frvbf_model_simple_u_exec (SIM_CPU *cpu, const IDESC *idesc, | |
3192 | int unit_num, int referenced) | |
3193 | { | |
3194 | return idesc->timing->units[unit_num].done; | |
3195 | } | |
3196 | ||
3197 | /* The tomcat machine is models a prototype fr500 machine which had a few | |
3198 | bugs and restrictions to work around. */ | |
3199 | int | |
3200 | frvbf_model_tomcat_u_exec (SIM_CPU *cpu, const IDESC *idesc, | |
3201 | int unit_num, int referenced) | |
3202 | { | |
3203 | return idesc->timing->units[unit_num].done; | |
3204 | } | |
3205 | ||
3206 | #endif /* WITH_PROFILE_MODEL_P */ |