]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/ft32/interp.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sim: cpu: change default init to handle all cpus
[thirdparty/binutils-gdb.git] / sim / ft32 / interp.c
CommitLineData
f46e4eb7
JB		 1/* Simulator for the FT32 processor
2
4a94e368 3 Copyright (C) 2008-2022 Free Software Foundation, Inc.
f46e4eb7
JB		 4 Contributed by FTDI <support@ftdichip.com>
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
6df01ab8
MF		 21/* This must come before any other includes. */
22#include "defs.h"
23
f46e4eb7
JB		 24#include <fcntl.h>
25#include <signal.h>
26#include <stdlib.h>
27#include <stdint.h>
28
29#include "bfd.h"
df68e12b 30#include "sim/callback.h"
f46e4eb7 31#include "libiberty.h"
df68e12b 32#include "sim/sim.h"
f46e4eb7
JB		 33
34#include "sim-main.h"
35#include "sim-options.h"
1fef66b0 36#include "sim-signal.h"
f46e4eb7
JB		 37
38#include "opcode/ft32.h"
39
84bc490d
MF		 40#include "ft32-sim.h"
41
f46e4eb7
JB		 42/*
43 * FT32 is a Harvard architecture: RAM and code occupy
44 * different address spaces.
45 *
46 * sim and gdb model FT32 memory by adding 0x800000 to RAM
47 * addresses. This means that sim/gdb can treat all addresses
48 * similarly.
49 *
50 * The address space looks like:
51 *
52 * 00000 start of code memory
53 * 3ffff end of code memory
54 * 800000 start of RAM
55 * 80ffff end of RAM
56 */
57
58#define RAM_BIAS 0x800000 /* Bias added to RAM addresses. */
59
60static unsigned long
ed60d3ed 61ft32_extract_unsigned_integer (const unsigned char *addr, int len)
f46e4eb7
JB		 62{
63 unsigned long retval;
64 unsigned char *p;
65 unsigned char *startaddr = (unsigned char *) addr;
66 unsigned char *endaddr = startaddr + len;
67
68 /* Start at the most significant end of the integer, and work towards
69 the least significant. */
70 retval = 0;
71
72 for (p = endaddr; p > startaddr;)
73 retval = (retval << 8) | * -- p;
74
75 return retval;
76}
77
78static void
79ft32_store_unsigned_integer (unsigned char *addr, int len, unsigned long val)
80{
81 unsigned char *p;
82 unsigned char *startaddr = (unsigned char *)addr;
83 unsigned char *endaddr = startaddr + len;
84
85 for (p = startaddr; p < endaddr; p++)
86 {
87 *p = val & 0xff;
88 val >>= 8;
89 }
90}
91
92/*
93 * Align EA according to its size DW.
94 * The FT32 ignores the low bit of a 16-bit addresss,
95 * and the low two bits of a 32-bit address.
96 */
97static uint32_t ft32_align (uint32_t dw, uint32_t ea)
98{
99 switch (dw)
100 {
101 case 1:
102 ea &= ~1;
103 break;
104 case 2:
105 ea &= ~3;
106 break;
107 default:
108 break;
109 }
110 return ea;
111}
112
113/* Read an item from memory address EA, sized DW. */
114static uint32_t
115ft32_read_item (SIM_DESC sd, int dw, uint32_t ea)
116{
117 sim_cpu *cpu = STATE_CPU (sd, 0);
034685f9 118 address_word cia = CPU_PC_GET (cpu);
f46e4eb7
JB		 119 uint8_t byte[4];
120 uint32_t r;
121
122 ea = ft32_align (dw, ea);
123
124 switch (dw) {
125 case 0:
126 return sim_core_read_aligned_1 (cpu, cia, read_map, ea);
127 case 1:
128 return sim_core_read_aligned_2 (cpu, cia, read_map, ea);
129 case 2:
130 return sim_core_read_aligned_4 (cpu, cia, read_map, ea);
131 default:
132 abort ();
133 }
134}
135
136/* Write item V to memory address EA, sized DW. */
137static void
138ft32_write_item (SIM_DESC sd, int dw, uint32_t ea, uint32_t v)
139{
140 sim_cpu *cpu = STATE_CPU (sd, 0);
034685f9 141 address_word cia = CPU_PC_GET (cpu);
f46e4eb7
JB		 142 uint8_t byte[4];
143
144 ea = ft32_align (dw, ea);
145
146 switch (dw) {
147 case 0:
148 sim_core_write_aligned_1 (cpu, cia, write_map, ea, v);
149 break;
150 case 1:
151 sim_core_write_aligned_2 (cpu, cia, write_map, ea, v);
152 break;
153 case 2:
154 sim_core_write_aligned_4 (cpu, cia, write_map, ea, v);
155 break;
156 default:
157 abort ();
158 }
159}
160
161#define ILLEGAL() \
162 sim_engine_halt (sd, cpu, NULL, insnpc, sim_signalled, SIM_SIGILL)
163
164static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw, uint32_t ea)
165{
166 sim_cpu *cpu = STATE_CPU (sd, 0);
6780d373
MF		 167 struct ft32_cpu_state *ft32_cpu = FT32_SIM_CPU (cpu);
168 uint32_t insnpc = ft32_cpu->pc;
f46e4eb7
JB		 169 uint32_t r;
170 uint8_t byte[4];
171
172 ea &= 0x1ffff;
173 if (ea & ~0xffff)
174 {
175 /* Simulate some IO devices */
176 switch (ea)
177 {
bcd68f9e
JB		 178 case 0x10000:
179 return getchar ();
f46e4eb7
JB		 180 case 0x1fff4:
181 /* Read the simulator cycle timer. */
6780d373 182 return ft32_cpu->cycles / 100;
f46e4eb7
JB		 183 default:
184 sim_io_eprintf (sd, "Illegal IO read address %08x, pc %#x\n",
185 ea, insnpc);
186 ILLEGAL ();
187 }
188 }
189 return ft32_read_item (sd, dw, RAM_BIAS + ea);
190}
191
192static void cpu_mem_write (SIM_DESC sd, uint32_t dw, uint32_t ea, uint32_t d)
193{
194 sim_cpu *cpu = STATE_CPU (sd, 0);
6780d373 195 struct ft32_cpu_state *ft32_cpu = FT32_SIM_CPU (cpu);
f46e4eb7
JB		 196 ea &= 0x1ffff;
197 if (ea & 0x10000)
198 {
199 /* Simulate some IO devices */
200 switch (ea)
201 {
202 case 0x10000:
203 /* Console output */
204 putchar (d & 0xff);
205 break;
206 case 0x1fc80:
207 /* Unlock the PM write port */
6780d373 208 ft32_cpu->pm_unlock = (d == 0x1337f7d1);
f46e4eb7
JB		 209 break;
210 case 0x1fc84:
211 /* Set the PM write address register */
6780d373 212 ft32_cpu->pm_addr = d;
f46e4eb7
JB		 213 break;
214 case 0x1fc88:
6780d373 215 if (ft32_cpu->pm_unlock)
71c34ca7
JB		 216 {
217 /* Write to PM. */
6780d373
MF		 218 ft32_write_item (sd, dw, ft32_cpu->pm_addr, d);
219 ft32_cpu->pm_addr += 4;
71c34ca7 220 }
f46e4eb7
JB		 221 break;
222 case 0x1fffc:
223 /* Normal exit. */
6780d373 224 sim_engine_halt (sd, cpu, NULL, ft32_cpu->pc, sim_exited, ft32_cpu->regs[0]);
f46e4eb7
JB		 225 break;
226 case 0x1fff8:
227 sim_io_printf (sd, "Debug write %08x\n", d);
228 break;
229 default:
230 sim_io_eprintf (sd, "Unknown IO write %08x to to %08x\n", d, ea);
231 }
232 }
233 else
234 ft32_write_item (sd, dw, RAM_BIAS + ea, d);
235}
236
237#define GET_BYTE(ea) cpu_mem_read (sd, 0, (ea))
238#define PUT_BYTE(ea, d) cpu_mem_write (sd, 0, (ea), (d))
239
240/* LSBS (n) is a mask of the least significant N bits. */
241#define LSBS(n) ((1U << (n)) - 1)
242
243static void ft32_push (SIM_DESC sd, uint32_t v)
244{
245 sim_cpu *cpu = STATE_CPU (sd, 0);
6780d373
MF		 246 struct ft32_cpu_state *ft32_cpu = FT32_SIM_CPU (cpu);
247 ft32_cpu->regs[FT32_HARD_SP] -= 4;
248 ft32_cpu->regs[FT32_HARD_SP] &= 0xffff;
249 cpu_mem_write (sd, 2, ft32_cpu->regs[FT32_HARD_SP], v);
f46e4eb7
JB		 250}
251
252static uint32_t ft32_pop (SIM_DESC sd)
253{
254 sim_cpu *cpu = STATE_CPU (sd, 0);
6780d373
MF		 255 struct ft32_cpu_state *ft32_cpu = FT32_SIM_CPU (cpu);
256 uint32_t r = cpu_mem_read (sd, 2, ft32_cpu->regs[FT32_HARD_SP]);
257 ft32_cpu->regs[FT32_HARD_SP] += 4;
258 ft32_cpu->regs[FT32_HARD_SP] &= 0xffff;
f46e4eb7
JB		 259 return r;
260}
261
262/* Extract the low SIZ bits of N as an unsigned number. */
263static int nunsigned (int siz, int n)
264{
265 return n & LSBS (siz);
266}
267
268/* Extract the low SIZ bits of N as a signed number. */
269static int nsigned (int siz, int n)
270{
271 int shift = (sizeof (int) * 8) - siz;
272 return (n << shift) >> shift;
273}
274
275/* Signed division N / D, matching hw behavior for (MIN_INT, -1). */
276static uint32_t ft32sdiv (uint32_t n, uint32_t d)
277{
278 if (n == 0x80000000UL && d == 0xffffffffUL)
279 return 0x80000000UL;
280 else
281 return (uint32_t)((int)n / (int)d);
282}
283
284/* Signed modulus N % D, matching hw behavior for (MIN_INT, -1). */
285static uint32_t ft32smod (uint32_t n, uint32_t d)
286{
287 if (n == 0x80000000UL && d == 0xffffffffUL)
288 return 0;
289 else
290 return (uint32_t)((int)n % (int)d);
291}
292
293/* Circular rotate right N by B bits. */
294static uint32_t ror (uint32_t n, uint32_t b)
295{
296 b &= 31;
297 return (n >> b) | (n << (32 - b));
298}
299
300/* Implement the BINS machine instruction.
301 See FT32 Programmer's Reference for details. */
302static uint32_t bins (uint32_t d, uint32_t f, uint32_t len, uint32_t pos)
303{
304 uint32_t bitmask = LSBS (len) << pos;
305 return (d & ~bitmask) | ((f << pos) & bitmask);
306}
307
308/* Implement the FLIP machine instruction.
309 See FT32 Programmer's Reference for details. */
310static uint32_t flip (uint32_t x, uint32_t b)
311{
312 if (b & 1)
313 x = (x & 0x55555555) << 1 | (x & 0xAAAAAAAA) >> 1;
314 if (b & 2)
315 x = (x & 0x33333333) << 2 | (x & 0xCCCCCCCC) >> 2;
316 if (b & 4)
317 x = (x & 0x0F0F0F0F) << 4 | (x & 0xF0F0F0F0) >> 4;
318 if (b & 8)
319 x = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8;
320 if (b & 16)
321 x = (x & 0x0000FFFF) << 16 | (x & 0xFFFF0000) >> 16;
322 return x;
323}
324
325static void
326step_once (SIM_DESC sd)
327{
328 sim_cpu *cpu = STATE_CPU (sd, 0);
6780d373 329 struct ft32_cpu_state *ft32_cpu = FT32_SIM_CPU (cpu);
034685f9 330 address_word cia = CPU_PC_GET (cpu);
f46e4eb7
JB		 331 uint32_t inst;
332 uint32_t dw;
333 uint32_t cb;
334 uint32_t r_d;
335 uint32_t cr;
336 uint32_t cv;
337 uint32_t bt;
338 uint32_t r_1;
339 uint32_t rimm;
340 uint32_t r_2;
341 uint32_t k20;
342 uint32_t pa;
343 uint32_t aa;
344 uint32_t k16;
3b4b0a62 345 uint32_t k15;
f46e4eb7
JB		 346 uint32_t al;
347 uint32_t r_1v;
348 uint32_t rimmv;
349 uint32_t bit_pos;
350 uint32_t bit_len;
351 uint32_t upper;
352 uint32_t insnpc;
dcc31d28
JB		 353 unsigned int sc[2];
354 int isize;
f46e4eb7 355
6780d373
MF		 356 inst = ft32_read_item (sd, 2, ft32_cpu->pc);
357 ft32_cpu->cycles += 1;
f46e4eb7 358
dcc31d28 359 if ((STATE_ARCHITECTURE (sd)->mach == bfd_mach_ft32b)
6780d373 360 && ft32_decode_shortcode (ft32_cpu->pc, inst, sc))
dcc31d28 361 {
6780d373 362 if ((ft32_cpu->pc & 3) == 0)
dcc31d28
JB		 363 inst = sc[0];
364 else
365 inst = sc[1];
366 isize = 2;
367 }
368 else
369 isize = 4;
370
f46e4eb7
JB		 371 /* Handle "call 8" (which is FT32's "break" equivalent) here. */
372 if (inst == 0x00340002)
373 {
374 sim_engine_halt (sd, cpu, NULL,
6780d373 375 ft32_cpu->pc,
f46e4eb7
JB		 376 sim_stopped, SIM_SIGTRAP);
377 goto escape;
378 }
379
380 dw = (inst >> FT32_FLD_DW_BIT) & LSBS (FT32_FLD_DW_SIZ);
381 cb = (inst >> FT32_FLD_CB_BIT) & LSBS (FT32_FLD_CB_SIZ);
382 r_d = (inst >> FT32_FLD_R_D_BIT) & LSBS (FT32_FLD_R_D_SIZ);
383 cr = (inst >> FT32_FLD_CR_BIT) & LSBS (FT32_FLD_CR_SIZ);
384 cv = (inst >> FT32_FLD_CV_BIT) & LSBS (FT32_FLD_CV_SIZ);
385 bt = (inst >> FT32_FLD_BT_BIT) & LSBS (FT32_FLD_BT_SIZ);
386 r_1 = (inst >> FT32_FLD_R_1_BIT) & LSBS (FT32_FLD_R_1_SIZ);
387 rimm = (inst >> FT32_FLD_RIMM_BIT) & LSBS (FT32_FLD_RIMM_SIZ);
388 r_2 = (inst >> FT32_FLD_R_2_BIT) & LSBS (FT32_FLD_R_2_SIZ);
389 k20 = nsigned (20, (inst >> FT32_FLD_K20_BIT) & LSBS (FT32_FLD_K20_SIZ));
390 pa = (inst >> FT32_FLD_PA_BIT) & LSBS (FT32_FLD_PA_SIZ);
391 aa = (inst >> FT32_FLD_AA_BIT) & LSBS (FT32_FLD_AA_SIZ);
392 k16 = (inst >> FT32_FLD_K16_BIT) & LSBS (FT32_FLD_K16_SIZ);
3b4b0a62
JB		 393 k15 = (inst >> FT32_FLD_K15_BIT) & LSBS (FT32_FLD_K15_SIZ);
394 if (k15 & 0x80)
395 k15 ^= 0x7f00;
396 if (k15 & 0x4000)
397 k15 -= 0x8000;
f46e4eb7
JB		 398 al = (inst >> FT32_FLD_AL_BIT) & LSBS (FT32_FLD_AL_SIZ);
399
6780d373
MF		 400 r_1v = ft32_cpu->regs[r_1];
401 rimmv = (rimm & 0x400) ? nsigned (10, rimm) : ft32_cpu->regs[rimm & 0x1f];
f46e4eb7
JB		 402
403 bit_pos = rimmv & 31;
404 bit_len = 0xf & (rimmv >> 5);
405 if (bit_len == 0)
406 bit_len = 16;
407
408 upper = (inst >> 27);
409
6780d373
MF		 410 insnpc = ft32_cpu->pc;
411 ft32_cpu->pc += isize;
f46e4eb7
JB		 412 switch (upper)
413 {
414 case FT32_PAT_TOC:
415 case FT32_PAT_TOCI:
416 {
6780d373 417 int take = (cr == 3) || ((1 & (ft32_cpu->regs[28 + cr] >> cb)) == cv);
f46e4eb7
JB		 418 if (take)
419 {
6780d373 420 ft32_cpu->cycles += 1;
f46e4eb7 421 if (bt)
6780d373 422 ft32_push (sd, ft32_cpu->pc); /* this is a call. */
f46e4eb7 423 if (upper == FT32_PAT_TOC)
6780d373 424 ft32_cpu->pc = pa << 2;
f46e4eb7 425 else
6780d373
MF		 426 ft32_cpu->pc = ft32_cpu->regs[r_2];
427 if (ft32_cpu->pc == 0x8)
f46e4eb7
JB		 428 goto escape;
429 }
430 }
431 break;
432
433 case FT32_PAT_ALUOP:
434 case FT32_PAT_CMPOP:
435 {
436 uint32_t result;
437 switch (al)
438 {
439 case 0x0: result = r_1v + rimmv; break;
440 case 0x1: result = ror (r_1v, rimmv); break;
441 case 0x2: result = r_1v - rimmv; break;
442 case 0x3: result = (r_1v << 10) | (1023 & rimmv); break;
443 case 0x4: result = r_1v & rimmv; break;
444 case 0x5: result = r_1v | rimmv; break;
445 case 0x6: result = r_1v ^ rimmv; break;
446 case 0x7: result = ~(r_1v ^ rimmv); break;
447 case 0x8: result = r_1v << rimmv; break;
448 case 0x9: result = r_1v >> rimmv; break;
449 case 0xa: result = (int32_t)r_1v >> rimmv; break;
450 case 0xb: result = bins (r_1v, rimmv >> 10, bit_len, bit_pos); break;
451 case 0xc: result = nsigned (bit_len, r_1v >> bit_pos); break;
452 case 0xd: result = nunsigned (bit_len, r_1v >> bit_pos); break;
453 case 0xe: result = flip (r_1v, rimmv); break;
454 default:
455 sim_io_eprintf (sd, "Unhandled alu %#x\n", al);
456 ILLEGAL ();
457 }
458 if (upper == FT32_PAT_ALUOP)
6780d373 459 ft32_cpu->regs[r_d] = result;
f46e4eb7
JB		 460 else
461 {
462 uint32_t dwmask = 0;
463 int dwsiz = 0;
464 int zero;
465 int sign;
466 int ahi;
467 int bhi;
468 int overflow;
469 int carry;
470 int bit;
471 uint64_t ra;
472 uint64_t rb;
473 int above;
474 int greater;
475 int greatereq;
476
477 switch (dw)
478 {
479 case 0: dwsiz = 7; dwmask = 0xffU; break;
480 case 1: dwsiz = 15; dwmask = 0xffffU; break;
481 case 2: dwsiz = 31; dwmask = 0xffffffffU; break;
482 }
483
484 zero = (0 == (result & dwmask));
485 sign = 1 & (result >> dwsiz);
486 ahi = 1 & (r_1v >> dwsiz);
487 bhi = 1 & (rimmv >> dwsiz);
488 overflow = (sign != ahi) & (ahi == !bhi);
489 bit = (dwsiz + 1);
490 ra = r_1v & dwmask;
491 rb = rimmv & dwmask;
492 switch (al)
493 {
494 case 0x0: carry = 1 & ((ra + rb) >> bit); break;
495 case 0x2: carry = 1 & ((ra - rb) >> bit); break;
496 default: carry = 0; break;
497 }
498 above = (!carry & !zero);
499 greater = (sign == overflow) & !zero;
500 greatereq = (sign == overflow);
501
6780d373 502 ft32_cpu->regs[r_d] = (
f46e4eb7
JB		 503 (above << 6) |
504 (greater << 5) |
505 (greatereq << 4) |
506 (sign << 3) |
507 (overflow << 2) |
508 (carry << 1) |
509 (zero << 0));
510 }
511 }
512 break;
513
514 case FT32_PAT_LDK:
6780d373 515 ft32_cpu->regs[r_d] = k20;
f46e4eb7
JB		 516 break;
517
518 case FT32_PAT_LPM:
6780d373
MF		 519 ft32_cpu->regs[r_d] = ft32_read_item (sd, dw, pa << 2);
520 ft32_cpu->cycles += 1;
f46e4eb7
JB		 521 break;
522
523 case FT32_PAT_LPMI:
6780d373
MF		 524 ft32_cpu->regs[r_d] = ft32_read_item (sd, dw, ft32_cpu->regs[r_1] + k15);
525 ft32_cpu->cycles += 1;
f46e4eb7
JB		 526 break;
527
528 case FT32_PAT_STA:
6780d373 529 cpu_mem_write (sd, dw, aa, ft32_cpu->regs[r_d]);
f46e4eb7
JB		 530 break;
531
532 case FT32_PAT_STI:
6780d373 533 cpu_mem_write (sd, dw, ft32_cpu->regs[r_d] + k15, ft32_cpu->regs[r_1]);
f46e4eb7
JB		 534 break;
535
536 case FT32_PAT_LDA:
6780d373
MF		 537 ft32_cpu->regs[r_d] = cpu_mem_read (sd, dw, aa);
538 ft32_cpu->cycles += 1;
f46e4eb7
JB		 539 break;
540
541 case FT32_PAT_LDI:
6780d373
MF		 542 ft32_cpu->regs[r_d] = cpu_mem_read (sd, dw, ft32_cpu->regs[r_1] + k15);
543 ft32_cpu->cycles += 1;
f46e4eb7
JB		 544 break;
545
546 case FT32_PAT_EXA:
547 {
548 uint32_t tmp;
549 tmp = cpu_mem_read (sd, dw, aa);
6780d373
MF		 550 cpu_mem_write (sd, dw, aa, ft32_cpu->regs[r_d]);
551 ft32_cpu->regs[r_d] = tmp;
552 ft32_cpu->cycles += 1;
f46e4eb7
JB		 553 }
554 break;
555
556 case FT32_PAT_EXI:
557 {
558 uint32_t tmp;
6780d373
MF		 559 tmp = cpu_mem_read (sd, dw, ft32_cpu->regs[r_1] + k15);
560 cpu_mem_write (sd, dw, ft32_cpu->regs[r_1] + k15, ft32_cpu->regs[r_d]);
561 ft32_cpu->regs[r_d] = tmp;
562 ft32_cpu->cycles += 1;
f46e4eb7
JB		 563 }
564 break;
565
566 case FT32_PAT_PUSH:
567 ft32_push (sd, r_1v);
568 break;
569
570 case FT32_PAT_LINK:
6780d373
MF		 571 ft32_push (sd, ft32_cpu->regs[r_d]);
572 ft32_cpu->regs[r_d] = ft32_cpu->regs[FT32_HARD_SP];
573 ft32_cpu->regs[FT32_HARD_SP] -= k16;
574 ft32_cpu->regs[FT32_HARD_SP] &= 0xffff;
f46e4eb7
JB		 575 break;
576
577 case FT32_PAT_UNLINK:
6780d373
MF		 578 ft32_cpu->regs[FT32_HARD_SP] = ft32_cpu->regs[r_d];
579 ft32_cpu->regs[FT32_HARD_SP] &= 0xffff;
580 ft32_cpu->regs[r_d] = ft32_pop (sd);
f46e4eb7
JB		 581 break;
582
583 case FT32_PAT_POP:
6780d373
MF		 584 ft32_cpu->cycles += 1;
585 ft32_cpu->regs[r_d] = ft32_pop (sd);
f46e4eb7
JB		 586 break;
587
588 case FT32_PAT_RETURN:
6780d373 589 ft32_cpu->pc = ft32_pop (sd);
f46e4eb7
JB		 590 break;
591
592 case FT32_PAT_FFUOP:
593 switch (al)
594 {
595 case 0x0:
6780d373 596 ft32_cpu->regs[r_d] = r_1v / rimmv;
f46e4eb7
JB		 597 break;
598 case 0x1:
6780d373 599 ft32_cpu->regs[r_d] = r_1v % rimmv;
f46e4eb7
JB		 600 break;
601 case 0x2:
6780d373 602 ft32_cpu->regs[r_d] = ft32sdiv (r_1v, rimmv);
f46e4eb7
JB		 603 break;
604 case 0x3:
6780d373 605 ft32_cpu->regs[r_d] = ft32smod (r_1v, rimmv);
f46e4eb7
JB		 606 break;
607
608 case 0x4:
609 {
610 /* strcmp instruction. */
611 uint32_t a = r_1v;
612 uint32_t b = rimmv;
613 uint32_t i = 0;
614 while ((GET_BYTE (a + i) != 0) &&
615 (GET_BYTE (a + i) == GET_BYTE (b + i)))
616 i++;
6780d373 617 ft32_cpu->regs[r_d] = GET_BYTE (a + i) - GET_BYTE (b + i);
f46e4eb7
JB		 618 }
619 break;
620
621 case 0x5:
622 {
623 /* memcpy instruction. */
624 uint32_t src = r_1v;
6780d373 625 uint32_t dst = ft32_cpu->regs[r_d];
f46e4eb7 626 uint32_t i;
395b0d8a 627 for (i = 0; i < (rimmv & 0x7fff); i++)
f46e4eb7
JB		 628 PUT_BYTE (dst + i, GET_BYTE (src + i));
629 }
630 break;
631 case 0x6:
632 {
633 /* strlen instruction. */
634 uint32_t src = r_1v;
635 uint32_t i;
636 for (i = 0; GET_BYTE (src + i) != 0; i++)
637 ;
6780d373 638 ft32_cpu->regs[r_d] = i;
f46e4eb7
JB		 639 }
640 break;
641 case 0x7:
642 {
643 /* memset instruction. */
6780d373 644 uint32_t dst = ft32_cpu->regs[r_d];
f46e4eb7 645 uint32_t i;
395b0d8a 646 for (i = 0; i < (rimmv & 0x7fff); i++)
f46e4eb7
JB		 647 PUT_BYTE (dst + i, r_1v);
648 }
649 break;
650 case 0x8:
6780d373 651 ft32_cpu->regs[r_d] = r_1v * rimmv;
f46e4eb7
JB		 652 break;
653 case 0x9:
6780d373 654 ft32_cpu->regs[r_d] = ((uint64_t)r_1v * (uint64_t)rimmv) >> 32;
f46e4eb7
JB		 655 break;
656 case 0xa:
657 {
658 /* stpcpy instruction. */
659 uint32_t src = r_1v;
6780d373 660 uint32_t dst = ft32_cpu->regs[r_d];
f46e4eb7
JB		 661 uint32_t i;
662 for (i = 0; GET_BYTE (src + i) != 0; i++)
663 PUT_BYTE (dst + i, GET_BYTE (src + i));
664 PUT_BYTE (dst + i, 0);
6780d373 665 ft32_cpu->regs[r_d] = dst + i;
f46e4eb7
JB		 666 }
667 break;
668 case 0xe:
669 {
670 /* streamout instruction. */
671 uint32_t i;
6780d373 672 uint32_t src = ft32_cpu->regs[r_1];
f46e4eb7
JB		 673 for (i = 0; i < rimmv; i += (1 << dw))
674 {
675 cpu_mem_write (sd,
676 dw,
6780d373 677 ft32_cpu->regs[r_d],
f46e4eb7
JB		 678 cpu_mem_read (sd, dw, src));
679 src += (1 << dw);
680 }
681 }
682 break;
683 default:
684 sim_io_eprintf (sd, "Unhandled ffu %#x at %08x\n", al, insnpc);
685 ILLEGAL ();
686 }
687 break;
688
689 default:
690 sim_io_eprintf (sd, "Unhandled pattern %d at %08x\n", upper, insnpc);
691 ILLEGAL ();
692 }
6780d373 693 ft32_cpu->num_i++;
f46e4eb7
JB		 694
695escape:
696 ;
697}
698
699void
700sim_engine_run (SIM_DESC sd,
701 int next_cpu_nr, /* ignore */
702 int nr_cpus, /* ignore */
703 int siggnal) /* ignore */
704{
705 sim_cpu *cpu;
706
707 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
708
709 cpu = STATE_CPU (sd, 0);
710
711 while (1)
712 {
713 step_once (sd);
714 if (sim_events_tick (sd))
715 sim_events_process (sd);
716 }
717}
718
f46e4eb7
JB		 719static uint32_t *
720ft32_lookup_register (SIM_CPU *cpu, int nr)
721{
722 /* Handle the register number translation here.
723 * Sim registers are 0-31.
724 * Other tools (gcc, gdb) use:
725 * 0 - fp
726 * 1 - sp
727 * 2 - r0
728 * 31 - cc
729 */
730
6780d373
MF		 731 struct ft32_cpu_state *ft32_cpu = FT32_SIM_CPU (cpu);
732
f46e4eb7
JB		 733 if ((nr < 0) || (nr > 32))
734 {
735 sim_io_eprintf (CPU_STATE (cpu), "unknown register %i\n", nr);
736 abort ();
737 }
738
739 switch (nr)
740 {
741 case FT32_FP_REGNUM:
6780d373 742 return &ft32_cpu->regs[FT32_HARD_FP];
f46e4eb7 743 case FT32_SP_REGNUM:
6780d373 744 return &ft32_cpu->regs[FT32_HARD_SP];
f46e4eb7 745 case FT32_CC_REGNUM:
6780d373 746 return &ft32_cpu->regs[FT32_HARD_CC];
f46e4eb7 747 case FT32_PC_REGNUM:
6780d373 748 return &ft32_cpu->pc;
f46e4eb7 749 default:
6780d373 750 return &ft32_cpu->regs[nr - 2];
f46e4eb7
JB		 751 }
752}
753
754static int
755ft32_reg_store (SIM_CPU *cpu,
756 int rn,
ee1cffd3 757 const void *memory,
f46e4eb7
JB		 758 int length)
759{
760 if (0 <= rn && rn <= 32)
761 {
762 if (length == 4)
763 *ft32_lookup_register (cpu, rn) = ft32_extract_unsigned_integer (memory, 4);
764
765 return 4;
766 }
767 else
768 return 0;
769}
770
771static int
772ft32_reg_fetch (SIM_CPU *cpu,
773 int rn,
ee1cffd3 774 void *memory,
f46e4eb7
JB		 775 int length)
776{
777 if (0 <= rn && rn <= 32)
778 {
779 if (length == 4)
780 ft32_store_unsigned_integer (memory, 4, *ft32_lookup_register (cpu, rn));
781
782 return 4;
783 }
784 else
785 return 0;
786}
787
788static sim_cia
789ft32_pc_get (SIM_CPU *cpu)
790{
6780d373 791 return FT32_SIM_CPU (cpu)->pc;
f46e4eb7
JB		 792}
793
794static void
795ft32_pc_set (SIM_CPU *cpu, sim_cia newpc)
796{
6780d373 797 FT32_SIM_CPU (cpu)->pc = newpc;
f46e4eb7
JB		 798}
799
800/* Cover function of sim_state_free to free the cpu buffers as well. */
801
802static void
803free_state (SIM_DESC sd)
804{
805 if (STATE_MODULES (sd) != NULL)
806 sim_module_uninstall (sd);
807 sim_cpu_free_all (sd);
808 sim_state_free (sd);
809}
810
811SIM_DESC
812sim_open (SIM_OPEN_KIND kind,
813 host_callback *cb,
814 struct bfd *abfd,
2e3d4f4d 815 char * const *argv)
f46e4eb7
JB		 816{
817 char c;
818 size_t i;
819 SIM_DESC sd = sim_state_alloc (kind, cb);
820
ba307cdd
MF		 821 /* Set default options before parsing user options. */
822 current_alignment = STRICT_ALIGNMENT;
f9a4d543 823 current_target_byte_order = BFD_ENDIAN_LITTLE;
ba307cdd 824
f46e4eb7 825 /* The cpu data is kept in a separately allocated chunk of memory. */
883be197 826 if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct ft32_cpu_state))
6780d373 827 != SIM_RC_OK)
f46e4eb7
JB		 828 {
829 free_state (sd);
830 return 0;
831 }
832
833 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
834 {
835 free_state (sd);
836 return 0;
837 }
838
77cf2ef5 839 /* The parser will print an error message for us, so we silently return. */
f46e4eb7
JB		 840 if (sim_parse_args (sd, argv) != SIM_RC_OK)
841 {
842 free_state (sd);
843 return 0;
844 }
845
846 /* Allocate external memory if none specified by user.
847 Use address 4 here in case the user wanted address 0 unmapped. */
848 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
849 {
850 sim_do_command (sd, "memory region 0x00000000,0x40000");
851 sim_do_command (sd, "memory region 0x800000,0x10000");
852 }
853
854 /* Check for/establish the reference program image. */
e8f20a28 855 if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
f46e4eb7
JB		 856 {
857 free_state (sd);
858 return 0;
859 }
860
861 /* Configure/verify the target byte order and other runtime
862 configuration options. */
863 if (sim_config (sd) != SIM_RC_OK)
864 {
865 free_state (sd);
866 return 0;
867 }
868
869 if (sim_post_argv_init (sd) != SIM_RC_OK)
870 {
871 free_state (sd);
872 return 0;
873 }
874
875 /* CPU specific initialization. */
876 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
877 {
878 SIM_CPU *cpu = STATE_CPU (sd, i);
879
880 CPU_REG_FETCH (cpu) = ft32_reg_fetch;
881 CPU_REG_STORE (cpu) = ft32_reg_store;
882 CPU_PC_FETCH (cpu) = ft32_pc_get;
883 CPU_PC_STORE (cpu) = ft32_pc_set;
884 }
885
886 return sd;
887}
888
f46e4eb7
JB		 889SIM_RC
890sim_create_inferior (SIM_DESC sd,
891 struct bfd *abfd,
2e3d4f4d
MF		 892 char * const *argv,
893 char * const *env)
f46e4eb7
JB		 894{
895 uint32_t addr;
896 sim_cpu *cpu = STATE_CPU (sd, 0);
6780d373 897 struct ft32_cpu_state *ft32_cpu = FT32_SIM_CPU (cpu);
8cfc9a18 898 host_callback *cb = STATE_CALLBACK (sd);
f46e4eb7
JB		 899
900 /* Set the PC. */
901 if (abfd != NULL)
902 addr = bfd_get_start_address (abfd);
903 else
904 addr = 0;
905
0e967299
MF		 906 /* Standalone mode (i.e. `run`) will take care of the argv for us in
907 sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
908 with `gdb`), we need to handle it because the user can change the
909 argv on the fly via gdb's 'run'. */
910 if (STATE_PROG_ARGV (sd) != argv)
f46e4eb7
JB		 911 {
912 freeargv (STATE_PROG_ARGV (sd));
913 STATE_PROG_ARGV (sd) = dupargv (argv);
914 }
54f7a83a
MF		 915
916 if (STATE_PROG_ENVP (sd) != env)
917 {
918 freeargv (STATE_PROG_ENVP (sd));
919 STATE_PROG_ENVP (sd) = dupargv (env);
920 }
921
8cfc9a18
MF		 922 cb->argv = STATE_PROG_ARGV (sd);
923 cb->envp = STATE_PROG_ENVP (sd);
924
6780d373
MF		 925 ft32_cpu->regs[FT32_HARD_SP] = addr;
926 ft32_cpu->num_i = 0;
927 ft32_cpu->cycles = 0;
928 ft32_cpu->next_tick_cycle = 100000;
f46e4eb7
JB		 929
930 return SIM_RC_OK;
931}
A mirror of the official binutils-gdb repository