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Commit | Line | Data |
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c906108c SS |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
18 | */ | |
19 | ||
20 | #include "config.h" | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <signal.h> | |
24 | #ifdef HAVE_TIME_H | |
25 | #include <time.h> | |
26 | #endif | |
27 | #ifdef HAVE_STDLIB_H | |
28 | #include <stdlib.h> | |
29 | #endif | |
30 | #ifdef HAVE_SYS_PARAM_H | |
31 | #include <sys/param.h> | |
32 | #endif | |
c906108c SS |
33 | #include "ansidecl.h" |
34 | #include "bfd.h" | |
3c25f8c7 AC |
35 | #include "gdb/callback.h" |
36 | #include "gdb/remote-sim.h" | |
a64bfde3 | 37 | #include "gdb/sim-h8300.h" |
c906108c SS |
38 | |
39 | #ifndef SIGTRAP | |
40 | # define SIGTRAP 5 | |
41 | #endif | |
42 | ||
43 | int debug; | |
44 | ||
45 | host_callback *sim_callback; | |
46 | ||
47 | static SIM_OPEN_KIND sim_kind; | |
48 | static char *myname; | |
49 | ||
50 | /* FIXME: Needs to live in header file. | |
51 | This header should also include the things in remote-sim.h. | |
52 | One could move this to remote-sim.h but this function isn't needed | |
53 | by gdb. */ | |
54 | void sim_set_simcache_size PARAMS ((int)); | |
55 | ||
de9b1892 | 56 | #define X(op, size) op * 4 + size |
c906108c | 57 | |
de9b1892 | 58 | #define SP (h8300hmode ? SL : SW) |
c906108c SS |
59 | #define SB 0 |
60 | #define SW 1 | |
61 | #define SL 2 | |
62 | #define OP_REG 1 | |
63 | #define OP_DEC 2 | |
64 | #define OP_DISP 3 | |
65 | #define OP_INC 4 | |
66 | #define OP_PCREL 5 | |
67 | #define OP_MEM 6 | |
68 | #define OP_CCR 7 | |
69 | #define OP_IMM 8 | |
70 | #define OP_ABS 10 | |
fc974602 | 71 | #define OP_EXR 11 |
c906108c SS |
72 | #define h8_opcodes ops |
73 | #define DEFINE_TABLE | |
74 | #include "opcode/h8300.h" | |
75 | ||
76 | #include "inst.h" | |
77 | ||
0ef9643e | 78 | /* The rate at which to call the host's poll_quit callback. */ |
7a292a7a SS |
79 | |
80 | #define POLL_QUIT_INTERVAL 0x80000 | |
81 | ||
c906108c | 82 | #define LOW_BYTE(x) ((x) & 0xff) |
de9b1892 KH |
83 | #define HIGH_BYTE(x) (((x) >> 8) & 0xff) |
84 | #define P(X,Y) ((X << 8) | Y) | |
c906108c | 85 | |
d0fe2f7e KH |
86 | #define BUILDSR() \ |
87 | cpu.ccr = ((I << 7) | (UI << 6) | (H << 5) | (U << 4) \ | |
88 | | (N << 3) | (Z << 2) | (V << 1) | C); | |
c906108c | 89 | |
fc974602 | 90 | #define BUILDEXR() \ |
d1335144 | 91 | if (h8300smode) cpu.exr = (trace<<7) | intMask; |
fc974602 | 92 | |
c906108c SS |
93 | #define GETSR() \ |
94 | c = (cpu.ccr >> 0) & 1;\ | |
95 | v = (cpu.ccr >> 1) & 1;\ | |
96 | nz = !((cpu.ccr >> 2) & 1);\ | |
f6225c96 AV |
97 | n = (cpu.ccr >> 3) & 1;\ |
98 | u = (cpu.ccr >> 4) & 1;\ | |
99 | h = (cpu.ccr >> 5) & 1;\ | |
100 | ui = ((cpu.ccr >> 6) & 1);\ | |
101 | intMaskBit = (cpu.ccr >> 7) & 1; | |
c906108c | 102 | |
d0fe2f7e KH |
103 | #define GETEXR() \ |
104 | if (h8300smode) \ | |
105 | { \ | |
106 | trace = (cpu.exr >> 7) & 1; \ | |
107 | intMask = cpu.exr & 7; \ | |
108 | } | |
fc974602 | 109 | |
c906108c | 110 | #ifdef __CHAR_IS_SIGNED__ |
de9b1892 | 111 | #define SEXTCHAR(x) ((char) (x)) |
c906108c SS |
112 | #endif |
113 | ||
114 | #ifndef SEXTCHAR | |
d0fe2f7e | 115 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff) |
c906108c SS |
116 | #endif |
117 | ||
118 | #define UEXTCHAR(x) ((x) & 0xff) | |
119 | #define UEXTSHORT(x) ((x) & 0xffff) | |
de9b1892 | 120 | #define SEXTSHORT(x) ((short) (x)) |
c906108c SS |
121 | |
122 | static cpu_state_type cpu; | |
123 | ||
124 | int h8300hmode = 0; | |
125 | int h8300smode = 0; | |
126 | ||
127 | static int memory_size; | |
128 | ||
c906108c SS |
129 | static int |
130 | get_now () | |
131 | { | |
3b02cf92 | 132 | return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */ |
c906108c SS |
133 | } |
134 | ||
135 | static int | |
136 | now_persec () | |
137 | { | |
138 | return 1; | |
139 | } | |
140 | ||
c906108c SS |
141 | static int |
142 | bitfrom (x) | |
143 | { | |
144 | switch (x & SIZE) | |
145 | { | |
146 | case L_8: | |
147 | return SB; | |
148 | case L_16: | |
149 | return SW; | |
150 | case L_32: | |
151 | return SL; | |
152 | case L_P: | |
153 | return h8300hmode ? SL : SW; | |
154 | } | |
155 | } | |
156 | ||
0ef9643e | 157 | static unsigned int |
c906108c SS |
158 | lvalue (x, rn) |
159 | { | |
160 | switch (x / 4) | |
161 | { | |
162 | case OP_DISP: | |
163 | if (rn == 8) | |
164 | { | |
165 | return X (OP_IMM, SP); | |
166 | } | |
167 | return X (OP_REG, SP); | |
168 | ||
169 | case OP_MEM: | |
c906108c | 170 | return X (OP_MEM, SP); |
0ef9643e | 171 | |
c906108c | 172 | default: |
3b02cf92 | 173 | abort (); /* ?? May be something more usefull? */ |
c906108c SS |
174 | } |
175 | } | |
176 | ||
177 | static unsigned int | |
178 | decode (addr, data, dst) | |
179 | int addr; | |
180 | unsigned char *data; | |
181 | decoded_inst *dst; | |
182 | ||
183 | { | |
184 | int rs = 0; | |
185 | int rd = 0; | |
186 | int rdisp = 0; | |
187 | int abs = 0; | |
c906108c | 188 | int bit = 0; |
0ef9643e | 189 | int plen = 0; |
6d028502 | 190 | struct h8_opcode *q; |
c906108c | 191 | int size = 0; |
0ef9643e | 192 | |
c906108c SS |
193 | dst->dst.type = -1; |
194 | dst->src.type = -1; | |
0ef9643e JL |
195 | |
196 | /* Find the exact opcode/arg combo. */ | |
6d028502 | 197 | for (q = h8_opcodes; q->name; q++) |
c906108c | 198 | { |
6d028502 | 199 | op_type *nib = q->data.nib; |
c906108c SS |
200 | unsigned int len = 0; |
201 | ||
c906108c SS |
202 | while (1) |
203 | { | |
204 | op_type looking_for = *nib; | |
205 | int thisnib = data[len >> 1]; | |
206 | ||
207 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
208 | ||
209 | if (looking_for < 16 && looking_for >= 0) | |
210 | { | |
211 | if (looking_for != thisnib) | |
212 | goto fail; | |
213 | } | |
214 | else | |
215 | { | |
216 | if ((int) looking_for & (int) B31) | |
217 | { | |
218 | if (!(((int) thisnib & 0x8) != 0)) | |
219 | goto fail; | |
0ef9643e JL |
220 | |
221 | looking_for = (op_type) ((int) looking_for & ~(int) B31); | |
c906108c SS |
222 | thisnib &= 0x7; |
223 | } | |
0ef9643e | 224 | |
c906108c SS |
225 | if ((int) looking_for & (int) B30) |
226 | { | |
227 | if (!(((int) thisnib & 0x8) == 0)) | |
228 | goto fail; | |
0ef9643e | 229 | |
c906108c SS |
230 | looking_for = (op_type) ((int) looking_for & ~(int) B30); |
231 | } | |
0ef9643e | 232 | |
c906108c SS |
233 | if (looking_for & DBIT) |
234 | { | |
0a17cd59 AC |
235 | /* Exclude adds/subs by looking at bit 0 and 2, and |
236 | make sure the operand size, either w or l, | |
237 | matches by looking at bit 1. */ | |
238 | if ((looking_for & 7) != (thisnib & 7)) | |
c906108c | 239 | goto fail; |
0ef9643e | 240 | |
c906108c SS |
241 | abs = (thisnib & 0x8) ? 2 : 1; |
242 | } | |
243 | else if (looking_for & (REG | IND | INC | DEC)) | |
244 | { | |
245 | if (looking_for & REG) | |
246 | { | |
0ef9643e | 247 | /* Can work out size from the register. */ |
c906108c SS |
248 | size = bitfrom (looking_for); |
249 | } | |
250 | if (looking_for & SRC) | |
0ef9643e | 251 | rs = thisnib; |
c906108c | 252 | else |
0ef9643e | 253 | rd = thisnib; |
c906108c SS |
254 | } |
255 | else if (looking_for & L_16) | |
256 | { | |
257 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
258 | plen = 16; | |
259 | if (looking_for & (PCREL | DISP)) | |
260 | { | |
261 | abs = (short) (abs); | |
262 | } | |
263 | } | |
264 | else if (looking_for & ABSJMP) | |
265 | { | |
0ef9643e | 266 | abs = (data[1] << 16) | (data[2] << 8) | (data[3]); |
c906108c SS |
267 | } |
268 | else if (looking_for & MEMIND) | |
269 | { | |
270 | abs = data[1]; | |
271 | } | |
272 | else if (looking_for & L_32) | |
273 | { | |
274 | int i = len >> 1; | |
0ef9643e | 275 | |
c906108c SS |
276 | abs = (data[i] << 24) |
277 | | (data[i + 1] << 16) | |
278 | | (data[i + 2] << 8) | |
279 | | (data[i + 3]); | |
280 | ||
281 | plen = 32; | |
282 | } | |
283 | else if (looking_for & L_24) | |
284 | { | |
285 | int i = len >> 1; | |
0ef9643e | 286 | |
c906108c SS |
287 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
288 | plen = 24; | |
289 | } | |
290 | else if (looking_for & IGNORE) | |
291 | { | |
0ef9643e | 292 | ; |
c906108c SS |
293 | } |
294 | else if (looking_for & DISPREG) | |
295 | { | |
296 | rdisp = thisnib & 0x7; | |
297 | } | |
298 | else if (looking_for & KBIT) | |
299 | { | |
300 | switch (thisnib) | |
301 | { | |
302 | case 9: | |
303 | abs = 4; | |
304 | break; | |
305 | case 8: | |
306 | abs = 2; | |
307 | break; | |
308 | case 0: | |
309 | abs = 1; | |
310 | break; | |
0a17cd59 AC |
311 | default: |
312 | goto fail; | |
c906108c SS |
313 | } |
314 | } | |
315 | else if (looking_for & L_8) | |
316 | { | |
317 | plen = 8; | |
318 | ||
319 | if (looking_for & PCREL) | |
320 | { | |
321 | abs = SEXTCHAR (data[len >> 1]); | |
322 | } | |
323 | else if (looking_for & ABS8MEM) | |
324 | { | |
325 | plen = 8; | |
326 | abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff; | |
0ef9643e | 327 | abs |= data[len >> 1] & 0xff; |
c906108c | 328 | } |
0ef9643e | 329 | else |
c906108c SS |
330 | { |
331 | abs = data[len >> 1] & 0xff; | |
332 | } | |
333 | } | |
334 | else if (looking_for & L_3) | |
335 | { | |
336 | plen = 3; | |
337 | ||
338 | bit = thisnib; | |
339 | } | |
340 | else if (looking_for == E) | |
341 | { | |
342 | dst->op = q; | |
343 | ||
0ef9643e | 344 | /* Fill in the args. */ |
c906108c SS |
345 | { |
346 | op_type *args = q->args.nib; | |
347 | int hadone = 0; | |
348 | ||
349 | while (*args != E) | |
350 | { | |
351 | int x = *args; | |
352 | int rn = (x & DST) ? rd : rs; | |
353 | ea_type *p; | |
354 | ||
355 | if (x & DST) | |
0ef9643e | 356 | p = &(dst->dst); |
c906108c | 357 | else |
0ef9643e | 358 | p = &(dst->src); |
c906108c | 359 | |
0ef9643e | 360 | if (x & L_3) |
c906108c SS |
361 | { |
362 | p->type = X (OP_IMM, size); | |
363 | p->literal = bit; | |
364 | } | |
365 | else if (x & (IMM | KBIT | DBIT)) | |
366 | { | |
367 | p->type = X (OP_IMM, size); | |
368 | p->literal = abs; | |
369 | } | |
370 | else if (x & REG) | |
371 | { | |
6d028502 KH |
372 | /* Reset the size. |
373 | Some ops (like mul) have two sizes. */ | |
c906108c SS |
374 | |
375 | size = bitfrom (x); | |
376 | p->type = X (OP_REG, size); | |
377 | p->reg = rn; | |
378 | } | |
379 | else if (x & INC) | |
380 | { | |
381 | p->type = X (OP_INC, size); | |
382 | p->reg = rn & 0x7; | |
383 | } | |
384 | else if (x & DEC) | |
385 | { | |
386 | p->type = X (OP_DEC, size); | |
387 | p->reg = rn & 0x7; | |
388 | } | |
389 | else if (x & IND) | |
390 | { | |
391 | p->type = X (OP_DISP, size); | |
392 | p->reg = rn & 0x7; | |
393 | p->literal = 0; | |
394 | } | |
395 | else if (x & (ABS | ABSJMP | ABS8MEM)) | |
396 | { | |
397 | p->type = X (OP_DISP, size); | |
398 | p->literal = abs; | |
399 | p->reg = 8; | |
400 | } | |
401 | else if (x & MEMIND) | |
402 | { | |
403 | p->type = X (OP_MEM, size); | |
404 | p->literal = abs; | |
405 | } | |
406 | else if (x & PCREL) | |
407 | { | |
408 | p->type = X (OP_PCREL, size); | |
409 | p->literal = abs + addr + 2; | |
410 | if (x & L_16) | |
411 | p->literal += 2; | |
412 | } | |
413 | else if (x & ABSJMP) | |
414 | { | |
415 | p->type = X (OP_IMM, SP); | |
416 | p->literal = abs; | |
417 | } | |
418 | else if (x & DISP) | |
419 | { | |
420 | p->type = X (OP_DISP, size); | |
421 | p->literal = abs; | |
422 | p->reg = rdisp & 0x7; | |
423 | } | |
424 | else if (x & CCR) | |
425 | { | |
426 | p->type = OP_CCR; | |
427 | } | |
fc974602 AV |
428 | else if (x & EXR) |
429 | { | |
430 | p->type = OP_EXR; | |
431 | } | |
c906108c SS |
432 | else |
433 | printf ("Hmmmm %x", x); | |
434 | ||
435 | args++; | |
436 | } | |
437 | } | |
438 | ||
0ef9643e JL |
439 | /* But a jmp or a jsr gets automagically lvalued, |
440 | since we branch to their address not their | |
441 | contents. */ | |
c906108c SS |
442 | if (q->how == O (O_JSR, SB) |
443 | || q->how == O (O_JMP, SB)) | |
444 | { | |
445 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
446 | } | |
447 | ||
448 | if (dst->dst.type == -1) | |
449 | dst->dst = dst->src; | |
450 | ||
451 | dst->opcode = q->how; | |
452 | dst->cycles = q->time; | |
453 | ||
0ef9643e | 454 | /* And a jsr to 0xc4 is turned into a magic trap. */ |
c906108c SS |
455 | |
456 | if (dst->opcode == O (O_JSR, SB)) | |
457 | { | |
458 | if (dst->src.literal == 0xc4) | |
459 | { | |
460 | dst->opcode = O (O_SYSCALL, SB); | |
461 | } | |
462 | } | |
463 | ||
464 | dst->next_pc = addr + len / 2; | |
465 | return; | |
466 | } | |
467 | else | |
98ecb0a7 | 468 | printf ("Don't understand %x \n", looking_for); |
c906108c SS |
469 | } |
470 | ||
471 | len++; | |
472 | nib++; | |
473 | } | |
474 | ||
475 | fail: | |
6d028502 | 476 | ; |
c906108c SS |
477 | } |
478 | ||
0ef9643e | 479 | /* Fell off the end. */ |
c906108c SS |
480 | dst->opcode = O (O_ILL, SB); |
481 | } | |
482 | ||
c906108c SS |
483 | static void |
484 | compile (pc) | |
485 | { | |
486 | int idx; | |
487 | ||
2ea716f6 | 488 | /* Find the next cache entry to use. */ |
c906108c SS |
489 | idx = cpu.cache_top + 1; |
490 | cpu.compiles++; | |
491 | if (idx >= cpu.csize) | |
492 | { | |
493 | idx = 1; | |
494 | } | |
495 | cpu.cache_top = idx; | |
496 | ||
2ea716f6 | 497 | /* Throw away its old meaning. */ |
c906108c SS |
498 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; |
499 | ||
2ea716f6 | 500 | /* Set to new address. */ |
c906108c SS |
501 | cpu.cache[idx].oldpc = pc; |
502 | ||
2ea716f6 | 503 | /* Fill in instruction info. */ |
c906108c SS |
504 | decode (pc, cpu.memory + pc, cpu.cache + idx); |
505 | ||
2ea716f6 | 506 | /* Point to new cache entry. */ |
c906108c SS |
507 | cpu.cache_idx[pc] = idx; |
508 | } | |
509 | ||
510 | ||
511 | static unsigned char *breg[18]; | |
512 | static unsigned short *wreg[18]; | |
513 | static unsigned int *lreg[18]; | |
514 | ||
515 | #define GET_B_REG(x) *(breg[x]) | |
516 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
517 | #define GET_W_REG(x) *(wreg[x]) | |
518 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
519 | ||
520 | #define GET_L_REG(x) *(lreg[x]) | |
521 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
522 | ||
523 | #define GET_MEMORY_L(x) \ | |
524 | (x < memory_size \ | |
525 | ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \ | |
526 | | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \ | |
527 | : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \ | |
528 | | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff])) | |
529 | ||
530 | #define GET_MEMORY_W(x) \ | |
531 | (x < memory_size \ | |
532 | ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \ | |
533 | : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0))) | |
534 | ||
535 | ||
536 | #define GET_MEMORY_B(x) \ | |
537 | (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff])) | |
538 | ||
539 | #define SET_MEMORY_L(x,y) \ | |
540 | { register unsigned char *_p; register int __y = y; \ | |
541 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
542 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; \ | |
543 | _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
544 | ||
545 | #define SET_MEMORY_W(x,y) \ | |
546 | { register unsigned char *_p; register int __y = y; \ | |
547 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
548 | _p[0] = (__y)>>8; _p[1] =(__y);} | |
549 | ||
550 | #define SET_MEMORY_B(x,y) \ | |
551 | (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y)) | |
552 | ||
553 | int | |
554 | fetch (arg, n) | |
555 | ea_type *arg; | |
556 | { | |
557 | int rn = arg->reg; | |
558 | int abs = arg->literal; | |
559 | int r; | |
560 | int t; | |
561 | ||
562 | switch (arg->type) | |
563 | { | |
564 | case X (OP_REG, SB): | |
565 | return GET_B_REG (rn); | |
566 | case X (OP_REG, SW): | |
567 | return GET_W_REG (rn); | |
568 | case X (OP_REG, SL): | |
569 | return GET_L_REG (rn); | |
570 | case X (OP_IMM, SB): | |
571 | case X (OP_IMM, SW): | |
572 | case X (OP_IMM, SL): | |
573 | return abs; | |
574 | case X (OP_DEC, SB): | |
575 | abort (); | |
576 | ||
577 | case X (OP_INC, SB): | |
578 | t = GET_L_REG (rn); | |
579 | t &= cpu.mask; | |
580 | r = GET_MEMORY_B (t); | |
581 | t++; | |
582 | t = t & cpu.mask; | |
583 | SET_L_REG (rn, t); | |
584 | return r; | |
585 | break; | |
586 | case X (OP_INC, SW): | |
587 | t = GET_L_REG (rn); | |
588 | t &= cpu.mask; | |
589 | r = GET_MEMORY_W (t); | |
590 | t += 2; | |
591 | t = t & cpu.mask; | |
592 | SET_L_REG (rn, t); | |
593 | return r; | |
594 | case X (OP_INC, SL): | |
595 | t = GET_L_REG (rn); | |
596 | t &= cpu.mask; | |
597 | r = GET_MEMORY_L (t); | |
598 | ||
599 | t += 4; | |
600 | t = t & cpu.mask; | |
601 | SET_L_REG (rn, t); | |
602 | return r; | |
603 | ||
604 | case X (OP_DISP, SB): | |
605 | t = GET_L_REG (rn) + abs; | |
606 | t &= cpu.mask; | |
607 | return GET_MEMORY_B (t); | |
608 | ||
609 | case X (OP_DISP, SW): | |
610 | t = GET_L_REG (rn) + abs; | |
611 | t &= cpu.mask; | |
612 | return GET_MEMORY_W (t); | |
613 | ||
614 | case X (OP_DISP, SL): | |
615 | t = GET_L_REG (rn) + abs; | |
616 | t &= cpu.mask; | |
617 | return GET_MEMORY_L (t); | |
618 | ||
619 | case X (OP_MEM, SL): | |
620 | t = GET_MEMORY_L (abs); | |
621 | t &= cpu.mask; | |
622 | return t; | |
623 | ||
624 | case X (OP_MEM, SW): | |
625 | t = GET_MEMORY_W (abs); | |
626 | t &= cpu.mask; | |
627 | return t; | |
628 | ||
629 | default: | |
3b02cf92 | 630 | abort (); /* ?? May be something more usefull? */ |
c906108c SS |
631 | |
632 | } | |
633 | } | |
634 | ||
635 | ||
de9b1892 | 636 | static void |
c906108c SS |
637 | store (arg, n) |
638 | ea_type *arg; | |
639 | int n; | |
640 | { | |
641 | int rn = arg->reg; | |
642 | int abs = arg->literal; | |
643 | int t; | |
644 | ||
645 | switch (arg->type) | |
646 | { | |
647 | case X (OP_REG, SB): | |
648 | SET_B_REG (rn, n); | |
649 | break; | |
650 | case X (OP_REG, SW): | |
651 | SET_W_REG (rn, n); | |
652 | break; | |
653 | case X (OP_REG, SL): | |
654 | SET_L_REG (rn, n); | |
655 | break; | |
656 | ||
657 | case X (OP_DEC, SB): | |
658 | t = GET_L_REG (rn) - 1; | |
659 | t &= cpu.mask; | |
660 | SET_L_REG (rn, t); | |
661 | SET_MEMORY_B (t, n); | |
662 | ||
663 | break; | |
664 | case X (OP_DEC, SW): | |
665 | t = (GET_L_REG (rn) - 2) & cpu.mask; | |
666 | SET_L_REG (rn, t); | |
667 | SET_MEMORY_W (t, n); | |
668 | break; | |
669 | ||
670 | case X (OP_DEC, SL): | |
671 | t = (GET_L_REG (rn) - 4) & cpu.mask; | |
672 | SET_L_REG (rn, t); | |
673 | SET_MEMORY_L (t, n); | |
674 | break; | |
675 | ||
676 | case X (OP_DISP, SB): | |
677 | t = GET_L_REG (rn) + abs; | |
678 | t &= cpu.mask; | |
679 | SET_MEMORY_B (t, n); | |
680 | break; | |
681 | ||
682 | case X (OP_DISP, SW): | |
683 | t = GET_L_REG (rn) + abs; | |
684 | t &= cpu.mask; | |
685 | SET_MEMORY_W (t, n); | |
686 | break; | |
687 | ||
688 | case X (OP_DISP, SL): | |
689 | t = GET_L_REG (rn) + abs; | |
690 | t &= cpu.mask; | |
691 | SET_MEMORY_L (t, n); | |
692 | break; | |
693 | default: | |
694 | abort (); | |
695 | } | |
696 | } | |
697 | ||
698 | ||
699 | static union | |
700 | { | |
701 | short int i; | |
702 | struct | |
703 | { | |
704 | char low; | |
705 | char high; | |
706 | } | |
707 | u; | |
708 | } | |
709 | ||
710 | littleendian; | |
711 | ||
de9b1892 | 712 | static void |
c906108c SS |
713 | init_pointers () |
714 | { | |
715 | static int init; | |
716 | ||
717 | if (!init) | |
718 | { | |
719 | int i; | |
720 | ||
721 | init = 1; | |
722 | littleendian.i = 1; | |
723 | ||
a8cdafbd AV |
724 | if (h8300smode) |
725 | memory_size = H8300S_MSIZE; | |
726 | else if (h8300hmode) | |
c906108c SS |
727 | memory_size = H8300H_MSIZE; |
728 | else | |
729 | memory_size = H8300_MSIZE; | |
730 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
731 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
732 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
733 | ||
2ea716f6 | 734 | /* `msize' must be a power of two. */ |
c906108c SS |
735 | if ((memory_size & (memory_size - 1)) != 0) |
736 | abort (); | |
737 | cpu.mask = memory_size - 1; | |
738 | ||
739 | for (i = 0; i < 9; i++) | |
740 | { | |
741 | cpu.regs[i] = 0; | |
742 | } | |
743 | ||
744 | for (i = 0; i < 8; i++) | |
745 | { | |
746 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
747 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
748 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
749 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
750 | cpu.regs[i] = 0x00112233; | |
751 | while (p < e) | |
752 | { | |
753 | if (*p == 0x22) | |
754 | { | |
755 | breg[i] = p; | |
756 | } | |
757 | if (*p == 0x33) | |
758 | { | |
759 | breg[i + 8] = p; | |
760 | } | |
761 | p++; | |
762 | } | |
763 | while (q < u) | |
764 | { | |
765 | if (*q == 0x2233) | |
766 | { | |
767 | wreg[i] = q; | |
768 | } | |
769 | if (*q == 0x0011) | |
770 | { | |
771 | wreg[i + 8] = q; | |
772 | } | |
773 | q++; | |
774 | } | |
775 | cpu.regs[i] = 0; | |
776 | lreg[i] = &cpu.regs[i]; | |
777 | } | |
778 | ||
779 | lreg[8] = &cpu.regs[8]; | |
780 | ||
2ea716f6 | 781 | /* Initialize the seg registers. */ |
c906108c SS |
782 | if (!cpu.cache) |
783 | sim_set_simcache_size (CSIZE); | |
784 | } | |
785 | } | |
786 | ||
787 | static void | |
788 | control_c (sig, code, scp, addr) | |
789 | int sig; | |
790 | int code; | |
791 | char *scp; | |
792 | char *addr; | |
793 | { | |
794 | cpu.state = SIM_STATE_STOPPED; | |
795 | cpu.exception = SIGINT; | |
796 | } | |
797 | ||
798 | #define C (c != 0) | |
799 | #define Z (nz == 0) | |
800 | #define V (v != 0) | |
801 | #define N (n != 0) | |
f6225c96 AV |
802 | #define U (u != 0) |
803 | #define H (h != 0) | |
804 | #define UI (ui != 0) | |
805 | #define I (intMaskBit != 0) | |
c906108c SS |
806 | |
807 | static int | |
808 | mop (code, bsize, sign) | |
809 | decoded_inst *code; | |
810 | int bsize; | |
811 | int sign; | |
812 | { | |
813 | int multiplier; | |
814 | int multiplicand; | |
815 | int result; | |
816 | int n, nz; | |
817 | ||
818 | if (sign) | |
819 | { | |
820 | multiplicand = | |
821 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
822 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
823 | multiplier = | |
824 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
825 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
826 | } | |
827 | else | |
828 | { | |
829 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
830 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
831 | multiplier = | |
832 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
833 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
834 | ||
835 | } | |
836 | result = multiplier * multiplicand; | |
837 | ||
838 | if (sign) | |
839 | { | |
840 | n = result & (bsize ? 0x8000 : 0x80000000); | |
841 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
842 | } | |
843 | if (bsize) | |
844 | { | |
845 | SET_W_REG (code->dst.reg, result); | |
846 | } | |
847 | else | |
848 | { | |
849 | SET_L_REG (code->dst.reg, result); | |
850 | } | |
de9b1892 KH |
851 | #if 0 |
852 | return ((n == 1) << 1) | (nz == 1); | |
853 | #endif | |
c906108c SS |
854 | } |
855 | ||
856 | #define ONOT(name, how) \ | |
d1335144 | 857 | case O (name, SB): \ |
c906108c SS |
858 | { \ |
859 | int t; \ | |
860 | int hm = 0x80; \ | |
861 | rd = GET_B_REG (code->src.reg); \ | |
862 | how; \ | |
863 | goto shift8; \ | |
864 | } \ | |
d1335144 | 865 | case O (name, SW): \ |
c906108c SS |
866 | { \ |
867 | int t; \ | |
868 | int hm = 0x8000; \ | |
869 | rd = GET_W_REG (code->src.reg); \ | |
870 | how; \ | |
871 | goto shift16; \ | |
872 | } \ | |
d1335144 | 873 | case O (name, SL): \ |
c906108c SS |
874 | { \ |
875 | int t; \ | |
876 | int hm = 0x80000000; \ | |
877 | rd = GET_L_REG (code->src.reg); \ | |
878 | how; \ | |
879 | goto shift32; \ | |
880 | } | |
881 | ||
882 | #define OSHIFTS(name, how1, how2) \ | |
d1335144 | 883 | case O (name, SB): \ |
c906108c SS |
884 | { \ |
885 | int t; \ | |
886 | int hm = 0x80; \ | |
887 | rd = GET_B_REG (code->src.reg); \ | |
888 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
889 | { \ | |
890 | how1; \ | |
891 | } \ | |
892 | else \ | |
893 | { \ | |
894 | how2; \ | |
895 | } \ | |
896 | goto shift8; \ | |
897 | } \ | |
d1335144 | 898 | case O (name, SW): \ |
c906108c SS |
899 | { \ |
900 | int t; \ | |
901 | int hm = 0x8000; \ | |
902 | rd = GET_W_REG (code->src.reg); \ | |
903 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
904 | { \ | |
905 | how1; \ | |
906 | } \ | |
907 | else \ | |
908 | { \ | |
909 | how2; \ | |
910 | } \ | |
911 | goto shift16; \ | |
912 | } \ | |
d1335144 | 913 | case O (name, SL): \ |
c906108c SS |
914 | { \ |
915 | int t; \ | |
916 | int hm = 0x80000000; \ | |
917 | rd = GET_L_REG (code->src.reg); \ | |
918 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
919 | { \ | |
920 | how1; \ | |
921 | } \ | |
922 | else \ | |
923 | { \ | |
924 | how2; \ | |
925 | } \ | |
926 | goto shift32; \ | |
927 | } | |
928 | ||
929 | #define OBITOP(name,f, s, op) \ | |
d1335144 | 930 | case O (name, SB): \ |
c906108c SS |
931 | { \ |
932 | int m; \ | |
933 | int b; \ | |
934 | if (f) ea = fetch (&code->dst); \ | |
d1335144 | 935 | m=1<< fetch (&code->src); \ |
c906108c | 936 | op; \ |
d1335144 | 937 | if (s) store (&code->dst,ea); goto next; \ |
c906108c SS |
938 | } |
939 | ||
940 | int | |
941 | sim_stop (sd) | |
942 | SIM_DESC sd; | |
943 | { | |
944 | cpu.state = SIM_STATE_STOPPED; | |
945 | cpu.exception = SIGINT; | |
946 | return 1; | |
947 | } | |
948 | ||
6147b1f6 AV |
949 | #define R0_REGNUM 0 |
950 | #define R1_REGNUM 1 | |
951 | #define R2_REGNUM 2 | |
952 | #define R3_REGNUM 3 | |
953 | #define R4_REGNUM 4 | |
954 | #define R5_REGNUM 5 | |
955 | #define R6_REGNUM 6 | |
956 | #define R7_REGNUM 7 | |
957 | ||
958 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
959 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
960 | * stack frame */ | |
961 | ||
962 | #define CCR_REGNUM 8 /* Contains processor status */ | |
963 | #define PC_REGNUM 9 /* Contains program counter */ | |
964 | ||
965 | #define CYCLE_REGNUM 10 | |
966 | ||
967 | #define EXR_REGNUM 11 | |
968 | #define INST_REGNUM 12 | |
969 | #define TICK_REGNUM 13 | |
970 | ||
c906108c SS |
971 | void |
972 | sim_resume (sd, step, siggnal) | |
973 | SIM_DESC sd; | |
974 | { | |
975 | static int init1; | |
976 | int cycles = 0; | |
977 | int insts = 0; | |
978 | int tick_start = get_now (); | |
979 | void (*prev) (); | |
980 | int poll_count = 0; | |
981 | int res; | |
982 | int tmp; | |
983 | int rd; | |
984 | int ea; | |
985 | int bit; | |
986 | int pc; | |
f6225c96 | 987 | int c, nz, v, n, u, h, ui, intMaskBit; |
fc974602 | 988 | int trace, intMask; |
c906108c SS |
989 | int oldmask; |
990 | init_pointers (); | |
991 | ||
992 | prev = signal (SIGINT, control_c); | |
993 | ||
994 | if (step) | |
995 | { | |
996 | cpu.state = SIM_STATE_STOPPED; | |
997 | cpu.exception = SIGTRAP; | |
998 | } | |
999 | else | |
1000 | { | |
1001 | cpu.state = SIM_STATE_RUNNING; | |
1002 | cpu.exception = 0; | |
1003 | } | |
1004 | ||
1005 | pc = cpu.pc; | |
1006 | ||
1007 | /* The PC should never be odd. */ | |
1008 | if (pc & 0x1) | |
1009 | abort (); | |
1010 | ||
1011 | GETSR (); | |
fc974602 AV |
1012 | GETEXR (); |
1013 | ||
c906108c SS |
1014 | oldmask = cpu.mask; |
1015 | if (!h8300hmode) | |
1016 | cpu.mask = 0xffff; | |
1017 | do | |
1018 | { | |
1019 | int cidx; | |
1020 | decoded_inst *code; | |
1021 | ||
1022 | top: | |
1023 | cidx = cpu.cache_idx[pc]; | |
1024 | code = cpu.cache + cidx; | |
1025 | ||
1026 | ||
1027 | #define ALUOP(STORE, NAME, HOW) \ | |
d0fe2f7e KH |
1028 | case O (NAME, SB): HOW; if (STORE) goto alu8; else goto just_flags_alu8; \ |
1029 | case O (NAME, SW): HOW; if (STORE) goto alu16; else goto just_flags_alu16; \ | |
1030 | case O (NAME, SL): HOW; if (STORE) goto alu32; else goto just_flags_alu32; | |
c906108c SS |
1031 | |
1032 | ||
d0fe2f7e KH |
1033 | #define LOGOP(NAME, HOW) \ |
1034 | case O (NAME, SB): HOW; goto log8; \ | |
1035 | case O (NAME, SW): HOW; goto log16; \ | |
1036 | case O (NAME, SL): HOW; goto log32; | |
c906108c SS |
1037 | |
1038 | ||
1039 | ||
1040 | #if ADEBUG | |
1041 | if (debug) | |
1042 | { | |
1043 | printf ("%x %d %s\n", pc, code->opcode, | |
1044 | code->op ? code->op->name : "**"); | |
1045 | } | |
1046 | cpu.stats[code->opcode]++; | |
1047 | ||
1048 | #endif | |
1049 | ||
3b02cf92 | 1050 | if (code->opcode) |
c3f4437e KH |
1051 | { |
1052 | cycles += code->cycles; | |
1053 | insts++; | |
1054 | } | |
3b02cf92 | 1055 | |
c906108c SS |
1056 | switch (code->opcode) |
1057 | { | |
1058 | case 0: | |
1059 | /* | |
1060 | * This opcode is a fake for when we get to an | |
1061 | * instruction which hasnt been compiled | |
1062 | */ | |
1063 | compile (pc); | |
1064 | goto top; | |
1065 | break; | |
1066 | ||
1067 | ||
1068 | case O (O_SUBX, SB): | |
1069 | rd = fetch (&code->dst); | |
1070 | ea = fetch (&code->src); | |
1071 | ea = -(ea + C); | |
1072 | res = rd + ea; | |
1073 | goto alu8; | |
1074 | ||
1075 | case O (O_ADDX, SB): | |
1076 | rd = fetch (&code->dst); | |
1077 | ea = fetch (&code->src); | |
1078 | ea = C + ea; | |
1079 | res = rd + ea; | |
1080 | goto alu8; | |
1081 | ||
d1335144 KH |
1082 | #define EA ea = fetch (&code->src); |
1083 | #define RD_EA ea = fetch (&code->src); rd = fetch (&code->dst); | |
c906108c SS |
1084 | |
1085 | ALUOP (1, O_SUB, RD_EA; | |
1086 | ea = -ea; | |
1087 | res = rd + ea); | |
1088 | ALUOP (1, O_NEG, EA; | |
1089 | ea = -ea; | |
1090 | rd = 0; | |
1091 | res = rd + ea); | |
1092 | ||
1093 | case O (O_ADD, SB): | |
1094 | rd = GET_B_REG (code->dst.reg); | |
1095 | ea = fetch (&code->src); | |
1096 | res = rd + ea; | |
1097 | goto alu8; | |
1098 | case O (O_ADD, SW): | |
1099 | rd = GET_W_REG (code->dst.reg); | |
1100 | ea = fetch (&code->src); | |
1101 | res = rd + ea; | |
1102 | goto alu16; | |
1103 | case O (O_ADD, SL): | |
1104 | rd = GET_L_REG (code->dst.reg); | |
1105 | ea = fetch (&code->src); | |
1106 | res = rd + ea; | |
1107 | goto alu32; | |
1108 | ||
1109 | ||
1110 | LOGOP (O_AND, RD_EA; | |
1111 | res = rd & ea); | |
1112 | ||
1113 | LOGOP (O_OR, RD_EA; | |
1114 | res = rd | ea); | |
1115 | ||
1116 | LOGOP (O_XOR, RD_EA; | |
1117 | res = rd ^ ea); | |
1118 | ||
1119 | ||
1120 | case O (O_MOV_TO_MEM, SB): | |
1121 | res = GET_B_REG (code->src.reg); | |
1122 | goto log8; | |
1123 | case O (O_MOV_TO_MEM, SW): | |
1124 | res = GET_W_REG (code->src.reg); | |
1125 | goto log16; | |
1126 | case O (O_MOV_TO_MEM, SL): | |
1127 | res = GET_L_REG (code->src.reg); | |
1128 | goto log32; | |
1129 | ||
1130 | ||
1131 | case O (O_MOV_TO_REG, SB): | |
1132 | res = fetch (&code->src); | |
1133 | SET_B_REG (code->dst.reg, res); | |
1134 | goto just_flags_log8; | |
1135 | case O (O_MOV_TO_REG, SW): | |
1136 | res = fetch (&code->src); | |
1137 | SET_W_REG (code->dst.reg, res); | |
1138 | goto just_flags_log16; | |
1139 | case O (O_MOV_TO_REG, SL): | |
1140 | res = fetch (&code->src); | |
1141 | SET_L_REG (code->dst.reg, res); | |
1142 | goto just_flags_log32; | |
1143 | ||
6147b1f6 AV |
1144 | case O (O_EEPMOV, SB): |
1145 | case O (O_EEPMOV, SW): | |
d0fe2f7e | 1146 | if (h8300hmode || h8300smode) |
c3f4437e | 1147 | { |
d0fe2f7e KH |
1148 | register unsigned char *_src, *_dst; |
1149 | unsigned int count = ((code->opcode == O (O_EEPMOV, SW)) | |
1150 | ? cpu.regs[R4_REGNUM] & 0xffff | |
1151 | : cpu.regs[R4_REGNUM] & 0xff); | |
1152 | ||
1153 | _src = (cpu.regs[R5_REGNUM] < memory_size | |
1154 | ? cpu.memory + cpu.regs[R5_REGNUM] | |
1155 | : cpu.eightbit + (cpu.regs[R5_REGNUM] & 0xff)); | |
1156 | if ((_src + count) >= (cpu.memory + memory_size)) | |
c3f4437e | 1157 | { |
d0fe2f7e | 1158 | if ((_src + count) >= (cpu.eightbit + 0x100)) |
c3f4437e KH |
1159 | goto illegal; |
1160 | } | |
d0fe2f7e KH |
1161 | _dst = (cpu.regs[R6_REGNUM] < memory_size |
1162 | ? cpu.memory + cpu.regs[R6_REGNUM] | |
1163 | : cpu.eightbit + (cpu.regs[R6_REGNUM] & 0xff)); | |
1164 | if ((_dst + count) >= (cpu.memory + memory_size)) | |
c3f4437e | 1165 | { |
d0fe2f7e | 1166 | if ((_dst + count) >= (cpu.eightbit + 0x100)) |
c3f4437e KH |
1167 | goto illegal; |
1168 | } | |
d0fe2f7e | 1169 | memcpy (_dst, _src, count); |
c3f4437e | 1170 | |
d0fe2f7e KH |
1171 | cpu.regs[R5_REGNUM] += count; |
1172 | cpu.regs[R6_REGNUM] += count; | |
1173 | cpu.regs[R4_REGNUM] &= ((code->opcode == O (O_EEPMOV, SW)) | |
1174 | ? (~0xffff) : (~0xff)); | |
1175 | cycles += 2 * count; | |
c3f4437e KH |
1176 | goto next; |
1177 | } | |
1178 | goto illegal; | |
c906108c SS |
1179 | |
1180 | case O (O_ADDS, SL): | |
1181 | SET_L_REG (code->dst.reg, | |
1182 | GET_L_REG (code->dst.reg) | |
1183 | + code->src.literal); | |
1184 | ||
1185 | goto next; | |
1186 | ||
1187 | case O (O_SUBS, SL): | |
1188 | SET_L_REG (code->dst.reg, | |
1189 | GET_L_REG (code->dst.reg) | |
1190 | - code->src.literal); | |
1191 | goto next; | |
1192 | ||
1193 | case O (O_CMP, SB): | |
1194 | rd = fetch (&code->dst); | |
1195 | ea = fetch (&code->src); | |
1196 | ea = -ea; | |
1197 | res = rd + ea; | |
1198 | goto just_flags_alu8; | |
1199 | ||
1200 | case O (O_CMP, SW): | |
1201 | rd = fetch (&code->dst); | |
1202 | ea = fetch (&code->src); | |
1203 | ea = -ea; | |
1204 | res = rd + ea; | |
1205 | goto just_flags_alu16; | |
1206 | ||
1207 | case O (O_CMP, SL): | |
1208 | rd = fetch (&code->dst); | |
1209 | ea = fetch (&code->src); | |
1210 | ea = -ea; | |
1211 | res = rd + ea; | |
1212 | goto just_flags_alu32; | |
1213 | ||
1214 | ||
1215 | case O (O_DEC, SB): | |
1216 | rd = GET_B_REG (code->src.reg); | |
1217 | ea = -1; | |
1218 | res = rd + ea; | |
1219 | SET_B_REG (code->src.reg, res); | |
1220 | goto just_flags_inc8; | |
1221 | ||
1222 | case O (O_DEC, SW): | |
1223 | rd = GET_W_REG (code->dst.reg); | |
1224 | ea = -code->src.literal; | |
1225 | res = rd + ea; | |
1226 | SET_W_REG (code->dst.reg, res); | |
1227 | goto just_flags_inc16; | |
1228 | ||
1229 | case O (O_DEC, SL): | |
1230 | rd = GET_L_REG (code->dst.reg); | |
1231 | ea = -code->src.literal; | |
1232 | res = rd + ea; | |
1233 | SET_L_REG (code->dst.reg, res); | |
1234 | goto just_flags_inc32; | |
1235 | ||
1236 | ||
1237 | case O (O_INC, SB): | |
1238 | rd = GET_B_REG (code->src.reg); | |
1239 | ea = 1; | |
1240 | res = rd + ea; | |
1241 | SET_B_REG (code->src.reg, res); | |
1242 | goto just_flags_inc8; | |
1243 | ||
1244 | case O (O_INC, SW): | |
1245 | rd = GET_W_REG (code->dst.reg); | |
1246 | ea = code->src.literal; | |
1247 | res = rd + ea; | |
1248 | SET_W_REG (code->dst.reg, res); | |
1249 | goto just_flags_inc16; | |
1250 | ||
1251 | case O (O_INC, SL): | |
1252 | rd = GET_L_REG (code->dst.reg); | |
1253 | ea = code->src.literal; | |
1254 | res = rd + ea; | |
1255 | SET_L_REG (code->dst.reg, res); | |
1256 | goto just_flags_inc32; | |
1257 | ||
c906108c | 1258 | #define GET_CCR(x) BUILDSR();x = cpu.ccr |
d1335144 | 1259 | #define GET_EXR(x) BUILDEXR ();x = cpu.exr |
c906108c | 1260 | |
6147b1f6 AV |
1261 | case O (O_LDC, SB): |
1262 | case O (O_LDC, SW): | |
d1335144 | 1263 | res = fetch (&code->src); |
6147b1f6 AV |
1264 | goto setc; |
1265 | case O (O_STC, SB): | |
1266 | case O (O_STC, SW): | |
d1335144 | 1267 | if (code->src.type == OP_CCR) |
c3f4437e | 1268 | { |
d1335144 | 1269 | GET_CCR (res); |
c3f4437e | 1270 | } |
d1335144 | 1271 | else if (code->src.type == OP_EXR && h8300smode) |
c3f4437e | 1272 | { |
d1335144 | 1273 | GET_EXR (res); |
c3f4437e KH |
1274 | } |
1275 | else | |
6147b1f6 AV |
1276 | goto illegal; |
1277 | store (&code->dst, res); | |
1278 | goto next; | |
1279 | ||
c906108c | 1280 | case O (O_ANDC, SB): |
d1335144 | 1281 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1282 | { |
1283 | GET_CCR (rd); | |
1284 | } | |
d1335144 | 1285 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1286 | { |
1287 | GET_EXR (rd); | |
1288 | } | |
1289 | else | |
fc974602 | 1290 | goto illegal; |
c906108c SS |
1291 | ea = code->src.literal; |
1292 | res = rd & ea; | |
1293 | goto setc; | |
1294 | ||
1295 | case O (O_ORC, SB): | |
d1335144 | 1296 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1297 | { |
1298 | GET_CCR (rd); | |
1299 | } | |
d1335144 | 1300 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1301 | { |
1302 | GET_EXR (rd); | |
1303 | } | |
1304 | else | |
fc974602 | 1305 | goto illegal; |
c906108c SS |
1306 | ea = code->src.literal; |
1307 | res = rd | ea; | |
1308 | goto setc; | |
1309 | ||
1310 | case O (O_XORC, SB): | |
d1335144 | 1311 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1312 | { |
1313 | GET_CCR (rd); | |
1314 | } | |
d1335144 | 1315 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1316 | { |
1317 | GET_EXR (rd); | |
1318 | } | |
1319 | else | |
fc974602 | 1320 | goto illegal; |
c906108c SS |
1321 | ea = code->src.literal; |
1322 | res = rd ^ ea; | |
1323 | goto setc; | |
1324 | ||
1325 | ||
1326 | case O (O_BRA, SB): | |
1327 | if (1) | |
1328 | goto condtrue; | |
1329 | goto next; | |
1330 | ||
1331 | case O (O_BRN, SB): | |
1332 | if (0) | |
1333 | goto condtrue; | |
1334 | goto next; | |
1335 | ||
1336 | case O (O_BHI, SB): | |
1337 | if ((C || Z) == 0) | |
1338 | goto condtrue; | |
1339 | goto next; | |
1340 | ||
1341 | ||
1342 | case O (O_BLS, SB): | |
1343 | if ((C || Z)) | |
1344 | goto condtrue; | |
1345 | goto next; | |
1346 | ||
1347 | case O (O_BCS, SB): | |
1348 | if ((C == 1)) | |
1349 | goto condtrue; | |
1350 | goto next; | |
1351 | ||
1352 | case O (O_BCC, SB): | |
1353 | if ((C == 0)) | |
1354 | goto condtrue; | |
1355 | goto next; | |
1356 | ||
1357 | case O (O_BEQ, SB): | |
1358 | if (Z) | |
1359 | goto condtrue; | |
1360 | goto next; | |
1361 | case O (O_BGT, SB): | |
1362 | if (((Z || (N ^ V)) == 0)) | |
1363 | goto condtrue; | |
1364 | goto next; | |
1365 | ||
1366 | ||
1367 | case O (O_BLE, SB): | |
1368 | if (((Z || (N ^ V)) == 1)) | |
1369 | goto condtrue; | |
1370 | goto next; | |
1371 | ||
1372 | case O (O_BGE, SB): | |
1373 | if ((N ^ V) == 0) | |
1374 | goto condtrue; | |
1375 | goto next; | |
1376 | case O (O_BLT, SB): | |
1377 | if ((N ^ V)) | |
1378 | goto condtrue; | |
1379 | goto next; | |
1380 | case O (O_BMI, SB): | |
1381 | if ((N)) | |
1382 | goto condtrue; | |
1383 | goto next; | |
1384 | case O (O_BNE, SB): | |
1385 | if ((Z == 0)) | |
1386 | goto condtrue; | |
1387 | goto next; | |
1388 | ||
1389 | case O (O_BPL, SB): | |
1390 | if (N == 0) | |
1391 | goto condtrue; | |
1392 | goto next; | |
1393 | case O (O_BVC, SB): | |
1394 | if ((V == 0)) | |
1395 | goto condtrue; | |
1396 | goto next; | |
1397 | case O (O_BVS, SB): | |
1398 | if ((V == 1)) | |
1399 | goto condtrue; | |
1400 | goto next; | |
1401 | ||
1402 | case O (O_SYSCALL, SB): | |
1403 | { | |
1404 | char c = cpu.regs[2]; | |
1405 | sim_callback->write_stdout (sim_callback, &c, 1); | |
1406 | } | |
1407 | goto next; | |
1408 | ||
1409 | ONOT (O_NOT, rd = ~rd; v = 0;); | |
1410 | OSHIFTS (O_SHLL, | |
1411 | c = rd & hm; v = 0; rd <<= 1, | |
1412 | c = rd & (hm >> 1); v = 0; rd <<= 2); | |
1413 | OSHIFTS (O_SHLR, | |
1414 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1, | |
1415 | c = rd & 2; v = 0; rd = (unsigned int) rd >> 2); | |
1416 | OSHIFTS (O_SHAL, | |
1417 | c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1, | |
1418 | c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2); | |
1419 | OSHIFTS (O_SHAR, | |
1420 | t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t, | |
d1335144 | 1421 | t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1); |
c906108c SS |
1422 | OSHIFTS (O_ROTL, |
1423 | c = rd & hm; v = 0; rd <<= 1; rd |= C, | |
1424 | c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C); | |
1425 | OSHIFTS (O_ROTR, | |
1426 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm, | |
1427 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm); | |
1428 | OSHIFTS (O_ROTXL, | |
1429 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0, | |
1430 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t); | |
1431 | OSHIFTS (O_ROTXR, | |
1432 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0, | |
1433 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t); | |
1434 | ||
1435 | case O (O_JMP, SB): | |
1436 | { | |
1437 | pc = fetch (&code->src); | |
1438 | goto end; | |
1439 | ||
1440 | } | |
1441 | ||
1442 | case O (O_JSR, SB): | |
1443 | { | |
1444 | int tmp; | |
1445 | pc = fetch (&code->src); | |
1446 | call: | |
1447 | tmp = cpu.regs[7]; | |
1448 | ||
1449 | if (h8300hmode) | |
1450 | { | |
1451 | tmp -= 4; | |
1452 | SET_MEMORY_L (tmp, code->next_pc); | |
1453 | } | |
1454 | else | |
1455 | { | |
1456 | tmp -= 2; | |
1457 | SET_MEMORY_W (tmp, code->next_pc); | |
1458 | } | |
1459 | cpu.regs[7] = tmp; | |
1460 | ||
1461 | goto end; | |
1462 | } | |
1463 | case O (O_BSR, SB): | |
1464 | pc = code->src.literal; | |
1465 | goto call; | |
1466 | ||
1467 | case O (O_RTS, SN): | |
1468 | { | |
1469 | int tmp; | |
1470 | ||
1471 | tmp = cpu.regs[7]; | |
1472 | ||
1473 | if (h8300hmode) | |
1474 | { | |
1475 | pc = GET_MEMORY_L (tmp); | |
1476 | tmp += 4; | |
1477 | } | |
1478 | else | |
1479 | { | |
1480 | pc = GET_MEMORY_W (tmp); | |
1481 | tmp += 2; | |
1482 | } | |
1483 | ||
1484 | cpu.regs[7] = tmp; | |
1485 | goto end; | |
1486 | } | |
1487 | ||
1488 | case O (O_ILL, SB): | |
1489 | cpu.state = SIM_STATE_STOPPED; | |
1490 | cpu.exception = SIGILL; | |
1491 | goto end; | |
1492 | case O (O_SLEEP, SN): | |
c906108c SS |
1493 | /* FIXME: Doesn't this break for breakpoints when r0 |
1494 | contains just the right (er, wrong) value? */ | |
1495 | cpu.state = SIM_STATE_STOPPED; | |
97ee9e5a FCE |
1496 | /* The format of r0 is defined by target newlib. Expand |
1497 | the macros here instead of looking for .../sys/wait.h. */ | |
1498 | #define SIM_WIFEXITED(v) (((v) & 0xff) == 0) | |
1499 | #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f)) | |
c3f4437e | 1500 | if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0])) |
c906108c SS |
1501 | cpu.exception = SIGILL; |
1502 | else | |
1503 | cpu.exception = SIGTRAP; | |
c906108c SS |
1504 | goto end; |
1505 | case O (O_BPT, SN): | |
1506 | cpu.state = SIM_STATE_STOPPED; | |
1507 | cpu.exception = SIGTRAP; | |
1508 | goto end; | |
1509 | ||
1510 | OBITOP (O_BNOT, 1, 1, ea ^= m); | |
1511 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1512 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
c3f4437e | 1513 | OBITOP (O_BSET, 1, 1, ea |= m); |
c906108c SS |
1514 | OBITOP (O_BLD, 1, 0, c = ea & m); |
1515 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1516 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1517 | if (C) ea |= m); | |
1518 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1519 | if (!C) ea |= m); | |
1520 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1521 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1522 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1523 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
1524 | OBITOP (O_BXOR, 1, 0, c = (ea & m) != C); | |
1525 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); | |
1526 | ||
de9b1892 KH |
1527 | #define MOP(bsize, signed) \ |
1528 | mop (code, bsize, signed); \ | |
1529 | goto next; | |
c906108c SS |
1530 | |
1531 | case O (O_MULS, SB): | |
1532 | MOP (1, 1); | |
1533 | break; | |
1534 | case O (O_MULS, SW): | |
1535 | MOP (0, 1); | |
1536 | break; | |
1537 | case O (O_MULU, SB): | |
1538 | MOP (1, 0); | |
1539 | break; | |
1540 | case O (O_MULU, SW): | |
1541 | MOP (0, 0); | |
1542 | break; | |
1543 | ||
6147b1f6 | 1544 | case O (O_TAS, SB): |
d1335144 | 1545 | if (!h8300smode || code->src.type != X (OP_REG, SL)) |
c3f4437e | 1546 | goto illegal; |
d1335144 | 1547 | switch (code->src.reg) |
c3f4437e KH |
1548 | { |
1549 | case R0_REGNUM: | |
1550 | case R1_REGNUM: | |
1551 | case R4_REGNUM: | |
1552 | case R5_REGNUM: | |
1553 | break; | |
1554 | default: | |
1555 | goto illegal; | |
1556 | } | |
1557 | res = fetch (&code->src); | |
d0fe2f7e | 1558 | store (&code->src, res | 0x80); |
6147b1f6 | 1559 | goto just_flags_log8; |
c906108c SS |
1560 | |
1561 | case O (O_DIVU, SB): | |
1562 | { | |
1563 | rd = GET_W_REG (code->dst.reg); | |
1564 | ea = GET_B_REG (code->src.reg); | |
1565 | if (ea) | |
1566 | { | |
de9b1892 KH |
1567 | tmp = (unsigned) rd % ea; |
1568 | rd = (unsigned) rd / ea; | |
c906108c SS |
1569 | } |
1570 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1571 | n = ea & 0x80; | |
1572 | nz = ea & 0xff; | |
1573 | ||
1574 | goto next; | |
1575 | } | |
1576 | case O (O_DIVU, SW): | |
1577 | { | |
1578 | rd = GET_L_REG (code->dst.reg); | |
1579 | ea = GET_W_REG (code->src.reg); | |
1580 | n = ea & 0x8000; | |
1581 | nz = ea & 0xffff; | |
1582 | if (ea) | |
1583 | { | |
de9b1892 KH |
1584 | tmp = (unsigned) rd % ea; |
1585 | rd = (unsigned) rd / ea; | |
c906108c SS |
1586 | } |
1587 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1588 | goto next; | |
1589 | } | |
1590 | ||
1591 | case O (O_DIVS, SB): | |
1592 | { | |
1593 | ||
1594 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); | |
1595 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1596 | if (ea) | |
1597 | { | |
1598 | tmp = (int) rd % (int) ea; | |
1599 | rd = (int) rd / (int) ea; | |
1600 | n = rd & 0x8000; | |
1601 | nz = 1; | |
1602 | } | |
1603 | else | |
1604 | nz = 0; | |
1605 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1606 | goto next; | |
1607 | } | |
1608 | case O (O_DIVS, SW): | |
1609 | { | |
1610 | rd = GET_L_REG (code->dst.reg); | |
1611 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1612 | if (ea) | |
1613 | { | |
1614 | tmp = (int) rd % (int) ea; | |
1615 | rd = (int) rd / (int) ea; | |
1616 | n = rd & 0x80000000; | |
1617 | nz = 1; | |
1618 | } | |
1619 | else | |
1620 | nz = 0; | |
1621 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1622 | goto next; | |
1623 | } | |
1624 | case O (O_EXTS, SW): | |
1625 | rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */ | |
1626 | ea = rd & 0x80 ? -256 : 0; | |
1627 | res = rd + ea; | |
1628 | goto log16; | |
1629 | case O (O_EXTS, SL): | |
1630 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1631 | ea = rd & 0x8000 ? -65536 : 0; | |
1632 | res = rd + ea; | |
1633 | goto log32; | |
1634 | case O (O_EXTU, SW): | |
1635 | rd = GET_B_REG (code->src.reg + 8) & 0xff; | |
1636 | ea = 0; | |
1637 | res = rd + ea; | |
1638 | goto log16; | |
1639 | case O (O_EXTU, SL): | |
1640 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1641 | ea = 0; | |
1642 | res = rd + ea; | |
1643 | goto log32; | |
1644 | ||
1645 | case O (O_NOP, SN): | |
1646 | goto next; | |
1647 | ||
1648 | case O (O_STM, SL): | |
1649 | { | |
1650 | int nregs, firstreg, i; | |
1651 | ||
1652 | nregs = GET_MEMORY_B (pc + 1); | |
1653 | nregs >>= 4; | |
1654 | nregs &= 0xf; | |
1655 | firstreg = GET_MEMORY_B (pc + 3); | |
1656 | firstreg &= 0xf; | |
1657 | for (i = firstreg; i <= firstreg + nregs; i++) | |
1658 | { | |
1659 | cpu.regs[7] -= 4; | |
1660 | SET_MEMORY_L (cpu.regs[7], cpu.regs[i]); | |
1661 | } | |
1662 | } | |
1663 | goto next; | |
1664 | ||
1665 | case O (O_LDM, SL): | |
1666 | { | |
1667 | int nregs, firstreg, i; | |
1668 | ||
1669 | nregs = GET_MEMORY_B (pc + 1); | |
1670 | nregs >>= 4; | |
1671 | nregs &= 0xf; | |
1672 | firstreg = GET_MEMORY_B (pc + 3); | |
1673 | firstreg &= 0xf; | |
1674 | for (i = firstreg; i >= firstreg - nregs; i--) | |
1675 | { | |
1676 | cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]); | |
1677 | cpu.regs[7] += 4; | |
1678 | } | |
1679 | } | |
1680 | goto next; | |
1681 | ||
1682 | default: | |
d0fe2f7e | 1683 | illegal: |
c906108c SS |
1684 | cpu.state = SIM_STATE_STOPPED; |
1685 | cpu.exception = SIGILL; | |
1686 | goto end; | |
1687 | ||
1688 | } | |
1689 | abort (); | |
1690 | ||
1691 | setc: | |
d1335144 | 1692 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1693 | { |
1694 | cpu.ccr = res; | |
1695 | GETSR (); | |
1696 | } | |
d1335144 | 1697 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1698 | { |
1699 | cpu.exr = res; | |
1700 | GETEXR (); | |
1701 | } | |
fc974602 | 1702 | else |
c3f4437e | 1703 | goto illegal; |
fc974602 | 1704 | |
c906108c SS |
1705 | goto next; |
1706 | ||
1707 | condtrue: | |
1708 | /* When a branch works */ | |
1709 | pc = code->src.literal; | |
1710 | goto end; | |
1711 | ||
1712 | /* Set the cond codes from res */ | |
1713 | bitop: | |
1714 | ||
1715 | /* Set the flags after an 8 bit inc/dec operation */ | |
1716 | just_flags_inc8: | |
1717 | n = res & 0x80; | |
1718 | nz = res & 0xff; | |
1719 | v = (rd & 0x7f) == 0x7f; | |
1720 | goto next; | |
1721 | ||
1722 | ||
1723 | /* Set the flags after an 16 bit inc/dec operation */ | |
1724 | just_flags_inc16: | |
1725 | n = res & 0x8000; | |
1726 | nz = res & 0xffff; | |
1727 | v = (rd & 0x7fff) == 0x7fff; | |
1728 | goto next; | |
1729 | ||
1730 | ||
1731 | /* Set the flags after an 32 bit inc/dec operation */ | |
1732 | just_flags_inc32: | |
1733 | n = res & 0x80000000; | |
1734 | nz = res & 0xffffffff; | |
1735 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
1736 | goto next; | |
1737 | ||
1738 | ||
1739 | shift8: | |
1740 | /* Set flags after an 8 bit shift op, carry,overflow set in insn */ | |
1741 | n = (rd & 0x80); | |
1742 | nz = rd & 0xff; | |
1743 | SET_B_REG (code->src.reg, rd); | |
1744 | goto next; | |
1745 | ||
1746 | shift16: | |
1747 | /* Set flags after an 16 bit shift op, carry,overflow set in insn */ | |
1748 | n = (rd & 0x8000); | |
1749 | nz = rd & 0xffff; | |
1750 | SET_W_REG (code->src.reg, rd); | |
1751 | goto next; | |
1752 | ||
1753 | shift32: | |
1754 | /* Set flags after an 32 bit shift op, carry,overflow set in insn */ | |
1755 | n = (rd & 0x80000000); | |
1756 | nz = rd & 0xffffffff; | |
1757 | SET_L_REG (code->src.reg, rd); | |
1758 | goto next; | |
1759 | ||
1760 | log32: | |
1761 | store (&code->dst, res); | |
1762 | just_flags_log32: | |
1763 | /* flags after a 32bit logical operation */ | |
1764 | n = res & 0x80000000; | |
1765 | nz = res & 0xffffffff; | |
1766 | v = 0; | |
1767 | goto next; | |
1768 | ||
1769 | log16: | |
1770 | store (&code->dst, res); | |
1771 | just_flags_log16: | |
1772 | /* flags after a 16bit logical operation */ | |
1773 | n = res & 0x8000; | |
1774 | nz = res & 0xffff; | |
1775 | v = 0; | |
1776 | goto next; | |
1777 | ||
1778 | ||
1779 | log8: | |
1780 | store (&code->dst, res); | |
1781 | just_flags_log8: | |
1782 | n = res & 0x80; | |
1783 | nz = res & 0xff; | |
1784 | v = 0; | |
1785 | goto next; | |
1786 | ||
1787 | alu8: | |
1788 | SET_B_REG (code->dst.reg, res); | |
1789 | just_flags_alu8: | |
1790 | n = res & 0x80; | |
1791 | nz = res & 0xff; | |
1792 | c = (res & 0x100); | |
1793 | switch (code->opcode / 4) | |
1794 | { | |
1795 | case O_ADD: | |
1796 | v = ((rd & 0x80) == (ea & 0x80) | |
1797 | && (rd & 0x80) != (res & 0x80)); | |
1798 | break; | |
1799 | case O_SUB: | |
1800 | case O_CMP: | |
1801 | v = ((rd & 0x80) != (-ea & 0x80) | |
1802 | && (rd & 0x80) != (res & 0x80)); | |
1803 | break; | |
1804 | case O_NEG: | |
1805 | v = (rd == 0x80); | |
1806 | break; | |
1807 | } | |
1808 | goto next; | |
1809 | ||
1810 | alu16: | |
1811 | SET_W_REG (code->dst.reg, res); | |
1812 | just_flags_alu16: | |
1813 | n = res & 0x8000; | |
1814 | nz = res & 0xffff; | |
1815 | c = (res & 0x10000); | |
1816 | switch (code->opcode / 4) | |
1817 | { | |
1818 | case O_ADD: | |
1819 | v = ((rd & 0x8000) == (ea & 0x8000) | |
1820 | && (rd & 0x8000) != (res & 0x8000)); | |
1821 | break; | |
1822 | case O_SUB: | |
1823 | case O_CMP: | |
1824 | v = ((rd & 0x8000) != (-ea & 0x8000) | |
1825 | && (rd & 0x8000) != (res & 0x8000)); | |
1826 | break; | |
1827 | case O_NEG: | |
1828 | v = (rd == 0x8000); | |
1829 | break; | |
1830 | } | |
1831 | goto next; | |
1832 | ||
1833 | alu32: | |
1834 | SET_L_REG (code->dst.reg, res); | |
1835 | just_flags_alu32: | |
1836 | n = res & 0x80000000; | |
1837 | nz = res & 0xffffffff; | |
1838 | switch (code->opcode / 4) | |
1839 | { | |
1840 | case O_ADD: | |
1841 | v = ((rd & 0x80000000) == (ea & 0x80000000) | |
1842 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1843 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); | |
1844 | break; | |
1845 | case O_SUB: | |
1846 | case O_CMP: | |
1847 | v = ((rd & 0x80000000) != (-ea & 0x80000000) | |
1848 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1849 | c = (unsigned) rd < (unsigned) -ea; | |
1850 | break; | |
1851 | case O_NEG: | |
1852 | v = (rd == 0x80000000); | |
1853 | c = res != 0; | |
1854 | break; | |
1855 | } | |
1856 | goto next; | |
1857 | ||
1858 | next:; | |
1859 | pc = code->next_pc; | |
1860 | ||
1861 | end: | |
1862 | ; | |
de9b1892 KH |
1863 | #if 0 |
1864 | if (cpu.regs[8]) | |
1865 | abort (); | |
1866 | #endif | |
c906108c SS |
1867 | |
1868 | if (--poll_count < 0) | |
1869 | { | |
7a292a7a | 1870 | poll_count = POLL_QUIT_INTERVAL; |
c906108c SS |
1871 | if ((*sim_callback->poll_quit) != NULL |
1872 | && (*sim_callback->poll_quit) (sim_callback)) | |
1873 | sim_stop (sd); | |
1874 | } | |
1875 | ||
1876 | } | |
1877 | while (cpu.state == SIM_STATE_RUNNING); | |
1878 | cpu.ticks += get_now () - tick_start; | |
1879 | cpu.cycles += cycles; | |
1880 | cpu.insts += insts; | |
de9b1892 | 1881 | |
c906108c SS |
1882 | cpu.pc = pc; |
1883 | BUILDSR (); | |
d1335144 | 1884 | BUILDEXR (); |
c906108c SS |
1885 | cpu.mask = oldmask; |
1886 | signal (SIGINT, prev); | |
1887 | } | |
1888 | ||
1889 | int | |
1890 | sim_trace (sd) | |
1891 | SIM_DESC sd; | |
1892 | { | |
2ea716f6 | 1893 | /* FIXME: Unfinished. */ |
c906108c SS |
1894 | abort (); |
1895 | } | |
1896 | ||
1897 | int | |
1898 | sim_write (sd, addr, buffer, size) | |
1899 | SIM_DESC sd; | |
1900 | SIM_ADDR addr; | |
1901 | unsigned char *buffer; | |
1902 | int size; | |
1903 | { | |
1904 | int i; | |
1905 | ||
1906 | init_pointers (); | |
1907 | if (addr < 0) | |
1908 | return 0; | |
1909 | for (i = 0; i < size; i++) | |
1910 | { | |
1911 | if (addr < memory_size) | |
1912 | { | |
1913 | cpu.memory[addr + i] = buffer[i]; | |
1914 | cpu.cache_idx[addr + i] = 0; | |
1915 | } | |
1916 | else | |
1917 | cpu.eightbit[(addr + i) & 0xff] = buffer[i]; | |
1918 | } | |
1919 | return size; | |
1920 | } | |
1921 | ||
1922 | int | |
1923 | sim_read (sd, addr, buffer, size) | |
1924 | SIM_DESC sd; | |
1925 | SIM_ADDR addr; | |
1926 | unsigned char *buffer; | |
1927 | int size; | |
1928 | { | |
1929 | init_pointers (); | |
1930 | if (addr < 0) | |
1931 | return 0; | |
1932 | if (addr < memory_size) | |
1933 | memcpy (buffer, cpu.memory + addr, size); | |
1934 | else | |
1935 | memcpy (buffer, cpu.eightbit + (addr & 0xff), size); | |
1936 | return size; | |
1937 | } | |
1938 | ||
1939 | ||
c906108c SS |
1940 | int |
1941 | sim_store_register (sd, rn, value, length) | |
1942 | SIM_DESC sd; | |
1943 | int rn; | |
1944 | unsigned char *value; | |
1945 | int length; | |
1946 | { | |
1947 | int longval; | |
1948 | int shortval; | |
1949 | int intval; | |
1950 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; | |
1951 | shortval = (value[0] << 8) | (value[1]); | |
1952 | intval = h8300hmode ? longval : shortval; | |
1953 | ||
1954 | init_pointers (); | |
1955 | switch (rn) | |
1956 | { | |
1957 | case PC_REGNUM: | |
1958 | cpu.pc = intval; | |
1959 | break; | |
1960 | default: | |
1961 | abort (); | |
1962 | case R0_REGNUM: | |
1963 | case R1_REGNUM: | |
1964 | case R2_REGNUM: | |
1965 | case R3_REGNUM: | |
1966 | case R4_REGNUM: | |
1967 | case R5_REGNUM: | |
1968 | case R6_REGNUM: | |
1969 | case R7_REGNUM: | |
1970 | cpu.regs[rn] = intval; | |
1971 | break; | |
1972 | case CCR_REGNUM: | |
1973 | cpu.ccr = intval; | |
1974 | break; | |
fc974602 AV |
1975 | case EXR_REGNUM: |
1976 | cpu.exr = intval; | |
1977 | break; | |
c906108c SS |
1978 | case CYCLE_REGNUM: |
1979 | cpu.cycles = longval; | |
1980 | break; | |
1981 | ||
1982 | case INST_REGNUM: | |
1983 | cpu.insts = longval; | |
1984 | break; | |
1985 | ||
1986 | case TICK_REGNUM: | |
1987 | cpu.ticks = longval; | |
1988 | break; | |
1989 | } | |
1990 | return -1; | |
1991 | } | |
1992 | ||
1993 | int | |
1994 | sim_fetch_register (sd, rn, buf, length) | |
1995 | SIM_DESC sd; | |
1996 | int rn; | |
1997 | unsigned char *buf; | |
1998 | int length; | |
1999 | { | |
2000 | int v; | |
2001 | int longreg = 0; | |
2002 | ||
2003 | init_pointers (); | |
2004 | ||
d0fe2f7e | 2005 | if (!h8300smode && rn >= EXR_REGNUM) |
c3f4437e | 2006 | rn++; |
c906108c SS |
2007 | switch (rn) |
2008 | { | |
2009 | default: | |
2010 | abort (); | |
3b02cf92 | 2011 | case CCR_REGNUM: |
c906108c SS |
2012 | v = cpu.ccr; |
2013 | break; | |
fc974602 AV |
2014 | case EXR_REGNUM: |
2015 | v = cpu.exr; | |
2016 | break; | |
3b02cf92 | 2017 | case PC_REGNUM: |
c906108c SS |
2018 | v = cpu.pc; |
2019 | break; | |
2020 | case R0_REGNUM: | |
2021 | case R1_REGNUM: | |
2022 | case R2_REGNUM: | |
2023 | case R3_REGNUM: | |
2024 | case R4_REGNUM: | |
2025 | case R5_REGNUM: | |
2026 | case R6_REGNUM: | |
2027 | case R7_REGNUM: | |
2028 | v = cpu.regs[rn]; | |
2029 | break; | |
3b02cf92 | 2030 | case CYCLE_REGNUM: |
c906108c SS |
2031 | v = cpu.cycles; |
2032 | longreg = 1; | |
2033 | break; | |
3b02cf92 | 2034 | case TICK_REGNUM: |
c906108c SS |
2035 | v = cpu.ticks; |
2036 | longreg = 1; | |
2037 | break; | |
3b02cf92 | 2038 | case INST_REGNUM: |
c906108c SS |
2039 | v = cpu.insts; |
2040 | longreg = 1; | |
2041 | break; | |
2042 | } | |
2043 | if (h8300hmode || longreg) | |
2044 | { | |
2045 | buf[0] = v >> 24; | |
2046 | buf[1] = v >> 16; | |
2047 | buf[2] = v >> 8; | |
2048 | buf[3] = v >> 0; | |
2049 | } | |
2050 | else | |
2051 | { | |
2052 | buf[0] = v >> 8; | |
2053 | buf[1] = v; | |
2054 | } | |
2055 | return -1; | |
2056 | } | |
2057 | ||
2058 | void | |
2059 | sim_stop_reason (sd, reason, sigrc) | |
2060 | SIM_DESC sd; | |
2061 | enum sim_stop *reason; | |
2062 | int *sigrc; | |
2063 | { | |
2064 | #if 0 /* FIXME: This should work but we can't use it. | |
2065 | grep for SLEEP above. */ | |
2066 | switch (cpu.state) | |
2067 | { | |
2068 | case SIM_STATE_EXITED : *reason = sim_exited; break; | |
2069 | case SIM_STATE_SIGNALLED : *reason = sim_signalled; break; | |
2070 | case SIM_STATE_STOPPED : *reason = sim_stopped; break; | |
2071 | default : abort (); | |
2072 | } | |
2073 | #else | |
2074 | *reason = sim_stopped; | |
2075 | #endif | |
2076 | *sigrc = cpu.exception; | |
2077 | } | |
2078 | ||
2079 | /* FIXME: Rename to sim_set_mem_size. */ | |
2080 | ||
2081 | void | |
2082 | sim_size (n) | |
2083 | int n; | |
2084 | { | |
2085 | /* Memory size is fixed. */ | |
2086 | } | |
2087 | ||
2088 | void | |
2089 | sim_set_simcache_size (n) | |
2090 | { | |
2091 | if (cpu.cache) | |
2092 | free (cpu.cache); | |
2093 | if (n < 2) | |
2094 | n = 2; | |
2095 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
2096 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
2097 | cpu.csize = n; | |
2098 | } | |
2099 | ||
2100 | ||
2101 | void | |
2102 | sim_info (sd, verbose) | |
2103 | SIM_DESC sd; | |
2104 | int verbose; | |
2105 | { | |
2106 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
2107 | double virttime = cpu.cycles / 10.0e6; | |
2108 | ||
2109 | (*sim_callback->printf_filtered) (sim_callback, | |
2110 | "\n\n#instructions executed %10d\n", | |
2111 | cpu.insts); | |
2112 | (*sim_callback->printf_filtered) (sim_callback, | |
2113 | "#cycles (v approximate) %10d\n", | |
2114 | cpu.cycles); | |
2115 | (*sim_callback->printf_filtered) (sim_callback, | |
2116 | "#real time taken %10.4f\n", | |
2117 | timetaken); | |
2118 | (*sim_callback->printf_filtered) (sim_callback, | |
2119 | "#virtual time taked %10.4f\n", | |
2120 | virttime); | |
2121 | if (timetaken != 0.0) | |
2122 | (*sim_callback->printf_filtered) (sim_callback, | |
2123 | "#simulation ratio %10.4f\n", | |
2124 | virttime / timetaken); | |
2125 | (*sim_callback->printf_filtered) (sim_callback, | |
2126 | "#compiles %10d\n", | |
2127 | cpu.compiles); | |
2128 | (*sim_callback->printf_filtered) (sim_callback, | |
2129 | "#cache size %10d\n", | |
2130 | cpu.csize); | |
2131 | ||
2132 | #ifdef ADEBUG | |
2133 | /* This to be conditional on `what' (aka `verbose'), | |
2134 | however it was never passed as non-zero. */ | |
2135 | if (1) | |
2136 | { | |
2137 | int i; | |
2138 | for (i = 0; i < O_LAST; i++) | |
2139 | { | |
2140 | if (cpu.stats[i]) | |
2141 | (*sim_callback->printf_filtered) (sim_callback, | |
2142 | "%d: %d\n", i, cpu.stats[i]); | |
2143 | } | |
2144 | } | |
2145 | #endif | |
2146 | } | |
2147 | ||
2ea716f6 KH |
2148 | /* Indicate whether the cpu is an H8/300 or H8/300H. |
2149 | FLAG is non-zero for the H8/300H. */ | |
c906108c SS |
2150 | |
2151 | void | |
a8cdafbd AV |
2152 | set_h8300h (h_flag, s_flag) |
2153 | int h_flag, s_flag; | |
c906108c SS |
2154 | { |
2155 | /* FIXME: Much of the code in sim_load can be moved to sim_open. | |
2156 | This function being replaced by a sim_open:ARGV configuration | |
2ea716f6 | 2157 | option. */ |
a8cdafbd AV |
2158 | h8300hmode = h_flag; |
2159 | h8300smode = s_flag; | |
c906108c SS |
2160 | } |
2161 | ||
2162 | SIM_DESC | |
2163 | sim_open (kind, ptr, abfd, argv) | |
2164 | SIM_OPEN_KIND kind; | |
2165 | struct host_callback_struct *ptr; | |
2166 | struct _bfd *abfd; | |
2167 | char **argv; | |
2168 | { | |
2ea716f6 | 2169 | /* FIXME: Much of the code in sim_load can be moved here. */ |
c906108c SS |
2170 | |
2171 | sim_kind = kind; | |
2172 | myname = argv[0]; | |
2173 | sim_callback = ptr; | |
2ea716f6 | 2174 | /* Fudge our descriptor. */ |
c906108c SS |
2175 | return (SIM_DESC) 1; |
2176 | } | |
2177 | ||
2178 | void | |
2179 | sim_close (sd, quitting) | |
2180 | SIM_DESC sd; | |
2181 | int quitting; | |
2182 | { | |
2ea716f6 | 2183 | /* Nothing to do. */ |
c906108c SS |
2184 | } |
2185 | ||
2186 | /* Called by gdb to load a program into memory. */ | |
2187 | ||
2188 | SIM_RC | |
2189 | sim_load (sd, prog, abfd, from_tty) | |
2190 | SIM_DESC sd; | |
2191 | char *prog; | |
2192 | bfd *abfd; | |
2193 | int from_tty; | |
2194 | { | |
2195 | bfd *prog_bfd; | |
2196 | ||
2ea716f6 KH |
2197 | /* FIXME: The code below that sets a specific variant of the H8/300 |
2198 | being simulated should be moved to sim_open(). */ | |
c906108c | 2199 | |
2ea716f6 | 2200 | /* See if the file is for the H8/300 or H8/300H. */ |
c906108c SS |
2201 | /* ??? This may not be the most efficient way. The z8k simulator |
2202 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
2203 | if (abfd != NULL) | |
2204 | prog_bfd = abfd; | |
2205 | else | |
2206 | prog_bfd = bfd_openr (prog, "coff-h8300"); | |
2207 | if (prog_bfd != NULL) | |
2208 | { | |
2209 | /* Set the cpu type. We ignore failure from bfd_check_format | |
2210 | and bfd_openr as sim_load_file checks too. */ | |
de9b1892 | 2211 | if (bfd_check_format (prog_bfd, bfd_object)) |
c906108c SS |
2212 | { |
2213 | unsigned long mach = bfd_get_mach (prog_bfd); | |
a8cdafbd AV |
2214 | set_h8300h (mach == bfd_mach_h8300h || mach == bfd_mach_h8300s, |
2215 | mach == bfd_mach_h8300s); | |
c906108c SS |
2216 | } |
2217 | } | |
2218 | ||
2219 | /* If we're using gdb attached to the simulator, then we have to | |
2220 | reallocate memory for the simulator. | |
2221 | ||
2222 | When gdb first starts, it calls fetch_registers (among other | |
2223 | functions), which in turn calls init_pointers, which allocates | |
2224 | simulator memory. | |
2225 | ||
2226 | The problem is when we do that, we don't know whether we're | |
2ea716f6 | 2227 | debugging an H8/300 or H8/300H program. |
c906108c SS |
2228 | |
2229 | This is the first point at which we can make that determination, | |
2230 | so we just reallocate memory now; this will also allow us to handle | |
2ea716f6 | 2231 | switching between H8/300 and H8/300H programs without exiting |
c906108c | 2232 | gdb. */ |
a8cdafbd AV |
2233 | |
2234 | if (h8300smode) | |
2235 | memory_size = H8300S_MSIZE; | |
2236 | else if (h8300hmode) | |
c906108c SS |
2237 | memory_size = H8300H_MSIZE; |
2238 | else | |
2239 | memory_size = H8300_MSIZE; | |
2240 | ||
2241 | if (cpu.memory) | |
2242 | free (cpu.memory); | |
2243 | if (cpu.cache_idx) | |
2244 | free (cpu.cache_idx); | |
2245 | if (cpu.eightbit) | |
2246 | free (cpu.eightbit); | |
2247 | ||
2248 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
2249 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
2250 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
2251 | ||
2ea716f6 | 2252 | /* `msize' must be a power of two. */ |
c906108c SS |
2253 | if ((memory_size & (memory_size - 1)) != 0) |
2254 | abort (); | |
2255 | cpu.mask = memory_size - 1; | |
2256 | ||
2257 | if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, | |
2258 | sim_kind == SIM_OPEN_DEBUG, | |
2259 | 0, sim_write) | |
2260 | == NULL) | |
2261 | { | |
2262 | /* Close the bfd if we opened it. */ | |
2263 | if (abfd == NULL && prog_bfd != NULL) | |
2264 | bfd_close (prog_bfd); | |
2265 | return SIM_RC_FAIL; | |
2266 | } | |
2267 | ||
2268 | /* Close the bfd if we opened it. */ | |
2269 | if (abfd == NULL && prog_bfd != NULL) | |
2270 | bfd_close (prog_bfd); | |
2271 | return SIM_RC_OK; | |
2272 | } | |
2273 | ||
2274 | SIM_RC | |
2275 | sim_create_inferior (sd, abfd, argv, env) | |
2276 | SIM_DESC sd; | |
2277 | struct _bfd *abfd; | |
2278 | char **argv; | |
2279 | char **env; | |
2280 | { | |
2281 | if (abfd != NULL) | |
2282 | cpu.pc = bfd_get_start_address (abfd); | |
2283 | else | |
2284 | cpu.pc = 0; | |
2285 | return SIM_RC_OK; | |
2286 | } | |
2287 | ||
2288 | void | |
2289 | sim_do_command (sd, cmd) | |
2290 | SIM_DESC sd; | |
2291 | char *cmd; | |
2292 | { | |
2293 | (*sim_callback->printf_filtered) (sim_callback, | |
2294 | "This simulator does not accept any commands.\n"); | |
2295 | } | |
2296 | ||
2297 | void | |
2298 | sim_set_callbacks (ptr) | |
2299 | struct host_callback_struct *ptr; | |
2300 | { | |
2301 | sim_callback = ptr; | |
2302 | } |