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edece237 CV |
1 | /* Simulator instruction semantics for iq2000bf. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
5 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. | |
6 | ||
7 | This file is part of the GNU simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
11 | the Free Software Foundation; either version 3 of the License, or |
12 | (at your option) any later version. | |
edece237 CV |
13 | |
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
4744ac1b JB |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. | |
edece237 CV |
21 | |
22 | */ | |
23 | ||
24 | #ifdef DEFINE_LABELS | |
25 | ||
26 | /* The labels have the case they have because the enum of insn types | |
27 | is all uppercase and in the non-stdc case the insn symbol is built | |
28 | into the enum name. */ | |
29 | ||
30 | static struct { | |
31 | int index; | |
32 | void *label; | |
33 | } labels[] = { | |
34 | { IQ2000BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, | |
35 | { IQ2000BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, | |
36 | { IQ2000BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, | |
37 | { IQ2000BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, | |
38 | { IQ2000BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, | |
39 | { IQ2000BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, | |
40 | { IQ2000BF_INSN_ADD, && case_sem_INSN_ADD }, | |
41 | { IQ2000BF_INSN_ADDI, && case_sem_INSN_ADDI }, | |
42 | { IQ2000BF_INSN_ADDIU, && case_sem_INSN_ADDIU }, | |
43 | { IQ2000BF_INSN_ADDU, && case_sem_INSN_ADDU }, | |
44 | { IQ2000BF_INSN_ADO16, && case_sem_INSN_ADO16 }, | |
45 | { IQ2000BF_INSN_AND, && case_sem_INSN_AND }, | |
46 | { IQ2000BF_INSN_ANDI, && case_sem_INSN_ANDI }, | |
47 | { IQ2000BF_INSN_ANDOI, && case_sem_INSN_ANDOI }, | |
48 | { IQ2000BF_INSN_NOR, && case_sem_INSN_NOR }, | |
49 | { IQ2000BF_INSN_OR, && case_sem_INSN_OR }, | |
50 | { IQ2000BF_INSN_ORI, && case_sem_INSN_ORI }, | |
51 | { IQ2000BF_INSN_RAM, && case_sem_INSN_RAM }, | |
52 | { IQ2000BF_INSN_SLL, && case_sem_INSN_SLL }, | |
53 | { IQ2000BF_INSN_SLLV, && case_sem_INSN_SLLV }, | |
54 | { IQ2000BF_INSN_SLMV, && case_sem_INSN_SLMV }, | |
55 | { IQ2000BF_INSN_SLT, && case_sem_INSN_SLT }, | |
56 | { IQ2000BF_INSN_SLTI, && case_sem_INSN_SLTI }, | |
57 | { IQ2000BF_INSN_SLTIU, && case_sem_INSN_SLTIU }, | |
58 | { IQ2000BF_INSN_SLTU, && case_sem_INSN_SLTU }, | |
59 | { IQ2000BF_INSN_SRA, && case_sem_INSN_SRA }, | |
60 | { IQ2000BF_INSN_SRAV, && case_sem_INSN_SRAV }, | |
61 | { IQ2000BF_INSN_SRL, && case_sem_INSN_SRL }, | |
62 | { IQ2000BF_INSN_SRLV, && case_sem_INSN_SRLV }, | |
63 | { IQ2000BF_INSN_SRMV, && case_sem_INSN_SRMV }, | |
64 | { IQ2000BF_INSN_SUB, && case_sem_INSN_SUB }, | |
65 | { IQ2000BF_INSN_SUBU, && case_sem_INSN_SUBU }, | |
66 | { IQ2000BF_INSN_XOR, && case_sem_INSN_XOR }, | |
67 | { IQ2000BF_INSN_XORI, && case_sem_INSN_XORI }, | |
68 | { IQ2000BF_INSN_BBI, && case_sem_INSN_BBI }, | |
69 | { IQ2000BF_INSN_BBIN, && case_sem_INSN_BBIN }, | |
70 | { IQ2000BF_INSN_BBV, && case_sem_INSN_BBV }, | |
71 | { IQ2000BF_INSN_BBVN, && case_sem_INSN_BBVN }, | |
72 | { IQ2000BF_INSN_BEQ, && case_sem_INSN_BEQ }, | |
73 | { IQ2000BF_INSN_BEQL, && case_sem_INSN_BEQL }, | |
74 | { IQ2000BF_INSN_BGEZ, && case_sem_INSN_BGEZ }, | |
75 | { IQ2000BF_INSN_BGEZAL, && case_sem_INSN_BGEZAL }, | |
76 | { IQ2000BF_INSN_BGEZALL, && case_sem_INSN_BGEZALL }, | |
77 | { IQ2000BF_INSN_BGEZL, && case_sem_INSN_BGEZL }, | |
78 | { IQ2000BF_INSN_BLTZ, && case_sem_INSN_BLTZ }, | |
79 | { IQ2000BF_INSN_BLTZL, && case_sem_INSN_BLTZL }, | |
80 | { IQ2000BF_INSN_BLTZAL, && case_sem_INSN_BLTZAL }, | |
81 | { IQ2000BF_INSN_BLTZALL, && case_sem_INSN_BLTZALL }, | |
82 | { IQ2000BF_INSN_BMB0, && case_sem_INSN_BMB0 }, | |
83 | { IQ2000BF_INSN_BMB1, && case_sem_INSN_BMB1 }, | |
84 | { IQ2000BF_INSN_BMB2, && case_sem_INSN_BMB2 }, | |
85 | { IQ2000BF_INSN_BMB3, && case_sem_INSN_BMB3 }, | |
86 | { IQ2000BF_INSN_BNE, && case_sem_INSN_BNE }, | |
87 | { IQ2000BF_INSN_BNEL, && case_sem_INSN_BNEL }, | |
88 | { IQ2000BF_INSN_JALR, && case_sem_INSN_JALR }, | |
89 | { IQ2000BF_INSN_JR, && case_sem_INSN_JR }, | |
90 | { IQ2000BF_INSN_LB, && case_sem_INSN_LB }, | |
91 | { IQ2000BF_INSN_LBU, && case_sem_INSN_LBU }, | |
92 | { IQ2000BF_INSN_LH, && case_sem_INSN_LH }, | |
93 | { IQ2000BF_INSN_LHU, && case_sem_INSN_LHU }, | |
94 | { IQ2000BF_INSN_LUI, && case_sem_INSN_LUI }, | |
95 | { IQ2000BF_INSN_LW, && case_sem_INSN_LW }, | |
96 | { IQ2000BF_INSN_SB, && case_sem_INSN_SB }, | |
97 | { IQ2000BF_INSN_SH, && case_sem_INSN_SH }, | |
98 | { IQ2000BF_INSN_SW, && case_sem_INSN_SW }, | |
99 | { IQ2000BF_INSN_BREAK, && case_sem_INSN_BREAK }, | |
100 | { IQ2000BF_INSN_SYSCALL, && case_sem_INSN_SYSCALL }, | |
101 | { IQ2000BF_INSN_ANDOUI, && case_sem_INSN_ANDOUI }, | |
102 | { IQ2000BF_INSN_ORUI, && case_sem_INSN_ORUI }, | |
103 | { IQ2000BF_INSN_BGTZ, && case_sem_INSN_BGTZ }, | |
104 | { IQ2000BF_INSN_BGTZL, && case_sem_INSN_BGTZL }, | |
105 | { IQ2000BF_INSN_BLEZ, && case_sem_INSN_BLEZ }, | |
106 | { IQ2000BF_INSN_BLEZL, && case_sem_INSN_BLEZL }, | |
107 | { IQ2000BF_INSN_MRGB, && case_sem_INSN_MRGB }, | |
108 | { IQ2000BF_INSN_BCTXT, && case_sem_INSN_BCTXT }, | |
109 | { IQ2000BF_INSN_BC0F, && case_sem_INSN_BC0F }, | |
110 | { IQ2000BF_INSN_BC0FL, && case_sem_INSN_BC0FL }, | |
111 | { IQ2000BF_INSN_BC3F, && case_sem_INSN_BC3F }, | |
112 | { IQ2000BF_INSN_BC3FL, && case_sem_INSN_BC3FL }, | |
113 | { IQ2000BF_INSN_BC0T, && case_sem_INSN_BC0T }, | |
114 | { IQ2000BF_INSN_BC0TL, && case_sem_INSN_BC0TL }, | |
115 | { IQ2000BF_INSN_BC3T, && case_sem_INSN_BC3T }, | |
116 | { IQ2000BF_INSN_BC3TL, && case_sem_INSN_BC3TL }, | |
117 | { IQ2000BF_INSN_CFC0, && case_sem_INSN_CFC0 }, | |
118 | { IQ2000BF_INSN_CFC1, && case_sem_INSN_CFC1 }, | |
119 | { IQ2000BF_INSN_CFC2, && case_sem_INSN_CFC2 }, | |
120 | { IQ2000BF_INSN_CFC3, && case_sem_INSN_CFC3 }, | |
121 | { IQ2000BF_INSN_CHKHDR, && case_sem_INSN_CHKHDR }, | |
122 | { IQ2000BF_INSN_CTC0, && case_sem_INSN_CTC0 }, | |
123 | { IQ2000BF_INSN_CTC1, && case_sem_INSN_CTC1 }, | |
124 | { IQ2000BF_INSN_CTC2, && case_sem_INSN_CTC2 }, | |
125 | { IQ2000BF_INSN_CTC3, && case_sem_INSN_CTC3 }, | |
126 | { IQ2000BF_INSN_JCR, && case_sem_INSN_JCR }, | |
127 | { IQ2000BF_INSN_LUC32, && case_sem_INSN_LUC32 }, | |
128 | { IQ2000BF_INSN_LUC32L, && case_sem_INSN_LUC32L }, | |
129 | { IQ2000BF_INSN_LUC64, && case_sem_INSN_LUC64 }, | |
130 | { IQ2000BF_INSN_LUC64L, && case_sem_INSN_LUC64L }, | |
131 | { IQ2000BF_INSN_LUK, && case_sem_INSN_LUK }, | |
132 | { IQ2000BF_INSN_LULCK, && case_sem_INSN_LULCK }, | |
133 | { IQ2000BF_INSN_LUM32, && case_sem_INSN_LUM32 }, | |
134 | { IQ2000BF_INSN_LUM32L, && case_sem_INSN_LUM32L }, | |
135 | { IQ2000BF_INSN_LUM64, && case_sem_INSN_LUM64 }, | |
136 | { IQ2000BF_INSN_LUM64L, && case_sem_INSN_LUM64L }, | |
137 | { IQ2000BF_INSN_LUR, && case_sem_INSN_LUR }, | |
138 | { IQ2000BF_INSN_LURL, && case_sem_INSN_LURL }, | |
139 | { IQ2000BF_INSN_LUULCK, && case_sem_INSN_LUULCK }, | |
140 | { IQ2000BF_INSN_MFC0, && case_sem_INSN_MFC0 }, | |
141 | { IQ2000BF_INSN_MFC1, && case_sem_INSN_MFC1 }, | |
142 | { IQ2000BF_INSN_MFC2, && case_sem_INSN_MFC2 }, | |
143 | { IQ2000BF_INSN_MFC3, && case_sem_INSN_MFC3 }, | |
144 | { IQ2000BF_INSN_MTC0, && case_sem_INSN_MTC0 }, | |
145 | { IQ2000BF_INSN_MTC1, && case_sem_INSN_MTC1 }, | |
146 | { IQ2000BF_INSN_MTC2, && case_sem_INSN_MTC2 }, | |
147 | { IQ2000BF_INSN_MTC3, && case_sem_INSN_MTC3 }, | |
148 | { IQ2000BF_INSN_PKRL, && case_sem_INSN_PKRL }, | |
149 | { IQ2000BF_INSN_PKRLR1, && case_sem_INSN_PKRLR1 }, | |
150 | { IQ2000BF_INSN_PKRLR30, && case_sem_INSN_PKRLR30 }, | |
151 | { IQ2000BF_INSN_RB, && case_sem_INSN_RB }, | |
152 | { IQ2000BF_INSN_RBR1, && case_sem_INSN_RBR1 }, | |
153 | { IQ2000BF_INSN_RBR30, && case_sem_INSN_RBR30 }, | |
154 | { IQ2000BF_INSN_RFE, && case_sem_INSN_RFE }, | |
155 | { IQ2000BF_INSN_RX, && case_sem_INSN_RX }, | |
156 | { IQ2000BF_INSN_RXR1, && case_sem_INSN_RXR1 }, | |
157 | { IQ2000BF_INSN_RXR30, && case_sem_INSN_RXR30 }, | |
158 | { IQ2000BF_INSN_SLEEP, && case_sem_INSN_SLEEP }, | |
159 | { IQ2000BF_INSN_SRRD, && case_sem_INSN_SRRD }, | |
160 | { IQ2000BF_INSN_SRRDL, && case_sem_INSN_SRRDL }, | |
161 | { IQ2000BF_INSN_SRULCK, && case_sem_INSN_SRULCK }, | |
162 | { IQ2000BF_INSN_SRWR, && case_sem_INSN_SRWR }, | |
163 | { IQ2000BF_INSN_SRWRU, && case_sem_INSN_SRWRU }, | |
164 | { IQ2000BF_INSN_TRAPQFL, && case_sem_INSN_TRAPQFL }, | |
165 | { IQ2000BF_INSN_TRAPQNE, && case_sem_INSN_TRAPQNE }, | |
166 | { IQ2000BF_INSN_TRAPREL, && case_sem_INSN_TRAPREL }, | |
167 | { IQ2000BF_INSN_WB, && case_sem_INSN_WB }, | |
168 | { IQ2000BF_INSN_WBU, && case_sem_INSN_WBU }, | |
169 | { IQ2000BF_INSN_WBR1, && case_sem_INSN_WBR1 }, | |
170 | { IQ2000BF_INSN_WBR1U, && case_sem_INSN_WBR1U }, | |
171 | { IQ2000BF_INSN_WBR30, && case_sem_INSN_WBR30 }, | |
172 | { IQ2000BF_INSN_WBR30U, && case_sem_INSN_WBR30U }, | |
173 | { IQ2000BF_INSN_WX, && case_sem_INSN_WX }, | |
174 | { IQ2000BF_INSN_WXU, && case_sem_INSN_WXU }, | |
175 | { IQ2000BF_INSN_WXR1, && case_sem_INSN_WXR1 }, | |
176 | { IQ2000BF_INSN_WXR1U, && case_sem_INSN_WXR1U }, | |
177 | { IQ2000BF_INSN_WXR30, && case_sem_INSN_WXR30 }, | |
178 | { IQ2000BF_INSN_WXR30U, && case_sem_INSN_WXR30U }, | |
179 | { IQ2000BF_INSN_LDW, && case_sem_INSN_LDW }, | |
180 | { IQ2000BF_INSN_SDW, && case_sem_INSN_SDW }, | |
181 | { IQ2000BF_INSN_J, && case_sem_INSN_J }, | |
182 | { IQ2000BF_INSN_JAL, && case_sem_INSN_JAL }, | |
183 | { IQ2000BF_INSN_BMB, && case_sem_INSN_BMB }, | |
184 | { 0, 0 } | |
185 | }; | |
186 | int i; | |
187 | ||
188 | for (i = 0; labels[i].label != 0; ++i) | |
189 | { | |
190 | #if FAST_P | |
191 | CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; | |
192 | #else | |
193 | CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; | |
194 | #endif | |
195 | } | |
196 | ||
197 | #undef DEFINE_LABELS | |
198 | #endif /* DEFINE_LABELS */ | |
199 | ||
200 | #ifdef DEFINE_SWITCH | |
201 | ||
202 | /* If hyper-fast [well not unnecessarily slow] execution is selected, turn | |
203 | off frills like tracing and profiling. */ | |
204 | /* FIXME: A better way would be to have TRACE_RESULT check for something | |
205 | that can cause it to be optimized out. Another way would be to emit | |
206 | special handlers into the instruction "stream". */ | |
207 | ||
208 | #if FAST_P | |
209 | #undef TRACE_RESULT | |
210 | #define TRACE_RESULT(cpu, abuf, name, type, val) | |
211 | #endif | |
212 | ||
213 | #undef GET_ATTR | |
214 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
215 | #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) | |
216 | #else | |
217 | #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr) | |
218 | #endif | |
219 | ||
220 | { | |
221 | ||
222 | #if WITH_SCACHE_PBB | |
223 | ||
224 | /* Branch to next handler without going around main loop. */ | |
225 | #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case | |
226 | SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) | |
227 | ||
228 | #else /* ! WITH_SCACHE_PBB */ | |
229 | ||
230 | #define NEXT(vpc) BREAK (sem) | |
231 | #ifdef __GNUC__ | |
232 | #if FAST_P | |
233 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) | |
234 | #else | |
235 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) | |
236 | #endif | |
237 | #else | |
238 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) | |
239 | #endif | |
240 | ||
241 | #endif /* ! WITH_SCACHE_PBB */ | |
242 | ||
243 | { | |
244 | ||
245 | CASE (sem, INSN_X_INVALID) : /* --invalid-- */ | |
246 | { | |
247 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
248 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
249 | #define FLD(f) abuf->fields.fmt_empty.f | |
250 | int UNUSED written = 0; | |
251 | IADDR UNUSED pc = abuf->addr; | |
252 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
253 | ||
254 | { | |
255 | /* Update the recorded pc in the cpu state struct. | |
256 | Only necessary for WITH_SCACHE case, but to avoid the | |
257 | conditional compilation .... */ | |
258 | SET_H_PC (pc); | |
259 | /* Virtual insns have zero size. Overwrite vpc with address of next insn | |
260 | using the default-insn-bitsize spec. When executing insns in parallel | |
261 | we may want to queue the fault and continue execution. */ | |
262 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
263 | vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); | |
264 | } | |
265 | ||
266 | #undef FLD | |
267 | } | |
268 | NEXT (vpc); | |
269 | ||
270 | CASE (sem, INSN_X_AFTER) : /* --after-- */ | |
271 | { | |
272 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
273 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
274 | #define FLD(f) abuf->fields.fmt_empty.f | |
275 | int UNUSED written = 0; | |
276 | IADDR UNUSED pc = abuf->addr; | |
277 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
278 | ||
279 | { | |
280 | #if WITH_SCACHE_PBB_IQ2000BF | |
281 | iq2000bf_pbb_after (current_cpu, sem_arg); | |
282 | #endif | |
283 | } | |
284 | ||
285 | #undef FLD | |
286 | } | |
287 | NEXT (vpc); | |
288 | ||
289 | CASE (sem, INSN_X_BEFORE) : /* --before-- */ | |
290 | { | |
291 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
292 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
293 | #define FLD(f) abuf->fields.fmt_empty.f | |
294 | int UNUSED written = 0; | |
295 | IADDR UNUSED pc = abuf->addr; | |
296 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
297 | ||
298 | { | |
299 | #if WITH_SCACHE_PBB_IQ2000BF | |
300 | iq2000bf_pbb_before (current_cpu, sem_arg); | |
301 | #endif | |
302 | } | |
303 | ||
304 | #undef FLD | |
305 | } | |
306 | NEXT (vpc); | |
307 | ||
308 | CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ | |
309 | { | |
310 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
311 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
312 | #define FLD(f) abuf->fields.fmt_empty.f | |
313 | int UNUSED written = 0; | |
314 | IADDR UNUSED pc = abuf->addr; | |
315 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
316 | ||
317 | { | |
318 | #if WITH_SCACHE_PBB_IQ2000BF | |
319 | #ifdef DEFINE_SWITCH | |
320 | vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg, | |
321 | pbb_br_type, pbb_br_npc); | |
322 | BREAK (sem); | |
323 | #else | |
324 | /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ | |
325 | vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg, | |
326 | CPU_PBB_BR_TYPE (current_cpu), | |
327 | CPU_PBB_BR_NPC (current_cpu)); | |
328 | #endif | |
329 | #endif | |
330 | } | |
331 | ||
332 | #undef FLD | |
333 | } | |
334 | NEXT (vpc); | |
335 | ||
336 | CASE (sem, INSN_X_CHAIN) : /* --chain-- */ | |
337 | { | |
338 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
339 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
340 | #define FLD(f) abuf->fields.fmt_empty.f | |
341 | int UNUSED written = 0; | |
342 | IADDR UNUSED pc = abuf->addr; | |
343 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
344 | ||
345 | { | |
346 | #if WITH_SCACHE_PBB_IQ2000BF | |
347 | vpc = iq2000bf_pbb_chain (current_cpu, sem_arg); | |
348 | #ifdef DEFINE_SWITCH | |
349 | BREAK (sem); | |
350 | #endif | |
351 | #endif | |
352 | } | |
353 | ||
354 | #undef FLD | |
355 | } | |
356 | NEXT (vpc); | |
357 | ||
358 | CASE (sem, INSN_X_BEGIN) : /* --begin-- */ | |
359 | { | |
360 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
361 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
362 | #define FLD(f) abuf->fields.fmt_empty.f | |
363 | int UNUSED written = 0; | |
364 | IADDR UNUSED pc = abuf->addr; | |
365 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
366 | ||
367 | { | |
368 | #if WITH_SCACHE_PBB_IQ2000BF | |
369 | #if defined DEFINE_SWITCH || defined FAST_P | |
370 | /* In the switch case FAST_P is a constant, allowing several optimizations | |
371 | in any called inline functions. */ | |
372 | vpc = iq2000bf_pbb_begin (current_cpu, FAST_P); | |
373 | #else | |
374 | #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ | |
375 | vpc = iq2000bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); | |
376 | #else | |
377 | vpc = iq2000bf_pbb_begin (current_cpu, 0); | |
378 | #endif | |
379 | #endif | |
380 | #endif | |
381 | } | |
382 | ||
383 | #undef FLD | |
384 | } | |
385 | NEXT (vpc); | |
386 | ||
387 | CASE (sem, INSN_ADD) : /* add $rd,$rs,$rt */ | |
388 | { | |
389 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
390 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
391 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
392 | int UNUSED written = 0; | |
393 | IADDR UNUSED pc = abuf->addr; | |
394 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
395 | ||
396 | { | |
397 | SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); | |
398 | SET_H_GR (FLD (f_rd), opval); | |
399 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
400 | } | |
401 | ||
402 | #undef FLD | |
403 | } | |
404 | NEXT (vpc); | |
405 | ||
406 | CASE (sem, INSN_ADDI) : /* addi $rt,$rs,$lo16 */ | |
407 | { | |
408 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
409 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
410 | #define FLD(f) abuf->fields.sfmt_addi.f | |
411 | int UNUSED written = 0; | |
412 | IADDR UNUSED pc = abuf->addr; | |
413 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
414 | ||
415 | { | |
416 | SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))); | |
417 | SET_H_GR (FLD (f_rt), opval); | |
418 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
419 | } | |
420 | ||
421 | #undef FLD | |
422 | } | |
423 | NEXT (vpc); | |
424 | ||
425 | CASE (sem, INSN_ADDIU) : /* addiu $rt,$rs,$lo16 */ | |
426 | { | |
427 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
428 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
429 | #define FLD(f) abuf->fields.sfmt_addi.f | |
430 | int UNUSED written = 0; | |
431 | IADDR UNUSED pc = abuf->addr; | |
432 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
433 | ||
434 | { | |
435 | SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))); | |
436 | SET_H_GR (FLD (f_rt), opval); | |
437 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
438 | } | |
439 | ||
440 | #undef FLD | |
441 | } | |
442 | NEXT (vpc); | |
443 | ||
444 | CASE (sem, INSN_ADDU) : /* addu $rd,$rs,$rt */ | |
445 | { | |
446 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
447 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
448 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
449 | int UNUSED written = 0; | |
450 | IADDR UNUSED pc = abuf->addr; | |
451 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
452 | ||
453 | { | |
454 | SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); | |
455 | SET_H_GR (FLD (f_rd), opval); | |
456 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
457 | } | |
458 | ||
459 | #undef FLD | |
460 | } | |
461 | NEXT (vpc); | |
462 | ||
463 | CASE (sem, INSN_ADO16) : /* ado16 $rd,$rs,$rt */ | |
464 | { | |
465 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
466 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
467 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
468 | int UNUSED written = 0; | |
469 | IADDR UNUSED pc = abuf->addr; | |
470 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
471 | ||
472 | { | |
473 | HI tmp_high; | |
474 | HI tmp_low; | |
475 | tmp_low = ADDHI (ANDHI (GET_H_GR (FLD (f_rs)), 65535), ANDHI (GET_H_GR (FLD (f_rt)), 65535)); | |
476 | tmp_high = ADDHI (SRLSI (GET_H_GR (FLD (f_rs)), 16), SRLSI (GET_H_GR (FLD (f_rt)), 16)); | |
477 | { | |
478 | SI opval = ORSI (SLLSI (tmp_high, 16), tmp_low); | |
479 | SET_H_GR (FLD (f_rd), opval); | |
480 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
481 | } | |
482 | } | |
483 | ||
484 | #undef FLD | |
485 | } | |
486 | NEXT (vpc); | |
487 | ||
488 | CASE (sem, INSN_AND) : /* and $rd,$rs,$rt */ | |
489 | { | |
490 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
491 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
492 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
493 | int UNUSED written = 0; | |
494 | IADDR UNUSED pc = abuf->addr; | |
495 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
496 | ||
497 | { | |
498 | SI opval = ANDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); | |
499 | SET_H_GR (FLD (f_rd), opval); | |
500 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
501 | } | |
502 | ||
503 | #undef FLD | |
504 | } | |
505 | NEXT (vpc); | |
506 | ||
507 | CASE (sem, INSN_ANDI) : /* andi $rt,$rs,$lo16 */ | |
508 | { | |
509 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
510 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
511 | #define FLD(f) abuf->fields.sfmt_addi.f | |
512 | int UNUSED written = 0; | |
513 | IADDR UNUSED pc = abuf->addr; | |
514 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
515 | ||
516 | { | |
517 | SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); | |
518 | SET_H_GR (FLD (f_rt), opval); | |
519 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
520 | } | |
521 | ||
522 | #undef FLD | |
523 | } | |
524 | NEXT (vpc); | |
525 | ||
526 | CASE (sem, INSN_ANDOI) : /* andoi $rt,$rs,$lo16 */ | |
527 | { | |
528 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
529 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
530 | #define FLD(f) abuf->fields.sfmt_addi.f | |
531 | int UNUSED written = 0; | |
532 | IADDR UNUSED pc = abuf->addr; | |
533 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
534 | ||
535 | { | |
536 | SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (0xffff0000, EXTHISI (TRUNCSIHI (FLD (f_imm))))); | |
537 | SET_H_GR (FLD (f_rt), opval); | |
538 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
539 | } | |
540 | ||
541 | #undef FLD | |
542 | } | |
543 | NEXT (vpc); | |
544 | ||
545 | CASE (sem, INSN_NOR) : /* nor $rd,$rs,$rt */ | |
546 | { | |
547 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
548 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
549 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
550 | int UNUSED written = 0; | |
551 | IADDR UNUSED pc = abuf->addr; | |
552 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
553 | ||
554 | { | |
555 | SI opval = INVSI (ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))); | |
556 | SET_H_GR (FLD (f_rd), opval); | |
557 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
558 | } | |
559 | ||
560 | #undef FLD | |
561 | } | |
562 | NEXT (vpc); | |
563 | ||
564 | CASE (sem, INSN_OR) : /* or $rd,$rs,$rt */ | |
565 | { | |
566 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
567 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
568 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
569 | int UNUSED written = 0; | |
570 | IADDR UNUSED pc = abuf->addr; | |
571 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
572 | ||
573 | { | |
574 | SI opval = ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); | |
575 | SET_H_GR (FLD (f_rd), opval); | |
576 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
577 | } | |
578 | ||
579 | #undef FLD | |
580 | } | |
581 | NEXT (vpc); | |
582 | ||
583 | CASE (sem, INSN_ORI) : /* ori $rt,$rs,$lo16 */ | |
584 | { | |
585 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
586 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
587 | #define FLD(f) abuf->fields.sfmt_addi.f | |
588 | int UNUSED written = 0; | |
589 | IADDR UNUSED pc = abuf->addr; | |
590 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
591 | ||
592 | { | |
593 | SI opval = ORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); | |
594 | SET_H_GR (FLD (f_rt), opval); | |
595 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
596 | } | |
597 | ||
598 | #undef FLD | |
599 | } | |
600 | NEXT (vpc); | |
601 | ||
602 | CASE (sem, INSN_RAM) : /* ram $rd,$rt,$shamt,$maskl,$maskr */ | |
603 | { | |
604 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
605 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
606 | #define FLD(f) abuf->fields.sfmt_ram.f | |
607 | int UNUSED written = 0; | |
608 | IADDR UNUSED pc = abuf->addr; | |
609 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
610 | ||
611 | { | |
612 | { | |
613 | SI opval = RORSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); | |
614 | SET_H_GR (FLD (f_rd), opval); | |
615 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
616 | } | |
617 | { | |
618 | SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SRLSI (0xffffffff, FLD (f_maskl))); | |
619 | SET_H_GR (FLD (f_rd), opval); | |
620 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
621 | } | |
622 | { | |
623 | SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SLLSI (0xffffffff, FLD (f_rs))); | |
624 | SET_H_GR (FLD (f_rd), opval); | |
625 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
626 | } | |
627 | } | |
628 | ||
629 | #undef FLD | |
630 | } | |
631 | NEXT (vpc); | |
632 | ||
633 | CASE (sem, INSN_SLL) : /* sll $rd,$rt,$shamt */ | |
634 | { | |
635 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
636 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
637 | #define FLD(f) abuf->fields.sfmt_ram.f | |
638 | int UNUSED written = 0; | |
639 | IADDR UNUSED pc = abuf->addr; | |
640 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
641 | ||
642 | { | |
643 | SI opval = SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); | |
644 | SET_H_GR (FLD (f_rd), opval); | |
645 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
646 | } | |
647 | ||
648 | #undef FLD | |
649 | } | |
650 | NEXT (vpc); | |
651 | ||
652 | CASE (sem, INSN_SLLV) : /* sllv $rd,$rt,$rs */ | |
653 | { | |
654 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
655 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
656 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
657 | int UNUSED written = 0; | |
658 | IADDR UNUSED pc = abuf->addr; | |
659 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
660 | ||
661 | { | |
662 | SI opval = SLLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); | |
663 | SET_H_GR (FLD (f_rd), opval); | |
664 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
665 | } | |
666 | ||
667 | #undef FLD | |
668 | } | |
669 | NEXT (vpc); | |
670 | ||
671 | CASE (sem, INSN_SLMV) : /* slmv $rd,$rt,$rs,$shamt */ | |
672 | { | |
673 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
674 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
675 | #define FLD(f) abuf->fields.sfmt_ram.f | |
676 | int UNUSED written = 0; | |
677 | IADDR UNUSED pc = abuf->addr; | |
678 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
679 | ||
680 | { | |
681 | SI opval = ANDSI (SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SRLSI (0xffffffff, GET_H_GR (FLD (f_rs)))); | |
682 | SET_H_GR (FLD (f_rd), opval); | |
683 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
684 | } | |
685 | ||
686 | #undef FLD | |
687 | } | |
688 | NEXT (vpc); | |
689 | ||
690 | CASE (sem, INSN_SLT) : /* slt $rd,$rs,$rt */ | |
691 | { | |
692 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
693 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
694 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
695 | int UNUSED written = 0; | |
696 | IADDR UNUSED pc = abuf->addr; | |
697 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
698 | ||
699 | if (LTSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { | |
700 | { | |
701 | SI opval = 1; | |
702 | SET_H_GR (FLD (f_rd), opval); | |
703 | written |= (1 << 2); | |
704 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
705 | } | |
706 | } else { | |
707 | { | |
708 | SI opval = 0; | |
709 | SET_H_GR (FLD (f_rd), opval); | |
710 | written |= (1 << 2); | |
711 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
712 | } | |
713 | } | |
714 | ||
715 | abuf->written = written; | |
716 | #undef FLD | |
717 | } | |
718 | NEXT (vpc); | |
719 | ||
720 | CASE (sem, INSN_SLTI) : /* slti $rt,$rs,$imm */ | |
721 | { | |
722 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
723 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
724 | #define FLD(f) abuf->fields.sfmt_addi.f | |
725 | int UNUSED written = 0; | |
726 | IADDR UNUSED pc = abuf->addr; | |
727 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
728 | ||
729 | if (LTSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))) { | |
730 | { | |
731 | SI opval = 1; | |
732 | SET_H_GR (FLD (f_rt), opval); | |
733 | written |= (1 << 2); | |
734 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
735 | } | |
736 | } else { | |
737 | { | |
738 | SI opval = 0; | |
739 | SET_H_GR (FLD (f_rt), opval); | |
740 | written |= (1 << 2); | |
741 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
742 | } | |
743 | } | |
744 | ||
745 | abuf->written = written; | |
746 | #undef FLD | |
747 | } | |
748 | NEXT (vpc); | |
749 | ||
750 | CASE (sem, INSN_SLTIU) : /* sltiu $rt,$rs,$imm */ | |
751 | { | |
752 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
753 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
754 | #define FLD(f) abuf->fields.sfmt_addi.f | |
755 | int UNUSED written = 0; | |
756 | IADDR UNUSED pc = abuf->addr; | |
757 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
758 | ||
759 | if (LTUSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))) { | |
760 | { | |
761 | SI opval = 1; | |
762 | SET_H_GR (FLD (f_rt), opval); | |
763 | written |= (1 << 2); | |
764 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
765 | } | |
766 | } else { | |
767 | { | |
768 | SI opval = 0; | |
769 | SET_H_GR (FLD (f_rt), opval); | |
770 | written |= (1 << 2); | |
771 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
772 | } | |
773 | } | |
774 | ||
775 | abuf->written = written; | |
776 | #undef FLD | |
777 | } | |
778 | NEXT (vpc); | |
779 | ||
780 | CASE (sem, INSN_SLTU) : /* sltu $rd,$rs,$rt */ | |
781 | { | |
782 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
783 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
784 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
785 | int UNUSED written = 0; | |
786 | IADDR UNUSED pc = abuf->addr; | |
787 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
788 | ||
789 | if (LTUSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { | |
790 | { | |
791 | SI opval = 1; | |
792 | SET_H_GR (FLD (f_rd), opval); | |
793 | written |= (1 << 2); | |
794 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
795 | } | |
796 | } else { | |
797 | { | |
798 | SI opval = 0; | |
799 | SET_H_GR (FLD (f_rd), opval); | |
800 | written |= (1 << 2); | |
801 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
802 | } | |
803 | } | |
804 | ||
805 | abuf->written = written; | |
806 | #undef FLD | |
807 | } | |
808 | NEXT (vpc); | |
809 | ||
810 | CASE (sem, INSN_SRA) : /* sra $rd,$rt,$shamt */ | |
811 | { | |
812 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
813 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
814 | #define FLD(f) abuf->fields.sfmt_ram.f | |
815 | int UNUSED written = 0; | |
816 | IADDR UNUSED pc = abuf->addr; | |
817 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
818 | ||
819 | { | |
820 | SI opval = SRASI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); | |
821 | SET_H_GR (FLD (f_rd), opval); | |
822 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
823 | } | |
824 | ||
825 | #undef FLD | |
826 | } | |
827 | NEXT (vpc); | |
828 | ||
829 | CASE (sem, INSN_SRAV) : /* srav $rd,$rt,$rs */ | |
830 | { | |
831 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
832 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
833 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
834 | int UNUSED written = 0; | |
835 | IADDR UNUSED pc = abuf->addr; | |
836 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
837 | ||
838 | { | |
839 | SI opval = SRASI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); | |
840 | SET_H_GR (FLD (f_rd), opval); | |
841 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
842 | } | |
843 | ||
844 | #undef FLD | |
845 | } | |
846 | NEXT (vpc); | |
847 | ||
848 | CASE (sem, INSN_SRL) : /* srl $rd,$rt,$shamt */ | |
849 | { | |
850 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
851 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
852 | #define FLD(f) abuf->fields.sfmt_ram.f | |
853 | int UNUSED written = 0; | |
854 | IADDR UNUSED pc = abuf->addr; | |
855 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
856 | ||
857 | { | |
858 | SI opval = SRLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); | |
859 | SET_H_GR (FLD (f_rd), opval); | |
860 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
861 | } | |
862 | ||
863 | #undef FLD | |
864 | } | |
865 | NEXT (vpc); | |
866 | ||
867 | CASE (sem, INSN_SRLV) : /* srlv $rd,$rt,$rs */ | |
868 | { | |
869 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
870 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
871 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
872 | int UNUSED written = 0; | |
873 | IADDR UNUSED pc = abuf->addr; | |
874 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
875 | ||
876 | { | |
877 | SI opval = SRLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); | |
878 | SET_H_GR (FLD (f_rd), opval); | |
879 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
880 | } | |
881 | ||
882 | #undef FLD | |
883 | } | |
884 | NEXT (vpc); | |
885 | ||
886 | CASE (sem, INSN_SRMV) : /* srmv $rd,$rt,$rs,$shamt */ | |
887 | { | |
888 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
889 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
890 | #define FLD(f) abuf->fields.sfmt_ram.f | |
891 | int UNUSED written = 0; | |
892 | IADDR UNUSED pc = abuf->addr; | |
893 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
894 | ||
895 | { | |
896 | SI opval = ANDSI (SRLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SLLSI (0xffffffff, GET_H_GR (FLD (f_rs)))); | |
897 | SET_H_GR (FLD (f_rd), opval); | |
898 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
899 | } | |
900 | ||
901 | #undef FLD | |
902 | } | |
903 | NEXT (vpc); | |
904 | ||
905 | CASE (sem, INSN_SUB) : /* sub $rd,$rs,$rt */ | |
906 | { | |
907 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
908 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
909 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
910 | int UNUSED written = 0; | |
911 | IADDR UNUSED pc = abuf->addr; | |
912 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
913 | ||
914 | { | |
915 | SI opval = SUBSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); | |
916 | SET_H_GR (FLD (f_rd), opval); | |
917 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
918 | } | |
919 | ||
920 | #undef FLD | |
921 | } | |
922 | NEXT (vpc); | |
923 | ||
924 | CASE (sem, INSN_SUBU) : /* subu $rd,$rs,$rt */ | |
925 | { | |
926 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
927 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
928 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
929 | int UNUSED written = 0; | |
930 | IADDR UNUSED pc = abuf->addr; | |
931 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
932 | ||
933 | { | |
934 | SI opval = SUBSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); | |
935 | SET_H_GR (FLD (f_rd), opval); | |
936 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
937 | } | |
938 | ||
939 | #undef FLD | |
940 | } | |
941 | NEXT (vpc); | |
942 | ||
943 | CASE (sem, INSN_XOR) : /* xor $rd,$rs,$rt */ | |
944 | { | |
945 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
946 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
947 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
948 | int UNUSED written = 0; | |
949 | IADDR UNUSED pc = abuf->addr; | |
950 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
951 | ||
952 | { | |
953 | SI opval = XORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); | |
954 | SET_H_GR (FLD (f_rd), opval); | |
955 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
956 | } | |
957 | ||
958 | #undef FLD | |
959 | } | |
960 | NEXT (vpc); | |
961 | ||
962 | CASE (sem, INSN_XORI) : /* xori $rt,$rs,$lo16 */ | |
963 | { | |
964 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
965 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
966 | #define FLD(f) abuf->fields.sfmt_addi.f | |
967 | int UNUSED written = 0; | |
968 | IADDR UNUSED pc = abuf->addr; | |
969 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
970 | ||
971 | { | |
972 | SI opval = XORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); | |
973 | SET_H_GR (FLD (f_rt), opval); | |
974 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
975 | } | |
976 | ||
977 | #undef FLD | |
978 | } | |
979 | NEXT (vpc); | |
980 | ||
981 | CASE (sem, INSN_BBI) : /* bbi $rs($bitnum),$offset */ | |
982 | { | |
983 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
984 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
985 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
986 | int UNUSED written = 0; | |
987 | IADDR UNUSED pc = abuf->addr; | |
988 | SEM_BRANCH_INIT | |
989 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
990 | ||
991 | if (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, FLD (f_rt)))) { | |
992 | { | |
993 | { | |
994 | USI opval = FLD (i_offset); | |
995 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
996 | written |= (1 << 3); | |
997 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
998 | } | |
999 | } | |
1000 | } | |
1001 | ||
1002 | abuf->written = written; | |
1003 | SEM_BRANCH_FINI (vpc); | |
1004 | #undef FLD | |
1005 | } | |
1006 | NEXT (vpc); | |
1007 | ||
1008 | CASE (sem, INSN_BBIN) : /* bbin $rs($bitnum),$offset */ | |
1009 | { | |
1010 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1011 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1012 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1013 | int UNUSED written = 0; | |
1014 | IADDR UNUSED pc = abuf->addr; | |
1015 | SEM_BRANCH_INIT | |
1016 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1017 | ||
1018 | if (NOTSI (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, FLD (f_rt))))) { | |
1019 | { | |
1020 | { | |
1021 | USI opval = FLD (i_offset); | |
1022 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1023 | written |= (1 << 3); | |
1024 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1025 | } | |
1026 | } | |
1027 | } | |
1028 | ||
1029 | abuf->written = written; | |
1030 | SEM_BRANCH_FINI (vpc); | |
1031 | #undef FLD | |
1032 | } | |
1033 | NEXT (vpc); | |
1034 | ||
1035 | CASE (sem, INSN_BBV) : /* bbv $rs,$rt,$offset */ | |
1036 | { | |
1037 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1038 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1039 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1040 | int UNUSED written = 0; | |
1041 | IADDR UNUSED pc = abuf->addr; | |
1042 | SEM_BRANCH_INIT | |
1043 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1044 | ||
1045 | if (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, ANDSI (GET_H_GR (FLD (f_rt)), 31)))) { | |
1046 | { | |
1047 | { | |
1048 | USI opval = FLD (i_offset); | |
1049 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1050 | written |= (1 << 3); | |
1051 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1052 | } | |
1053 | } | |
1054 | } | |
1055 | ||
1056 | abuf->written = written; | |
1057 | SEM_BRANCH_FINI (vpc); | |
1058 | #undef FLD | |
1059 | } | |
1060 | NEXT (vpc); | |
1061 | ||
1062 | CASE (sem, INSN_BBVN) : /* bbvn $rs,$rt,$offset */ | |
1063 | { | |
1064 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1065 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1066 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1067 | int UNUSED written = 0; | |
1068 | IADDR UNUSED pc = abuf->addr; | |
1069 | SEM_BRANCH_INIT | |
1070 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1071 | ||
1072 | if (NOTSI (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, ANDSI (GET_H_GR (FLD (f_rt)), 31))))) { | |
1073 | { | |
1074 | { | |
1075 | USI opval = FLD (i_offset); | |
1076 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1077 | written |= (1 << 3); | |
1078 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1079 | } | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | abuf->written = written; | |
1084 | SEM_BRANCH_FINI (vpc); | |
1085 | #undef FLD | |
1086 | } | |
1087 | NEXT (vpc); | |
1088 | ||
1089 | CASE (sem, INSN_BEQ) : /* beq $rs,$rt,$offset */ | |
1090 | { | |
1091 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1092 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1093 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1094 | int UNUSED written = 0; | |
1095 | IADDR UNUSED pc = abuf->addr; | |
1096 | SEM_BRANCH_INIT | |
1097 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1098 | ||
1099 | if (EQSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { | |
1100 | { | |
1101 | { | |
1102 | USI opval = FLD (i_offset); | |
1103 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1104 | written |= (1 << 3); | |
1105 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1106 | } | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | abuf->written = written; | |
1111 | SEM_BRANCH_FINI (vpc); | |
1112 | #undef FLD | |
1113 | } | |
1114 | NEXT (vpc); | |
1115 | ||
1116 | CASE (sem, INSN_BEQL) : /* beql $rs,$rt,$offset */ | |
1117 | { | |
1118 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1119 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1120 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1121 | int UNUSED written = 0; | |
1122 | IADDR UNUSED pc = abuf->addr; | |
1123 | SEM_BRANCH_INIT | |
1124 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1125 | ||
1126 | if (EQSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { | |
1127 | { | |
1128 | { | |
1129 | USI opval = FLD (i_offset); | |
1130 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1131 | written |= (1 << 3); | |
1132 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1133 | } | |
1134 | } | |
1135 | } else { | |
1136 | if (1) | |
1137 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
1138 | } | |
1139 | ||
1140 | abuf->written = written; | |
1141 | SEM_BRANCH_FINI (vpc); | |
1142 | #undef FLD | |
1143 | } | |
1144 | NEXT (vpc); | |
1145 | ||
1146 | CASE (sem, INSN_BGEZ) : /* bgez $rs,$offset */ | |
1147 | { | |
1148 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1149 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1150 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1151 | int UNUSED written = 0; | |
1152 | IADDR UNUSED pc = abuf->addr; | |
1153 | SEM_BRANCH_INIT | |
1154 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1155 | ||
1156 | if (GESI (GET_H_GR (FLD (f_rs)), 0)) { | |
1157 | { | |
1158 | { | |
1159 | USI opval = FLD (i_offset); | |
1160 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1161 | written |= (1 << 2); | |
1162 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1163 | } | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | abuf->written = written; | |
1168 | SEM_BRANCH_FINI (vpc); | |
1169 | #undef FLD | |
1170 | } | |
1171 | NEXT (vpc); | |
1172 | ||
1173 | CASE (sem, INSN_BGEZAL) : /* bgezal $rs,$offset */ | |
1174 | { | |
1175 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1176 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1177 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1178 | int UNUSED written = 0; | |
1179 | IADDR UNUSED pc = abuf->addr; | |
1180 | SEM_BRANCH_INIT | |
1181 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1182 | ||
1183 | if (GESI (GET_H_GR (FLD (f_rs)), 0)) { | |
1184 | { | |
1185 | { | |
1186 | SI opval = ADDSI (pc, 8); | |
1187 | SET_H_GR (((UINT) 31), opval); | |
1188 | written |= (1 << 3); | |
1189 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1190 | } | |
1191 | { | |
1192 | { | |
1193 | USI opval = FLD (i_offset); | |
1194 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1195 | written |= (1 << 4); | |
1196 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1197 | } | |
1198 | } | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | abuf->written = written; | |
1203 | SEM_BRANCH_FINI (vpc); | |
1204 | #undef FLD | |
1205 | } | |
1206 | NEXT (vpc); | |
1207 | ||
1208 | CASE (sem, INSN_BGEZALL) : /* bgezall $rs,$offset */ | |
1209 | { | |
1210 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1211 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1212 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1213 | int UNUSED written = 0; | |
1214 | IADDR UNUSED pc = abuf->addr; | |
1215 | SEM_BRANCH_INIT | |
1216 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1217 | ||
1218 | if (GESI (GET_H_GR (FLD (f_rs)), 0)) { | |
1219 | { | |
1220 | { | |
1221 | SI opval = ADDSI (pc, 8); | |
1222 | SET_H_GR (((UINT) 31), opval); | |
1223 | written |= (1 << 3); | |
1224 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1225 | } | |
1226 | { | |
1227 | { | |
1228 | USI opval = FLD (i_offset); | |
1229 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1230 | written |= (1 << 4); | |
1231 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1232 | } | |
1233 | } | |
1234 | } | |
1235 | } else { | |
1236 | if (1) | |
1237 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
1238 | } | |
1239 | ||
1240 | abuf->written = written; | |
1241 | SEM_BRANCH_FINI (vpc); | |
1242 | #undef FLD | |
1243 | } | |
1244 | NEXT (vpc); | |
1245 | ||
1246 | CASE (sem, INSN_BGEZL) : /* bgezl $rs,$offset */ | |
1247 | { | |
1248 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1249 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1250 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1251 | int UNUSED written = 0; | |
1252 | IADDR UNUSED pc = abuf->addr; | |
1253 | SEM_BRANCH_INIT | |
1254 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1255 | ||
1256 | if (GESI (GET_H_GR (FLD (f_rs)), 0)) { | |
1257 | { | |
1258 | { | |
1259 | USI opval = FLD (i_offset); | |
1260 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1261 | written |= (1 << 2); | |
1262 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1263 | } | |
1264 | } | |
1265 | } else { | |
1266 | if (1) | |
1267 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
1268 | } | |
1269 | ||
1270 | abuf->written = written; | |
1271 | SEM_BRANCH_FINI (vpc); | |
1272 | #undef FLD | |
1273 | } | |
1274 | NEXT (vpc); | |
1275 | ||
1276 | CASE (sem, INSN_BLTZ) : /* bltz $rs,$offset */ | |
1277 | { | |
1278 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1279 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1280 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1281 | int UNUSED written = 0; | |
1282 | IADDR UNUSED pc = abuf->addr; | |
1283 | SEM_BRANCH_INIT | |
1284 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1285 | ||
1286 | if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { | |
1287 | { | |
1288 | { | |
1289 | USI opval = FLD (i_offset); | |
1290 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1291 | written |= (1 << 2); | |
1292 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1293 | } | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | abuf->written = written; | |
1298 | SEM_BRANCH_FINI (vpc); | |
1299 | #undef FLD | |
1300 | } | |
1301 | NEXT (vpc); | |
1302 | ||
1303 | CASE (sem, INSN_BLTZL) : /* bltzl $rs,$offset */ | |
1304 | { | |
1305 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1306 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1307 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1308 | int UNUSED written = 0; | |
1309 | IADDR UNUSED pc = abuf->addr; | |
1310 | SEM_BRANCH_INIT | |
1311 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1312 | ||
1313 | if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { | |
1314 | { | |
1315 | { | |
1316 | USI opval = FLD (i_offset); | |
1317 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1318 | written |= (1 << 2); | |
1319 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1320 | } | |
1321 | } | |
1322 | } else { | |
1323 | if (1) | |
1324 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
1325 | } | |
1326 | ||
1327 | abuf->written = written; | |
1328 | SEM_BRANCH_FINI (vpc); | |
1329 | #undef FLD | |
1330 | } | |
1331 | NEXT (vpc); | |
1332 | ||
1333 | CASE (sem, INSN_BLTZAL) : /* bltzal $rs,$offset */ | |
1334 | { | |
1335 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1336 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1337 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1338 | int UNUSED written = 0; | |
1339 | IADDR UNUSED pc = abuf->addr; | |
1340 | SEM_BRANCH_INIT | |
1341 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1342 | ||
1343 | if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { | |
1344 | { | |
1345 | { | |
1346 | SI opval = ADDSI (pc, 8); | |
1347 | SET_H_GR (((UINT) 31), opval); | |
1348 | written |= (1 << 3); | |
1349 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1350 | } | |
1351 | { | |
1352 | { | |
1353 | USI opval = FLD (i_offset); | |
1354 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1355 | written |= (1 << 4); | |
1356 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1357 | } | |
1358 | } | |
1359 | } | |
1360 | } | |
1361 | ||
1362 | abuf->written = written; | |
1363 | SEM_BRANCH_FINI (vpc); | |
1364 | #undef FLD | |
1365 | } | |
1366 | NEXT (vpc); | |
1367 | ||
1368 | CASE (sem, INSN_BLTZALL) : /* bltzall $rs,$offset */ | |
1369 | { | |
1370 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1371 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1372 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1373 | int UNUSED written = 0; | |
1374 | IADDR UNUSED pc = abuf->addr; | |
1375 | SEM_BRANCH_INIT | |
1376 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1377 | ||
1378 | if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { | |
1379 | { | |
1380 | { | |
1381 | SI opval = ADDSI (pc, 8); | |
1382 | SET_H_GR (((UINT) 31), opval); | |
1383 | written |= (1 << 3); | |
1384 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1385 | } | |
1386 | { | |
1387 | { | |
1388 | USI opval = FLD (i_offset); | |
1389 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1390 | written |= (1 << 4); | |
1391 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1392 | } | |
1393 | } | |
1394 | } | |
1395 | } else { | |
1396 | if (1) | |
1397 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
1398 | } | |
1399 | ||
1400 | abuf->written = written; | |
1401 | SEM_BRANCH_FINI (vpc); | |
1402 | #undef FLD | |
1403 | } | |
1404 | NEXT (vpc); | |
1405 | ||
1406 | CASE (sem, INSN_BMB0) : /* bmb0 $rs,$rt,$offset */ | |
1407 | { | |
1408 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1409 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1410 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1411 | int UNUSED written = 0; | |
1412 | IADDR UNUSED pc = abuf->addr; | |
1413 | SEM_BRANCH_INIT | |
1414 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1415 | ||
1416 | if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 255), ANDSI (GET_H_GR (FLD (f_rt)), 255))) { | |
1417 | { | |
1418 | { | |
1419 | USI opval = FLD (i_offset); | |
1420 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1421 | written |= (1 << 3); | |
1422 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1423 | } | |
1424 | } | |
1425 | } | |
1426 | ||
1427 | abuf->written = written; | |
1428 | SEM_BRANCH_FINI (vpc); | |
1429 | #undef FLD | |
1430 | } | |
1431 | NEXT (vpc); | |
1432 | ||
1433 | CASE (sem, INSN_BMB1) : /* bmb1 $rs,$rt,$offset */ | |
1434 | { | |
1435 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1436 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1437 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1438 | int UNUSED written = 0; | |
1439 | IADDR UNUSED pc = abuf->addr; | |
1440 | SEM_BRANCH_INIT | |
1441 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1442 | ||
1443 | if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 65280), ANDSI (GET_H_GR (FLD (f_rt)), 65280))) { | |
1444 | { | |
1445 | { | |
1446 | USI opval = FLD (i_offset); | |
1447 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1448 | written |= (1 << 3); | |
1449 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1450 | } | |
1451 | } | |
1452 | } | |
1453 | ||
1454 | abuf->written = written; | |
1455 | SEM_BRANCH_FINI (vpc); | |
1456 | #undef FLD | |
1457 | } | |
1458 | NEXT (vpc); | |
1459 | ||
1460 | CASE (sem, INSN_BMB2) : /* bmb2 $rs,$rt,$offset */ | |
1461 | { | |
1462 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1463 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1464 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1465 | int UNUSED written = 0; | |
1466 | IADDR UNUSED pc = abuf->addr; | |
1467 | SEM_BRANCH_INIT | |
1468 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1469 | ||
1470 | if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 16711680), ANDSI (GET_H_GR (FLD (f_rt)), 16711680))) { | |
1471 | { | |
1472 | { | |
1473 | USI opval = FLD (i_offset); | |
1474 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1475 | written |= (1 << 3); | |
1476 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1477 | } | |
1478 | } | |
1479 | } | |
1480 | ||
1481 | abuf->written = written; | |
1482 | SEM_BRANCH_FINI (vpc); | |
1483 | #undef FLD | |
1484 | } | |
1485 | NEXT (vpc); | |
1486 | ||
1487 | CASE (sem, INSN_BMB3) : /* bmb3 $rs,$rt,$offset */ | |
1488 | { | |
1489 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1490 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1491 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1492 | int UNUSED written = 0; | |
1493 | IADDR UNUSED pc = abuf->addr; | |
1494 | SEM_BRANCH_INIT | |
1495 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1496 | ||
1497 | if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000), ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000))) { | |
1498 | { | |
1499 | { | |
1500 | USI opval = FLD (i_offset); | |
1501 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1502 | written |= (1 << 3); | |
1503 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1504 | } | |
1505 | } | |
1506 | } | |
1507 | ||
1508 | abuf->written = written; | |
1509 | SEM_BRANCH_FINI (vpc); | |
1510 | #undef FLD | |
1511 | } | |
1512 | NEXT (vpc); | |
1513 | ||
1514 | CASE (sem, INSN_BNE) : /* bne $rs,$rt,$offset */ | |
1515 | { | |
1516 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1517 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1518 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1519 | int UNUSED written = 0; | |
1520 | IADDR UNUSED pc = abuf->addr; | |
1521 | SEM_BRANCH_INIT | |
1522 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1523 | ||
1524 | if (NESI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { | |
1525 | { | |
1526 | { | |
1527 | USI opval = FLD (i_offset); | |
1528 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1529 | written |= (1 << 3); | |
1530 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1531 | } | |
1532 | } | |
1533 | } | |
1534 | ||
1535 | abuf->written = written; | |
1536 | SEM_BRANCH_FINI (vpc); | |
1537 | #undef FLD | |
1538 | } | |
1539 | NEXT (vpc); | |
1540 | ||
1541 | CASE (sem, INSN_BNEL) : /* bnel $rs,$rt,$offset */ | |
1542 | { | |
1543 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1544 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1545 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1546 | int UNUSED written = 0; | |
1547 | IADDR UNUSED pc = abuf->addr; | |
1548 | SEM_BRANCH_INIT | |
1549 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1550 | ||
1551 | if (NESI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { | |
1552 | { | |
1553 | { | |
1554 | USI opval = FLD (i_offset); | |
1555 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1556 | written |= (1 << 3); | |
1557 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1558 | } | |
1559 | } | |
1560 | } else { | |
1561 | if (1) | |
1562 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
1563 | } | |
1564 | ||
1565 | abuf->written = written; | |
1566 | SEM_BRANCH_FINI (vpc); | |
1567 | #undef FLD | |
1568 | } | |
1569 | NEXT (vpc); | |
1570 | ||
1571 | CASE (sem, INSN_JALR) : /* jalr $rd,$rs */ | |
1572 | { | |
1573 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1574 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1575 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
1576 | int UNUSED written = 0; | |
1577 | IADDR UNUSED pc = abuf->addr; | |
1578 | SEM_BRANCH_INIT | |
1579 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1580 | ||
1581 | { | |
1582 | { | |
1583 | { | |
1584 | SI opval = ADDSI (pc, 8); | |
1585 | SET_H_GR (FLD (f_rd), opval); | |
1586 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1587 | } | |
1588 | { | |
1589 | USI opval = GET_H_GR (FLD (f_rs)); | |
1590 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
1591 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1592 | } | |
1593 | } | |
1594 | } | |
1595 | ||
1596 | SEM_BRANCH_FINI (vpc); | |
1597 | #undef FLD | |
1598 | } | |
1599 | NEXT (vpc); | |
1600 | ||
1601 | CASE (sem, INSN_JR) : /* jr $rs */ | |
1602 | { | |
1603 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1604 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1605 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1606 | int UNUSED written = 0; | |
1607 | IADDR UNUSED pc = abuf->addr; | |
1608 | SEM_BRANCH_INIT | |
1609 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1610 | ||
1611 | { | |
1612 | { | |
1613 | USI opval = GET_H_GR (FLD (f_rs)); | |
1614 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
1615 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1616 | } | |
1617 | } | |
1618 | ||
1619 | SEM_BRANCH_FINI (vpc); | |
1620 | #undef FLD | |
1621 | } | |
1622 | NEXT (vpc); | |
1623 | ||
1624 | CASE (sem, INSN_LB) : /* lb $rt,$lo16($base) */ | |
1625 | { | |
1626 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1627 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1628 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1629 | int UNUSED written = 0; | |
1630 | IADDR UNUSED pc = abuf->addr; | |
1631 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1632 | ||
1633 | { | |
1634 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); | |
1635 | SET_H_GR (FLD (f_rt), opval); | |
1636 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1637 | } | |
1638 | ||
1639 | #undef FLD | |
1640 | } | |
1641 | NEXT (vpc); | |
1642 | ||
1643 | CASE (sem, INSN_LBU) : /* lbu $rt,$lo16($base) */ | |
1644 | { | |
1645 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1646 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1647 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1648 | int UNUSED written = 0; | |
1649 | IADDR UNUSED pc = abuf->addr; | |
1650 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1651 | ||
1652 | { | |
1653 | SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); | |
1654 | SET_H_GR (FLD (f_rt), opval); | |
1655 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1656 | } | |
1657 | ||
1658 | #undef FLD | |
1659 | } | |
1660 | NEXT (vpc); | |
1661 | ||
1662 | CASE (sem, INSN_LH) : /* lh $rt,$lo16($base) */ | |
1663 | { | |
1664 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1665 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1666 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1667 | int UNUSED written = 0; | |
1668 | IADDR UNUSED pc = abuf->addr; | |
1669 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1670 | ||
1671 | { | |
1672 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); | |
1673 | SET_H_GR (FLD (f_rt), opval); | |
1674 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1675 | } | |
1676 | ||
1677 | #undef FLD | |
1678 | } | |
1679 | NEXT (vpc); | |
1680 | ||
1681 | CASE (sem, INSN_LHU) : /* lhu $rt,$lo16($base) */ | |
1682 | { | |
1683 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1684 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1685 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1686 | int UNUSED written = 0; | |
1687 | IADDR UNUSED pc = abuf->addr; | |
1688 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1689 | ||
1690 | { | |
1691 | SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); | |
1692 | SET_H_GR (FLD (f_rt), opval); | |
1693 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1694 | } | |
1695 | ||
1696 | #undef FLD | |
1697 | } | |
1698 | NEXT (vpc); | |
1699 | ||
1700 | CASE (sem, INSN_LUI) : /* lui $rt,$hi16 */ | |
1701 | { | |
1702 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1703 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1704 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1705 | int UNUSED written = 0; | |
1706 | IADDR UNUSED pc = abuf->addr; | |
1707 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1708 | ||
1709 | { | |
1710 | SI opval = SLLSI (FLD (f_imm), 16); | |
1711 | SET_H_GR (FLD (f_rt), opval); | |
1712 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1713 | } | |
1714 | ||
1715 | #undef FLD | |
1716 | } | |
1717 | NEXT (vpc); | |
1718 | ||
1719 | CASE (sem, INSN_LW) : /* lw $rt,$lo16($base) */ | |
1720 | { | |
1721 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1722 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1723 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1724 | int UNUSED written = 0; | |
1725 | IADDR UNUSED pc = abuf->addr; | |
1726 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1727 | ||
1728 | { | |
1729 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))); | |
1730 | SET_H_GR (FLD (f_rt), opval); | |
1731 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1732 | } | |
1733 | ||
1734 | #undef FLD | |
1735 | } | |
1736 | NEXT (vpc); | |
1737 | ||
1738 | CASE (sem, INSN_SB) : /* sb $rt,$lo16($base) */ | |
1739 | { | |
1740 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1741 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1742 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1743 | int UNUSED written = 0; | |
1744 | IADDR UNUSED pc = abuf->addr; | |
1745 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1746 | ||
1747 | { | |
1748 | QI opval = ANDQI (GET_H_GR (FLD (f_rt)), 255); | |
1749 | SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); | |
1750 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
1751 | } | |
1752 | ||
1753 | #undef FLD | |
1754 | } | |
1755 | NEXT (vpc); | |
1756 | ||
1757 | CASE (sem, INSN_SH) : /* sh $rt,$lo16($base) */ | |
1758 | { | |
1759 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1760 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1761 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1762 | int UNUSED written = 0; | |
1763 | IADDR UNUSED pc = abuf->addr; | |
1764 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1765 | ||
1766 | { | |
1767 | HI opval = ANDHI (GET_H_GR (FLD (f_rt)), 65535); | |
1768 | SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); | |
1769 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
1770 | } | |
1771 | ||
1772 | #undef FLD | |
1773 | } | |
1774 | NEXT (vpc); | |
1775 | ||
1776 | CASE (sem, INSN_SW) : /* sw $rt,$lo16($base) */ | |
1777 | { | |
1778 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1779 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1780 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1781 | int UNUSED written = 0; | |
1782 | IADDR UNUSED pc = abuf->addr; | |
1783 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1784 | ||
1785 | { | |
1786 | SI opval = GET_H_GR (FLD (f_rt)); | |
1787 | SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); | |
1788 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
1789 | } | |
1790 | ||
1791 | #undef FLD | |
1792 | } | |
1793 | NEXT (vpc); | |
1794 | ||
1795 | CASE (sem, INSN_BREAK) : /* break */ | |
1796 | { | |
1797 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1798 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1799 | #define FLD(f) abuf->fields.fmt_empty.f | |
1800 | int UNUSED written = 0; | |
1801 | IADDR UNUSED pc = abuf->addr; | |
1802 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1803 | ||
1804 | do_break (current_cpu, pc); | |
1805 | ||
1806 | #undef FLD | |
1807 | } | |
1808 | NEXT (vpc); | |
1809 | ||
1810 | CASE (sem, INSN_SYSCALL) : /* syscall */ | |
1811 | { | |
1812 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1813 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1814 | #define FLD(f) abuf->fields.fmt_empty.f | |
1815 | int UNUSED written = 0; | |
1816 | IADDR UNUSED pc = abuf->addr; | |
1817 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1818 | ||
1819 | do_syscall (current_cpu); | |
1820 | ||
1821 | #undef FLD | |
1822 | } | |
1823 | NEXT (vpc); | |
1824 | ||
1825 | CASE (sem, INSN_ANDOUI) : /* andoui $rt,$rs,$hi16 */ | |
1826 | { | |
1827 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1828 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1829 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1830 | int UNUSED written = 0; | |
1831 | IADDR UNUSED pc = abuf->addr; | |
1832 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1833 | ||
1834 | { | |
1835 | SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (SLLSI (FLD (f_imm), 16), 65535)); | |
1836 | SET_H_GR (FLD (f_rt), opval); | |
1837 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1838 | } | |
1839 | ||
1840 | #undef FLD | |
1841 | } | |
1842 | NEXT (vpc); | |
1843 | ||
1844 | CASE (sem, INSN_ORUI) : /* orui $rt,$rs,$hi16 */ | |
1845 | { | |
1846 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1847 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1848 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1849 | int UNUSED written = 0; | |
1850 | IADDR UNUSED pc = abuf->addr; | |
1851 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1852 | ||
1853 | { | |
1854 | SI opval = ORSI (GET_H_GR (FLD (f_rs)), SLLSI (FLD (f_imm), 16)); | |
1855 | SET_H_GR (FLD (f_rt), opval); | |
1856 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1857 | } | |
1858 | ||
1859 | #undef FLD | |
1860 | } | |
1861 | NEXT (vpc); | |
1862 | ||
1863 | CASE (sem, INSN_BGTZ) : /* bgtz $rs,$offset */ | |
1864 | { | |
1865 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1866 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1867 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1868 | int UNUSED written = 0; | |
1869 | IADDR UNUSED pc = abuf->addr; | |
1870 | SEM_BRANCH_INIT | |
1871 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1872 | ||
1873 | if (GTSI (GET_H_GR (FLD (f_rs)), 0)) { | |
1874 | { | |
1875 | { | |
1876 | USI opval = FLD (i_offset); | |
1877 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1878 | written |= (1 << 2); | |
1879 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1880 | } | |
1881 | } | |
1882 | } | |
1883 | ||
1884 | abuf->written = written; | |
1885 | SEM_BRANCH_FINI (vpc); | |
1886 | #undef FLD | |
1887 | } | |
1888 | NEXT (vpc); | |
1889 | ||
1890 | CASE (sem, INSN_BGTZL) : /* bgtzl $rs,$offset */ | |
1891 | { | |
1892 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1893 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1894 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1895 | int UNUSED written = 0; | |
1896 | IADDR UNUSED pc = abuf->addr; | |
1897 | SEM_BRANCH_INIT | |
1898 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1899 | ||
1900 | if (GTSI (GET_H_GR (FLD (f_rs)), 0)) { | |
1901 | { | |
1902 | { | |
1903 | USI opval = FLD (i_offset); | |
1904 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1905 | written |= (1 << 2); | |
1906 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1907 | } | |
1908 | } | |
1909 | } else { | |
1910 | if (1) | |
1911 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
1912 | } | |
1913 | ||
1914 | abuf->written = written; | |
1915 | SEM_BRANCH_FINI (vpc); | |
1916 | #undef FLD | |
1917 | } | |
1918 | NEXT (vpc); | |
1919 | ||
1920 | CASE (sem, INSN_BLEZ) : /* blez $rs,$offset */ | |
1921 | { | |
1922 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1923 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1924 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1925 | int UNUSED written = 0; | |
1926 | IADDR UNUSED pc = abuf->addr; | |
1927 | SEM_BRANCH_INIT | |
1928 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1929 | ||
1930 | if (LESI (GET_H_GR (FLD (f_rs)), 0)) { | |
1931 | { | |
1932 | { | |
1933 | USI opval = FLD (i_offset); | |
1934 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1935 | written |= (1 << 2); | |
1936 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1937 | } | |
1938 | } | |
1939 | } | |
1940 | ||
1941 | abuf->written = written; | |
1942 | SEM_BRANCH_FINI (vpc); | |
1943 | #undef FLD | |
1944 | } | |
1945 | NEXT (vpc); | |
1946 | ||
1947 | CASE (sem, INSN_BLEZL) : /* blezl $rs,$offset */ | |
1948 | { | |
1949 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1950 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1951 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
1952 | int UNUSED written = 0; | |
1953 | IADDR UNUSED pc = abuf->addr; | |
1954 | SEM_BRANCH_INIT | |
1955 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1956 | ||
1957 | if (LESI (GET_H_GR (FLD (f_rs)), 0)) { | |
1958 | { | |
1959 | { | |
1960 | USI opval = FLD (i_offset); | |
1961 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1962 | written |= (1 << 2); | |
1963 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1964 | } | |
1965 | } | |
1966 | } else { | |
1967 | if (1) | |
1968 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
1969 | } | |
1970 | ||
1971 | abuf->written = written; | |
1972 | SEM_BRANCH_FINI (vpc); | |
1973 | #undef FLD | |
1974 | } | |
1975 | NEXT (vpc); | |
1976 | ||
1977 | CASE (sem, INSN_MRGB) : /* mrgb $rd,$rs,$rt,$mask */ | |
1978 | { | |
1979 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1980 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1981 | #define FLD(f) abuf->fields.sfmt_mrgb.f | |
1982 | int UNUSED written = 0; | |
1983 | IADDR UNUSED pc = abuf->addr; | |
1984 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1985 | ||
1986 | { | |
1987 | SI tmp_temp; | |
1988 | if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 0)))) { | |
1989 | tmp_temp = ANDSI (GET_H_GR (FLD (f_rs)), 255); | |
1990 | } else { | |
1991 | tmp_temp = ANDSI (GET_H_GR (FLD (f_rt)), 255); | |
1992 | } | |
1993 | if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 1)))) { | |
1994 | tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 65280)); | |
1995 | } else { | |
1996 | tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 65280)); | |
1997 | } | |
1998 | if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 2)))) { | |
1999 | tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 16711680)); | |
2000 | } else { | |
2001 | tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 16711680)); | |
2002 | } | |
2003 | if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 3)))) { | |
2004 | tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000)); | |
2005 | } else { | |
2006 | tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000)); | |
2007 | } | |
2008 | { | |
2009 | SI opval = tmp_temp; | |
2010 | SET_H_GR (FLD (f_rd), opval); | |
2011 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2012 | } | |
2013 | } | |
2014 | ||
2015 | #undef FLD | |
2016 | } | |
2017 | NEXT (vpc); | |
2018 | ||
2019 | CASE (sem, INSN_BCTXT) : /* bctxt $rs,$offset */ | |
2020 | { | |
2021 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2022 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2023 | #define FLD(f) abuf->fields.fmt_empty.f | |
2024 | int UNUSED written = 0; | |
2025 | IADDR UNUSED pc = abuf->addr; | |
2026 | SEM_BRANCH_INIT | |
2027 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2028 | ||
2029 | ((void) 0); /*nop*/ | |
2030 | ||
2031 | SEM_BRANCH_FINI (vpc); | |
2032 | #undef FLD | |
2033 | } | |
2034 | NEXT (vpc); | |
2035 | ||
2036 | CASE (sem, INSN_BC0F) : /* bc0f $offset */ | |
2037 | { | |
2038 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2039 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2040 | #define FLD(f) abuf->fields.fmt_empty.f | |
2041 | int UNUSED written = 0; | |
2042 | IADDR UNUSED pc = abuf->addr; | |
2043 | SEM_BRANCH_INIT | |
2044 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2045 | ||
2046 | ((void) 0); /*nop*/ | |
2047 | ||
2048 | SEM_BRANCH_FINI (vpc); | |
2049 | #undef FLD | |
2050 | } | |
2051 | NEXT (vpc); | |
2052 | ||
2053 | CASE (sem, INSN_BC0FL) : /* bc0fl $offset */ | |
2054 | { | |
2055 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2056 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2057 | #define FLD(f) abuf->fields.fmt_empty.f | |
2058 | int UNUSED written = 0; | |
2059 | IADDR UNUSED pc = abuf->addr; | |
2060 | SEM_BRANCH_INIT | |
2061 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2062 | ||
2063 | ((void) 0); /*nop*/ | |
2064 | ||
2065 | SEM_BRANCH_FINI (vpc); | |
2066 | #undef FLD | |
2067 | } | |
2068 | NEXT (vpc); | |
2069 | ||
2070 | CASE (sem, INSN_BC3F) : /* bc3f $offset */ | |
2071 | { | |
2072 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2073 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2074 | #define FLD(f) abuf->fields.fmt_empty.f | |
2075 | int UNUSED written = 0; | |
2076 | IADDR UNUSED pc = abuf->addr; | |
2077 | SEM_BRANCH_INIT | |
2078 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2079 | ||
2080 | ((void) 0); /*nop*/ | |
2081 | ||
2082 | SEM_BRANCH_FINI (vpc); | |
2083 | #undef FLD | |
2084 | } | |
2085 | NEXT (vpc); | |
2086 | ||
2087 | CASE (sem, INSN_BC3FL) : /* bc3fl $offset */ | |
2088 | { | |
2089 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2090 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2091 | #define FLD(f) abuf->fields.fmt_empty.f | |
2092 | int UNUSED written = 0; | |
2093 | IADDR UNUSED pc = abuf->addr; | |
2094 | SEM_BRANCH_INIT | |
2095 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2096 | ||
2097 | ((void) 0); /*nop*/ | |
2098 | ||
2099 | SEM_BRANCH_FINI (vpc); | |
2100 | #undef FLD | |
2101 | } | |
2102 | NEXT (vpc); | |
2103 | ||
2104 | CASE (sem, INSN_BC0T) : /* bc0t $offset */ | |
2105 | { | |
2106 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2107 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2108 | #define FLD(f) abuf->fields.fmt_empty.f | |
2109 | int UNUSED written = 0; | |
2110 | IADDR UNUSED pc = abuf->addr; | |
2111 | SEM_BRANCH_INIT | |
2112 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2113 | ||
2114 | ((void) 0); /*nop*/ | |
2115 | ||
2116 | SEM_BRANCH_FINI (vpc); | |
2117 | #undef FLD | |
2118 | } | |
2119 | NEXT (vpc); | |
2120 | ||
2121 | CASE (sem, INSN_BC0TL) : /* bc0tl $offset */ | |
2122 | { | |
2123 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2124 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2125 | #define FLD(f) abuf->fields.fmt_empty.f | |
2126 | int UNUSED written = 0; | |
2127 | IADDR UNUSED pc = abuf->addr; | |
2128 | SEM_BRANCH_INIT | |
2129 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2130 | ||
2131 | ((void) 0); /*nop*/ | |
2132 | ||
2133 | SEM_BRANCH_FINI (vpc); | |
2134 | #undef FLD | |
2135 | } | |
2136 | NEXT (vpc); | |
2137 | ||
2138 | CASE (sem, INSN_BC3T) : /* bc3t $offset */ | |
2139 | { | |
2140 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2141 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2142 | #define FLD(f) abuf->fields.fmt_empty.f | |
2143 | int UNUSED written = 0; | |
2144 | IADDR UNUSED pc = abuf->addr; | |
2145 | SEM_BRANCH_INIT | |
2146 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2147 | ||
2148 | ((void) 0); /*nop*/ | |
2149 | ||
2150 | SEM_BRANCH_FINI (vpc); | |
2151 | #undef FLD | |
2152 | } | |
2153 | NEXT (vpc); | |
2154 | ||
2155 | CASE (sem, INSN_BC3TL) : /* bc3tl $offset */ | |
2156 | { | |
2157 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2158 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2159 | #define FLD(f) abuf->fields.fmt_empty.f | |
2160 | int UNUSED written = 0; | |
2161 | IADDR UNUSED pc = abuf->addr; | |
2162 | SEM_BRANCH_INIT | |
2163 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2164 | ||
2165 | ((void) 0); /*nop*/ | |
2166 | ||
2167 | SEM_BRANCH_FINI (vpc); | |
2168 | #undef FLD | |
2169 | } | |
2170 | NEXT (vpc); | |
2171 | ||
2172 | CASE (sem, INSN_CFC0) : /* cfc0 $rt,$rd */ | |
2173 | { | |
2174 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2175 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2176 | #define FLD(f) abuf->fields.fmt_empty.f | |
2177 | int UNUSED written = 0; | |
2178 | IADDR UNUSED pc = abuf->addr; | |
2179 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2180 | ||
2181 | ((void) 0); /*nop*/ | |
2182 | ||
2183 | #undef FLD | |
2184 | } | |
2185 | NEXT (vpc); | |
2186 | ||
2187 | CASE (sem, INSN_CFC1) : /* cfc1 $rt,$rd */ | |
2188 | { | |
2189 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2190 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2191 | #define FLD(f) abuf->fields.fmt_empty.f | |
2192 | int UNUSED written = 0; | |
2193 | IADDR UNUSED pc = abuf->addr; | |
2194 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2195 | ||
2196 | ((void) 0); /*nop*/ | |
2197 | ||
2198 | #undef FLD | |
2199 | } | |
2200 | NEXT (vpc); | |
2201 | ||
2202 | CASE (sem, INSN_CFC2) : /* cfc2 $rt,$rd */ | |
2203 | { | |
2204 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2205 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2206 | #define FLD(f) abuf->fields.fmt_empty.f | |
2207 | int UNUSED written = 0; | |
2208 | IADDR UNUSED pc = abuf->addr; | |
2209 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2210 | ||
2211 | ((void) 0); /*nop*/ | |
2212 | ||
2213 | #undef FLD | |
2214 | } | |
2215 | NEXT (vpc); | |
2216 | ||
2217 | CASE (sem, INSN_CFC3) : /* cfc3 $rt,$rd */ | |
2218 | { | |
2219 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2220 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2221 | #define FLD(f) abuf->fields.fmt_empty.f | |
2222 | int UNUSED written = 0; | |
2223 | IADDR UNUSED pc = abuf->addr; | |
2224 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2225 | ||
2226 | ((void) 0); /*nop*/ | |
2227 | ||
2228 | #undef FLD | |
2229 | } | |
2230 | NEXT (vpc); | |
2231 | ||
2232 | CASE (sem, INSN_CHKHDR) : /* chkhdr $rd,$rt */ | |
2233 | { | |
2234 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2235 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2236 | #define FLD(f) abuf->fields.fmt_empty.f | |
2237 | int UNUSED written = 0; | |
2238 | IADDR UNUSED pc = abuf->addr; | |
2239 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2240 | ||
2241 | ((void) 0); /*nop*/ | |
2242 | ||
2243 | #undef FLD | |
2244 | } | |
2245 | NEXT (vpc); | |
2246 | ||
2247 | CASE (sem, INSN_CTC0) : /* ctc0 $rt,$rd */ | |
2248 | { | |
2249 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2250 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2251 | #define FLD(f) abuf->fields.fmt_empty.f | |
2252 | int UNUSED written = 0; | |
2253 | IADDR UNUSED pc = abuf->addr; | |
2254 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2255 | ||
2256 | ((void) 0); /*nop*/ | |
2257 | ||
2258 | #undef FLD | |
2259 | } | |
2260 | NEXT (vpc); | |
2261 | ||
2262 | CASE (sem, INSN_CTC1) : /* ctc1 $rt,$rd */ | |
2263 | { | |
2264 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2265 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2266 | #define FLD(f) abuf->fields.fmt_empty.f | |
2267 | int UNUSED written = 0; | |
2268 | IADDR UNUSED pc = abuf->addr; | |
2269 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2270 | ||
2271 | ((void) 0); /*nop*/ | |
2272 | ||
2273 | #undef FLD | |
2274 | } | |
2275 | NEXT (vpc); | |
2276 | ||
2277 | CASE (sem, INSN_CTC2) : /* ctc2 $rt,$rd */ | |
2278 | { | |
2279 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2280 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2281 | #define FLD(f) abuf->fields.fmt_empty.f | |
2282 | int UNUSED written = 0; | |
2283 | IADDR UNUSED pc = abuf->addr; | |
2284 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2285 | ||
2286 | ((void) 0); /*nop*/ | |
2287 | ||
2288 | #undef FLD | |
2289 | } | |
2290 | NEXT (vpc); | |
2291 | ||
2292 | CASE (sem, INSN_CTC3) : /* ctc3 $rt,$rd */ | |
2293 | { | |
2294 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2295 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2296 | #define FLD(f) abuf->fields.fmt_empty.f | |
2297 | int UNUSED written = 0; | |
2298 | IADDR UNUSED pc = abuf->addr; | |
2299 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2300 | ||
2301 | ((void) 0); /*nop*/ | |
2302 | ||
2303 | #undef FLD | |
2304 | } | |
2305 | NEXT (vpc); | |
2306 | ||
2307 | CASE (sem, INSN_JCR) : /* jcr $rs */ | |
2308 | { | |
2309 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2310 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2311 | #define FLD(f) abuf->fields.fmt_empty.f | |
2312 | int UNUSED written = 0; | |
2313 | IADDR UNUSED pc = abuf->addr; | |
2314 | SEM_BRANCH_INIT | |
2315 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2316 | ||
2317 | ((void) 0); /*nop*/ | |
2318 | ||
2319 | SEM_BRANCH_FINI (vpc); | |
2320 | #undef FLD | |
2321 | } | |
2322 | NEXT (vpc); | |
2323 | ||
2324 | CASE (sem, INSN_LUC32) : /* luc32 $rt,$rd */ | |
2325 | { | |
2326 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2327 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2328 | #define FLD(f) abuf->fields.fmt_empty.f | |
2329 | int UNUSED written = 0; | |
2330 | IADDR UNUSED pc = abuf->addr; | |
2331 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2332 | ||
2333 | ((void) 0); /*nop*/ | |
2334 | ||
2335 | #undef FLD | |
2336 | } | |
2337 | NEXT (vpc); | |
2338 | ||
2339 | CASE (sem, INSN_LUC32L) : /* luc32l $rt,$rd */ | |
2340 | { | |
2341 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2342 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2343 | #define FLD(f) abuf->fields.fmt_empty.f | |
2344 | int UNUSED written = 0; | |
2345 | IADDR UNUSED pc = abuf->addr; | |
2346 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2347 | ||
2348 | ((void) 0); /*nop*/ | |
2349 | ||
2350 | #undef FLD | |
2351 | } | |
2352 | NEXT (vpc); | |
2353 | ||
2354 | CASE (sem, INSN_LUC64) : /* luc64 $rt,$rd */ | |
2355 | { | |
2356 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2357 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2358 | #define FLD(f) abuf->fields.fmt_empty.f | |
2359 | int UNUSED written = 0; | |
2360 | IADDR UNUSED pc = abuf->addr; | |
2361 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2362 | ||
2363 | ((void) 0); /*nop*/ | |
2364 | ||
2365 | #undef FLD | |
2366 | } | |
2367 | NEXT (vpc); | |
2368 | ||
2369 | CASE (sem, INSN_LUC64L) : /* luc64l $rt,$rd */ | |
2370 | { | |
2371 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2372 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2373 | #define FLD(f) abuf->fields.fmt_empty.f | |
2374 | int UNUSED written = 0; | |
2375 | IADDR UNUSED pc = abuf->addr; | |
2376 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2377 | ||
2378 | ((void) 0); /*nop*/ | |
2379 | ||
2380 | #undef FLD | |
2381 | } | |
2382 | NEXT (vpc); | |
2383 | ||
2384 | CASE (sem, INSN_LUK) : /* luk $rt,$rd */ | |
2385 | { | |
2386 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2387 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2388 | #define FLD(f) abuf->fields.fmt_empty.f | |
2389 | int UNUSED written = 0; | |
2390 | IADDR UNUSED pc = abuf->addr; | |
2391 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2392 | ||
2393 | ((void) 0); /*nop*/ | |
2394 | ||
2395 | #undef FLD | |
2396 | } | |
2397 | NEXT (vpc); | |
2398 | ||
2399 | CASE (sem, INSN_LULCK) : /* lulck $rt */ | |
2400 | { | |
2401 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2402 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2403 | #define FLD(f) abuf->fields.fmt_empty.f | |
2404 | int UNUSED written = 0; | |
2405 | IADDR UNUSED pc = abuf->addr; | |
2406 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2407 | ||
2408 | ((void) 0); /*nop*/ | |
2409 | ||
2410 | #undef FLD | |
2411 | } | |
2412 | NEXT (vpc); | |
2413 | ||
2414 | CASE (sem, INSN_LUM32) : /* lum32 $rt,$rd */ | |
2415 | { | |
2416 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2417 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2418 | #define FLD(f) abuf->fields.fmt_empty.f | |
2419 | int UNUSED written = 0; | |
2420 | IADDR UNUSED pc = abuf->addr; | |
2421 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2422 | ||
2423 | ((void) 0); /*nop*/ | |
2424 | ||
2425 | #undef FLD | |
2426 | } | |
2427 | NEXT (vpc); | |
2428 | ||
2429 | CASE (sem, INSN_LUM32L) : /* lum32l $rt,$rd */ | |
2430 | { | |
2431 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2432 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2433 | #define FLD(f) abuf->fields.fmt_empty.f | |
2434 | int UNUSED written = 0; | |
2435 | IADDR UNUSED pc = abuf->addr; | |
2436 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2437 | ||
2438 | ((void) 0); /*nop*/ | |
2439 | ||
2440 | #undef FLD | |
2441 | } | |
2442 | NEXT (vpc); | |
2443 | ||
2444 | CASE (sem, INSN_LUM64) : /* lum64 $rt,$rd */ | |
2445 | { | |
2446 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2447 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2448 | #define FLD(f) abuf->fields.fmt_empty.f | |
2449 | int UNUSED written = 0; | |
2450 | IADDR UNUSED pc = abuf->addr; | |
2451 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2452 | ||
2453 | ((void) 0); /*nop*/ | |
2454 | ||
2455 | #undef FLD | |
2456 | } | |
2457 | NEXT (vpc); | |
2458 | ||
2459 | CASE (sem, INSN_LUM64L) : /* lum64l $rt,$rd */ | |
2460 | { | |
2461 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2462 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2463 | #define FLD(f) abuf->fields.fmt_empty.f | |
2464 | int UNUSED written = 0; | |
2465 | IADDR UNUSED pc = abuf->addr; | |
2466 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2467 | ||
2468 | ((void) 0); /*nop*/ | |
2469 | ||
2470 | #undef FLD | |
2471 | } | |
2472 | NEXT (vpc); | |
2473 | ||
2474 | CASE (sem, INSN_LUR) : /* lur $rt,$rd */ | |
2475 | { | |
2476 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2477 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2478 | #define FLD(f) abuf->fields.fmt_empty.f | |
2479 | int UNUSED written = 0; | |
2480 | IADDR UNUSED pc = abuf->addr; | |
2481 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2482 | ||
2483 | ((void) 0); /*nop*/ | |
2484 | ||
2485 | #undef FLD | |
2486 | } | |
2487 | NEXT (vpc); | |
2488 | ||
2489 | CASE (sem, INSN_LURL) : /* lurl $rt,$rd */ | |
2490 | { | |
2491 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2492 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2493 | #define FLD(f) abuf->fields.fmt_empty.f | |
2494 | int UNUSED written = 0; | |
2495 | IADDR UNUSED pc = abuf->addr; | |
2496 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2497 | ||
2498 | ((void) 0); /*nop*/ | |
2499 | ||
2500 | #undef FLD | |
2501 | } | |
2502 | NEXT (vpc); | |
2503 | ||
2504 | CASE (sem, INSN_LUULCK) : /* luulck $rt */ | |
2505 | { | |
2506 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2507 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2508 | #define FLD(f) abuf->fields.fmt_empty.f | |
2509 | int UNUSED written = 0; | |
2510 | IADDR UNUSED pc = abuf->addr; | |
2511 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2512 | ||
2513 | ((void) 0); /*nop*/ | |
2514 | ||
2515 | #undef FLD | |
2516 | } | |
2517 | NEXT (vpc); | |
2518 | ||
2519 | CASE (sem, INSN_MFC0) : /* mfc0 $rt,$rd */ | |
2520 | { | |
2521 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2522 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2523 | #define FLD(f) abuf->fields.fmt_empty.f | |
2524 | int UNUSED written = 0; | |
2525 | IADDR UNUSED pc = abuf->addr; | |
2526 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2527 | ||
2528 | ((void) 0); /*nop*/ | |
2529 | ||
2530 | #undef FLD | |
2531 | } | |
2532 | NEXT (vpc); | |
2533 | ||
2534 | CASE (sem, INSN_MFC1) : /* mfc1 $rt,$rd */ | |
2535 | { | |
2536 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2537 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2538 | #define FLD(f) abuf->fields.fmt_empty.f | |
2539 | int UNUSED written = 0; | |
2540 | IADDR UNUSED pc = abuf->addr; | |
2541 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2542 | ||
2543 | ((void) 0); /*nop*/ | |
2544 | ||
2545 | #undef FLD | |
2546 | } | |
2547 | NEXT (vpc); | |
2548 | ||
2549 | CASE (sem, INSN_MFC2) : /* mfc2 $rt,$rd */ | |
2550 | { | |
2551 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2552 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2553 | #define FLD(f) abuf->fields.fmt_empty.f | |
2554 | int UNUSED written = 0; | |
2555 | IADDR UNUSED pc = abuf->addr; | |
2556 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2557 | ||
2558 | ((void) 0); /*nop*/ | |
2559 | ||
2560 | #undef FLD | |
2561 | } | |
2562 | NEXT (vpc); | |
2563 | ||
2564 | CASE (sem, INSN_MFC3) : /* mfc3 $rt,$rd */ | |
2565 | { | |
2566 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2567 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2568 | #define FLD(f) abuf->fields.fmt_empty.f | |
2569 | int UNUSED written = 0; | |
2570 | IADDR UNUSED pc = abuf->addr; | |
2571 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2572 | ||
2573 | ((void) 0); /*nop*/ | |
2574 | ||
2575 | #undef FLD | |
2576 | } | |
2577 | NEXT (vpc); | |
2578 | ||
2579 | CASE (sem, INSN_MTC0) : /* mtc0 $rt,$rd */ | |
2580 | { | |
2581 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2582 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2583 | #define FLD(f) abuf->fields.fmt_empty.f | |
2584 | int UNUSED written = 0; | |
2585 | IADDR UNUSED pc = abuf->addr; | |
2586 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2587 | ||
2588 | ((void) 0); /*nop*/ | |
2589 | ||
2590 | #undef FLD | |
2591 | } | |
2592 | NEXT (vpc); | |
2593 | ||
2594 | CASE (sem, INSN_MTC1) : /* mtc1 $rt,$rd */ | |
2595 | { | |
2596 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2597 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2598 | #define FLD(f) abuf->fields.fmt_empty.f | |
2599 | int UNUSED written = 0; | |
2600 | IADDR UNUSED pc = abuf->addr; | |
2601 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2602 | ||
2603 | ((void) 0); /*nop*/ | |
2604 | ||
2605 | #undef FLD | |
2606 | } | |
2607 | NEXT (vpc); | |
2608 | ||
2609 | CASE (sem, INSN_MTC2) : /* mtc2 $rt,$rd */ | |
2610 | { | |
2611 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2612 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2613 | #define FLD(f) abuf->fields.fmt_empty.f | |
2614 | int UNUSED written = 0; | |
2615 | IADDR UNUSED pc = abuf->addr; | |
2616 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2617 | ||
2618 | ((void) 0); /*nop*/ | |
2619 | ||
2620 | #undef FLD | |
2621 | } | |
2622 | NEXT (vpc); | |
2623 | ||
2624 | CASE (sem, INSN_MTC3) : /* mtc3 $rt,$rd */ | |
2625 | { | |
2626 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2627 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2628 | #define FLD(f) abuf->fields.fmt_empty.f | |
2629 | int UNUSED written = 0; | |
2630 | IADDR UNUSED pc = abuf->addr; | |
2631 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2632 | ||
2633 | ((void) 0); /*nop*/ | |
2634 | ||
2635 | #undef FLD | |
2636 | } | |
2637 | NEXT (vpc); | |
2638 | ||
2639 | CASE (sem, INSN_PKRL) : /* pkrl $rd,$rt */ | |
2640 | { | |
2641 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2642 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2643 | #define FLD(f) abuf->fields.fmt_empty.f | |
2644 | int UNUSED written = 0; | |
2645 | IADDR UNUSED pc = abuf->addr; | |
2646 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2647 | ||
2648 | ((void) 0); /*nop*/ | |
2649 | ||
2650 | #undef FLD | |
2651 | } | |
2652 | NEXT (vpc); | |
2653 | ||
2654 | CASE (sem, INSN_PKRLR1) : /* pkrlr1 $rt,$index,$count */ | |
2655 | { | |
2656 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2657 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2658 | #define FLD(f) abuf->fields.fmt_empty.f | |
2659 | int UNUSED written = 0; | |
2660 | IADDR UNUSED pc = abuf->addr; | |
2661 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2662 | ||
2663 | ((void) 0); /*nop*/ | |
2664 | ||
2665 | #undef FLD | |
2666 | } | |
2667 | NEXT (vpc); | |
2668 | ||
2669 | CASE (sem, INSN_PKRLR30) : /* pkrlr30 $rt,$index,$count */ | |
2670 | { | |
2671 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2672 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2673 | #define FLD(f) abuf->fields.fmt_empty.f | |
2674 | int UNUSED written = 0; | |
2675 | IADDR UNUSED pc = abuf->addr; | |
2676 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2677 | ||
2678 | ((void) 0); /*nop*/ | |
2679 | ||
2680 | #undef FLD | |
2681 | } | |
2682 | NEXT (vpc); | |
2683 | ||
2684 | CASE (sem, INSN_RB) : /* rb $rd,$rt */ | |
2685 | { | |
2686 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2687 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2688 | #define FLD(f) abuf->fields.fmt_empty.f | |
2689 | int UNUSED written = 0; | |
2690 | IADDR UNUSED pc = abuf->addr; | |
2691 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2692 | ||
2693 | ((void) 0); /*nop*/ | |
2694 | ||
2695 | #undef FLD | |
2696 | } | |
2697 | NEXT (vpc); | |
2698 | ||
2699 | CASE (sem, INSN_RBR1) : /* rbr1 $rt,$index,$count */ | |
2700 | { | |
2701 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2702 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2703 | #define FLD(f) abuf->fields.fmt_empty.f | |
2704 | int UNUSED written = 0; | |
2705 | IADDR UNUSED pc = abuf->addr; | |
2706 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2707 | ||
2708 | ((void) 0); /*nop*/ | |
2709 | ||
2710 | #undef FLD | |
2711 | } | |
2712 | NEXT (vpc); | |
2713 | ||
2714 | CASE (sem, INSN_RBR30) : /* rbr30 $rt,$index,$count */ | |
2715 | { | |
2716 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2717 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2718 | #define FLD(f) abuf->fields.fmt_empty.f | |
2719 | int UNUSED written = 0; | |
2720 | IADDR UNUSED pc = abuf->addr; | |
2721 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2722 | ||
2723 | ((void) 0); /*nop*/ | |
2724 | ||
2725 | #undef FLD | |
2726 | } | |
2727 | NEXT (vpc); | |
2728 | ||
2729 | CASE (sem, INSN_RFE) : /* rfe */ | |
2730 | { | |
2731 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2732 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2733 | #define FLD(f) abuf->fields.fmt_empty.f | |
2734 | int UNUSED written = 0; | |
2735 | IADDR UNUSED pc = abuf->addr; | |
2736 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2737 | ||
2738 | ((void) 0); /*nop*/ | |
2739 | ||
2740 | #undef FLD | |
2741 | } | |
2742 | NEXT (vpc); | |
2743 | ||
2744 | CASE (sem, INSN_RX) : /* rx $rd,$rt */ | |
2745 | { | |
2746 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2747 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2748 | #define FLD(f) abuf->fields.fmt_empty.f | |
2749 | int UNUSED written = 0; | |
2750 | IADDR UNUSED pc = abuf->addr; | |
2751 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2752 | ||
2753 | ((void) 0); /*nop*/ | |
2754 | ||
2755 | #undef FLD | |
2756 | } | |
2757 | NEXT (vpc); | |
2758 | ||
2759 | CASE (sem, INSN_RXR1) : /* rxr1 $rt,$index,$count */ | |
2760 | { | |
2761 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2762 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2763 | #define FLD(f) abuf->fields.fmt_empty.f | |
2764 | int UNUSED written = 0; | |
2765 | IADDR UNUSED pc = abuf->addr; | |
2766 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2767 | ||
2768 | ((void) 0); /*nop*/ | |
2769 | ||
2770 | #undef FLD | |
2771 | } | |
2772 | NEXT (vpc); | |
2773 | ||
2774 | CASE (sem, INSN_RXR30) : /* rxr30 $rt,$index,$count */ | |
2775 | { | |
2776 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2777 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2778 | #define FLD(f) abuf->fields.fmt_empty.f | |
2779 | int UNUSED written = 0; | |
2780 | IADDR UNUSED pc = abuf->addr; | |
2781 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2782 | ||
2783 | ((void) 0); /*nop*/ | |
2784 | ||
2785 | #undef FLD | |
2786 | } | |
2787 | NEXT (vpc); | |
2788 | ||
2789 | CASE (sem, INSN_SLEEP) : /* sleep */ | |
2790 | { | |
2791 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2792 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2793 | #define FLD(f) abuf->fields.fmt_empty.f | |
2794 | int UNUSED written = 0; | |
2795 | IADDR UNUSED pc = abuf->addr; | |
2796 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2797 | ||
2798 | ((void) 0); /*nop*/ | |
2799 | ||
2800 | #undef FLD | |
2801 | } | |
2802 | NEXT (vpc); | |
2803 | ||
2804 | CASE (sem, INSN_SRRD) : /* srrd $rt */ | |
2805 | { | |
2806 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2807 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2808 | #define FLD(f) abuf->fields.fmt_empty.f | |
2809 | int UNUSED written = 0; | |
2810 | IADDR UNUSED pc = abuf->addr; | |
2811 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2812 | ||
2813 | ((void) 0); /*nop*/ | |
2814 | ||
2815 | #undef FLD | |
2816 | } | |
2817 | NEXT (vpc); | |
2818 | ||
2819 | CASE (sem, INSN_SRRDL) : /* srrdl $rt */ | |
2820 | { | |
2821 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2822 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2823 | #define FLD(f) abuf->fields.fmt_empty.f | |
2824 | int UNUSED written = 0; | |
2825 | IADDR UNUSED pc = abuf->addr; | |
2826 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2827 | ||
2828 | ((void) 0); /*nop*/ | |
2829 | ||
2830 | #undef FLD | |
2831 | } | |
2832 | NEXT (vpc); | |
2833 | ||
2834 | CASE (sem, INSN_SRULCK) : /* srulck $rt */ | |
2835 | { | |
2836 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2837 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2838 | #define FLD(f) abuf->fields.fmt_empty.f | |
2839 | int UNUSED written = 0; | |
2840 | IADDR UNUSED pc = abuf->addr; | |
2841 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2842 | ||
2843 | ((void) 0); /*nop*/ | |
2844 | ||
2845 | #undef FLD | |
2846 | } | |
2847 | NEXT (vpc); | |
2848 | ||
2849 | CASE (sem, INSN_SRWR) : /* srwr $rt,$rd */ | |
2850 | { | |
2851 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2852 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2853 | #define FLD(f) abuf->fields.fmt_empty.f | |
2854 | int UNUSED written = 0; | |
2855 | IADDR UNUSED pc = abuf->addr; | |
2856 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2857 | ||
2858 | ((void) 0); /*nop*/ | |
2859 | ||
2860 | #undef FLD | |
2861 | } | |
2862 | NEXT (vpc); | |
2863 | ||
2864 | CASE (sem, INSN_SRWRU) : /* srwru $rt,$rd */ | |
2865 | { | |
2866 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2867 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2868 | #define FLD(f) abuf->fields.fmt_empty.f | |
2869 | int UNUSED written = 0; | |
2870 | IADDR UNUSED pc = abuf->addr; | |
2871 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2872 | ||
2873 | ((void) 0); /*nop*/ | |
2874 | ||
2875 | #undef FLD | |
2876 | } | |
2877 | NEXT (vpc); | |
2878 | ||
2879 | CASE (sem, INSN_TRAPQFL) : /* trapqfl */ | |
2880 | { | |
2881 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2882 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2883 | #define FLD(f) abuf->fields.fmt_empty.f | |
2884 | int UNUSED written = 0; | |
2885 | IADDR UNUSED pc = abuf->addr; | |
2886 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2887 | ||
2888 | ((void) 0); /*nop*/ | |
2889 | ||
2890 | #undef FLD | |
2891 | } | |
2892 | NEXT (vpc); | |
2893 | ||
2894 | CASE (sem, INSN_TRAPQNE) : /* trapqne */ | |
2895 | { | |
2896 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2897 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2898 | #define FLD(f) abuf->fields.fmt_empty.f | |
2899 | int UNUSED written = 0; | |
2900 | IADDR UNUSED pc = abuf->addr; | |
2901 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2902 | ||
2903 | ((void) 0); /*nop*/ | |
2904 | ||
2905 | #undef FLD | |
2906 | } | |
2907 | NEXT (vpc); | |
2908 | ||
2909 | CASE (sem, INSN_TRAPREL) : /* traprel $rt */ | |
2910 | { | |
2911 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2912 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2913 | #define FLD(f) abuf->fields.fmt_empty.f | |
2914 | int UNUSED written = 0; | |
2915 | IADDR UNUSED pc = abuf->addr; | |
2916 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2917 | ||
2918 | ((void) 0); /*nop*/ | |
2919 | ||
2920 | #undef FLD | |
2921 | } | |
2922 | NEXT (vpc); | |
2923 | ||
2924 | CASE (sem, INSN_WB) : /* wb $rd,$rt */ | |
2925 | { | |
2926 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2927 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2928 | #define FLD(f) abuf->fields.fmt_empty.f | |
2929 | int UNUSED written = 0; | |
2930 | IADDR UNUSED pc = abuf->addr; | |
2931 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2932 | ||
2933 | ((void) 0); /*nop*/ | |
2934 | ||
2935 | #undef FLD | |
2936 | } | |
2937 | NEXT (vpc); | |
2938 | ||
2939 | CASE (sem, INSN_WBU) : /* wbu $rd,$rt */ | |
2940 | { | |
2941 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2942 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2943 | #define FLD(f) abuf->fields.fmt_empty.f | |
2944 | int UNUSED written = 0; | |
2945 | IADDR UNUSED pc = abuf->addr; | |
2946 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2947 | ||
2948 | ((void) 0); /*nop*/ | |
2949 | ||
2950 | #undef FLD | |
2951 | } | |
2952 | NEXT (vpc); | |
2953 | ||
2954 | CASE (sem, INSN_WBR1) : /* wbr1 $rt,$index,$count */ | |
2955 | { | |
2956 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2957 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2958 | #define FLD(f) abuf->fields.fmt_empty.f | |
2959 | int UNUSED written = 0; | |
2960 | IADDR UNUSED pc = abuf->addr; | |
2961 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2962 | ||
2963 | ((void) 0); /*nop*/ | |
2964 | ||
2965 | #undef FLD | |
2966 | } | |
2967 | NEXT (vpc); | |
2968 | ||
2969 | CASE (sem, INSN_WBR1U) : /* wbr1u $rt,$index,$count */ | |
2970 | { | |
2971 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2972 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2973 | #define FLD(f) abuf->fields.fmt_empty.f | |
2974 | int UNUSED written = 0; | |
2975 | IADDR UNUSED pc = abuf->addr; | |
2976 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2977 | ||
2978 | ((void) 0); /*nop*/ | |
2979 | ||
2980 | #undef FLD | |
2981 | } | |
2982 | NEXT (vpc); | |
2983 | ||
2984 | CASE (sem, INSN_WBR30) : /* wbr30 $rt,$index,$count */ | |
2985 | { | |
2986 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2987 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2988 | #define FLD(f) abuf->fields.fmt_empty.f | |
2989 | int UNUSED written = 0; | |
2990 | IADDR UNUSED pc = abuf->addr; | |
2991 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2992 | ||
2993 | ((void) 0); /*nop*/ | |
2994 | ||
2995 | #undef FLD | |
2996 | } | |
2997 | NEXT (vpc); | |
2998 | ||
2999 | CASE (sem, INSN_WBR30U) : /* wbr30u $rt,$index,$count */ | |
3000 | { | |
3001 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3002 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3003 | #define FLD(f) abuf->fields.fmt_empty.f | |
3004 | int UNUSED written = 0; | |
3005 | IADDR UNUSED pc = abuf->addr; | |
3006 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3007 | ||
3008 | ((void) 0); /*nop*/ | |
3009 | ||
3010 | #undef FLD | |
3011 | } | |
3012 | NEXT (vpc); | |
3013 | ||
3014 | CASE (sem, INSN_WX) : /* wx $rd,$rt */ | |
3015 | { | |
3016 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3017 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3018 | #define FLD(f) abuf->fields.fmt_empty.f | |
3019 | int UNUSED written = 0; | |
3020 | IADDR UNUSED pc = abuf->addr; | |
3021 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3022 | ||
3023 | ((void) 0); /*nop*/ | |
3024 | ||
3025 | #undef FLD | |
3026 | } | |
3027 | NEXT (vpc); | |
3028 | ||
3029 | CASE (sem, INSN_WXU) : /* wxu $rd,$rt */ | |
3030 | { | |
3031 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3032 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3033 | #define FLD(f) abuf->fields.fmt_empty.f | |
3034 | int UNUSED written = 0; | |
3035 | IADDR UNUSED pc = abuf->addr; | |
3036 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3037 | ||
3038 | ((void) 0); /*nop*/ | |
3039 | ||
3040 | #undef FLD | |
3041 | } | |
3042 | NEXT (vpc); | |
3043 | ||
3044 | CASE (sem, INSN_WXR1) : /* wxr1 $rt,$index,$count */ | |
3045 | { | |
3046 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3047 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3048 | #define FLD(f) abuf->fields.fmt_empty.f | |
3049 | int UNUSED written = 0; | |
3050 | IADDR UNUSED pc = abuf->addr; | |
3051 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3052 | ||
3053 | ((void) 0); /*nop*/ | |
3054 | ||
3055 | #undef FLD | |
3056 | } | |
3057 | NEXT (vpc); | |
3058 | ||
3059 | CASE (sem, INSN_WXR1U) : /* wxr1u $rt,$index,$count */ | |
3060 | { | |
3061 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3062 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3063 | #define FLD(f) abuf->fields.fmt_empty.f | |
3064 | int UNUSED written = 0; | |
3065 | IADDR UNUSED pc = abuf->addr; | |
3066 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3067 | ||
3068 | ((void) 0); /*nop*/ | |
3069 | ||
3070 | #undef FLD | |
3071 | } | |
3072 | NEXT (vpc); | |
3073 | ||
3074 | CASE (sem, INSN_WXR30) : /* wxr30 $rt,$index,$count */ | |
3075 | { | |
3076 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3077 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3078 | #define FLD(f) abuf->fields.fmt_empty.f | |
3079 | int UNUSED written = 0; | |
3080 | IADDR UNUSED pc = abuf->addr; | |
3081 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3082 | ||
3083 | ((void) 0); /*nop*/ | |
3084 | ||
3085 | #undef FLD | |
3086 | } | |
3087 | NEXT (vpc); | |
3088 | ||
3089 | CASE (sem, INSN_WXR30U) : /* wxr30u $rt,$index,$count */ | |
3090 | { | |
3091 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3092 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3093 | #define FLD(f) abuf->fields.fmt_empty.f | |
3094 | int UNUSED written = 0; | |
3095 | IADDR UNUSED pc = abuf->addr; | |
3096 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3097 | ||
3098 | ((void) 0); /*nop*/ | |
3099 | ||
3100 | #undef FLD | |
3101 | } | |
3102 | NEXT (vpc); | |
3103 | ||
3104 | CASE (sem, INSN_LDW) : /* ldw $rt,$lo16($base) */ | |
3105 | { | |
3106 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3107 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3108 | #define FLD(f) abuf->fields.sfmt_addi.f | |
3109 | int UNUSED written = 0; | |
3110 | IADDR UNUSED pc = abuf->addr; | |
3111 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3112 | ||
3113 | { | |
3114 | SI tmp_addr; | |
3115 | tmp_addr = ANDSI (ADDSI (GET_H_GR (FLD (f_rs)), FLD (f_imm)), INVSI (3)); | |
3116 | { | |
3117 | SI opval = GETMEMSI (current_cpu, pc, tmp_addr); | |
3118 | SET_H_GR (ADDSI (FLD (f_rt), 1), opval); | |
3119 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3120 | } | |
3121 | { | |
3122 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_addr, 4)); | |
3123 | SET_H_GR (FLD (f_rt), opval); | |
3124 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3125 | } | |
3126 | } | |
3127 | ||
3128 | #undef FLD | |
3129 | } | |
3130 | NEXT (vpc); | |
3131 | ||
3132 | CASE (sem, INSN_SDW) : /* sdw $rt,$lo16($base) */ | |
3133 | { | |
3134 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3135 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3136 | #define FLD(f) abuf->fields.sfmt_addi.f | |
3137 | int UNUSED written = 0; | |
3138 | IADDR UNUSED pc = abuf->addr; | |
3139 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3140 | ||
3141 | { | |
3142 | SI tmp_addr; | |
3143 | tmp_addr = ANDSI (ADDSI (GET_H_GR (FLD (f_rs)), FLD (f_imm)), INVSI (3)); | |
3144 | { | |
3145 | SI opval = GET_H_GR (FLD (f_rt)); | |
3146 | SETMEMSI (current_cpu, pc, ADDSI (tmp_addr, 4), opval); | |
3147 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3148 | } | |
3149 | { | |
3150 | SI opval = GET_H_GR (ADDSI (FLD (f_rt), 1)); | |
3151 | SETMEMSI (current_cpu, pc, tmp_addr, opval); | |
3152 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3153 | } | |
3154 | } | |
3155 | ||
3156 | #undef FLD | |
3157 | } | |
3158 | NEXT (vpc); | |
3159 | ||
3160 | CASE (sem, INSN_J) : /* j $jmptarg */ | |
3161 | { | |
3162 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3163 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3164 | #define FLD(f) abuf->fields.sfmt_j.f | |
3165 | int UNUSED written = 0; | |
3166 | IADDR UNUSED pc = abuf->addr; | |
3167 | SEM_BRANCH_INIT | |
3168 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3169 | ||
3170 | { | |
3171 | { | |
3172 | USI opval = FLD (i_jmptarg); | |
3173 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
3174 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
3175 | } | |
3176 | } | |
3177 | ||
3178 | SEM_BRANCH_FINI (vpc); | |
3179 | #undef FLD | |
3180 | } | |
3181 | NEXT (vpc); | |
3182 | ||
3183 | CASE (sem, INSN_JAL) : /* jal $jmptarg */ | |
3184 | { | |
3185 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3186 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3187 | #define FLD(f) abuf->fields.sfmt_j.f | |
3188 | int UNUSED written = 0; | |
3189 | IADDR UNUSED pc = abuf->addr; | |
3190 | SEM_BRANCH_INIT | |
3191 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3192 | ||
3193 | { | |
3194 | { | |
3195 | { | |
3196 | SI opval = ADDSI (pc, 8); | |
3197 | SET_H_GR (((UINT) 31), opval); | |
3198 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3199 | } | |
3200 | { | |
3201 | USI opval = FLD (i_jmptarg); | |
3202 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
3203 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
3204 | } | |
3205 | } | |
3206 | } | |
3207 | ||
3208 | SEM_BRANCH_FINI (vpc); | |
3209 | #undef FLD | |
3210 | } | |
3211 | NEXT (vpc); | |
3212 | ||
3213 | CASE (sem, INSN_BMB) : /* bmb $rs,$rt,$offset */ | |
3214 | { | |
3215 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3216 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3217 | #define FLD(f) abuf->fields.sfmt_bbi.f | |
3218 | int UNUSED written = 0; | |
3219 | IADDR UNUSED pc = abuf->addr; | |
3220 | SEM_BRANCH_INIT | |
3221 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3222 | ||
3223 | { | |
3224 | BI tmp_branch_; | |
3225 | tmp_branch_ = 0; | |
3226 | if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 255), ANDSI (GET_H_GR (FLD (f_rt)), 255))) { | |
3227 | tmp_branch_ = 1; | |
3228 | } | |
3229 | if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 65280), ANDSI (GET_H_GR (FLD (f_rt)), 65280))) { | |
3230 | tmp_branch_ = 1; | |
3231 | } | |
3232 | if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 16711680), ANDSI (GET_H_GR (FLD (f_rt)), 16711680))) { | |
3233 | tmp_branch_ = 1; | |
3234 | } | |
3235 | if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000), ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000))) { | |
3236 | tmp_branch_ = 1; | |
3237 | } | |
3238 | if (tmp_branch_) { | |
3239 | { | |
3240 | { | |
3241 | USI opval = FLD (i_offset); | |
3242 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
3243 | written |= (1 << 3); | |
3244 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
3245 | } | |
3246 | } | |
3247 | } | |
3248 | } | |
3249 | ||
3250 | abuf->written = written; | |
3251 | SEM_BRANCH_FINI (vpc); | |
3252 | #undef FLD | |
3253 | } | |
3254 | NEXT (vpc); | |
3255 | ||
3256 | ||
3257 | } | |
3258 | ENDSWITCH (sem) /* End of semantic switch. */ | |
3259 | ; | |
3260 | ||
3261 | /* At this point `vpc' contains the next insn to execute. */ | |
3262 | } | |
3263 | ||
3264 | #undef DEFINE_SWITCH | |
3265 | #endif /* DEFINE_SWITCH */ |