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Commit | Line | Data |
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8de434bf | 1 | /* CPU family header for m32rxf. |
8e420152 | 2 | |
7422fa0c | 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
b8a9943d | 4 | |
8e420152 DE |
5 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. |
6 | ||
7 | This file is part of the GNU Simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
8de434bf DE |
25 | #ifndef CPU_M32RXF_H |
26 | #define CPU_M32RXF_H | |
8e420152 DE |
27 | |
28 | /* Maximum number of instructions that are fetched at a time. | |
29 | This is for LIW type instructions sets (e.g. m32r). */ | |
30 | #define MAX_LIW_INSNS 2 | |
31 | ||
32 | /* Maximum number of instructions that can be executed in parallel. */ | |
33 | #define MAX_PARALLEL_INSNS 2 | |
34 | ||
35 | /* CPU state information. */ | |
36 | typedef struct { | |
37 | /* Hardware elements. */ | |
38 | struct { | |
39 | /* program counter */ | |
40 | USI h_pc; | |
41 | #define GET_H_PC() CPU (h_pc) | |
42 | #define SET_H_PC(x) (CPU (h_pc) = (x)) | |
43 | /* general registers */ | |
44 | SI h_gr[16]; | |
45 | #define GET_H_GR(a1) CPU (h_gr)[a1] | |
46 | #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) | |
47 | /* control registers */ | |
7422fa0c | 48 | USI h_cr[16]; |
8e420152 DE |
49 | #define GET_H_CR(a1) CPU (h_cr)[a1] |
50 | #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x)) | |
51 | /* accumulator */ | |
52 | DI h_accum; | |
53 | #define GET_H_ACCUM() CPU (h_accum) | |
54 | #define SET_H_ACCUM(x) (CPU (h_accum) = (x)) | |
b8a9943d | 55 | /* start-sanitize-m32rx */ |
8e420152 DE |
56 | /* accumulators */ |
57 | DI h_accums[2]; | |
b8a9943d | 58 | /* end-sanitize-m32rx */ |
8e420152 DE |
59 | #define GET_H_ACCUMS(a1) CPU (h_accums)[a1] |
60 | #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x)) | |
8e420152 | 61 | /* condition bit */ |
8de434bf | 62 | BI h_cond; |
8e420152 DE |
63 | #define GET_H_COND() CPU (h_cond) |
64 | #define SET_H_COND(x) (CPU (h_cond) = (x)) | |
8de434bf DE |
65 | /* psw part of psw */ |
66 | UQI h_psw; | |
67 | #define GET_H_PSW() CPU (h_psw) | |
68 | #define SET_H_PSW(x) (CPU (h_psw) = (x)) | |
69 | /* backup psw */ | |
70 | UQI h_bpsw; | |
71 | #define GET_H_BPSW() CPU (h_bpsw) | |
72 | #define SET_H_BPSW(x) (CPU (h_bpsw) = (x)) | |
73 | /* backup bpsw */ | |
74 | UQI h_bbpsw; | |
75 | #define GET_H_BBPSW() CPU (h_bbpsw) | |
76 | #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x)) | |
cab58155 | 77 | /* lock */ |
8de434bf | 78 | BI h_lock; |
cab58155 DE |
79 | #define GET_H_LOCK() CPU (h_lock) |
80 | #define SET_H_LOCK(x) (CPU (h_lock) = (x)) | |
8e420152 DE |
81 | } hardware; |
82 | #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) | |
8de434bf | 83 | } M32RXF_CPU_DATA; |
8e420152 | 84 | |
190659a2 | 85 | /* Cover fns for register access. */ |
8de434bf DE |
86 | USI m32rxf_h_pc_get (SIM_CPU *); |
87 | void m32rxf_h_pc_set (SIM_CPU *, USI); | |
88 | SI m32rxf_h_gr_get (SIM_CPU *, UINT); | |
89 | void m32rxf_h_gr_set (SIM_CPU *, UINT, SI); | |
90 | USI m32rxf_h_cr_get (SIM_CPU *, UINT); | |
91 | void m32rxf_h_cr_set (SIM_CPU *, UINT, USI); | |
92 | DI m32rxf_h_accum_get (SIM_CPU *); | |
93 | void m32rxf_h_accum_set (SIM_CPU *, DI); | |
94 | DI m32rxf_h_accums_get (SIM_CPU *, UINT); | |
95 | void m32rxf_h_accums_set (SIM_CPU *, UINT, DI); | |
96 | BI m32rxf_h_cond_get (SIM_CPU *); | |
97 | void m32rxf_h_cond_set (SIM_CPU *, BI); | |
98 | UQI m32rxf_h_psw_get (SIM_CPU *); | |
99 | void m32rxf_h_psw_set (SIM_CPU *, UQI); | |
100 | UQI m32rxf_h_bpsw_get (SIM_CPU *); | |
101 | void m32rxf_h_bpsw_set (SIM_CPU *, UQI); | |
102 | UQI m32rxf_h_bbpsw_get (SIM_CPU *); | |
103 | void m32rxf_h_bbpsw_set (SIM_CPU *, UQI); | |
104 | BI m32rxf_h_lock_get (SIM_CPU *); | |
105 | void m32rxf_h_lock_set (SIM_CPU *, BI); | |
7422fa0c DE |
106 | |
107 | /* These must be hand-written. */ | |
8de434bf DE |
108 | extern CPUREG_FETCH_FN m32rxf_fetch_register; |
109 | extern CPUREG_STORE_FN m32rxf_store_register; | |
110 | ||
111 | typedef struct { | |
112 | int empty; | |
113 | } MODEL_M32RX_DATA; | |
8e420152 DE |
114 | |
115 | /* The ARGBUF struct. */ | |
116 | struct argbuf { | |
117 | /* These are the baseclass definitions. */ | |
8e420152 | 118 | PCADDR addr; |
7422fa0c | 119 | const IDESC *idesc; |
0a18a6b8 DE |
120 | char trace_p; |
121 | char profile_p; | |
8e420152 | 122 | /* cpu specific data follows */ |
8de434bf DE |
123 | union sem semantic; |
124 | int written; | |
8e420152 DE |
125 | union { |
126 | struct { /* e.g. add $dr,$sr */ | |
99c53aa9 DE |
127 | SI * i_dr; |
128 | SI * i_sr; | |
8de434bf DE |
129 | unsigned char in_dr; |
130 | unsigned char in_sr; | |
131 | unsigned char out_dr; | |
7422fa0c DE |
132 | } fmt_add; |
133 | struct { /* e.g. add3 $dr,$sr,$hash$slo16 */ | |
99c53aa9 | 134 | SI * i_sr; |
8e420152 | 135 | HI f_simm16; |
99c53aa9 | 136 | SI * i_dr; |
8de434bf DE |
137 | unsigned char in_sr; |
138 | unsigned char out_dr; | |
7422fa0c DE |
139 | } fmt_add3; |
140 | struct { /* e.g. and3 $dr,$sr,$uimm16 */ | |
99c53aa9 | 141 | SI * i_sr; |
8e420152 | 142 | USI f_uimm16; |
99c53aa9 | 143 | SI * i_dr; |
8de434bf DE |
144 | unsigned char in_sr; |
145 | unsigned char out_dr; | |
7422fa0c DE |
146 | } fmt_and3; |
147 | struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */ | |
99c53aa9 | 148 | SI * i_sr; |
8e420152 | 149 | UHI f_uimm16; |
99c53aa9 | 150 | SI * i_dr; |
8de434bf DE |
151 | unsigned char in_sr; |
152 | unsigned char out_dr; | |
7422fa0c DE |
153 | } fmt_or3; |
154 | struct { /* e.g. addi $dr,$simm8 */ | |
99c53aa9 | 155 | SI * i_dr; |
8e420152 | 156 | SI f_simm8; |
8de434bf DE |
157 | unsigned char in_dr; |
158 | unsigned char out_dr; | |
7422fa0c | 159 | } fmt_addi; |
cab58155 | 160 | struct { /* e.g. addv $dr,$sr */ |
99c53aa9 DE |
161 | SI * i_dr; |
162 | SI * i_sr; | |
8de434bf DE |
163 | unsigned char in_dr; |
164 | unsigned char in_sr; | |
165 | unsigned char out_dr; | |
7422fa0c DE |
166 | } fmt_addv; |
167 | struct { /* e.g. addv3 $dr,$sr,$simm16 */ | |
99c53aa9 | 168 | SI * i_sr; |
8e420152 | 169 | SI f_simm16; |
99c53aa9 | 170 | SI * i_dr; |
8de434bf DE |
171 | unsigned char in_sr; |
172 | unsigned char out_dr; | |
7422fa0c | 173 | } fmt_addv3; |
8e420152 | 174 | struct { /* e.g. addx $dr,$sr */ |
99c53aa9 DE |
175 | SI * i_dr; |
176 | SI * i_sr; | |
8de434bf DE |
177 | unsigned char in_dr; |
178 | unsigned char in_sr; | |
179 | unsigned char out_dr; | |
7422fa0c | 180 | } fmt_addx; |
8e420152 | 181 | struct { /* e.g. cmp $src1,$src2 */ |
99c53aa9 DE |
182 | SI * i_src1; |
183 | SI * i_src2; | |
8de434bf DE |
184 | unsigned char in_src1; |
185 | unsigned char in_src2; | |
7422fa0c DE |
186 | } fmt_cmp; |
187 | struct { /* e.g. cmpi $src2,$simm16 */ | |
99c53aa9 | 188 | SI * i_src2; |
8e420152 | 189 | SI f_simm16; |
8de434bf | 190 | unsigned char in_src2; |
7422fa0c | 191 | } fmt_cmpi; |
8e420152 | 192 | struct { /* e.g. cmpz $src2 */ |
99c53aa9 | 193 | SI * i_src2; |
8de434bf | 194 | unsigned char in_src2; |
7422fa0c | 195 | } fmt_cmpz; |
8e420152 | 196 | struct { /* e.g. div $dr,$sr */ |
99c53aa9 DE |
197 | SI * i_sr; |
198 | SI * i_dr; | |
8de434bf DE |
199 | unsigned char in_sr; |
200 | unsigned char in_dr; | |
201 | unsigned char out_dr; | |
7422fa0c | 202 | } fmt_div; |
8e420152 | 203 | struct { /* e.g. ld $dr,@$sr */ |
99c53aa9 DE |
204 | SI * i_sr; |
205 | SI * i_dr; | |
8de434bf DE |
206 | unsigned char in_sr; |
207 | unsigned char out_dr; | |
7422fa0c | 208 | } fmt_ld; |
8e420152 | 209 | struct { /* e.g. ld $dr,@($slo16,$sr) */ |
99c53aa9 | 210 | SI * i_sr; |
8e420152 | 211 | HI f_simm16; |
99c53aa9 | 212 | SI * i_dr; |
8de434bf DE |
213 | unsigned char in_sr; |
214 | unsigned char out_dr; | |
7422fa0c | 215 | } fmt_ld_d; |
8e420152 | 216 | struct { /* e.g. ldb $dr,@$sr */ |
99c53aa9 DE |
217 | SI * i_sr; |
218 | SI * i_dr; | |
8de434bf DE |
219 | unsigned char in_sr; |
220 | unsigned char out_dr; | |
7422fa0c | 221 | } fmt_ldb; |
8e420152 | 222 | struct { /* e.g. ldb $dr,@($slo16,$sr) */ |
99c53aa9 | 223 | SI * i_sr; |
8e420152 | 224 | HI f_simm16; |
99c53aa9 | 225 | SI * i_dr; |
8de434bf DE |
226 | unsigned char in_sr; |
227 | unsigned char out_dr; | |
7422fa0c | 228 | } fmt_ldb_d; |
8e420152 | 229 | struct { /* e.g. ldh $dr,@$sr */ |
99c53aa9 DE |
230 | SI * i_sr; |
231 | SI * i_dr; | |
8de434bf DE |
232 | unsigned char in_sr; |
233 | unsigned char out_dr; | |
7422fa0c | 234 | } fmt_ldh; |
8e420152 | 235 | struct { /* e.g. ldh $dr,@($slo16,$sr) */ |
99c53aa9 | 236 | SI * i_sr; |
8e420152 | 237 | HI f_simm16; |
99c53aa9 | 238 | SI * i_dr; |
8de434bf DE |
239 | unsigned char in_sr; |
240 | unsigned char out_dr; | |
7422fa0c | 241 | } fmt_ldh_d; |
cab58155 | 242 | struct { /* e.g. ld $dr,@$sr+ */ |
99c53aa9 DE |
243 | SI * i_sr; |
244 | SI * i_dr; | |
8de434bf DE |
245 | unsigned char in_sr; |
246 | unsigned char out_dr; | |
247 | unsigned char out_sr; | |
7422fa0c DE |
248 | } fmt_ld_plus; |
249 | struct { /* e.g. ld24 $dr,$uimm24 */ | |
8e420152 | 250 | ADDR f_uimm24; |
99c53aa9 | 251 | SI * i_dr; |
8de434bf | 252 | unsigned char out_dr; |
7422fa0c DE |
253 | } fmt_ld24; |
254 | struct { /* e.g. ldi8 $dr,$simm8 */ | |
8e420152 | 255 | SI f_simm8; |
99c53aa9 | 256 | SI * i_dr; |
8de434bf | 257 | unsigned char out_dr; |
7422fa0c DE |
258 | } fmt_ldi8; |
259 | struct { /* e.g. ldi16 $dr,$hash$slo16 */ | |
8e420152 | 260 | HI f_simm16; |
99c53aa9 | 261 | SI * i_dr; |
8de434bf | 262 | unsigned char out_dr; |
7422fa0c | 263 | } fmt_ldi16; |
cab58155 | 264 | struct { /* e.g. lock $dr,@$sr */ |
99c53aa9 DE |
265 | SI * i_sr; |
266 | SI * i_dr; | |
8de434bf DE |
267 | unsigned char in_sr; |
268 | unsigned char out_dr; | |
7422fa0c | 269 | } fmt_lock; |
8e420152 | 270 | struct { /* e.g. machi $src1,$src2,$acc */ |
8e420152 | 271 | UINT f_acc; |
99c53aa9 DE |
272 | SI * i_src1; |
273 | SI * i_src2; | |
8de434bf DE |
274 | unsigned char in_src1; |
275 | unsigned char in_src2; | |
7422fa0c | 276 | } fmt_machi_a; |
8e420152 | 277 | struct { /* e.g. mulhi $src1,$src2,$acc */ |
99c53aa9 DE |
278 | SI * i_src1; |
279 | SI * i_src2; | |
8e420152 | 280 | UINT f_acc; |
8de434bf DE |
281 | unsigned char in_src1; |
282 | unsigned char in_src2; | |
7422fa0c | 283 | } fmt_mulhi_a; |
8e420152 | 284 | struct { /* e.g. mv $dr,$sr */ |
99c53aa9 DE |
285 | SI * i_sr; |
286 | SI * i_dr; | |
8de434bf DE |
287 | unsigned char in_sr; |
288 | unsigned char out_dr; | |
7422fa0c | 289 | } fmt_mv; |
8e420152 | 290 | struct { /* e.g. mvfachi $dr,$accs */ |
8e420152 | 291 | UINT f_accs; |
99c53aa9 | 292 | SI * i_dr; |
8de434bf | 293 | unsigned char out_dr; |
7422fa0c | 294 | } fmt_mvfachi_a; |
8e420152 | 295 | struct { /* e.g. mvfc $dr,$scr */ |
8e420152 | 296 | UINT f_r2; |
99c53aa9 | 297 | SI * i_dr; |
8de434bf | 298 | unsigned char out_dr; |
7422fa0c | 299 | } fmt_mvfc; |
8e420152 | 300 | struct { /* e.g. mvtachi $src1,$accs */ |
8e420152 | 301 | UINT f_accs; |
99c53aa9 | 302 | SI * i_src1; |
8de434bf | 303 | unsigned char in_src1; |
7422fa0c | 304 | } fmt_mvtachi_a; |
8e420152 | 305 | struct { /* e.g. mvtc $sr,$dcr */ |
99c53aa9 | 306 | SI * i_sr; |
8e420152 | 307 | UINT f_r1; |
8de434bf | 308 | unsigned char in_sr; |
7422fa0c | 309 | } fmt_mvtc; |
8e420152 DE |
310 | struct { /* e.g. nop */ |
311 | int empty; | |
7422fa0c DE |
312 | } fmt_nop; |
313 | struct { /* e.g. rac $accd,$accs,$imm1 */ | |
e0bd6e18 DE |
314 | UINT f_accs; |
315 | USI f_imm1; | |
99c53aa9 | 316 | UINT f_accd; |
7422fa0c | 317 | } fmt_rac_dsi; |
7422fa0c | 318 | struct { /* e.g. seth $dr,$hash$hi16 */ |
8e420152 | 319 | UHI f_hi16; |
99c53aa9 | 320 | SI * i_dr; |
8de434bf | 321 | unsigned char out_dr; |
7422fa0c DE |
322 | } fmt_seth; |
323 | struct { /* e.g. sll3 $dr,$sr,$simm16 */ | |
99c53aa9 | 324 | SI * i_sr; |
cab58155 | 325 | SI f_simm16; |
99c53aa9 | 326 | SI * i_dr; |
8de434bf DE |
327 | unsigned char in_sr; |
328 | unsigned char out_dr; | |
7422fa0c DE |
329 | } fmt_sll3; |
330 | struct { /* e.g. slli $dr,$uimm5 */ | |
99c53aa9 | 331 | SI * i_dr; |
8e420152 | 332 | USI f_uimm5; |
8de434bf DE |
333 | unsigned char in_dr; |
334 | unsigned char out_dr; | |
7422fa0c | 335 | } fmt_slli; |
cab58155 | 336 | struct { /* e.g. st $src1,@$src2 */ |
99c53aa9 DE |
337 | SI * i_src2; |
338 | SI * i_src1; | |
8de434bf DE |
339 | unsigned char in_src2; |
340 | unsigned char in_src1; | |
7422fa0c | 341 | } fmt_st; |
8e420152 | 342 | struct { /* e.g. st $src1,@($slo16,$src2) */ |
99c53aa9 | 343 | SI * i_src2; |
8e420152 | 344 | HI f_simm16; |
99c53aa9 | 345 | SI * i_src1; |
8de434bf DE |
346 | unsigned char in_src2; |
347 | unsigned char in_src1; | |
7422fa0c | 348 | } fmt_st_d; |
cab58155 | 349 | struct { /* e.g. stb $src1,@$src2 */ |
99c53aa9 DE |
350 | SI * i_src2; |
351 | SI * i_src1; | |
8de434bf DE |
352 | unsigned char in_src2; |
353 | unsigned char in_src1; | |
7422fa0c | 354 | } fmt_stb; |
cab58155 | 355 | struct { /* e.g. stb $src1,@($slo16,$src2) */ |
99c53aa9 | 356 | SI * i_src2; |
cab58155 | 357 | HI f_simm16; |
99c53aa9 | 358 | SI * i_src1; |
8de434bf DE |
359 | unsigned char in_src2; |
360 | unsigned char in_src1; | |
7422fa0c | 361 | } fmt_stb_d; |
cab58155 | 362 | struct { /* e.g. sth $src1,@$src2 */ |
99c53aa9 DE |
363 | SI * i_src2; |
364 | SI * i_src1; | |
8de434bf DE |
365 | unsigned char in_src2; |
366 | unsigned char in_src1; | |
7422fa0c | 367 | } fmt_sth; |
cab58155 | 368 | struct { /* e.g. sth $src1,@($slo16,$src2) */ |
99c53aa9 | 369 | SI * i_src2; |
cab58155 | 370 | HI f_simm16; |
99c53aa9 | 371 | SI * i_src1; |
8de434bf DE |
372 | unsigned char in_src2; |
373 | unsigned char in_src1; | |
7422fa0c | 374 | } fmt_sth_d; |
cab58155 | 375 | struct { /* e.g. st $src1,@+$src2 */ |
99c53aa9 DE |
376 | SI * i_src2; |
377 | SI * i_src1; | |
8de434bf DE |
378 | unsigned char in_src2; |
379 | unsigned char in_src1; | |
380 | unsigned char out_src2; | |
7422fa0c | 381 | } fmt_st_plus; |
cab58155 | 382 | struct { /* e.g. unlock $src1,@$src2 */ |
99c53aa9 DE |
383 | SI * i_src2; |
384 | SI * i_src1; | |
8de434bf DE |
385 | unsigned char in_src2; |
386 | unsigned char in_src1; | |
7422fa0c | 387 | } fmt_unlock; |
cab58155 | 388 | struct { /* e.g. satb $dr,$sr */ |
99c53aa9 DE |
389 | SI * i_sr; |
390 | SI * i_dr; | |
8de434bf DE |
391 | unsigned char in_sr; |
392 | unsigned char out_dr; | |
7422fa0c | 393 | } fmt_satb; |
cab58155 | 394 | struct { /* e.g. sat $dr,$sr */ |
99c53aa9 DE |
395 | SI * i_sr; |
396 | SI * i_dr; | |
8de434bf DE |
397 | unsigned char in_sr; |
398 | unsigned char out_dr; | |
7422fa0c | 399 | } fmt_sat; |
8e420152 DE |
400 | struct { /* e.g. sadd */ |
401 | int empty; | |
7422fa0c | 402 | } fmt_sadd; |
8e420152 | 403 | struct { /* e.g. macwu1 $src1,$src2 */ |
99c53aa9 DE |
404 | SI * i_src1; |
405 | SI * i_src2; | |
8de434bf DE |
406 | unsigned char in_src1; |
407 | unsigned char in_src2; | |
7422fa0c | 408 | } fmt_macwu1; |
190659a2 | 409 | struct { /* e.g. msblo $src1,$src2 */ |
99c53aa9 DE |
410 | SI * i_src1; |
411 | SI * i_src2; | |
8de434bf DE |
412 | unsigned char in_src1; |
413 | unsigned char in_src2; | |
190659a2 | 414 | } fmt_msblo; |
cab58155 | 415 | struct { /* e.g. mulwu1 $src1,$src2 */ |
99c53aa9 DE |
416 | SI * i_src1; |
417 | SI * i_src2; | |
8de434bf DE |
418 | unsigned char in_src1; |
419 | unsigned char in_src2; | |
7422fa0c | 420 | } fmt_mulwu1; |
8de434bf DE |
421 | /* cti insns, kept separately so addr_cache is in fixed place */ |
422 | struct { | |
423 | union { | |
424 | struct { /* e.g. bc.s $disp8 */ | |
425 | IADDR f_disp8; | |
426 | } fmt_bc8; | |
427 | struct { /* e.g. bc.l $disp24 */ | |
428 | IADDR f_disp24; | |
429 | } fmt_bc24; | |
430 | struct { /* e.g. beq $src1,$src2,$disp16 */ | |
99c53aa9 DE |
431 | SI * i_src1; |
432 | SI * i_src2; | |
8de434bf DE |
433 | IADDR f_disp16; |
434 | unsigned char in_src1; | |
435 | unsigned char in_src2; | |
436 | } fmt_beq; | |
437 | struct { /* e.g. beqz $src2,$disp16 */ | |
99c53aa9 | 438 | SI * i_src2; |
8de434bf DE |
439 | IADDR f_disp16; |
440 | unsigned char in_src2; | |
441 | } fmt_beqz; | |
442 | struct { /* e.g. bl.s $disp8 */ | |
443 | IADDR f_disp8; | |
444 | unsigned char out_h_gr_14; | |
445 | } fmt_bl8; | |
446 | struct { /* e.g. bl.l $disp24 */ | |
447 | IADDR f_disp24; | |
448 | unsigned char out_h_gr_14; | |
449 | } fmt_bl24; | |
450 | struct { /* e.g. bcl.s $disp8 */ | |
451 | IADDR f_disp8; | |
452 | unsigned char out_h_gr_14; | |
453 | } fmt_bcl8; | |
454 | struct { /* e.g. bcl.l $disp24 */ | |
455 | IADDR f_disp24; | |
456 | unsigned char out_h_gr_14; | |
457 | } fmt_bcl24; | |
458 | struct { /* e.g. bra.s $disp8 */ | |
459 | IADDR f_disp8; | |
460 | } fmt_bra8; | |
461 | struct { /* e.g. bra.l $disp24 */ | |
462 | IADDR f_disp24; | |
463 | } fmt_bra24; | |
464 | struct { /* e.g. jc $sr */ | |
99c53aa9 | 465 | SI * i_sr; |
8de434bf DE |
466 | unsigned char in_sr; |
467 | } fmt_jc; | |
468 | struct { /* e.g. jl $sr */ | |
99c53aa9 | 469 | SI * i_sr; |
8de434bf DE |
470 | unsigned char in_sr; |
471 | unsigned char out_h_gr_14; | |
472 | } fmt_jl; | |
473 | struct { /* e.g. jmp $sr */ | |
99c53aa9 | 474 | SI * i_sr; |
8de434bf DE |
475 | unsigned char in_sr; |
476 | } fmt_jmp; | |
477 | struct { /* e.g. rte */ | |
478 | int empty; | |
479 | } fmt_rte; | |
480 | struct { /* e.g. trap $uimm4 */ | |
481 | USI f_uimm4; | |
482 | } fmt_trap; | |
99c53aa9 DE |
483 | struct { /* e.g. sc */ |
484 | int empty; | |
485 | } fmt_sc; | |
8de434bf DE |
486 | } fields; |
487 | #if WITH_SCACHE_PBB_M32RXF | |
488 | SEM_PC addr_cache; | |
489 | #endif | |
490 | } cti; | |
491 | #if WITH_SCACHE_PBB_M32RXF | |
492 | /* Writeback handler. */ | |
493 | struct { | |
494 | /* Pointer to argbuf entry for insn whose results need writing back. */ | |
495 | const struct argbuf *abuf; | |
496 | } write; | |
497 | /* x-before handler */ | |
498 | struct { | |
499 | /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ | |
500 | int first_p; | |
501 | } before; | |
502 | /* x-after handler */ | |
503 | struct { | |
504 | int empty; | |
505 | } after; | |
506 | /* This entry is used to terminate each pbb. */ | |
507 | struct { | |
508 | /* Number of insns in pbb. */ | |
509 | int insn_count; | |
510 | /* Next pbb to execute. */ | |
511 | SCACHE *next; | |
512 | } chain; | |
8e420152 | 513 | #endif |
8de434bf | 514 | } fields; |
8e420152 DE |
515 | }; |
516 | ||
517 | /* A cached insn. | |
8de434bf DE |
518 | |
519 | ??? SCACHE used to contain more than just argbuf. We could delete the | |
520 | type entirely and always just use ARGBUF, but for future concerns and as | |
521 | a level of abstraction it is left in. */ | |
8e420152 DE |
522 | |
523 | struct scache { | |
8e420152 DE |
524 | struct argbuf argbuf; |
525 | }; | |
526 | ||
527 | /* Macros to simplify extraction, reading and semantic code. | |
528 | These define and assign the local vars that contain the insn's fields. */ | |
529 | ||
7422fa0c | 530 | #define EXTRACT_FMT_ADD_VARS \ |
8e420152 DE |
531 | /* Instruction fields. */ \ |
532 | UINT f_op1; \ | |
533 | UINT f_r1; \ | |
534 | UINT f_op2; \ | |
535 | UINT f_r2; \ | |
536 | unsigned int length; | |
7422fa0c | 537 | #define EXTRACT_FMT_ADD_CODE \ |
8e420152 | 538 | length = 2; \ |
99c53aa9 DE |
539 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
540 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
541 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
542 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 543 | |
7422fa0c | 544 | #define EXTRACT_FMT_ADD3_VARS \ |
8e420152 DE |
545 | /* Instruction fields. */ \ |
546 | UINT f_op1; \ | |
547 | UINT f_r1; \ | |
548 | UINT f_op2; \ | |
549 | UINT f_r2; \ | |
99c53aa9 | 550 | INT f_simm16; \ |
8e420152 | 551 | unsigned int length; |
7422fa0c | 552 | #define EXTRACT_FMT_ADD3_CODE \ |
8e420152 | 553 | length = 4; \ |
99c53aa9 DE |
554 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
555 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
556 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
557 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
558 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
8e420152 | 559 | |
7422fa0c | 560 | #define EXTRACT_FMT_AND3_VARS \ |
8e420152 DE |
561 | /* Instruction fields. */ \ |
562 | UINT f_op1; \ | |
563 | UINT f_r1; \ | |
564 | UINT f_op2; \ | |
565 | UINT f_r2; \ | |
566 | UINT f_uimm16; \ | |
567 | unsigned int length; | |
7422fa0c | 568 | #define EXTRACT_FMT_AND3_CODE \ |
8e420152 | 569 | length = 4; \ |
99c53aa9 DE |
570 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
571 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
572 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
573 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
574 | f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ | |
8e420152 | 575 | |
7422fa0c | 576 | #define EXTRACT_FMT_OR3_VARS \ |
8e420152 DE |
577 | /* Instruction fields. */ \ |
578 | UINT f_op1; \ | |
579 | UINT f_r1; \ | |
580 | UINT f_op2; \ | |
581 | UINT f_r2; \ | |
582 | UINT f_uimm16; \ | |
583 | unsigned int length; | |
7422fa0c | 584 | #define EXTRACT_FMT_OR3_CODE \ |
8e420152 | 585 | length = 4; \ |
99c53aa9 DE |
586 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
587 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
588 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
589 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
590 | f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ | |
8e420152 | 591 | |
7422fa0c | 592 | #define EXTRACT_FMT_ADDI_VARS \ |
8e420152 DE |
593 | /* Instruction fields. */ \ |
594 | UINT f_op1; \ | |
595 | UINT f_r1; \ | |
99c53aa9 | 596 | INT f_simm8; \ |
8e420152 | 597 | unsigned int length; |
7422fa0c | 598 | #define EXTRACT_FMT_ADDI_CODE \ |
8e420152 | 599 | length = 2; \ |
99c53aa9 DE |
600 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
601 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
602 | f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \ | |
8e420152 | 603 | |
7422fa0c | 604 | #define EXTRACT_FMT_ADDV_VARS \ |
cab58155 DE |
605 | /* Instruction fields. */ \ |
606 | UINT f_op1; \ | |
607 | UINT f_r1; \ | |
608 | UINT f_op2; \ | |
609 | UINT f_r2; \ | |
610 | unsigned int length; | |
7422fa0c | 611 | #define EXTRACT_FMT_ADDV_CODE \ |
cab58155 | 612 | length = 2; \ |
99c53aa9 DE |
613 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
614 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
615 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
616 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
cab58155 | 617 | |
7422fa0c | 618 | #define EXTRACT_FMT_ADDV3_VARS \ |
8e420152 DE |
619 | /* Instruction fields. */ \ |
620 | UINT f_op1; \ | |
621 | UINT f_r1; \ | |
622 | UINT f_op2; \ | |
623 | UINT f_r2; \ | |
99c53aa9 | 624 | INT f_simm16; \ |
8e420152 | 625 | unsigned int length; |
7422fa0c | 626 | #define EXTRACT_FMT_ADDV3_CODE \ |
8e420152 | 627 | length = 4; \ |
99c53aa9 DE |
628 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
629 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
630 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
631 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
632 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
8e420152 | 633 | |
7422fa0c | 634 | #define EXTRACT_FMT_ADDX_VARS \ |
8e420152 DE |
635 | /* Instruction fields. */ \ |
636 | UINT f_op1; \ | |
637 | UINT f_r1; \ | |
638 | UINT f_op2; \ | |
639 | UINT f_r2; \ | |
640 | unsigned int length; | |
7422fa0c | 641 | #define EXTRACT_FMT_ADDX_CODE \ |
8e420152 | 642 | length = 2; \ |
99c53aa9 DE |
643 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
644 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
645 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
646 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 647 | |
7422fa0c | 648 | #define EXTRACT_FMT_BC8_VARS \ |
8e420152 DE |
649 | /* Instruction fields. */ \ |
650 | UINT f_op1; \ | |
651 | UINT f_r1; \ | |
99c53aa9 | 652 | INT f_disp8; \ |
8e420152 | 653 | unsigned int length; |
7422fa0c | 654 | #define EXTRACT_FMT_BC8_CODE \ |
8e420152 | 655 | length = 2; \ |
99c53aa9 DE |
656 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
657 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
658 | f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ | |
8e420152 | 659 | |
7422fa0c | 660 | #define EXTRACT_FMT_BC24_VARS \ |
8e420152 DE |
661 | /* Instruction fields. */ \ |
662 | UINT f_op1; \ | |
663 | UINT f_r1; \ | |
99c53aa9 | 664 | INT f_disp24; \ |
8e420152 | 665 | unsigned int length; |
7422fa0c | 666 | #define EXTRACT_FMT_BC24_CODE \ |
8e420152 | 667 | length = 4; \ |
99c53aa9 DE |
668 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
669 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
670 | f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ | |
8e420152 | 671 | |
7422fa0c | 672 | #define EXTRACT_FMT_BEQ_VARS \ |
8e420152 DE |
673 | /* Instruction fields. */ \ |
674 | UINT f_op1; \ | |
675 | UINT f_r1; \ | |
676 | UINT f_op2; \ | |
677 | UINT f_r2; \ | |
99c53aa9 | 678 | INT f_disp16; \ |
8e420152 | 679 | unsigned int length; |
7422fa0c | 680 | #define EXTRACT_FMT_BEQ_CODE \ |
8e420152 | 681 | length = 4; \ |
99c53aa9 DE |
682 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
683 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
684 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
685 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
686 | f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ | |
8e420152 | 687 | |
7422fa0c | 688 | #define EXTRACT_FMT_BEQZ_VARS \ |
8e420152 DE |
689 | /* Instruction fields. */ \ |
690 | UINT f_op1; \ | |
691 | UINT f_r1; \ | |
692 | UINT f_op2; \ | |
693 | UINT f_r2; \ | |
99c53aa9 | 694 | INT f_disp16; \ |
8e420152 | 695 | unsigned int length; |
7422fa0c | 696 | #define EXTRACT_FMT_BEQZ_CODE \ |
8e420152 | 697 | length = 4; \ |
99c53aa9 DE |
698 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
699 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
700 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
701 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
702 | f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ | |
8e420152 | 703 | |
7422fa0c | 704 | #define EXTRACT_FMT_BL8_VARS \ |
8e420152 DE |
705 | /* Instruction fields. */ \ |
706 | UINT f_op1; \ | |
707 | UINT f_r1; \ | |
99c53aa9 | 708 | INT f_disp8; \ |
8e420152 | 709 | unsigned int length; |
7422fa0c | 710 | #define EXTRACT_FMT_BL8_CODE \ |
8e420152 | 711 | length = 2; \ |
99c53aa9 DE |
712 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
713 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
714 | f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ | |
8e420152 | 715 | |
7422fa0c | 716 | #define EXTRACT_FMT_BL24_VARS \ |
8e420152 DE |
717 | /* Instruction fields. */ \ |
718 | UINT f_op1; \ | |
719 | UINT f_r1; \ | |
99c53aa9 | 720 | INT f_disp24; \ |
8e420152 | 721 | unsigned int length; |
7422fa0c | 722 | #define EXTRACT_FMT_BL24_CODE \ |
8e420152 | 723 | length = 4; \ |
99c53aa9 DE |
724 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
725 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
726 | f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ | |
8e420152 | 727 | |
7422fa0c | 728 | #define EXTRACT_FMT_BCL8_VARS \ |
8e420152 DE |
729 | /* Instruction fields. */ \ |
730 | UINT f_op1; \ | |
731 | UINT f_r1; \ | |
99c53aa9 | 732 | INT f_disp8; \ |
8e420152 | 733 | unsigned int length; |
7422fa0c | 734 | #define EXTRACT_FMT_BCL8_CODE \ |
8e420152 | 735 | length = 2; \ |
99c53aa9 DE |
736 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
737 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
738 | f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ | |
8e420152 | 739 | |
7422fa0c | 740 | #define EXTRACT_FMT_BCL24_VARS \ |
8e420152 DE |
741 | /* Instruction fields. */ \ |
742 | UINT f_op1; \ | |
743 | UINT f_r1; \ | |
99c53aa9 | 744 | INT f_disp24; \ |
8e420152 | 745 | unsigned int length; |
7422fa0c | 746 | #define EXTRACT_FMT_BCL24_CODE \ |
8e420152 | 747 | length = 4; \ |
99c53aa9 DE |
748 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
749 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
750 | f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ | |
8e420152 | 751 | |
7422fa0c | 752 | #define EXTRACT_FMT_BRA8_VARS \ |
8e420152 DE |
753 | /* Instruction fields. */ \ |
754 | UINT f_op1; \ | |
755 | UINT f_r1; \ | |
99c53aa9 | 756 | INT f_disp8; \ |
8e420152 | 757 | unsigned int length; |
7422fa0c | 758 | #define EXTRACT_FMT_BRA8_CODE \ |
8e420152 | 759 | length = 2; \ |
99c53aa9 DE |
760 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
761 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
762 | f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ | |
8e420152 | 763 | |
7422fa0c | 764 | #define EXTRACT_FMT_BRA24_VARS \ |
8e420152 DE |
765 | /* Instruction fields. */ \ |
766 | UINT f_op1; \ | |
767 | UINT f_r1; \ | |
99c53aa9 | 768 | INT f_disp24; \ |
8e420152 | 769 | unsigned int length; |
7422fa0c | 770 | #define EXTRACT_FMT_BRA24_CODE \ |
8e420152 | 771 | length = 4; \ |
99c53aa9 DE |
772 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
773 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
774 | f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ | |
8e420152 | 775 | |
7422fa0c | 776 | #define EXTRACT_FMT_CMP_VARS \ |
8e420152 DE |
777 | /* Instruction fields. */ \ |
778 | UINT f_op1; \ | |
779 | UINT f_r1; \ | |
780 | UINT f_op2; \ | |
781 | UINT f_r2; \ | |
782 | unsigned int length; | |
7422fa0c | 783 | #define EXTRACT_FMT_CMP_CODE \ |
8e420152 | 784 | length = 2; \ |
99c53aa9 DE |
785 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
786 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
787 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
788 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 789 | |
7422fa0c | 790 | #define EXTRACT_FMT_CMPI_VARS \ |
8e420152 DE |
791 | /* Instruction fields. */ \ |
792 | UINT f_op1; \ | |
793 | UINT f_r1; \ | |
794 | UINT f_op2; \ | |
795 | UINT f_r2; \ | |
99c53aa9 | 796 | INT f_simm16; \ |
8e420152 | 797 | unsigned int length; |
7422fa0c | 798 | #define EXTRACT_FMT_CMPI_CODE \ |
8e420152 | 799 | length = 4; \ |
99c53aa9 DE |
800 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
801 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
802 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
803 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
804 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
8e420152 | 805 | |
7422fa0c | 806 | #define EXTRACT_FMT_CMPZ_VARS \ |
8e420152 DE |
807 | /* Instruction fields. */ \ |
808 | UINT f_op1; \ | |
809 | UINT f_r1; \ | |
810 | UINT f_op2; \ | |
811 | UINT f_r2; \ | |
8e420152 | 812 | unsigned int length; |
7422fa0c | 813 | #define EXTRACT_FMT_CMPZ_CODE \ |
8e420152 | 814 | length = 2; \ |
99c53aa9 DE |
815 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
816 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
817 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
818 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 819 | |
7422fa0c | 820 | #define EXTRACT_FMT_DIV_VARS \ |
8e420152 DE |
821 | /* Instruction fields. */ \ |
822 | UINT f_op1; \ | |
823 | UINT f_r1; \ | |
824 | UINT f_op2; \ | |
825 | UINT f_r2; \ | |
99c53aa9 | 826 | INT f_simm16; \ |
8e420152 | 827 | unsigned int length; |
7422fa0c | 828 | #define EXTRACT_FMT_DIV_CODE \ |
8e420152 | 829 | length = 4; \ |
99c53aa9 DE |
830 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
831 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
832 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
833 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
834 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
8e420152 | 835 | |
7422fa0c | 836 | #define EXTRACT_FMT_JC_VARS \ |
8e420152 DE |
837 | /* Instruction fields. */ \ |
838 | UINT f_op1; \ | |
839 | UINT f_r1; \ | |
840 | UINT f_op2; \ | |
841 | UINT f_r2; \ | |
842 | unsigned int length; | |
7422fa0c | 843 | #define EXTRACT_FMT_JC_CODE \ |
8e420152 | 844 | length = 2; \ |
99c53aa9 DE |
845 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
846 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
847 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
848 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 849 | |
7422fa0c | 850 | #define EXTRACT_FMT_JL_VARS \ |
8e420152 DE |
851 | /* Instruction fields. */ \ |
852 | UINT f_op1; \ | |
853 | UINT f_r1; \ | |
854 | UINT f_op2; \ | |
855 | UINT f_r2; \ | |
856 | unsigned int length; | |
7422fa0c | 857 | #define EXTRACT_FMT_JL_CODE \ |
8e420152 | 858 | length = 2; \ |
99c53aa9 DE |
859 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
860 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
861 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
862 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 863 | |
7422fa0c | 864 | #define EXTRACT_FMT_JMP_VARS \ |
8e420152 DE |
865 | /* Instruction fields. */ \ |
866 | UINT f_op1; \ | |
867 | UINT f_r1; \ | |
868 | UINT f_op2; \ | |
869 | UINT f_r2; \ | |
870 | unsigned int length; | |
7422fa0c | 871 | #define EXTRACT_FMT_JMP_CODE \ |
8e420152 | 872 | length = 2; \ |
99c53aa9 DE |
873 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
874 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
875 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
876 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 877 | |
7422fa0c | 878 | #define EXTRACT_FMT_LD_VARS \ |
8e420152 DE |
879 | /* Instruction fields. */ \ |
880 | UINT f_op1; \ | |
881 | UINT f_r1; \ | |
882 | UINT f_op2; \ | |
883 | UINT f_r2; \ | |
884 | unsigned int length; | |
7422fa0c | 885 | #define EXTRACT_FMT_LD_CODE \ |
8e420152 | 886 | length = 2; \ |
99c53aa9 DE |
887 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
888 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
889 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
890 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 891 | |
7422fa0c | 892 | #define EXTRACT_FMT_LD_D_VARS \ |
8e420152 DE |
893 | /* Instruction fields. */ \ |
894 | UINT f_op1; \ | |
895 | UINT f_r1; \ | |
896 | UINT f_op2; \ | |
897 | UINT f_r2; \ | |
99c53aa9 | 898 | INT f_simm16; \ |
8e420152 | 899 | unsigned int length; |
7422fa0c | 900 | #define EXTRACT_FMT_LD_D_CODE \ |
8e420152 | 901 | length = 4; \ |
99c53aa9 DE |
902 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
903 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
904 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
905 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
906 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
8e420152 | 907 | |
7422fa0c | 908 | #define EXTRACT_FMT_LDB_VARS \ |
8e420152 DE |
909 | /* Instruction fields. */ \ |
910 | UINT f_op1; \ | |
911 | UINT f_r1; \ | |
912 | UINT f_op2; \ | |
913 | UINT f_r2; \ | |
914 | unsigned int length; | |
7422fa0c | 915 | #define EXTRACT_FMT_LDB_CODE \ |
8e420152 | 916 | length = 2; \ |
99c53aa9 DE |
917 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
918 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
919 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
920 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 921 | |
7422fa0c | 922 | #define EXTRACT_FMT_LDB_D_VARS \ |
8e420152 DE |
923 | /* Instruction fields. */ \ |
924 | UINT f_op1; \ | |
925 | UINT f_r1; \ | |
926 | UINT f_op2; \ | |
927 | UINT f_r2; \ | |
99c53aa9 | 928 | INT f_simm16; \ |
8e420152 | 929 | unsigned int length; |
7422fa0c | 930 | #define EXTRACT_FMT_LDB_D_CODE \ |
8e420152 | 931 | length = 4; \ |
99c53aa9 DE |
932 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
933 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
934 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
935 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
936 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
8e420152 | 937 | |
7422fa0c | 938 | #define EXTRACT_FMT_LDH_VARS \ |
8e420152 DE |
939 | /* Instruction fields. */ \ |
940 | UINT f_op1; \ | |
941 | UINT f_r1; \ | |
942 | UINT f_op2; \ | |
943 | UINT f_r2; \ | |
944 | unsigned int length; | |
7422fa0c | 945 | #define EXTRACT_FMT_LDH_CODE \ |
8e420152 | 946 | length = 2; \ |
99c53aa9 DE |
947 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
948 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
949 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
950 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 951 | |
7422fa0c | 952 | #define EXTRACT_FMT_LDH_D_VARS \ |
8e420152 DE |
953 | /* Instruction fields. */ \ |
954 | UINT f_op1; \ | |
955 | UINT f_r1; \ | |
956 | UINT f_op2; \ | |
957 | UINT f_r2; \ | |
99c53aa9 | 958 | INT f_simm16; \ |
8e420152 | 959 | unsigned int length; |
7422fa0c | 960 | #define EXTRACT_FMT_LDH_D_CODE \ |
8e420152 | 961 | length = 4; \ |
99c53aa9 DE |
962 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
963 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
964 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
965 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
966 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
8e420152 | 967 | |
7422fa0c | 968 | #define EXTRACT_FMT_LD_PLUS_VARS \ |
cab58155 DE |
969 | /* Instruction fields. */ \ |
970 | UINT f_op1; \ | |
971 | UINT f_r1; \ | |
972 | UINT f_op2; \ | |
973 | UINT f_r2; \ | |
974 | unsigned int length; | |
7422fa0c | 975 | #define EXTRACT_FMT_LD_PLUS_CODE \ |
cab58155 | 976 | length = 2; \ |
99c53aa9 DE |
977 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
978 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
979 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
980 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
cab58155 | 981 | |
7422fa0c | 982 | #define EXTRACT_FMT_LD24_VARS \ |
8e420152 DE |
983 | /* Instruction fields. */ \ |
984 | UINT f_op1; \ | |
985 | UINT f_r1; \ | |
986 | UINT f_uimm24; \ | |
987 | unsigned int length; | |
7422fa0c | 988 | #define EXTRACT_FMT_LD24_CODE \ |
8e420152 | 989 | length = 4; \ |
99c53aa9 DE |
990 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
991 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
992 | f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \ | |
8e420152 | 993 | |
7422fa0c | 994 | #define EXTRACT_FMT_LDI8_VARS \ |
8e420152 DE |
995 | /* Instruction fields. */ \ |
996 | UINT f_op1; \ | |
997 | UINT f_r1; \ | |
99c53aa9 | 998 | INT f_simm8; \ |
8e420152 | 999 | unsigned int length; |
7422fa0c | 1000 | #define EXTRACT_FMT_LDI8_CODE \ |
8e420152 | 1001 | length = 2; \ |
99c53aa9 DE |
1002 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1003 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1004 | f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \ | |
8e420152 | 1005 | |
7422fa0c | 1006 | #define EXTRACT_FMT_LDI16_VARS \ |
8e420152 DE |
1007 | /* Instruction fields. */ \ |
1008 | UINT f_op1; \ | |
1009 | UINT f_r1; \ | |
1010 | UINT f_op2; \ | |
1011 | UINT f_r2; \ | |
99c53aa9 | 1012 | INT f_simm16; \ |
8e420152 | 1013 | unsigned int length; |
7422fa0c | 1014 | #define EXTRACT_FMT_LDI16_CODE \ |
8e420152 | 1015 | length = 4; \ |
99c53aa9 DE |
1016 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
1017 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
1018 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
1019 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
1020 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
8e420152 | 1021 | |
7422fa0c | 1022 | #define EXTRACT_FMT_LOCK_VARS \ |
cab58155 DE |
1023 | /* Instruction fields. */ \ |
1024 | UINT f_op1; \ | |
1025 | UINT f_r1; \ | |
1026 | UINT f_op2; \ | |
1027 | UINT f_r2; \ | |
1028 | unsigned int length; | |
7422fa0c | 1029 | #define EXTRACT_FMT_LOCK_CODE \ |
cab58155 | 1030 | length = 2; \ |
99c53aa9 DE |
1031 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1032 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1033 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1034 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
cab58155 | 1035 | |
7422fa0c | 1036 | #define EXTRACT_FMT_MACHI_A_VARS \ |
8e420152 DE |
1037 | /* Instruction fields. */ \ |
1038 | UINT f_op1; \ | |
1039 | UINT f_r1; \ | |
1040 | UINT f_acc; \ | |
1041 | UINT f_op23; \ | |
1042 | UINT f_r2; \ | |
1043 | unsigned int length; | |
7422fa0c | 1044 | #define EXTRACT_FMT_MACHI_A_CODE \ |
8e420152 | 1045 | length = 2; \ |
99c53aa9 DE |
1046 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1047 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1048 | f_acc = EXTRACT_UINT (insn, 16, 8, 1); \ | |
1049 | f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \ | |
1050 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1051 | |
7422fa0c | 1052 | #define EXTRACT_FMT_MULHI_A_VARS \ |
8e420152 DE |
1053 | /* Instruction fields. */ \ |
1054 | UINT f_op1; \ | |
1055 | UINT f_r1; \ | |
1056 | UINT f_acc; \ | |
1057 | UINT f_op23; \ | |
1058 | UINT f_r2; \ | |
1059 | unsigned int length; | |
7422fa0c | 1060 | #define EXTRACT_FMT_MULHI_A_CODE \ |
8e420152 | 1061 | length = 2; \ |
99c53aa9 DE |
1062 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1063 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1064 | f_acc = EXTRACT_UINT (insn, 16, 8, 1); \ | |
1065 | f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \ | |
1066 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1067 | |
7422fa0c DE |
1068 | #define EXTRACT_FMT_MV_VARS \ |
1069 | /* Instruction fields. */ \ | |
1070 | UINT f_op1; \ | |
1071 | UINT f_r1; \ | |
1072 | UINT f_op2; \ | |
1073 | UINT f_r2; \ | |
1074 | unsigned int length; | |
1075 | #define EXTRACT_FMT_MV_CODE \ | |
1076 | length = 2; \ | |
99c53aa9 DE |
1077 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1078 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1079 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1080 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
7422fa0c DE |
1081 | |
1082 | #define EXTRACT_FMT_MVFACHI_A_VARS \ | |
8e420152 DE |
1083 | /* Instruction fields. */ \ |
1084 | UINT f_op1; \ | |
1085 | UINT f_r1; \ | |
1086 | UINT f_op2; \ | |
1087 | UINT f_accs; \ | |
1088 | UINT f_op3; \ | |
1089 | unsigned int length; | |
7422fa0c | 1090 | #define EXTRACT_FMT_MVFACHI_A_CODE \ |
8e420152 | 1091 | length = 2; \ |
99c53aa9 DE |
1092 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1093 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1094 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1095 | f_accs = EXTRACT_UINT (insn, 16, 12, 2); \ | |
1096 | f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \ | |
8e420152 | 1097 | |
7422fa0c | 1098 | #define EXTRACT_FMT_MVFC_VARS \ |
8e420152 DE |
1099 | /* Instruction fields. */ \ |
1100 | UINT f_op1; \ | |
1101 | UINT f_r1; \ | |
1102 | UINT f_op2; \ | |
1103 | UINT f_r2; \ | |
1104 | unsigned int length; | |
7422fa0c | 1105 | #define EXTRACT_FMT_MVFC_CODE \ |
8e420152 | 1106 | length = 2; \ |
99c53aa9 DE |
1107 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1108 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1109 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1110 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1111 | |
7422fa0c | 1112 | #define EXTRACT_FMT_MVTACHI_A_VARS \ |
8e420152 DE |
1113 | /* Instruction fields. */ \ |
1114 | UINT f_op1; \ | |
1115 | UINT f_r1; \ | |
1116 | UINT f_op2; \ | |
1117 | UINT f_accs; \ | |
1118 | UINT f_op3; \ | |
1119 | unsigned int length; | |
7422fa0c | 1120 | #define EXTRACT_FMT_MVTACHI_A_CODE \ |
8e420152 | 1121 | length = 2; \ |
99c53aa9 DE |
1122 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1123 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1124 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1125 | f_accs = EXTRACT_UINT (insn, 16, 12, 2); \ | |
1126 | f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \ | |
8e420152 | 1127 | |
7422fa0c | 1128 | #define EXTRACT_FMT_MVTC_VARS \ |
8e420152 DE |
1129 | /* Instruction fields. */ \ |
1130 | UINT f_op1; \ | |
1131 | UINT f_r1; \ | |
1132 | UINT f_op2; \ | |
1133 | UINT f_r2; \ | |
1134 | unsigned int length; | |
7422fa0c | 1135 | #define EXTRACT_FMT_MVTC_CODE \ |
8e420152 | 1136 | length = 2; \ |
99c53aa9 DE |
1137 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1138 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1139 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1140 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1141 | |
7422fa0c | 1142 | #define EXTRACT_FMT_NOP_VARS \ |
8e420152 DE |
1143 | /* Instruction fields. */ \ |
1144 | UINT f_op1; \ | |
1145 | UINT f_r1; \ | |
1146 | UINT f_op2; \ | |
1147 | UINT f_r2; \ | |
1148 | unsigned int length; | |
7422fa0c | 1149 | #define EXTRACT_FMT_NOP_CODE \ |
8e420152 | 1150 | length = 2; \ |
99c53aa9 DE |
1151 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1152 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1153 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1154 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1155 | |
7422fa0c | 1156 | #define EXTRACT_FMT_RAC_DSI_VARS \ |
8e420152 DE |
1157 | /* Instruction fields. */ \ |
1158 | UINT f_op1; \ | |
e0bd6e18 DE |
1159 | UINT f_accd; \ |
1160 | UINT f_bits67; \ | |
8e420152 | 1161 | UINT f_op2; \ |
b8a9943d | 1162 | UINT f_accs; \ |
e0bd6e18 DE |
1163 | UINT f_bit14; \ |
1164 | UINT f_imm1; \ | |
8e420152 | 1165 | unsigned int length; |
7422fa0c | 1166 | #define EXTRACT_FMT_RAC_DSI_CODE \ |
8e420152 | 1167 | length = 2; \ |
99c53aa9 DE |
1168 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1169 | f_accd = EXTRACT_UINT (insn, 16, 4, 2); \ | |
1170 | f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \ | |
1171 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1172 | f_accs = EXTRACT_UINT (insn, 16, 12, 2); \ | |
1173 | f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \ | |
1174 | f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \ | |
8e420152 | 1175 | |
7422fa0c | 1176 | #define EXTRACT_FMT_RTE_VARS \ |
e0bd6e18 DE |
1177 | /* Instruction fields. */ \ |
1178 | UINT f_op1; \ | |
cab58155 | 1179 | UINT f_r1; \ |
e0bd6e18 | 1180 | UINT f_op2; \ |
cab58155 | 1181 | UINT f_r2; \ |
e0bd6e18 | 1182 | unsigned int length; |
7422fa0c | 1183 | #define EXTRACT_FMT_RTE_CODE \ |
e0bd6e18 | 1184 | length = 2; \ |
99c53aa9 DE |
1185 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1186 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1187 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1188 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
e0bd6e18 | 1189 | |
7422fa0c | 1190 | #define EXTRACT_FMT_SETH_VARS \ |
e0bd6e18 DE |
1191 | /* Instruction fields. */ \ |
1192 | UINT f_op1; \ | |
cab58155 | 1193 | UINT f_r1; \ |
e0bd6e18 | 1194 | UINT f_op2; \ |
cab58155 DE |
1195 | UINT f_r2; \ |
1196 | UINT f_hi16; \ | |
1197 | unsigned int length; | |
7422fa0c | 1198 | #define EXTRACT_FMT_SETH_CODE \ |
cab58155 | 1199 | length = 4; \ |
99c53aa9 DE |
1200 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
1201 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
1202 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
1203 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
1204 | f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \ | |
cab58155 | 1205 | |
7422fa0c | 1206 | #define EXTRACT_FMT_SLL3_VARS \ |
cab58155 DE |
1207 | /* Instruction fields. */ \ |
1208 | UINT f_op1; \ | |
1209 | UINT f_r1; \ | |
1210 | UINT f_op2; \ | |
1211 | UINT f_r2; \ | |
99c53aa9 | 1212 | INT f_simm16; \ |
e0bd6e18 | 1213 | unsigned int length; |
7422fa0c | 1214 | #define EXTRACT_FMT_SLL3_CODE \ |
cab58155 | 1215 | length = 4; \ |
99c53aa9 DE |
1216 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
1217 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
1218 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
1219 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
1220 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
cab58155 | 1221 | |
7422fa0c | 1222 | #define EXTRACT_FMT_SLLI_VARS \ |
cab58155 DE |
1223 | /* Instruction fields. */ \ |
1224 | UINT f_op1; \ | |
1225 | UINT f_r1; \ | |
1226 | UINT f_shift_op2; \ | |
1227 | UINT f_uimm5; \ | |
1228 | unsigned int length; | |
7422fa0c | 1229 | #define EXTRACT_FMT_SLLI_CODE \ |
e0bd6e18 | 1230 | length = 2; \ |
99c53aa9 DE |
1231 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1232 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1233 | f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \ | |
1234 | f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \ | |
cab58155 | 1235 | |
7422fa0c | 1236 | #define EXTRACT_FMT_ST_VARS \ |
cab58155 DE |
1237 | /* Instruction fields. */ \ |
1238 | UINT f_op1; \ | |
1239 | UINT f_r1; \ | |
1240 | UINT f_op2; \ | |
1241 | UINT f_r2; \ | |
1242 | unsigned int length; | |
7422fa0c | 1243 | #define EXTRACT_FMT_ST_CODE \ |
cab58155 | 1244 | length = 2; \ |
99c53aa9 DE |
1245 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1246 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1247 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1248 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
e0bd6e18 | 1249 | |
7422fa0c | 1250 | #define EXTRACT_FMT_ST_D_VARS \ |
8e420152 DE |
1251 | /* Instruction fields. */ \ |
1252 | UINT f_op1; \ | |
1253 | UINT f_r1; \ | |
1254 | UINT f_op2; \ | |
b8a9943d | 1255 | UINT f_r2; \ |
99c53aa9 | 1256 | INT f_simm16; \ |
8e420152 | 1257 | unsigned int length; |
7422fa0c | 1258 | #define EXTRACT_FMT_ST_D_CODE \ |
cab58155 | 1259 | length = 4; \ |
99c53aa9 DE |
1260 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
1261 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
1262 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
1263 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
1264 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
cab58155 | 1265 | |
7422fa0c | 1266 | #define EXTRACT_FMT_STB_VARS \ |
cab58155 DE |
1267 | /* Instruction fields. */ \ |
1268 | UINT f_op1; \ | |
1269 | UINT f_r1; \ | |
1270 | UINT f_op2; \ | |
1271 | UINT f_r2; \ | |
1272 | unsigned int length; | |
7422fa0c | 1273 | #define EXTRACT_FMT_STB_CODE \ |
8e420152 | 1274 | length = 2; \ |
99c53aa9 DE |
1275 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1276 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1277 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1278 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1279 | |
7422fa0c | 1280 | #define EXTRACT_FMT_STB_D_VARS \ |
8e420152 DE |
1281 | /* Instruction fields. */ \ |
1282 | UINT f_op1; \ | |
1283 | UINT f_r1; \ | |
1284 | UINT f_op2; \ | |
1285 | UINT f_r2; \ | |
99c53aa9 | 1286 | INT f_simm16; \ |
8e420152 | 1287 | unsigned int length; |
7422fa0c | 1288 | #define EXTRACT_FMT_STB_D_CODE \ |
8e420152 | 1289 | length = 4; \ |
99c53aa9 DE |
1290 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
1291 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
1292 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
1293 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
1294 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
8e420152 | 1295 | |
7422fa0c | 1296 | #define EXTRACT_FMT_STH_VARS \ |
8e420152 DE |
1297 | /* Instruction fields. */ \ |
1298 | UINT f_op1; \ | |
1299 | UINT f_r1; \ | |
cab58155 DE |
1300 | UINT f_op2; \ |
1301 | UINT f_r2; \ | |
8e420152 | 1302 | unsigned int length; |
7422fa0c | 1303 | #define EXTRACT_FMT_STH_CODE \ |
8e420152 | 1304 | length = 2; \ |
99c53aa9 DE |
1305 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1306 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1307 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1308 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1309 | |
7422fa0c | 1310 | #define EXTRACT_FMT_STH_D_VARS \ |
8e420152 DE |
1311 | /* Instruction fields. */ \ |
1312 | UINT f_op1; \ | |
1313 | UINT f_r1; \ | |
1314 | UINT f_op2; \ | |
1315 | UINT f_r2; \ | |
99c53aa9 | 1316 | INT f_simm16; \ |
8e420152 | 1317 | unsigned int length; |
7422fa0c | 1318 | #define EXTRACT_FMT_STH_D_CODE \ |
8e420152 | 1319 | length = 4; \ |
99c53aa9 DE |
1320 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
1321 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
1322 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
1323 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
1324 | f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ | |
8e420152 | 1325 | |
7422fa0c | 1326 | #define EXTRACT_FMT_ST_PLUS_VARS \ |
cab58155 DE |
1327 | /* Instruction fields. */ \ |
1328 | UINT f_op1; \ | |
1329 | UINT f_r1; \ | |
1330 | UINT f_op2; \ | |
1331 | UINT f_r2; \ | |
1332 | unsigned int length; | |
7422fa0c | 1333 | #define EXTRACT_FMT_ST_PLUS_CODE \ |
cab58155 | 1334 | length = 2; \ |
99c53aa9 DE |
1335 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1336 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1337 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1338 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
cab58155 | 1339 | |
7422fa0c | 1340 | #define EXTRACT_FMT_TRAP_VARS \ |
8e420152 DE |
1341 | /* Instruction fields. */ \ |
1342 | UINT f_op1; \ | |
1343 | UINT f_r1; \ | |
1344 | UINT f_op2; \ | |
1345 | UINT f_uimm4; \ | |
1346 | unsigned int length; | |
7422fa0c | 1347 | #define EXTRACT_FMT_TRAP_CODE \ |
8e420152 | 1348 | length = 2; \ |
99c53aa9 DE |
1349 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1350 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1351 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1352 | f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1353 | |
7422fa0c | 1354 | #define EXTRACT_FMT_UNLOCK_VARS \ |
cab58155 DE |
1355 | /* Instruction fields. */ \ |
1356 | UINT f_op1; \ | |
1357 | UINT f_r1; \ | |
1358 | UINT f_op2; \ | |
1359 | UINT f_r2; \ | |
1360 | unsigned int length; | |
7422fa0c | 1361 | #define EXTRACT_FMT_UNLOCK_CODE \ |
cab58155 | 1362 | length = 2; \ |
99c53aa9 DE |
1363 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1364 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1365 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1366 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
cab58155 | 1367 | |
7422fa0c | 1368 | #define EXTRACT_FMT_SATB_VARS \ |
b8a9943d DE |
1369 | /* Instruction fields. */ \ |
1370 | UINT f_op1; \ | |
1371 | UINT f_r1; \ | |
1372 | UINT f_op2; \ | |
1373 | UINT f_r2; \ | |
1374 | UINT f_uimm16; \ | |
1375 | unsigned int length; | |
7422fa0c | 1376 | #define EXTRACT_FMT_SATB_CODE \ |
b8a9943d | 1377 | length = 4; \ |
99c53aa9 DE |
1378 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
1379 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
1380 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
1381 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
1382 | f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ | |
b8a9943d | 1383 | |
7422fa0c | 1384 | #define EXTRACT_FMT_SAT_VARS \ |
8e420152 DE |
1385 | /* Instruction fields. */ \ |
1386 | UINT f_op1; \ | |
1387 | UINT f_r1; \ | |
1388 | UINT f_op2; \ | |
1389 | UINT f_r2; \ | |
1390 | UINT f_uimm16; \ | |
1391 | unsigned int length; | |
7422fa0c | 1392 | #define EXTRACT_FMT_SAT_CODE \ |
8e420152 | 1393 | length = 4; \ |
99c53aa9 DE |
1394 | f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ |
1395 | f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ | |
1396 | f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ | |
1397 | f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ | |
1398 | f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ | |
8e420152 | 1399 | |
7422fa0c | 1400 | #define EXTRACT_FMT_SADD_VARS \ |
8e420152 DE |
1401 | /* Instruction fields. */ \ |
1402 | UINT f_op1; \ | |
1403 | UINT f_r1; \ | |
1404 | UINT f_op2; \ | |
1405 | UINT f_r2; \ | |
1406 | unsigned int length; | |
7422fa0c | 1407 | #define EXTRACT_FMT_SADD_CODE \ |
8e420152 | 1408 | length = 2; \ |
99c53aa9 DE |
1409 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1410 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1411 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1412 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1413 | |
7422fa0c | 1414 | #define EXTRACT_FMT_MACWU1_VARS \ |
8e420152 DE |
1415 | /* Instruction fields. */ \ |
1416 | UINT f_op1; \ | |
1417 | UINT f_r1; \ | |
1418 | UINT f_op2; \ | |
1419 | UINT f_r2; \ | |
1420 | unsigned int length; | |
7422fa0c | 1421 | #define EXTRACT_FMT_MACWU1_CODE \ |
8e420152 | 1422 | length = 2; \ |
99c53aa9 DE |
1423 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1424 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1425 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1426 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1427 | |
190659a2 DE |
1428 | #define EXTRACT_FMT_MSBLO_VARS \ |
1429 | /* Instruction fields. */ \ | |
1430 | UINT f_op1; \ | |
1431 | UINT f_r1; \ | |
1432 | UINT f_op2; \ | |
1433 | UINT f_r2; \ | |
1434 | unsigned int length; | |
1435 | #define EXTRACT_FMT_MSBLO_CODE \ | |
1436 | length = 2; \ | |
99c53aa9 DE |
1437 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1438 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1439 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1440 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
190659a2 | 1441 | |
7422fa0c | 1442 | #define EXTRACT_FMT_MULWU1_VARS \ |
8e420152 DE |
1443 | /* Instruction fields. */ \ |
1444 | UINT f_op1; \ | |
1445 | UINT f_r1; \ | |
1446 | UINT f_op2; \ | |
1447 | UINT f_r2; \ | |
1448 | unsigned int length; | |
7422fa0c | 1449 | #define EXTRACT_FMT_MULWU1_CODE \ |
8e420152 | 1450 | length = 2; \ |
99c53aa9 DE |
1451 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1452 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1453 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1454 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1455 | |
7422fa0c | 1456 | #define EXTRACT_FMT_SC_VARS \ |
8e420152 DE |
1457 | /* Instruction fields. */ \ |
1458 | UINT f_op1; \ | |
1459 | UINT f_r1; \ | |
1460 | UINT f_op2; \ | |
1461 | UINT f_r2; \ | |
1462 | unsigned int length; | |
7422fa0c | 1463 | #define EXTRACT_FMT_SC_CODE \ |
8e420152 | 1464 | length = 2; \ |
99c53aa9 DE |
1465 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
1466 | f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1467 | f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1468 | f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
8e420152 | 1469 | |
8de434bf | 1470 | /* Queued output values of an instruction. */ |
8e420152 | 1471 | |
e0bd6e18 | 1472 | struct parexec { |
8e420152 DE |
1473 | union { |
1474 | struct { /* e.g. add $dr,$sr */ | |
1475 | SI dr; | |
7422fa0c DE |
1476 | } fmt_add; |
1477 | struct { /* e.g. add3 $dr,$sr,$hash$slo16 */ | |
8de434bf | 1478 | SI dr; |
7422fa0c DE |
1479 | } fmt_add3; |
1480 | struct { /* e.g. and3 $dr,$sr,$uimm16 */ | |
8de434bf | 1481 | SI dr; |
7422fa0c DE |
1482 | } fmt_and3; |
1483 | struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */ | |
8de434bf | 1484 | SI dr; |
7422fa0c DE |
1485 | } fmt_or3; |
1486 | struct { /* e.g. addi $dr,$simm8 */ | |
8e420152 | 1487 | SI dr; |
7422fa0c | 1488 | } fmt_addi; |
cab58155 DE |
1489 | struct { /* e.g. addv $dr,$sr */ |
1490 | SI dr; | |
8de434bf | 1491 | BI condbit; |
7422fa0c DE |
1492 | } fmt_addv; |
1493 | struct { /* e.g. addv3 $dr,$sr,$simm16 */ | |
8de434bf DE |
1494 | SI dr; |
1495 | BI condbit; | |
7422fa0c | 1496 | } fmt_addv3; |
8e420152 | 1497 | struct { /* e.g. addx $dr,$sr */ |
8e420152 | 1498 | SI dr; |
8de434bf | 1499 | BI condbit; |
7422fa0c DE |
1500 | } fmt_addx; |
1501 | struct { /* e.g. bc.s $disp8 */ | |
8de434bf | 1502 | USI pc; |
7422fa0c DE |
1503 | } fmt_bc8; |
1504 | struct { /* e.g. bc.l $disp24 */ | |
8de434bf | 1505 | USI pc; |
7422fa0c | 1506 | } fmt_bc24; |
8e420152 | 1507 | struct { /* e.g. beq $src1,$src2,$disp16 */ |
8de434bf | 1508 | USI pc; |
7422fa0c | 1509 | } fmt_beq; |
8e420152 | 1510 | struct { /* e.g. beqz $src2,$disp16 */ |
8de434bf | 1511 | USI pc; |
7422fa0c DE |
1512 | } fmt_beqz; |
1513 | struct { /* e.g. bl.s $disp8 */ | |
8de434bf | 1514 | SI h_gr_14; |
8e420152 | 1515 | USI pc; |
7422fa0c DE |
1516 | } fmt_bl8; |
1517 | struct { /* e.g. bl.l $disp24 */ | |
8de434bf | 1518 | SI h_gr_14; |
8e420152 | 1519 | USI pc; |
7422fa0c DE |
1520 | } fmt_bl24; |
1521 | struct { /* e.g. bcl.s $disp8 */ | |
8de434bf | 1522 | SI h_gr_14; |
8e420152 | 1523 | USI pc; |
7422fa0c DE |
1524 | } fmt_bcl8; |
1525 | struct { /* e.g. bcl.l $disp24 */ | |
8de434bf | 1526 | SI h_gr_14; |
8e420152 | 1527 | USI pc; |
7422fa0c DE |
1528 | } fmt_bcl24; |
1529 | struct { /* e.g. bra.s $disp8 */ | |
8de434bf | 1530 | USI pc; |
7422fa0c DE |
1531 | } fmt_bra8; |
1532 | struct { /* e.g. bra.l $disp24 */ | |
8de434bf | 1533 | USI pc; |
7422fa0c | 1534 | } fmt_bra24; |
8e420152 | 1535 | struct { /* e.g. cmp $src1,$src2 */ |
8de434bf | 1536 | BI condbit; |
7422fa0c DE |
1537 | } fmt_cmp; |
1538 | struct { /* e.g. cmpi $src2,$simm16 */ | |
8de434bf | 1539 | BI condbit; |
7422fa0c | 1540 | } fmt_cmpi; |
8e420152 | 1541 | struct { /* e.g. cmpz $src2 */ |
8de434bf | 1542 | BI condbit; |
7422fa0c | 1543 | } fmt_cmpz; |
8e420152 DE |
1544 | struct { /* e.g. div $dr,$sr */ |
1545 | SI dr; | |
7422fa0c | 1546 | } fmt_div; |
8e420152 | 1547 | struct { /* e.g. jc $sr */ |
8de434bf | 1548 | USI pc; |
7422fa0c | 1549 | } fmt_jc; |
8e420152 | 1550 | struct { /* e.g. jl $sr */ |
8de434bf | 1551 | SI h_gr_14; |
8e420152 | 1552 | USI pc; |
7422fa0c | 1553 | } fmt_jl; |
8e420152 | 1554 | struct { /* e.g. jmp $sr */ |
8de434bf | 1555 | USI pc; |
7422fa0c | 1556 | } fmt_jmp; |
8e420152 | 1557 | struct { /* e.g. ld $dr,@$sr */ |
8de434bf | 1558 | SI dr; |
7422fa0c | 1559 | } fmt_ld; |
8e420152 | 1560 | struct { /* e.g. ld $dr,@($slo16,$sr) */ |
8de434bf | 1561 | SI dr; |
7422fa0c | 1562 | } fmt_ld_d; |
8e420152 | 1563 | struct { /* e.g. ldb $dr,@$sr */ |
8de434bf | 1564 | SI dr; |
7422fa0c | 1565 | } fmt_ldb; |
8e420152 | 1566 | struct { /* e.g. ldb $dr,@($slo16,$sr) */ |
8de434bf | 1567 | SI dr; |
7422fa0c | 1568 | } fmt_ldb_d; |
8e420152 | 1569 | struct { /* e.g. ldh $dr,@$sr */ |
8de434bf | 1570 | SI dr; |
7422fa0c | 1571 | } fmt_ldh; |
8e420152 | 1572 | struct { /* e.g. ldh $dr,@($slo16,$sr) */ |
8de434bf | 1573 | SI dr; |
7422fa0c | 1574 | } fmt_ldh_d; |
cab58155 | 1575 | struct { /* e.g. ld $dr,@$sr+ */ |
8de434bf | 1576 | SI dr; |
cab58155 | 1577 | SI sr; |
7422fa0c DE |
1578 | } fmt_ld_plus; |
1579 | struct { /* e.g. ld24 $dr,$uimm24 */ | |
8de434bf | 1580 | SI dr; |
7422fa0c DE |
1581 | } fmt_ld24; |
1582 | struct { /* e.g. ldi8 $dr,$simm8 */ | |
8de434bf | 1583 | SI dr; |
7422fa0c DE |
1584 | } fmt_ldi8; |
1585 | struct { /* e.g. ldi16 $dr,$hash$slo16 */ | |
8de434bf | 1586 | SI dr; |
7422fa0c | 1587 | } fmt_ldi16; |
cab58155 | 1588 | struct { /* e.g. lock $dr,@$sr */ |
8de434bf DE |
1589 | BI h_lock_0; |
1590 | SI dr; | |
7422fa0c | 1591 | } fmt_lock; |
8e420152 DE |
1592 | struct { /* e.g. machi $src1,$src2,$acc */ |
1593 | DI acc; | |
7422fa0c | 1594 | } fmt_machi_a; |
8e420152 | 1595 | struct { /* e.g. mulhi $src1,$src2,$acc */ |
8de434bf | 1596 | DI acc; |
7422fa0c | 1597 | } fmt_mulhi_a; |
8e420152 | 1598 | struct { /* e.g. mv $dr,$sr */ |
8de434bf | 1599 | SI dr; |
7422fa0c | 1600 | } fmt_mv; |
8e420152 | 1601 | struct { /* e.g. mvfachi $dr,$accs */ |
8de434bf | 1602 | SI dr; |
7422fa0c | 1603 | } fmt_mvfachi_a; |
8e420152 | 1604 | struct { /* e.g. mvfc $dr,$scr */ |
8de434bf | 1605 | SI dr; |
7422fa0c | 1606 | } fmt_mvfc; |
8e420152 DE |
1607 | struct { /* e.g. mvtachi $src1,$accs */ |
1608 | DI accs; | |
7422fa0c | 1609 | } fmt_mvtachi_a; |
8e420152 | 1610 | struct { /* e.g. mvtc $sr,$dcr */ |
8de434bf | 1611 | USI dcr; |
7422fa0c | 1612 | } fmt_mvtc; |
8e420152 DE |
1613 | struct { /* e.g. nop */ |
1614 | int empty; | |
7422fa0c DE |
1615 | } fmt_nop; |
1616 | struct { /* e.g. rac $accd,$accs,$imm1 */ | |
8de434bf | 1617 | DI accd; |
7422fa0c | 1618 | } fmt_rac_dsi; |
b8a9943d | 1619 | struct { /* e.g. rte */ |
8de434bf DE |
1620 | USI pc; |
1621 | USI h_cr_6; | |
1622 | UQI h_psw_0; | |
1623 | UQI h_bpsw_0; | |
7422fa0c DE |
1624 | } fmt_rte; |
1625 | struct { /* e.g. seth $dr,$hash$hi16 */ | |
8de434bf | 1626 | SI dr; |
7422fa0c DE |
1627 | } fmt_seth; |
1628 | struct { /* e.g. sll3 $dr,$sr,$simm16 */ | |
8de434bf | 1629 | SI dr; |
7422fa0c DE |
1630 | } fmt_sll3; |
1631 | struct { /* e.g. slli $dr,$uimm5 */ | |
8e420152 | 1632 | SI dr; |
7422fa0c | 1633 | } fmt_slli; |
cab58155 | 1634 | struct { /* e.g. st $src1,@$src2 */ |
8de434bf DE |
1635 | SI h_memory_src2; |
1636 | USI h_memory_src2_idx; | |
7422fa0c | 1637 | } fmt_st; |
8e420152 | 1638 | struct { /* e.g. st $src1,@($slo16,$src2) */ |
8de434bf DE |
1639 | SI h_memory_add__VM_src2_slo16; |
1640 | USI h_memory_add__VM_src2_slo16_idx; | |
7422fa0c | 1641 | } fmt_st_d; |
cab58155 | 1642 | struct { /* e.g. stb $src1,@$src2 */ |
8de434bf DE |
1643 | QI h_memory_src2; |
1644 | USI h_memory_src2_idx; | |
7422fa0c | 1645 | } fmt_stb; |
cab58155 | 1646 | struct { /* e.g. stb $src1,@($slo16,$src2) */ |
8de434bf DE |
1647 | QI h_memory_add__VM_src2_slo16; |
1648 | USI h_memory_add__VM_src2_slo16_idx; | |
7422fa0c | 1649 | } fmt_stb_d; |
cab58155 | 1650 | struct { /* e.g. sth $src1,@$src2 */ |
8de434bf DE |
1651 | HI h_memory_src2; |
1652 | USI h_memory_src2_idx; | |
7422fa0c | 1653 | } fmt_sth; |
cab58155 | 1654 | struct { /* e.g. sth $src1,@($slo16,$src2) */ |
8de434bf DE |
1655 | HI h_memory_add__VM_src2_slo16; |
1656 | USI h_memory_add__VM_src2_slo16_idx; | |
7422fa0c | 1657 | } fmt_sth_d; |
cab58155 | 1658 | struct { /* e.g. st $src1,@+$src2 */ |
8de434bf DE |
1659 | SI h_memory_new_src2; |
1660 | USI h_memory_new_src2_idx; | |
cab58155 | 1661 | SI src2; |
7422fa0c DE |
1662 | } fmt_st_plus; |
1663 | struct { /* e.g. trap $uimm4 */ | |
8de434bf DE |
1664 | USI h_cr_14; |
1665 | USI h_cr_6; | |
1666 | UQI h_bbpsw_0; | |
1667 | UQI h_bpsw_0; | |
1668 | UQI h_psw_0; | |
190659a2 | 1669 | SI pc; |
7422fa0c | 1670 | } fmt_trap; |
cab58155 | 1671 | struct { /* e.g. unlock $src1,@$src2 */ |
8de434bf DE |
1672 | SI h_memory_src2; |
1673 | USI h_memory_src2_idx; | |
1674 | BI h_lock_0; | |
7422fa0c | 1675 | } fmt_unlock; |
cab58155 | 1676 | struct { /* e.g. satb $dr,$sr */ |
8de434bf | 1677 | SI dr; |
7422fa0c | 1678 | } fmt_satb; |
cab58155 | 1679 | struct { /* e.g. sat $dr,$sr */ |
8de434bf | 1680 | SI dr; |
7422fa0c | 1681 | } fmt_sat; |
8e420152 | 1682 | struct { /* e.g. sadd */ |
7422fa0c DE |
1683 | DI h_accums_0; |
1684 | } fmt_sadd; | |
8e420152 | 1685 | struct { /* e.g. macwu1 $src1,$src2 */ |
b8a9943d | 1686 | DI h_accums_1; |
7422fa0c | 1687 | } fmt_macwu1; |
190659a2 DE |
1688 | struct { /* e.g. msblo $src1,$src2 */ |
1689 | DI accum; | |
190659a2 | 1690 | } fmt_msblo; |
cab58155 | 1691 | struct { /* e.g. mulwu1 $src1,$src2 */ |
8de434bf | 1692 | DI h_accums_1; |
7422fa0c | 1693 | } fmt_mulwu1; |
8e420152 | 1694 | struct { /* e.g. sc */ |
8de434bf | 1695 | int empty; |
7422fa0c | 1696 | } fmt_sc; |
8e420152 | 1697 | } operands; |
8de434bf DE |
1698 | /* For conditionally written operands, bitmask of which ones were. */ |
1699 | int written; | |
8e420152 DE |
1700 | }; |
1701 | ||
99c53aa9 DE |
1702 | /* Collection of various things for the trace handler to use. */ |
1703 | ||
1704 | typedef struct trace_record { | |
1705 | PCADDR pc; | |
1706 | /* FIXME:wip */ | |
1707 | } TRACE_RECORD; | |
1708 | ||
8de434bf | 1709 | #endif /* CPU_M32RXF_H */ |