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16b47b25 NC |
1 | /* Simulator instruction semantics for m32r2f. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
0f51e9bf | 5 | Copyright 1996-2010 Free Software Foundation, Inc. |
16b47b25 NC |
6 | |
7 | This file is part of the GNU simulators. | |
8 | ||
e9c60591 DE |
9 | This file is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
16b47b25 | 13 | |
e9c60591 DE |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
16b47b25 | 18 | |
e9c60591 DE |
19 | You should have received a copy of the GNU General Public License along |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
16b47b25 NC |
22 | |
23 | */ | |
24 | ||
25 | #ifdef DEFINE_LABELS | |
26 | ||
27 | /* The labels have the case they have because the enum of insn types | |
28 | is all uppercase and in the non-stdc case the insn symbol is built | |
29 | into the enum name. */ | |
30 | ||
31 | static struct { | |
32 | int index; | |
33 | void *label; | |
34 | } labels[] = { | |
35 | { M32R2F_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, | |
36 | { M32R2F_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, | |
37 | { M32R2F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, | |
38 | { M32R2F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, | |
39 | { M32R2F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, | |
40 | { M32R2F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, | |
41 | { M32R2F_INSN_ADD, && case_sem_INSN_ADD }, | |
42 | { M32R2F_INSN_ADD3, && case_sem_INSN_ADD3 }, | |
43 | { M32R2F_INSN_AND, && case_sem_INSN_AND }, | |
44 | { M32R2F_INSN_AND3, && case_sem_INSN_AND3 }, | |
45 | { M32R2F_INSN_OR, && case_sem_INSN_OR }, | |
46 | { M32R2F_INSN_OR3, && case_sem_INSN_OR3 }, | |
47 | { M32R2F_INSN_XOR, && case_sem_INSN_XOR }, | |
48 | { M32R2F_INSN_XOR3, && case_sem_INSN_XOR3 }, | |
49 | { M32R2F_INSN_ADDI, && case_sem_INSN_ADDI }, | |
50 | { M32R2F_INSN_ADDV, && case_sem_INSN_ADDV }, | |
51 | { M32R2F_INSN_ADDV3, && case_sem_INSN_ADDV3 }, | |
52 | { M32R2F_INSN_ADDX, && case_sem_INSN_ADDX }, | |
53 | { M32R2F_INSN_BC8, && case_sem_INSN_BC8 }, | |
54 | { M32R2F_INSN_BC24, && case_sem_INSN_BC24 }, | |
55 | { M32R2F_INSN_BEQ, && case_sem_INSN_BEQ }, | |
56 | { M32R2F_INSN_BEQZ, && case_sem_INSN_BEQZ }, | |
57 | { M32R2F_INSN_BGEZ, && case_sem_INSN_BGEZ }, | |
58 | { M32R2F_INSN_BGTZ, && case_sem_INSN_BGTZ }, | |
59 | { M32R2F_INSN_BLEZ, && case_sem_INSN_BLEZ }, | |
60 | { M32R2F_INSN_BLTZ, && case_sem_INSN_BLTZ }, | |
61 | { M32R2F_INSN_BNEZ, && case_sem_INSN_BNEZ }, | |
62 | { M32R2F_INSN_BL8, && case_sem_INSN_BL8 }, | |
63 | { M32R2F_INSN_BL24, && case_sem_INSN_BL24 }, | |
64 | { M32R2F_INSN_BCL8, && case_sem_INSN_BCL8 }, | |
65 | { M32R2F_INSN_BCL24, && case_sem_INSN_BCL24 }, | |
66 | { M32R2F_INSN_BNC8, && case_sem_INSN_BNC8 }, | |
67 | { M32R2F_INSN_BNC24, && case_sem_INSN_BNC24 }, | |
68 | { M32R2F_INSN_BNE, && case_sem_INSN_BNE }, | |
69 | { M32R2F_INSN_BRA8, && case_sem_INSN_BRA8 }, | |
70 | { M32R2F_INSN_BRA24, && case_sem_INSN_BRA24 }, | |
71 | { M32R2F_INSN_BNCL8, && case_sem_INSN_BNCL8 }, | |
72 | { M32R2F_INSN_BNCL24, && case_sem_INSN_BNCL24 }, | |
73 | { M32R2F_INSN_CMP, && case_sem_INSN_CMP }, | |
74 | { M32R2F_INSN_CMPI, && case_sem_INSN_CMPI }, | |
75 | { M32R2F_INSN_CMPU, && case_sem_INSN_CMPU }, | |
76 | { M32R2F_INSN_CMPUI, && case_sem_INSN_CMPUI }, | |
77 | { M32R2F_INSN_CMPEQ, && case_sem_INSN_CMPEQ }, | |
78 | { M32R2F_INSN_CMPZ, && case_sem_INSN_CMPZ }, | |
79 | { M32R2F_INSN_DIV, && case_sem_INSN_DIV }, | |
80 | { M32R2F_INSN_DIVU, && case_sem_INSN_DIVU }, | |
81 | { M32R2F_INSN_REM, && case_sem_INSN_REM }, | |
82 | { M32R2F_INSN_REMU, && case_sem_INSN_REMU }, | |
83 | { M32R2F_INSN_REMH, && case_sem_INSN_REMH }, | |
84 | { M32R2F_INSN_REMUH, && case_sem_INSN_REMUH }, | |
85 | { M32R2F_INSN_REMB, && case_sem_INSN_REMB }, | |
86 | { M32R2F_INSN_REMUB, && case_sem_INSN_REMUB }, | |
87 | { M32R2F_INSN_DIVUH, && case_sem_INSN_DIVUH }, | |
88 | { M32R2F_INSN_DIVB, && case_sem_INSN_DIVB }, | |
89 | { M32R2F_INSN_DIVUB, && case_sem_INSN_DIVUB }, | |
90 | { M32R2F_INSN_DIVH, && case_sem_INSN_DIVH }, | |
91 | { M32R2F_INSN_JC, && case_sem_INSN_JC }, | |
92 | { M32R2F_INSN_JNC, && case_sem_INSN_JNC }, | |
93 | { M32R2F_INSN_JL, && case_sem_INSN_JL }, | |
94 | { M32R2F_INSN_JMP, && case_sem_INSN_JMP }, | |
95 | { M32R2F_INSN_LD, && case_sem_INSN_LD }, | |
96 | { M32R2F_INSN_LD_D, && case_sem_INSN_LD_D }, | |
97 | { M32R2F_INSN_LDB, && case_sem_INSN_LDB }, | |
98 | { M32R2F_INSN_LDB_D, && case_sem_INSN_LDB_D }, | |
99 | { M32R2F_INSN_LDH, && case_sem_INSN_LDH }, | |
100 | { M32R2F_INSN_LDH_D, && case_sem_INSN_LDH_D }, | |
101 | { M32R2F_INSN_LDUB, && case_sem_INSN_LDUB }, | |
102 | { M32R2F_INSN_LDUB_D, && case_sem_INSN_LDUB_D }, | |
103 | { M32R2F_INSN_LDUH, && case_sem_INSN_LDUH }, | |
104 | { M32R2F_INSN_LDUH_D, && case_sem_INSN_LDUH_D }, | |
105 | { M32R2F_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS }, | |
106 | { M32R2F_INSN_LD24, && case_sem_INSN_LD24 }, | |
107 | { M32R2F_INSN_LDI8, && case_sem_INSN_LDI8 }, | |
108 | { M32R2F_INSN_LDI16, && case_sem_INSN_LDI16 }, | |
109 | { M32R2F_INSN_LOCK, && case_sem_INSN_LOCK }, | |
110 | { M32R2F_INSN_MACHI_A, && case_sem_INSN_MACHI_A }, | |
111 | { M32R2F_INSN_MACLO_A, && case_sem_INSN_MACLO_A }, | |
112 | { M32R2F_INSN_MACWHI_A, && case_sem_INSN_MACWHI_A }, | |
113 | { M32R2F_INSN_MACWLO_A, && case_sem_INSN_MACWLO_A }, | |
114 | { M32R2F_INSN_MUL, && case_sem_INSN_MUL }, | |
115 | { M32R2F_INSN_MULHI_A, && case_sem_INSN_MULHI_A }, | |
116 | { M32R2F_INSN_MULLO_A, && case_sem_INSN_MULLO_A }, | |
117 | { M32R2F_INSN_MULWHI_A, && case_sem_INSN_MULWHI_A }, | |
118 | { M32R2F_INSN_MULWLO_A, && case_sem_INSN_MULWLO_A }, | |
119 | { M32R2F_INSN_MV, && case_sem_INSN_MV }, | |
120 | { M32R2F_INSN_MVFACHI_A, && case_sem_INSN_MVFACHI_A }, | |
121 | { M32R2F_INSN_MVFACLO_A, && case_sem_INSN_MVFACLO_A }, | |
122 | { M32R2F_INSN_MVFACMI_A, && case_sem_INSN_MVFACMI_A }, | |
123 | { M32R2F_INSN_MVFC, && case_sem_INSN_MVFC }, | |
124 | { M32R2F_INSN_MVTACHI_A, && case_sem_INSN_MVTACHI_A }, | |
125 | { M32R2F_INSN_MVTACLO_A, && case_sem_INSN_MVTACLO_A }, | |
126 | { M32R2F_INSN_MVTC, && case_sem_INSN_MVTC }, | |
127 | { M32R2F_INSN_NEG, && case_sem_INSN_NEG }, | |
128 | { M32R2F_INSN_NOP, && case_sem_INSN_NOP }, | |
129 | { M32R2F_INSN_NOT, && case_sem_INSN_NOT }, | |
130 | { M32R2F_INSN_RAC_DSI, && case_sem_INSN_RAC_DSI }, | |
131 | { M32R2F_INSN_RACH_DSI, && case_sem_INSN_RACH_DSI }, | |
132 | { M32R2F_INSN_RTE, && case_sem_INSN_RTE }, | |
133 | { M32R2F_INSN_SETH, && case_sem_INSN_SETH }, | |
134 | { M32R2F_INSN_SLL, && case_sem_INSN_SLL }, | |
135 | { M32R2F_INSN_SLL3, && case_sem_INSN_SLL3 }, | |
136 | { M32R2F_INSN_SLLI, && case_sem_INSN_SLLI }, | |
137 | { M32R2F_INSN_SRA, && case_sem_INSN_SRA }, | |
138 | { M32R2F_INSN_SRA3, && case_sem_INSN_SRA3 }, | |
139 | { M32R2F_INSN_SRAI, && case_sem_INSN_SRAI }, | |
140 | { M32R2F_INSN_SRL, && case_sem_INSN_SRL }, | |
141 | { M32R2F_INSN_SRL3, && case_sem_INSN_SRL3 }, | |
142 | { M32R2F_INSN_SRLI, && case_sem_INSN_SRLI }, | |
143 | { M32R2F_INSN_ST, && case_sem_INSN_ST }, | |
144 | { M32R2F_INSN_ST_D, && case_sem_INSN_ST_D }, | |
145 | { M32R2F_INSN_STB, && case_sem_INSN_STB }, | |
146 | { M32R2F_INSN_STB_D, && case_sem_INSN_STB_D }, | |
147 | { M32R2F_INSN_STH, && case_sem_INSN_STH }, | |
148 | { M32R2F_INSN_STH_D, && case_sem_INSN_STH_D }, | |
149 | { M32R2F_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS }, | |
150 | { M32R2F_INSN_STH_PLUS, && case_sem_INSN_STH_PLUS }, | |
151 | { M32R2F_INSN_STB_PLUS, && case_sem_INSN_STB_PLUS }, | |
152 | { M32R2F_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS }, | |
153 | { M32R2F_INSN_SUB, && case_sem_INSN_SUB }, | |
154 | { M32R2F_INSN_SUBV, && case_sem_INSN_SUBV }, | |
155 | { M32R2F_INSN_SUBX, && case_sem_INSN_SUBX }, | |
156 | { M32R2F_INSN_TRAP, && case_sem_INSN_TRAP }, | |
157 | { M32R2F_INSN_UNLOCK, && case_sem_INSN_UNLOCK }, | |
158 | { M32R2F_INSN_SATB, && case_sem_INSN_SATB }, | |
159 | { M32R2F_INSN_SATH, && case_sem_INSN_SATH }, | |
160 | { M32R2F_INSN_SAT, && case_sem_INSN_SAT }, | |
161 | { M32R2F_INSN_PCMPBZ, && case_sem_INSN_PCMPBZ }, | |
162 | { M32R2F_INSN_SADD, && case_sem_INSN_SADD }, | |
163 | { M32R2F_INSN_MACWU1, && case_sem_INSN_MACWU1 }, | |
164 | { M32R2F_INSN_MSBLO, && case_sem_INSN_MSBLO }, | |
165 | { M32R2F_INSN_MULWU1, && case_sem_INSN_MULWU1 }, | |
166 | { M32R2F_INSN_MACLH1, && case_sem_INSN_MACLH1 }, | |
167 | { M32R2F_INSN_SC, && case_sem_INSN_SC }, | |
168 | { M32R2F_INSN_SNC, && case_sem_INSN_SNC }, | |
169 | { M32R2F_INSN_CLRPSW, && case_sem_INSN_CLRPSW }, | |
170 | { M32R2F_INSN_SETPSW, && case_sem_INSN_SETPSW }, | |
171 | { M32R2F_INSN_BSET, && case_sem_INSN_BSET }, | |
172 | { M32R2F_INSN_BCLR, && case_sem_INSN_BCLR }, | |
173 | { M32R2F_INSN_BTST, && case_sem_INSN_BTST }, | |
174 | { M32R2F_INSN_PAR_ADD, && case_sem_INSN_PAR_ADD }, | |
175 | { M32R2F_INSN_WRITE_ADD, && case_sem_INSN_WRITE_ADD }, | |
176 | { M32R2F_INSN_PAR_AND, && case_sem_INSN_PAR_AND }, | |
177 | { M32R2F_INSN_WRITE_AND, && case_sem_INSN_WRITE_AND }, | |
178 | { M32R2F_INSN_PAR_OR, && case_sem_INSN_PAR_OR }, | |
179 | { M32R2F_INSN_WRITE_OR, && case_sem_INSN_WRITE_OR }, | |
180 | { M32R2F_INSN_PAR_XOR, && case_sem_INSN_PAR_XOR }, | |
181 | { M32R2F_INSN_WRITE_XOR, && case_sem_INSN_WRITE_XOR }, | |
182 | { M32R2F_INSN_PAR_ADDI, && case_sem_INSN_PAR_ADDI }, | |
183 | { M32R2F_INSN_WRITE_ADDI, && case_sem_INSN_WRITE_ADDI }, | |
184 | { M32R2F_INSN_PAR_ADDV, && case_sem_INSN_PAR_ADDV }, | |
185 | { M32R2F_INSN_WRITE_ADDV, && case_sem_INSN_WRITE_ADDV }, | |
186 | { M32R2F_INSN_PAR_ADDX, && case_sem_INSN_PAR_ADDX }, | |
187 | { M32R2F_INSN_WRITE_ADDX, && case_sem_INSN_WRITE_ADDX }, | |
188 | { M32R2F_INSN_PAR_BC8, && case_sem_INSN_PAR_BC8 }, | |
189 | { M32R2F_INSN_WRITE_BC8, && case_sem_INSN_WRITE_BC8 }, | |
190 | { M32R2F_INSN_PAR_BL8, && case_sem_INSN_PAR_BL8 }, | |
191 | { M32R2F_INSN_WRITE_BL8, && case_sem_INSN_WRITE_BL8 }, | |
192 | { M32R2F_INSN_PAR_BCL8, && case_sem_INSN_PAR_BCL8 }, | |
193 | { M32R2F_INSN_WRITE_BCL8, && case_sem_INSN_WRITE_BCL8 }, | |
194 | { M32R2F_INSN_PAR_BNC8, && case_sem_INSN_PAR_BNC8 }, | |
195 | { M32R2F_INSN_WRITE_BNC8, && case_sem_INSN_WRITE_BNC8 }, | |
196 | { M32R2F_INSN_PAR_BRA8, && case_sem_INSN_PAR_BRA8 }, | |
197 | { M32R2F_INSN_WRITE_BRA8, && case_sem_INSN_WRITE_BRA8 }, | |
198 | { M32R2F_INSN_PAR_BNCL8, && case_sem_INSN_PAR_BNCL8 }, | |
199 | { M32R2F_INSN_WRITE_BNCL8, && case_sem_INSN_WRITE_BNCL8 }, | |
200 | { M32R2F_INSN_PAR_CMP, && case_sem_INSN_PAR_CMP }, | |
201 | { M32R2F_INSN_WRITE_CMP, && case_sem_INSN_WRITE_CMP }, | |
202 | { M32R2F_INSN_PAR_CMPU, && case_sem_INSN_PAR_CMPU }, | |
203 | { M32R2F_INSN_WRITE_CMPU, && case_sem_INSN_WRITE_CMPU }, | |
204 | { M32R2F_INSN_PAR_CMPEQ, && case_sem_INSN_PAR_CMPEQ }, | |
205 | { M32R2F_INSN_WRITE_CMPEQ, && case_sem_INSN_WRITE_CMPEQ }, | |
206 | { M32R2F_INSN_PAR_CMPZ, && case_sem_INSN_PAR_CMPZ }, | |
207 | { M32R2F_INSN_WRITE_CMPZ, && case_sem_INSN_WRITE_CMPZ }, | |
208 | { M32R2F_INSN_PAR_JC, && case_sem_INSN_PAR_JC }, | |
209 | { M32R2F_INSN_WRITE_JC, && case_sem_INSN_WRITE_JC }, | |
210 | { M32R2F_INSN_PAR_JNC, && case_sem_INSN_PAR_JNC }, | |
211 | { M32R2F_INSN_WRITE_JNC, && case_sem_INSN_WRITE_JNC }, | |
212 | { M32R2F_INSN_PAR_JL, && case_sem_INSN_PAR_JL }, | |
213 | { M32R2F_INSN_WRITE_JL, && case_sem_INSN_WRITE_JL }, | |
214 | { M32R2F_INSN_PAR_JMP, && case_sem_INSN_PAR_JMP }, | |
215 | { M32R2F_INSN_WRITE_JMP, && case_sem_INSN_WRITE_JMP }, | |
216 | { M32R2F_INSN_PAR_LD, && case_sem_INSN_PAR_LD }, | |
217 | { M32R2F_INSN_WRITE_LD, && case_sem_INSN_WRITE_LD }, | |
218 | { M32R2F_INSN_PAR_LDB, && case_sem_INSN_PAR_LDB }, | |
219 | { M32R2F_INSN_WRITE_LDB, && case_sem_INSN_WRITE_LDB }, | |
220 | { M32R2F_INSN_PAR_LDH, && case_sem_INSN_PAR_LDH }, | |
221 | { M32R2F_INSN_WRITE_LDH, && case_sem_INSN_WRITE_LDH }, | |
222 | { M32R2F_INSN_PAR_LDUB, && case_sem_INSN_PAR_LDUB }, | |
223 | { M32R2F_INSN_WRITE_LDUB, && case_sem_INSN_WRITE_LDUB }, | |
224 | { M32R2F_INSN_PAR_LDUH, && case_sem_INSN_PAR_LDUH }, | |
225 | { M32R2F_INSN_WRITE_LDUH, && case_sem_INSN_WRITE_LDUH }, | |
226 | { M32R2F_INSN_PAR_LD_PLUS, && case_sem_INSN_PAR_LD_PLUS }, | |
227 | { M32R2F_INSN_WRITE_LD_PLUS, && case_sem_INSN_WRITE_LD_PLUS }, | |
228 | { M32R2F_INSN_PAR_LDI8, && case_sem_INSN_PAR_LDI8 }, | |
229 | { M32R2F_INSN_WRITE_LDI8, && case_sem_INSN_WRITE_LDI8 }, | |
230 | { M32R2F_INSN_PAR_LOCK, && case_sem_INSN_PAR_LOCK }, | |
231 | { M32R2F_INSN_WRITE_LOCK, && case_sem_INSN_WRITE_LOCK }, | |
232 | { M32R2F_INSN_PAR_MACHI_A, && case_sem_INSN_PAR_MACHI_A }, | |
233 | { M32R2F_INSN_WRITE_MACHI_A, && case_sem_INSN_WRITE_MACHI_A }, | |
234 | { M32R2F_INSN_PAR_MACLO_A, && case_sem_INSN_PAR_MACLO_A }, | |
235 | { M32R2F_INSN_WRITE_MACLO_A, && case_sem_INSN_WRITE_MACLO_A }, | |
236 | { M32R2F_INSN_PAR_MACWHI_A, && case_sem_INSN_PAR_MACWHI_A }, | |
237 | { M32R2F_INSN_WRITE_MACWHI_A, && case_sem_INSN_WRITE_MACWHI_A }, | |
238 | { M32R2F_INSN_PAR_MACWLO_A, && case_sem_INSN_PAR_MACWLO_A }, | |
239 | { M32R2F_INSN_WRITE_MACWLO_A, && case_sem_INSN_WRITE_MACWLO_A }, | |
240 | { M32R2F_INSN_PAR_MUL, && case_sem_INSN_PAR_MUL }, | |
241 | { M32R2F_INSN_WRITE_MUL, && case_sem_INSN_WRITE_MUL }, | |
242 | { M32R2F_INSN_PAR_MULHI_A, && case_sem_INSN_PAR_MULHI_A }, | |
243 | { M32R2F_INSN_WRITE_MULHI_A, && case_sem_INSN_WRITE_MULHI_A }, | |
244 | { M32R2F_INSN_PAR_MULLO_A, && case_sem_INSN_PAR_MULLO_A }, | |
245 | { M32R2F_INSN_WRITE_MULLO_A, && case_sem_INSN_WRITE_MULLO_A }, | |
246 | { M32R2F_INSN_PAR_MULWHI_A, && case_sem_INSN_PAR_MULWHI_A }, | |
247 | { M32R2F_INSN_WRITE_MULWHI_A, && case_sem_INSN_WRITE_MULWHI_A }, | |
248 | { M32R2F_INSN_PAR_MULWLO_A, && case_sem_INSN_PAR_MULWLO_A }, | |
249 | { M32R2F_INSN_WRITE_MULWLO_A, && case_sem_INSN_WRITE_MULWLO_A }, | |
250 | { M32R2F_INSN_PAR_MV, && case_sem_INSN_PAR_MV }, | |
251 | { M32R2F_INSN_WRITE_MV, && case_sem_INSN_WRITE_MV }, | |
252 | { M32R2F_INSN_PAR_MVFACHI_A, && case_sem_INSN_PAR_MVFACHI_A }, | |
253 | { M32R2F_INSN_WRITE_MVFACHI_A, && case_sem_INSN_WRITE_MVFACHI_A }, | |
254 | { M32R2F_INSN_PAR_MVFACLO_A, && case_sem_INSN_PAR_MVFACLO_A }, | |
255 | { M32R2F_INSN_WRITE_MVFACLO_A, && case_sem_INSN_WRITE_MVFACLO_A }, | |
256 | { M32R2F_INSN_PAR_MVFACMI_A, && case_sem_INSN_PAR_MVFACMI_A }, | |
257 | { M32R2F_INSN_WRITE_MVFACMI_A, && case_sem_INSN_WRITE_MVFACMI_A }, | |
258 | { M32R2F_INSN_PAR_MVFC, && case_sem_INSN_PAR_MVFC }, | |
259 | { M32R2F_INSN_WRITE_MVFC, && case_sem_INSN_WRITE_MVFC }, | |
260 | { M32R2F_INSN_PAR_MVTACHI_A, && case_sem_INSN_PAR_MVTACHI_A }, | |
261 | { M32R2F_INSN_WRITE_MVTACHI_A, && case_sem_INSN_WRITE_MVTACHI_A }, | |
262 | { M32R2F_INSN_PAR_MVTACLO_A, && case_sem_INSN_PAR_MVTACLO_A }, | |
263 | { M32R2F_INSN_WRITE_MVTACLO_A, && case_sem_INSN_WRITE_MVTACLO_A }, | |
264 | { M32R2F_INSN_PAR_MVTC, && case_sem_INSN_PAR_MVTC }, | |
265 | { M32R2F_INSN_WRITE_MVTC, && case_sem_INSN_WRITE_MVTC }, | |
266 | { M32R2F_INSN_PAR_NEG, && case_sem_INSN_PAR_NEG }, | |
267 | { M32R2F_INSN_WRITE_NEG, && case_sem_INSN_WRITE_NEG }, | |
268 | { M32R2F_INSN_PAR_NOP, && case_sem_INSN_PAR_NOP }, | |
269 | { M32R2F_INSN_WRITE_NOP, && case_sem_INSN_WRITE_NOP }, | |
270 | { M32R2F_INSN_PAR_NOT, && case_sem_INSN_PAR_NOT }, | |
271 | { M32R2F_INSN_WRITE_NOT, && case_sem_INSN_WRITE_NOT }, | |
272 | { M32R2F_INSN_PAR_RAC_DSI, && case_sem_INSN_PAR_RAC_DSI }, | |
273 | { M32R2F_INSN_WRITE_RAC_DSI, && case_sem_INSN_WRITE_RAC_DSI }, | |
274 | { M32R2F_INSN_PAR_RACH_DSI, && case_sem_INSN_PAR_RACH_DSI }, | |
275 | { M32R2F_INSN_WRITE_RACH_DSI, && case_sem_INSN_WRITE_RACH_DSI }, | |
276 | { M32R2F_INSN_PAR_RTE, && case_sem_INSN_PAR_RTE }, | |
277 | { M32R2F_INSN_WRITE_RTE, && case_sem_INSN_WRITE_RTE }, | |
278 | { M32R2F_INSN_PAR_SLL, && case_sem_INSN_PAR_SLL }, | |
279 | { M32R2F_INSN_WRITE_SLL, && case_sem_INSN_WRITE_SLL }, | |
280 | { M32R2F_INSN_PAR_SLLI, && case_sem_INSN_PAR_SLLI }, | |
281 | { M32R2F_INSN_WRITE_SLLI, && case_sem_INSN_WRITE_SLLI }, | |
282 | { M32R2F_INSN_PAR_SRA, && case_sem_INSN_PAR_SRA }, | |
283 | { M32R2F_INSN_WRITE_SRA, && case_sem_INSN_WRITE_SRA }, | |
284 | { M32R2F_INSN_PAR_SRAI, && case_sem_INSN_PAR_SRAI }, | |
285 | { M32R2F_INSN_WRITE_SRAI, && case_sem_INSN_WRITE_SRAI }, | |
286 | { M32R2F_INSN_PAR_SRL, && case_sem_INSN_PAR_SRL }, | |
287 | { M32R2F_INSN_WRITE_SRL, && case_sem_INSN_WRITE_SRL }, | |
288 | { M32R2F_INSN_PAR_SRLI, && case_sem_INSN_PAR_SRLI }, | |
289 | { M32R2F_INSN_WRITE_SRLI, && case_sem_INSN_WRITE_SRLI }, | |
290 | { M32R2F_INSN_PAR_ST, && case_sem_INSN_PAR_ST }, | |
291 | { M32R2F_INSN_WRITE_ST, && case_sem_INSN_WRITE_ST }, | |
292 | { M32R2F_INSN_PAR_STB, && case_sem_INSN_PAR_STB }, | |
293 | { M32R2F_INSN_WRITE_STB, && case_sem_INSN_WRITE_STB }, | |
294 | { M32R2F_INSN_PAR_STH, && case_sem_INSN_PAR_STH }, | |
295 | { M32R2F_INSN_WRITE_STH, && case_sem_INSN_WRITE_STH }, | |
296 | { M32R2F_INSN_PAR_ST_PLUS, && case_sem_INSN_PAR_ST_PLUS }, | |
297 | { M32R2F_INSN_WRITE_ST_PLUS, && case_sem_INSN_WRITE_ST_PLUS }, | |
298 | { M32R2F_INSN_PAR_STH_PLUS, && case_sem_INSN_PAR_STH_PLUS }, | |
299 | { M32R2F_INSN_WRITE_STH_PLUS, && case_sem_INSN_WRITE_STH_PLUS }, | |
300 | { M32R2F_INSN_PAR_STB_PLUS, && case_sem_INSN_PAR_STB_PLUS }, | |
301 | { M32R2F_INSN_WRITE_STB_PLUS, && case_sem_INSN_WRITE_STB_PLUS }, | |
302 | { M32R2F_INSN_PAR_ST_MINUS, && case_sem_INSN_PAR_ST_MINUS }, | |
303 | { M32R2F_INSN_WRITE_ST_MINUS, && case_sem_INSN_WRITE_ST_MINUS }, | |
304 | { M32R2F_INSN_PAR_SUB, && case_sem_INSN_PAR_SUB }, | |
305 | { M32R2F_INSN_WRITE_SUB, && case_sem_INSN_WRITE_SUB }, | |
306 | { M32R2F_INSN_PAR_SUBV, && case_sem_INSN_PAR_SUBV }, | |
307 | { M32R2F_INSN_WRITE_SUBV, && case_sem_INSN_WRITE_SUBV }, | |
308 | { M32R2F_INSN_PAR_SUBX, && case_sem_INSN_PAR_SUBX }, | |
309 | { M32R2F_INSN_WRITE_SUBX, && case_sem_INSN_WRITE_SUBX }, | |
310 | { M32R2F_INSN_PAR_TRAP, && case_sem_INSN_PAR_TRAP }, | |
311 | { M32R2F_INSN_WRITE_TRAP, && case_sem_INSN_WRITE_TRAP }, | |
312 | { M32R2F_INSN_PAR_UNLOCK, && case_sem_INSN_PAR_UNLOCK }, | |
313 | { M32R2F_INSN_WRITE_UNLOCK, && case_sem_INSN_WRITE_UNLOCK }, | |
314 | { M32R2F_INSN_PAR_PCMPBZ, && case_sem_INSN_PAR_PCMPBZ }, | |
315 | { M32R2F_INSN_WRITE_PCMPBZ, && case_sem_INSN_WRITE_PCMPBZ }, | |
316 | { M32R2F_INSN_PAR_SADD, && case_sem_INSN_PAR_SADD }, | |
317 | { M32R2F_INSN_WRITE_SADD, && case_sem_INSN_WRITE_SADD }, | |
318 | { M32R2F_INSN_PAR_MACWU1, && case_sem_INSN_PAR_MACWU1 }, | |
319 | { M32R2F_INSN_WRITE_MACWU1, && case_sem_INSN_WRITE_MACWU1 }, | |
320 | { M32R2F_INSN_PAR_MSBLO, && case_sem_INSN_PAR_MSBLO }, | |
321 | { M32R2F_INSN_WRITE_MSBLO, && case_sem_INSN_WRITE_MSBLO }, | |
322 | { M32R2F_INSN_PAR_MULWU1, && case_sem_INSN_PAR_MULWU1 }, | |
323 | { M32R2F_INSN_WRITE_MULWU1, && case_sem_INSN_WRITE_MULWU1 }, | |
324 | { M32R2F_INSN_PAR_MACLH1, && case_sem_INSN_PAR_MACLH1 }, | |
325 | { M32R2F_INSN_WRITE_MACLH1, && case_sem_INSN_WRITE_MACLH1 }, | |
326 | { M32R2F_INSN_PAR_SC, && case_sem_INSN_PAR_SC }, | |
327 | { M32R2F_INSN_WRITE_SC, && case_sem_INSN_WRITE_SC }, | |
328 | { M32R2F_INSN_PAR_SNC, && case_sem_INSN_PAR_SNC }, | |
329 | { M32R2F_INSN_WRITE_SNC, && case_sem_INSN_WRITE_SNC }, | |
330 | { M32R2F_INSN_PAR_CLRPSW, && case_sem_INSN_PAR_CLRPSW }, | |
331 | { M32R2F_INSN_WRITE_CLRPSW, && case_sem_INSN_WRITE_CLRPSW }, | |
332 | { M32R2F_INSN_PAR_SETPSW, && case_sem_INSN_PAR_SETPSW }, | |
333 | { M32R2F_INSN_WRITE_SETPSW, && case_sem_INSN_WRITE_SETPSW }, | |
334 | { M32R2F_INSN_PAR_BTST, && case_sem_INSN_PAR_BTST }, | |
335 | { M32R2F_INSN_WRITE_BTST, && case_sem_INSN_WRITE_BTST }, | |
336 | { 0, 0 } | |
337 | }; | |
338 | int i; | |
339 | ||
340 | for (i = 0; labels[i].label != 0; ++i) | |
341 | { | |
342 | #if FAST_P | |
343 | CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; | |
344 | #else | |
345 | CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; | |
346 | #endif | |
347 | } | |
348 | ||
349 | #undef DEFINE_LABELS | |
350 | #endif /* DEFINE_LABELS */ | |
351 | ||
352 | #ifdef DEFINE_SWITCH | |
353 | ||
354 | /* If hyper-fast [well not unnecessarily slow] execution is selected, turn | |
355 | off frills like tracing and profiling. */ | |
356 | /* FIXME: A better way would be to have TRACE_RESULT check for something | |
357 | that can cause it to be optimized out. Another way would be to emit | |
358 | special handlers into the instruction "stream". */ | |
359 | ||
360 | #if FAST_P | |
361 | #undef TRACE_RESULT | |
362 | #define TRACE_RESULT(cpu, abuf, name, type, val) | |
363 | #endif | |
364 | ||
365 | #undef GET_ATTR | |
16b47b25 | 366 | #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) |
16b47b25 NC |
367 | |
368 | { | |
369 | ||
370 | #if WITH_SCACHE_PBB | |
371 | ||
372 | /* Branch to next handler without going around main loop. */ | |
373 | #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case | |
374 | SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) | |
375 | ||
376 | #else /* ! WITH_SCACHE_PBB */ | |
377 | ||
378 | #define NEXT(vpc) BREAK (sem) | |
379 | #ifdef __GNUC__ | |
380 | #if FAST_P | |
381 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) | |
382 | #else | |
383 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) | |
384 | #endif | |
385 | #else | |
386 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) | |
387 | #endif | |
388 | ||
389 | #endif /* ! WITH_SCACHE_PBB */ | |
390 | ||
391 | { | |
392 | ||
393 | CASE (sem, INSN_X_INVALID) : /* --invalid-- */ | |
394 | { | |
395 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
396 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 397 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
398 | int UNUSED written = 0; |
399 | IADDR UNUSED pc = abuf->addr; | |
400 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
401 | ||
402 | { | |
403 | /* Update the recorded pc in the cpu state struct. | |
404 | Only necessary for WITH_SCACHE case, but to avoid the | |
405 | conditional compilation .... */ | |
406 | SET_H_PC (pc); | |
407 | /* Virtual insns have zero size. Overwrite vpc with address of next insn | |
408 | using the default-insn-bitsize spec. When executing insns in parallel | |
409 | we may want to queue the fault and continue execution. */ | |
410 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
411 | vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); | |
412 | } | |
413 | ||
414 | #undef FLD | |
415 | } | |
416 | NEXT (vpc); | |
417 | ||
418 | CASE (sem, INSN_X_AFTER) : /* --after-- */ | |
419 | { | |
420 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
421 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 422 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
423 | int UNUSED written = 0; |
424 | IADDR UNUSED pc = abuf->addr; | |
425 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
426 | ||
427 | { | |
428 | #if WITH_SCACHE_PBB_M32R2F | |
429 | m32r2f_pbb_after (current_cpu, sem_arg); | |
430 | #endif | |
431 | } | |
432 | ||
433 | #undef FLD | |
434 | } | |
435 | NEXT (vpc); | |
436 | ||
437 | CASE (sem, INSN_X_BEFORE) : /* --before-- */ | |
438 | { | |
439 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
440 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 441 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
442 | int UNUSED written = 0; |
443 | IADDR UNUSED pc = abuf->addr; | |
444 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
445 | ||
446 | { | |
447 | #if WITH_SCACHE_PBB_M32R2F | |
448 | m32r2f_pbb_before (current_cpu, sem_arg); | |
449 | #endif | |
450 | } | |
451 | ||
452 | #undef FLD | |
453 | } | |
454 | NEXT (vpc); | |
455 | ||
456 | CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ | |
457 | { | |
458 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
459 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 460 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
461 | int UNUSED written = 0; |
462 | IADDR UNUSED pc = abuf->addr; | |
463 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
464 | ||
465 | { | |
466 | #if WITH_SCACHE_PBB_M32R2F | |
467 | #ifdef DEFINE_SWITCH | |
468 | vpc = m32r2f_pbb_cti_chain (current_cpu, sem_arg, | |
469 | pbb_br_type, pbb_br_npc); | |
470 | BREAK (sem); | |
471 | #else | |
472 | /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ | |
473 | vpc = m32r2f_pbb_cti_chain (current_cpu, sem_arg, | |
474 | CPU_PBB_BR_TYPE (current_cpu), | |
475 | CPU_PBB_BR_NPC (current_cpu)); | |
476 | #endif | |
477 | #endif | |
478 | } | |
479 | ||
480 | #undef FLD | |
481 | } | |
482 | NEXT (vpc); | |
483 | ||
484 | CASE (sem, INSN_X_CHAIN) : /* --chain-- */ | |
485 | { | |
486 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
487 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 488 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
489 | int UNUSED written = 0; |
490 | IADDR UNUSED pc = abuf->addr; | |
491 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
492 | ||
493 | { | |
494 | #if WITH_SCACHE_PBB_M32R2F | |
495 | vpc = m32r2f_pbb_chain (current_cpu, sem_arg); | |
496 | #ifdef DEFINE_SWITCH | |
497 | BREAK (sem); | |
498 | #endif | |
499 | #endif | |
500 | } | |
501 | ||
502 | #undef FLD | |
503 | } | |
504 | NEXT (vpc); | |
505 | ||
506 | CASE (sem, INSN_X_BEGIN) : /* --begin-- */ | |
507 | { | |
508 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
509 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 510 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
511 | int UNUSED written = 0; |
512 | IADDR UNUSED pc = abuf->addr; | |
513 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
514 | ||
515 | { | |
516 | #if WITH_SCACHE_PBB_M32R2F | |
517 | #if defined DEFINE_SWITCH || defined FAST_P | |
518 | /* In the switch case FAST_P is a constant, allowing several optimizations | |
519 | in any called inline functions. */ | |
520 | vpc = m32r2f_pbb_begin (current_cpu, FAST_P); | |
521 | #else | |
522 | #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ | |
523 | vpc = m32r2f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); | |
524 | #else | |
525 | vpc = m32r2f_pbb_begin (current_cpu, 0); | |
526 | #endif | |
527 | #endif | |
528 | #endif | |
529 | } | |
530 | ||
531 | #undef FLD | |
532 | } | |
533 | NEXT (vpc); | |
534 | ||
535 | CASE (sem, INSN_ADD) : /* add $dr,$sr */ | |
536 | { | |
537 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
538 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
539 | #define FLD(f) abuf->fields.sfmt_add.f | |
540 | int UNUSED written = 0; | |
541 | IADDR UNUSED pc = abuf->addr; | |
542 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
543 | ||
544 | { | |
545 | SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr)); | |
546 | * FLD (i_dr) = opval; | |
547 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
548 | } | |
549 | ||
550 | #undef FLD | |
551 | } | |
552 | NEXT (vpc); | |
553 | ||
554 | CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */ | |
555 | { | |
556 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
557 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
558 | #define FLD(f) abuf->fields.sfmt_add3.f | |
559 | int UNUSED written = 0; | |
560 | IADDR UNUSED pc = abuf->addr; | |
561 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
562 | ||
563 | { | |
564 | SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16)); | |
565 | * FLD (i_dr) = opval; | |
566 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
567 | } | |
568 | ||
569 | #undef FLD | |
570 | } | |
571 | NEXT (vpc); | |
572 | ||
573 | CASE (sem, INSN_AND) : /* and $dr,$sr */ | |
574 | { | |
575 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
576 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
577 | #define FLD(f) abuf->fields.sfmt_add.f | |
578 | int UNUSED written = 0; | |
579 | IADDR UNUSED pc = abuf->addr; | |
580 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
581 | ||
582 | { | |
583 | SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr)); | |
584 | * FLD (i_dr) = opval; | |
585 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
586 | } | |
587 | ||
588 | #undef FLD | |
589 | } | |
590 | NEXT (vpc); | |
591 | ||
592 | CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */ | |
593 | { | |
594 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
595 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
596 | #define FLD(f) abuf->fields.sfmt_and3.f | |
597 | int UNUSED written = 0; | |
598 | IADDR UNUSED pc = abuf->addr; | |
599 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
600 | ||
601 | { | |
602 | SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16)); | |
603 | * FLD (i_dr) = opval; | |
604 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
605 | } | |
606 | ||
607 | #undef FLD | |
608 | } | |
609 | NEXT (vpc); | |
610 | ||
611 | CASE (sem, INSN_OR) : /* or $dr,$sr */ | |
612 | { | |
613 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
614 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
615 | #define FLD(f) abuf->fields.sfmt_add.f | |
616 | int UNUSED written = 0; | |
617 | IADDR UNUSED pc = abuf->addr; | |
618 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
619 | ||
620 | { | |
621 | SI opval = ORSI (* FLD (i_dr), * FLD (i_sr)); | |
622 | * FLD (i_dr) = opval; | |
623 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
624 | } | |
625 | ||
626 | #undef FLD | |
627 | } | |
628 | NEXT (vpc); | |
629 | ||
630 | CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */ | |
631 | { | |
632 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
633 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
634 | #define FLD(f) abuf->fields.sfmt_and3.f | |
635 | int UNUSED written = 0; | |
636 | IADDR UNUSED pc = abuf->addr; | |
637 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
638 | ||
639 | { | |
640 | SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16)); | |
641 | * FLD (i_dr) = opval; | |
642 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
643 | } | |
644 | ||
645 | #undef FLD | |
646 | } | |
647 | NEXT (vpc); | |
648 | ||
649 | CASE (sem, INSN_XOR) : /* xor $dr,$sr */ | |
650 | { | |
651 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
652 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
653 | #define FLD(f) abuf->fields.sfmt_add.f | |
654 | int UNUSED written = 0; | |
655 | IADDR UNUSED pc = abuf->addr; | |
656 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
657 | ||
658 | { | |
659 | SI opval = XORSI (* FLD (i_dr), * FLD (i_sr)); | |
660 | * FLD (i_dr) = opval; | |
661 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
662 | } | |
663 | ||
664 | #undef FLD | |
665 | } | |
666 | NEXT (vpc); | |
667 | ||
668 | CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */ | |
669 | { | |
670 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
671 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
672 | #define FLD(f) abuf->fields.sfmt_and3.f | |
673 | int UNUSED written = 0; | |
674 | IADDR UNUSED pc = abuf->addr; | |
675 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
676 | ||
677 | { | |
678 | SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16)); | |
679 | * FLD (i_dr) = opval; | |
680 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
681 | } | |
682 | ||
683 | #undef FLD | |
684 | } | |
685 | NEXT (vpc); | |
686 | ||
687 | CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */ | |
688 | { | |
689 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
690 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
691 | #define FLD(f) abuf->fields.sfmt_addi.f | |
692 | int UNUSED written = 0; | |
693 | IADDR UNUSED pc = abuf->addr; | |
694 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
695 | ||
696 | { | |
697 | SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8)); | |
698 | * FLD (i_dr) = opval; | |
699 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
700 | } | |
701 | ||
702 | #undef FLD | |
703 | } | |
704 | NEXT (vpc); | |
705 | ||
706 | CASE (sem, INSN_ADDV) : /* addv $dr,$sr */ | |
707 | { | |
708 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
709 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
710 | #define FLD(f) abuf->fields.sfmt_add.f | |
711 | int UNUSED written = 0; | |
712 | IADDR UNUSED pc = abuf->addr; | |
713 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
714 | ||
715 | { | |
716 | SI temp0;BI temp1; | |
717 | temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr)); | |
718 | temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0); | |
719 | { | |
720 | SI opval = temp0; | |
721 | * FLD (i_dr) = opval; | |
722 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
723 | } | |
724 | { | |
725 | BI opval = temp1; | |
726 | CPU (h_cond) = opval; | |
727 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
728 | } | |
729 | } | |
730 | ||
731 | #undef FLD | |
732 | } | |
733 | NEXT (vpc); | |
734 | ||
735 | CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */ | |
736 | { | |
737 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
738 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
739 | #define FLD(f) abuf->fields.sfmt_add3.f | |
740 | int UNUSED written = 0; | |
741 | IADDR UNUSED pc = abuf->addr; | |
742 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
743 | ||
744 | { | |
745 | SI temp0;BI temp1; | |
746 | temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16)); | |
747 | temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0); | |
748 | { | |
749 | SI opval = temp0; | |
750 | * FLD (i_dr) = opval; | |
751 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
752 | } | |
753 | { | |
754 | BI opval = temp1; | |
755 | CPU (h_cond) = opval; | |
756 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
757 | } | |
758 | } | |
759 | ||
760 | #undef FLD | |
761 | } | |
762 | NEXT (vpc); | |
763 | ||
764 | CASE (sem, INSN_ADDX) : /* addx $dr,$sr */ | |
765 | { | |
766 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
767 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
768 | #define FLD(f) abuf->fields.sfmt_add.f | |
769 | int UNUSED written = 0; | |
770 | IADDR UNUSED pc = abuf->addr; | |
771 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
772 | ||
773 | { | |
774 | SI temp0;BI temp1; | |
775 | temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); | |
776 | temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); | |
777 | { | |
778 | SI opval = temp0; | |
779 | * FLD (i_dr) = opval; | |
780 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
781 | } | |
782 | { | |
783 | BI opval = temp1; | |
784 | CPU (h_cond) = opval; | |
785 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
786 | } | |
787 | } | |
788 | ||
789 | #undef FLD | |
790 | } | |
791 | NEXT (vpc); | |
792 | ||
793 | CASE (sem, INSN_BC8) : /* bc.s $disp8 */ | |
794 | { | |
795 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
796 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
797 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
798 | int UNUSED written = 0; | |
799 | IADDR UNUSED pc = abuf->addr; | |
800 | SEM_BRANCH_INIT | |
801 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
802 | ||
803 | if (CPU (h_cond)) { | |
804 | { | |
805 | USI opval = FLD (i_disp8); | |
806 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
807 | written |= (1 << 2); | |
808 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
809 | } | |
810 | } | |
811 | ||
812 | abuf->written = written; | |
813 | SEM_BRANCH_FINI (vpc); | |
814 | #undef FLD | |
815 | } | |
816 | NEXT (vpc); | |
817 | ||
818 | CASE (sem, INSN_BC24) : /* bc.l $disp24 */ | |
819 | { | |
820 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
821 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
822 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
823 | int UNUSED written = 0; | |
824 | IADDR UNUSED pc = abuf->addr; | |
825 | SEM_BRANCH_INIT | |
826 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
827 | ||
828 | if (CPU (h_cond)) { | |
829 | { | |
830 | USI opval = FLD (i_disp24); | |
831 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
832 | written |= (1 << 2); | |
833 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
834 | } | |
835 | } | |
836 | ||
837 | abuf->written = written; | |
838 | SEM_BRANCH_FINI (vpc); | |
839 | #undef FLD | |
840 | } | |
841 | NEXT (vpc); | |
842 | ||
843 | CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */ | |
844 | { | |
845 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
846 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
847 | #define FLD(f) abuf->fields.sfmt_beq.f | |
848 | int UNUSED written = 0; | |
849 | IADDR UNUSED pc = abuf->addr; | |
850 | SEM_BRANCH_INIT | |
851 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
852 | ||
853 | if (EQSI (* FLD (i_src1), * FLD (i_src2))) { | |
854 | { | |
855 | USI opval = FLD (i_disp16); | |
856 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
857 | written |= (1 << 3); | |
858 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
859 | } | |
860 | } | |
861 | ||
862 | abuf->written = written; | |
863 | SEM_BRANCH_FINI (vpc); | |
864 | #undef FLD | |
865 | } | |
866 | NEXT (vpc); | |
867 | ||
868 | CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */ | |
869 | { | |
870 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
871 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
872 | #define FLD(f) abuf->fields.sfmt_beq.f | |
873 | int UNUSED written = 0; | |
874 | IADDR UNUSED pc = abuf->addr; | |
875 | SEM_BRANCH_INIT | |
876 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
877 | ||
878 | if (EQSI (* FLD (i_src2), 0)) { | |
879 | { | |
880 | USI opval = FLD (i_disp16); | |
881 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
882 | written |= (1 << 2); | |
883 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
884 | } | |
885 | } | |
886 | ||
887 | abuf->written = written; | |
888 | SEM_BRANCH_FINI (vpc); | |
889 | #undef FLD | |
890 | } | |
891 | NEXT (vpc); | |
892 | ||
893 | CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */ | |
894 | { | |
895 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
896 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
897 | #define FLD(f) abuf->fields.sfmt_beq.f | |
898 | int UNUSED written = 0; | |
899 | IADDR UNUSED pc = abuf->addr; | |
900 | SEM_BRANCH_INIT | |
901 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
902 | ||
903 | if (GESI (* FLD (i_src2), 0)) { | |
904 | { | |
905 | USI opval = FLD (i_disp16); | |
906 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
907 | written |= (1 << 2); | |
908 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
909 | } | |
910 | } | |
911 | ||
912 | abuf->written = written; | |
913 | SEM_BRANCH_FINI (vpc); | |
914 | #undef FLD | |
915 | } | |
916 | NEXT (vpc); | |
917 | ||
918 | CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */ | |
919 | { | |
920 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
921 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
922 | #define FLD(f) abuf->fields.sfmt_beq.f | |
923 | int UNUSED written = 0; | |
924 | IADDR UNUSED pc = abuf->addr; | |
925 | SEM_BRANCH_INIT | |
926 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
927 | ||
928 | if (GTSI (* FLD (i_src2), 0)) { | |
929 | { | |
930 | USI opval = FLD (i_disp16); | |
931 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
932 | written |= (1 << 2); | |
933 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
934 | } | |
935 | } | |
936 | ||
937 | abuf->written = written; | |
938 | SEM_BRANCH_FINI (vpc); | |
939 | #undef FLD | |
940 | } | |
941 | NEXT (vpc); | |
942 | ||
943 | CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */ | |
944 | { | |
945 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
946 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
947 | #define FLD(f) abuf->fields.sfmt_beq.f | |
948 | int UNUSED written = 0; | |
949 | IADDR UNUSED pc = abuf->addr; | |
950 | SEM_BRANCH_INIT | |
951 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
952 | ||
953 | if (LESI (* FLD (i_src2), 0)) { | |
954 | { | |
955 | USI opval = FLD (i_disp16); | |
956 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
957 | written |= (1 << 2); | |
958 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
959 | } | |
960 | } | |
961 | ||
962 | abuf->written = written; | |
963 | SEM_BRANCH_FINI (vpc); | |
964 | #undef FLD | |
965 | } | |
966 | NEXT (vpc); | |
967 | ||
968 | CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */ | |
969 | { | |
970 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
971 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
972 | #define FLD(f) abuf->fields.sfmt_beq.f | |
973 | int UNUSED written = 0; | |
974 | IADDR UNUSED pc = abuf->addr; | |
975 | SEM_BRANCH_INIT | |
976 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
977 | ||
978 | if (LTSI (* FLD (i_src2), 0)) { | |
979 | { | |
980 | USI opval = FLD (i_disp16); | |
981 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
982 | written |= (1 << 2); | |
983 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
984 | } | |
985 | } | |
986 | ||
987 | abuf->written = written; | |
988 | SEM_BRANCH_FINI (vpc); | |
989 | #undef FLD | |
990 | } | |
991 | NEXT (vpc); | |
992 | ||
993 | CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */ | |
994 | { | |
995 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
996 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
997 | #define FLD(f) abuf->fields.sfmt_beq.f | |
998 | int UNUSED written = 0; | |
999 | IADDR UNUSED pc = abuf->addr; | |
1000 | SEM_BRANCH_INIT | |
1001 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1002 | ||
1003 | if (NESI (* FLD (i_src2), 0)) { | |
1004 | { | |
1005 | USI opval = FLD (i_disp16); | |
1006 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1007 | written |= (1 << 2); | |
1008 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1009 | } | |
1010 | } | |
1011 | ||
1012 | abuf->written = written; | |
1013 | SEM_BRANCH_FINI (vpc); | |
1014 | #undef FLD | |
1015 | } | |
1016 | NEXT (vpc); | |
1017 | ||
1018 | CASE (sem, INSN_BL8) : /* bl.s $disp8 */ | |
1019 | { | |
1020 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1021 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1022 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
1023 | int UNUSED written = 0; | |
1024 | IADDR UNUSED pc = abuf->addr; | |
1025 | SEM_BRANCH_INIT | |
1026 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1027 | ||
1028 | { | |
1029 | { | |
1030 | SI opval = ADDSI (ANDSI (pc, -4), 4); | |
1031 | CPU (h_gr[((UINT) 14)]) = opval; | |
1032 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1033 | } | |
1034 | { | |
1035 | USI opval = FLD (i_disp8); | |
1036 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1037 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1038 | } | |
1039 | } | |
1040 | ||
1041 | SEM_BRANCH_FINI (vpc); | |
1042 | #undef FLD | |
1043 | } | |
1044 | NEXT (vpc); | |
1045 | ||
1046 | CASE (sem, INSN_BL24) : /* bl.l $disp24 */ | |
1047 | { | |
1048 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1049 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1050 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
1051 | int UNUSED written = 0; | |
1052 | IADDR UNUSED pc = abuf->addr; | |
1053 | SEM_BRANCH_INIT | |
1054 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1055 | ||
1056 | { | |
1057 | { | |
1058 | SI opval = ADDSI (pc, 4); | |
1059 | CPU (h_gr[((UINT) 14)]) = opval; | |
1060 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1061 | } | |
1062 | { | |
1063 | USI opval = FLD (i_disp24); | |
1064 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1065 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1066 | } | |
1067 | } | |
1068 | ||
1069 | SEM_BRANCH_FINI (vpc); | |
1070 | #undef FLD | |
1071 | } | |
1072 | NEXT (vpc); | |
1073 | ||
1074 | CASE (sem, INSN_BCL8) : /* bcl.s $disp8 */ | |
1075 | { | |
1076 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1077 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1078 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
1079 | int UNUSED written = 0; | |
1080 | IADDR UNUSED pc = abuf->addr; | |
1081 | SEM_BRANCH_INIT | |
1082 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1083 | ||
1084 | if (CPU (h_cond)) { | |
1085 | { | |
1086 | { | |
1087 | SI opval = ADDSI (ANDSI (pc, -4), 4); | |
1088 | CPU (h_gr[((UINT) 14)]) = opval; | |
1089 | written |= (1 << 3); | |
1090 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1091 | } | |
1092 | { | |
1093 | USI opval = FLD (i_disp8); | |
1094 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1095 | written |= (1 << 4); | |
1096 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1097 | } | |
1098 | } | |
1099 | } | |
1100 | ||
1101 | abuf->written = written; | |
1102 | SEM_BRANCH_FINI (vpc); | |
1103 | #undef FLD | |
1104 | } | |
1105 | NEXT (vpc); | |
1106 | ||
1107 | CASE (sem, INSN_BCL24) : /* bcl.l $disp24 */ | |
1108 | { | |
1109 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1110 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1111 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
1112 | int UNUSED written = 0; | |
1113 | IADDR UNUSED pc = abuf->addr; | |
1114 | SEM_BRANCH_INIT | |
1115 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1116 | ||
1117 | if (CPU (h_cond)) { | |
1118 | { | |
1119 | { | |
1120 | SI opval = ADDSI (pc, 4); | |
1121 | CPU (h_gr[((UINT) 14)]) = opval; | |
1122 | written |= (1 << 3); | |
1123 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1124 | } | |
1125 | { | |
1126 | USI opval = FLD (i_disp24); | |
1127 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1128 | written |= (1 << 4); | |
1129 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1130 | } | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | abuf->written = written; | |
1135 | SEM_BRANCH_FINI (vpc); | |
1136 | #undef FLD | |
1137 | } | |
1138 | NEXT (vpc); | |
1139 | ||
1140 | CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */ | |
1141 | { | |
1142 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1143 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1144 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
1145 | int UNUSED written = 0; | |
1146 | IADDR UNUSED pc = abuf->addr; | |
1147 | SEM_BRANCH_INIT | |
1148 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1149 | ||
1150 | if (NOTBI (CPU (h_cond))) { | |
1151 | { | |
1152 | USI opval = FLD (i_disp8); | |
1153 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1154 | written |= (1 << 2); | |
1155 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | abuf->written = written; | |
1160 | SEM_BRANCH_FINI (vpc); | |
1161 | #undef FLD | |
1162 | } | |
1163 | NEXT (vpc); | |
1164 | ||
1165 | CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */ | |
1166 | { | |
1167 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1168 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1169 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
1170 | int UNUSED written = 0; | |
1171 | IADDR UNUSED pc = abuf->addr; | |
1172 | SEM_BRANCH_INIT | |
1173 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1174 | ||
1175 | if (NOTBI (CPU (h_cond))) { | |
1176 | { | |
1177 | USI opval = FLD (i_disp24); | |
1178 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1179 | written |= (1 << 2); | |
1180 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1181 | } | |
1182 | } | |
1183 | ||
1184 | abuf->written = written; | |
1185 | SEM_BRANCH_FINI (vpc); | |
1186 | #undef FLD | |
1187 | } | |
1188 | NEXT (vpc); | |
1189 | ||
1190 | CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */ | |
1191 | { | |
1192 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1193 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1194 | #define FLD(f) abuf->fields.sfmt_beq.f | |
1195 | int UNUSED written = 0; | |
1196 | IADDR UNUSED pc = abuf->addr; | |
1197 | SEM_BRANCH_INIT | |
1198 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1199 | ||
1200 | if (NESI (* FLD (i_src1), * FLD (i_src2))) { | |
1201 | { | |
1202 | USI opval = FLD (i_disp16); | |
1203 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1204 | written |= (1 << 3); | |
1205 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1206 | } | |
1207 | } | |
1208 | ||
1209 | abuf->written = written; | |
1210 | SEM_BRANCH_FINI (vpc); | |
1211 | #undef FLD | |
1212 | } | |
1213 | NEXT (vpc); | |
1214 | ||
1215 | CASE (sem, INSN_BRA8) : /* bra.s $disp8 */ | |
1216 | { | |
1217 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1218 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1219 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
1220 | int UNUSED written = 0; | |
1221 | IADDR UNUSED pc = abuf->addr; | |
1222 | SEM_BRANCH_INIT | |
1223 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1224 | ||
1225 | { | |
1226 | USI opval = FLD (i_disp8); | |
1227 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1228 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1229 | } | |
1230 | ||
1231 | SEM_BRANCH_FINI (vpc); | |
1232 | #undef FLD | |
1233 | } | |
1234 | NEXT (vpc); | |
1235 | ||
1236 | CASE (sem, INSN_BRA24) : /* bra.l $disp24 */ | |
1237 | { | |
1238 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1239 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1240 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
1241 | int UNUSED written = 0; | |
1242 | IADDR UNUSED pc = abuf->addr; | |
1243 | SEM_BRANCH_INIT | |
1244 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1245 | ||
1246 | { | |
1247 | USI opval = FLD (i_disp24); | |
1248 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1249 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1250 | } | |
1251 | ||
1252 | SEM_BRANCH_FINI (vpc); | |
1253 | #undef FLD | |
1254 | } | |
1255 | NEXT (vpc); | |
1256 | ||
1257 | CASE (sem, INSN_BNCL8) : /* bncl.s $disp8 */ | |
1258 | { | |
1259 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1260 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1261 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
1262 | int UNUSED written = 0; | |
1263 | IADDR UNUSED pc = abuf->addr; | |
1264 | SEM_BRANCH_INIT | |
1265 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1266 | ||
1267 | if (NOTBI (CPU (h_cond))) { | |
1268 | { | |
1269 | { | |
1270 | SI opval = ADDSI (ANDSI (pc, -4), 4); | |
1271 | CPU (h_gr[((UINT) 14)]) = opval; | |
1272 | written |= (1 << 3); | |
1273 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1274 | } | |
1275 | { | |
1276 | USI opval = FLD (i_disp8); | |
1277 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1278 | written |= (1 << 4); | |
1279 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1280 | } | |
1281 | } | |
1282 | } | |
1283 | ||
1284 | abuf->written = written; | |
1285 | SEM_BRANCH_FINI (vpc); | |
1286 | #undef FLD | |
1287 | } | |
1288 | NEXT (vpc); | |
1289 | ||
1290 | CASE (sem, INSN_BNCL24) : /* bncl.l $disp24 */ | |
1291 | { | |
1292 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1293 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1294 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
1295 | int UNUSED written = 0; | |
1296 | IADDR UNUSED pc = abuf->addr; | |
1297 | SEM_BRANCH_INIT | |
1298 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1299 | ||
1300 | if (NOTBI (CPU (h_cond))) { | |
1301 | { | |
1302 | { | |
1303 | SI opval = ADDSI (pc, 4); | |
1304 | CPU (h_gr[((UINT) 14)]) = opval; | |
1305 | written |= (1 << 3); | |
1306 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1307 | } | |
1308 | { | |
1309 | USI opval = FLD (i_disp24); | |
1310 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
1311 | written |= (1 << 4); | |
1312 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1313 | } | |
1314 | } | |
1315 | } | |
1316 | ||
1317 | abuf->written = written; | |
1318 | SEM_BRANCH_FINI (vpc); | |
1319 | #undef FLD | |
1320 | } | |
1321 | NEXT (vpc); | |
1322 | ||
1323 | CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */ | |
1324 | { | |
1325 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1326 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1327 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1328 | int UNUSED written = 0; | |
1329 | IADDR UNUSED pc = abuf->addr; | |
1330 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1331 | ||
1332 | { | |
1333 | BI opval = LTSI (* FLD (i_src1), * FLD (i_src2)); | |
1334 | CPU (h_cond) = opval; | |
1335 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
1336 | } | |
1337 | ||
1338 | #undef FLD | |
1339 | } | |
1340 | NEXT (vpc); | |
1341 | ||
1342 | CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */ | |
1343 | { | |
1344 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1345 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1346 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
1347 | int UNUSED written = 0; | |
1348 | IADDR UNUSED pc = abuf->addr; | |
1349 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1350 | ||
1351 | { | |
1352 | BI opval = LTSI (* FLD (i_src2), FLD (f_simm16)); | |
1353 | CPU (h_cond) = opval; | |
1354 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
1355 | } | |
1356 | ||
1357 | #undef FLD | |
1358 | } | |
1359 | NEXT (vpc); | |
1360 | ||
1361 | CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */ | |
1362 | { | |
1363 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1364 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1365 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1366 | int UNUSED written = 0; | |
1367 | IADDR UNUSED pc = abuf->addr; | |
1368 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1369 | ||
1370 | { | |
1371 | BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2)); | |
1372 | CPU (h_cond) = opval; | |
1373 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
1374 | } | |
1375 | ||
1376 | #undef FLD | |
1377 | } | |
1378 | NEXT (vpc); | |
1379 | ||
1380 | CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */ | |
1381 | { | |
1382 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1383 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1384 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
1385 | int UNUSED written = 0; | |
1386 | IADDR UNUSED pc = abuf->addr; | |
1387 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1388 | ||
1389 | { | |
1390 | BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16)); | |
1391 | CPU (h_cond) = opval; | |
1392 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
1393 | } | |
1394 | ||
1395 | #undef FLD | |
1396 | } | |
1397 | NEXT (vpc); | |
1398 | ||
1399 | CASE (sem, INSN_CMPEQ) : /* cmpeq $src1,$src2 */ | |
1400 | { | |
1401 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1402 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1403 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1404 | int UNUSED written = 0; | |
1405 | IADDR UNUSED pc = abuf->addr; | |
1406 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1407 | ||
1408 | { | |
1409 | BI opval = EQSI (* FLD (i_src1), * FLD (i_src2)); | |
1410 | CPU (h_cond) = opval; | |
1411 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
1412 | } | |
1413 | ||
1414 | #undef FLD | |
1415 | } | |
1416 | NEXT (vpc); | |
1417 | ||
1418 | CASE (sem, INSN_CMPZ) : /* cmpz $src2 */ | |
1419 | { | |
1420 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1421 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1422 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1423 | int UNUSED written = 0; | |
1424 | IADDR UNUSED pc = abuf->addr; | |
1425 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1426 | ||
1427 | { | |
1428 | BI opval = EQSI (* FLD (i_src2), 0); | |
1429 | CPU (h_cond) = opval; | |
1430 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
1431 | } | |
1432 | ||
1433 | #undef FLD | |
1434 | } | |
1435 | NEXT (vpc); | |
1436 | ||
1437 | CASE (sem, INSN_DIV) : /* div $dr,$sr */ | |
1438 | { | |
1439 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1440 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1441 | #define FLD(f) abuf->fields.sfmt_add.f | |
1442 | int UNUSED written = 0; | |
1443 | IADDR UNUSED pc = abuf->addr; | |
1444 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1445 | ||
1446 | if (NESI (* FLD (i_sr), 0)) { | |
1447 | { | |
1448 | SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr)); | |
1449 | * FLD (i_dr) = opval; | |
1450 | written |= (1 << 2); | |
1451 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1452 | } | |
1453 | } | |
1454 | ||
1455 | abuf->written = written; | |
1456 | #undef FLD | |
1457 | } | |
1458 | NEXT (vpc); | |
1459 | ||
1460 | CASE (sem, INSN_DIVU) : /* divu $dr,$sr */ | |
1461 | { | |
1462 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1463 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1464 | #define FLD(f) abuf->fields.sfmt_add.f | |
1465 | int UNUSED written = 0; | |
1466 | IADDR UNUSED pc = abuf->addr; | |
1467 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1468 | ||
1469 | if (NESI (* FLD (i_sr), 0)) { | |
1470 | { | |
1471 | SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr)); | |
1472 | * FLD (i_dr) = opval; | |
1473 | written |= (1 << 2); | |
1474 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1475 | } | |
1476 | } | |
1477 | ||
1478 | abuf->written = written; | |
1479 | #undef FLD | |
1480 | } | |
1481 | NEXT (vpc); | |
1482 | ||
1483 | CASE (sem, INSN_REM) : /* rem $dr,$sr */ | |
1484 | { | |
1485 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1486 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1487 | #define FLD(f) abuf->fields.sfmt_add.f | |
1488 | int UNUSED written = 0; | |
1489 | IADDR UNUSED pc = abuf->addr; | |
1490 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1491 | ||
1492 | if (NESI (* FLD (i_sr), 0)) { | |
1493 | { | |
1494 | SI opval = MODSI (* FLD (i_dr), * FLD (i_sr)); | |
1495 | * FLD (i_dr) = opval; | |
1496 | written |= (1 << 2); | |
1497 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1498 | } | |
1499 | } | |
1500 | ||
1501 | abuf->written = written; | |
1502 | #undef FLD | |
1503 | } | |
1504 | NEXT (vpc); | |
1505 | ||
1506 | CASE (sem, INSN_REMU) : /* remu $dr,$sr */ | |
1507 | { | |
1508 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1509 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1510 | #define FLD(f) abuf->fields.sfmt_add.f | |
1511 | int UNUSED written = 0; | |
1512 | IADDR UNUSED pc = abuf->addr; | |
1513 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1514 | ||
1515 | if (NESI (* FLD (i_sr), 0)) { | |
1516 | { | |
1517 | SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr)); | |
1518 | * FLD (i_dr) = opval; | |
1519 | written |= (1 << 2); | |
1520 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1521 | } | |
1522 | } | |
1523 | ||
1524 | abuf->written = written; | |
1525 | #undef FLD | |
1526 | } | |
1527 | NEXT (vpc); | |
1528 | ||
1529 | CASE (sem, INSN_REMH) : /* remh $dr,$sr */ | |
1530 | { | |
1531 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1532 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1533 | #define FLD(f) abuf->fields.sfmt_add.f | |
1534 | int UNUSED written = 0; | |
1535 | IADDR UNUSED pc = abuf->addr; | |
1536 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1537 | ||
1538 | if (NESI (* FLD (i_sr), 0)) { | |
1539 | { | |
1540 | SI opval = MODSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr)); | |
1541 | * FLD (i_dr) = opval; | |
1542 | written |= (1 << 2); | |
1543 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1544 | } | |
1545 | } | |
1546 | ||
1547 | abuf->written = written; | |
1548 | #undef FLD | |
1549 | } | |
1550 | NEXT (vpc); | |
1551 | ||
1552 | CASE (sem, INSN_REMUH) : /* remuh $dr,$sr */ | |
1553 | { | |
1554 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1555 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1556 | #define FLD(f) abuf->fields.sfmt_add.f | |
1557 | int UNUSED written = 0; | |
1558 | IADDR UNUSED pc = abuf->addr; | |
1559 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1560 | ||
1561 | if (NESI (* FLD (i_sr), 0)) { | |
1562 | { | |
1563 | SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr)); | |
1564 | * FLD (i_dr) = opval; | |
1565 | written |= (1 << 2); | |
1566 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1567 | } | |
1568 | } | |
1569 | ||
1570 | abuf->written = written; | |
1571 | #undef FLD | |
1572 | } | |
1573 | NEXT (vpc); | |
1574 | ||
1575 | CASE (sem, INSN_REMB) : /* remb $dr,$sr */ | |
1576 | { | |
1577 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1578 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1579 | #define FLD(f) abuf->fields.sfmt_add.f | |
1580 | int UNUSED written = 0; | |
1581 | IADDR UNUSED pc = abuf->addr; | |
1582 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1583 | ||
1584 | if (NESI (* FLD (i_sr), 0)) { | |
1585 | { | |
1586 | SI opval = MODSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr)); | |
1587 | * FLD (i_dr) = opval; | |
1588 | written |= (1 << 2); | |
1589 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1590 | } | |
1591 | } | |
1592 | ||
1593 | abuf->written = written; | |
1594 | #undef FLD | |
1595 | } | |
1596 | NEXT (vpc); | |
1597 | ||
1598 | CASE (sem, INSN_REMUB) : /* remub $dr,$sr */ | |
1599 | { | |
1600 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1601 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1602 | #define FLD(f) abuf->fields.sfmt_add.f | |
1603 | int UNUSED written = 0; | |
1604 | IADDR UNUSED pc = abuf->addr; | |
1605 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1606 | ||
1607 | if (NESI (* FLD (i_sr), 0)) { | |
1608 | { | |
1609 | SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr)); | |
1610 | * FLD (i_dr) = opval; | |
1611 | written |= (1 << 2); | |
1612 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1613 | } | |
1614 | } | |
1615 | ||
1616 | abuf->written = written; | |
1617 | #undef FLD | |
1618 | } | |
1619 | NEXT (vpc); | |
1620 | ||
1621 | CASE (sem, INSN_DIVUH) : /* divuh $dr,$sr */ | |
1622 | { | |
1623 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1624 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1625 | #define FLD(f) abuf->fields.sfmt_add.f | |
1626 | int UNUSED written = 0; | |
1627 | IADDR UNUSED pc = abuf->addr; | |
1628 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1629 | ||
1630 | if (NESI (* FLD (i_sr), 0)) { | |
1631 | { | |
1632 | SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr)); | |
1633 | * FLD (i_dr) = opval; | |
1634 | written |= (1 << 2); | |
1635 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1636 | } | |
1637 | } | |
1638 | ||
1639 | abuf->written = written; | |
1640 | #undef FLD | |
1641 | } | |
1642 | NEXT (vpc); | |
1643 | ||
1644 | CASE (sem, INSN_DIVB) : /* divb $dr,$sr */ | |
1645 | { | |
1646 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1647 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1648 | #define FLD(f) abuf->fields.sfmt_add.f | |
1649 | int UNUSED written = 0; | |
1650 | IADDR UNUSED pc = abuf->addr; | |
1651 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1652 | ||
1653 | if (NESI (* FLD (i_sr), 0)) { | |
1654 | { | |
1655 | SI opval = DIVSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr)); | |
1656 | * FLD (i_dr) = opval; | |
1657 | written |= (1 << 2); | |
1658 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1659 | } | |
1660 | } | |
1661 | ||
1662 | abuf->written = written; | |
1663 | #undef FLD | |
1664 | } | |
1665 | NEXT (vpc); | |
1666 | ||
1667 | CASE (sem, INSN_DIVUB) : /* divub $dr,$sr */ | |
1668 | { | |
1669 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1670 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1671 | #define FLD(f) abuf->fields.sfmt_add.f | |
1672 | int UNUSED written = 0; | |
1673 | IADDR UNUSED pc = abuf->addr; | |
1674 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1675 | ||
1676 | if (NESI (* FLD (i_sr), 0)) { | |
1677 | { | |
1678 | SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr)); | |
1679 | * FLD (i_dr) = opval; | |
1680 | written |= (1 << 2); | |
1681 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1682 | } | |
1683 | } | |
1684 | ||
1685 | abuf->written = written; | |
1686 | #undef FLD | |
1687 | } | |
1688 | NEXT (vpc); | |
1689 | ||
1690 | CASE (sem, INSN_DIVH) : /* divh $dr,$sr */ | |
1691 | { | |
1692 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1693 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1694 | #define FLD(f) abuf->fields.sfmt_add.f | |
1695 | int UNUSED written = 0; | |
1696 | IADDR UNUSED pc = abuf->addr; | |
1697 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1698 | ||
1699 | if (NESI (* FLD (i_sr), 0)) { | |
1700 | { | |
1701 | SI opval = DIVSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr)); | |
1702 | * FLD (i_dr) = opval; | |
1703 | written |= (1 << 2); | |
1704 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1705 | } | |
1706 | } | |
1707 | ||
1708 | abuf->written = written; | |
1709 | #undef FLD | |
1710 | } | |
1711 | NEXT (vpc); | |
1712 | ||
1713 | CASE (sem, INSN_JC) : /* jc $sr */ | |
1714 | { | |
1715 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1716 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1717 | #define FLD(f) abuf->fields.sfmt_jl.f | |
1718 | int UNUSED written = 0; | |
1719 | IADDR UNUSED pc = abuf->addr; | |
1720 | SEM_BRANCH_INIT | |
1721 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1722 | ||
1723 | if (CPU (h_cond)) { | |
1724 | { | |
1725 | USI opval = ANDSI (* FLD (i_sr), -4); | |
1726 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
1727 | written |= (1 << 2); | |
1728 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1729 | } | |
1730 | } | |
1731 | ||
1732 | abuf->written = written; | |
1733 | SEM_BRANCH_FINI (vpc); | |
1734 | #undef FLD | |
1735 | } | |
1736 | NEXT (vpc); | |
1737 | ||
1738 | CASE (sem, INSN_JNC) : /* jnc $sr */ | |
1739 | { | |
1740 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1741 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1742 | #define FLD(f) abuf->fields.sfmt_jl.f | |
1743 | int UNUSED written = 0; | |
1744 | IADDR UNUSED pc = abuf->addr; | |
1745 | SEM_BRANCH_INIT | |
1746 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1747 | ||
1748 | if (NOTBI (CPU (h_cond))) { | |
1749 | { | |
1750 | USI opval = ANDSI (* FLD (i_sr), -4); | |
1751 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
1752 | written |= (1 << 2); | |
1753 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1754 | } | |
1755 | } | |
1756 | ||
1757 | abuf->written = written; | |
1758 | SEM_BRANCH_FINI (vpc); | |
1759 | #undef FLD | |
1760 | } | |
1761 | NEXT (vpc); | |
1762 | ||
1763 | CASE (sem, INSN_JL) : /* jl $sr */ | |
1764 | { | |
1765 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1766 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1767 | #define FLD(f) abuf->fields.sfmt_jl.f | |
1768 | int UNUSED written = 0; | |
1769 | IADDR UNUSED pc = abuf->addr; | |
1770 | SEM_BRANCH_INIT | |
1771 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1772 | ||
1773 | { | |
1774 | SI temp0;USI temp1; | |
1775 | temp0 = ADDSI (ANDSI (pc, -4), 4); | |
1776 | temp1 = ANDSI (* FLD (i_sr), -4); | |
1777 | { | |
1778 | SI opval = temp0; | |
1779 | CPU (h_gr[((UINT) 14)]) = opval; | |
1780 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1781 | } | |
1782 | { | |
1783 | USI opval = temp1; | |
1784 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
1785 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1786 | } | |
1787 | } | |
1788 | ||
1789 | SEM_BRANCH_FINI (vpc); | |
1790 | #undef FLD | |
1791 | } | |
1792 | NEXT (vpc); | |
1793 | ||
1794 | CASE (sem, INSN_JMP) : /* jmp $sr */ | |
1795 | { | |
1796 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1797 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1798 | #define FLD(f) abuf->fields.sfmt_jl.f | |
1799 | int UNUSED written = 0; | |
1800 | IADDR UNUSED pc = abuf->addr; | |
1801 | SEM_BRANCH_INIT | |
1802 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1803 | ||
1804 | { | |
1805 | USI opval = ANDSI (* FLD (i_sr), -4); | |
1806 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
1807 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
1808 | } | |
1809 | ||
1810 | SEM_BRANCH_FINI (vpc); | |
1811 | #undef FLD | |
1812 | } | |
1813 | NEXT (vpc); | |
1814 | ||
1815 | CASE (sem, INSN_LD) : /* ld $dr,@$sr */ | |
1816 | { | |
1817 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1818 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1819 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1820 | int UNUSED written = 0; | |
1821 | IADDR UNUSED pc = abuf->addr; | |
1822 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1823 | ||
1824 | { | |
1825 | SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); | |
1826 | * FLD (i_dr) = opval; | |
1827 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1828 | } | |
1829 | ||
1830 | #undef FLD | |
1831 | } | |
1832 | NEXT (vpc); | |
1833 | ||
1834 | CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */ | |
1835 | { | |
1836 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1837 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1838 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1839 | int UNUSED written = 0; | |
1840 | IADDR UNUSED pc = abuf->addr; | |
1841 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1842 | ||
1843 | { | |
1844 | SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))); | |
1845 | * FLD (i_dr) = opval; | |
1846 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1847 | } | |
1848 | ||
1849 | #undef FLD | |
1850 | } | |
1851 | NEXT (vpc); | |
1852 | ||
1853 | CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */ | |
1854 | { | |
1855 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1856 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1857 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1858 | int UNUSED written = 0; | |
1859 | IADDR UNUSED pc = abuf->addr; | |
1860 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1861 | ||
1862 | { | |
1863 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); | |
1864 | * FLD (i_dr) = opval; | |
1865 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1866 | } | |
1867 | ||
1868 | #undef FLD | |
1869 | } | |
1870 | NEXT (vpc); | |
1871 | ||
1872 | CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */ | |
1873 | { | |
1874 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1875 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1876 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1877 | int UNUSED written = 0; | |
1878 | IADDR UNUSED pc = abuf->addr; | |
1879 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1880 | ||
1881 | { | |
1882 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); | |
1883 | * FLD (i_dr) = opval; | |
1884 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1885 | } | |
1886 | ||
1887 | #undef FLD | |
1888 | } | |
1889 | NEXT (vpc); | |
1890 | ||
1891 | CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */ | |
1892 | { | |
1893 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1894 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1895 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1896 | int UNUSED written = 0; | |
1897 | IADDR UNUSED pc = abuf->addr; | |
1898 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1899 | ||
1900 | { | |
1901 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); | |
1902 | * FLD (i_dr) = opval; | |
1903 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1904 | } | |
1905 | ||
1906 | #undef FLD | |
1907 | } | |
1908 | NEXT (vpc); | |
1909 | ||
1910 | CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */ | |
1911 | { | |
1912 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1913 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1914 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1915 | int UNUSED written = 0; | |
1916 | IADDR UNUSED pc = abuf->addr; | |
1917 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1918 | ||
1919 | { | |
1920 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); | |
1921 | * FLD (i_dr) = opval; | |
1922 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1923 | } | |
1924 | ||
1925 | #undef FLD | |
1926 | } | |
1927 | NEXT (vpc); | |
1928 | ||
1929 | CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */ | |
1930 | { | |
1931 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1932 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1933 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1934 | int UNUSED written = 0; | |
1935 | IADDR UNUSED pc = abuf->addr; | |
1936 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1937 | ||
1938 | { | |
1939 | SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); | |
1940 | * FLD (i_dr) = opval; | |
1941 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1942 | } | |
1943 | ||
1944 | #undef FLD | |
1945 | } | |
1946 | NEXT (vpc); | |
1947 | ||
1948 | CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */ | |
1949 | { | |
1950 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1951 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1952 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1953 | int UNUSED written = 0; | |
1954 | IADDR UNUSED pc = abuf->addr; | |
1955 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1956 | ||
1957 | { | |
1958 | SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); | |
1959 | * FLD (i_dr) = opval; | |
1960 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1961 | } | |
1962 | ||
1963 | #undef FLD | |
1964 | } | |
1965 | NEXT (vpc); | |
1966 | ||
1967 | CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */ | |
1968 | { | |
1969 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1970 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1971 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1972 | int UNUSED written = 0; | |
1973 | IADDR UNUSED pc = abuf->addr; | |
1974 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
1975 | ||
1976 | { | |
1977 | SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); | |
1978 | * FLD (i_dr) = opval; | |
1979 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1980 | } | |
1981 | ||
1982 | #undef FLD | |
1983 | } | |
1984 | NEXT (vpc); | |
1985 | ||
1986 | CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */ | |
1987 | { | |
1988 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1989 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1990 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1991 | int UNUSED written = 0; | |
1992 | IADDR UNUSED pc = abuf->addr; | |
1993 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1994 | ||
1995 | { | |
1996 | SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); | |
1997 | * FLD (i_dr) = opval; | |
1998 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
1999 | } | |
2000 | ||
2001 | #undef FLD | |
2002 | } | |
2003 | NEXT (vpc); | |
2004 | ||
2005 | CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */ | |
2006 | { | |
2007 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2008 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2009 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
2010 | int UNUSED written = 0; | |
2011 | IADDR UNUSED pc = abuf->addr; | |
2012 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2013 | ||
2014 | { | |
2015 | SI temp0;SI temp1; | |
2016 | temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr)); | |
2017 | temp1 = ADDSI (* FLD (i_sr), 4); | |
2018 | { | |
2019 | SI opval = temp0; | |
2020 | * FLD (i_dr) = opval; | |
2021 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2022 | } | |
2023 | { | |
2024 | SI opval = temp1; | |
2025 | * FLD (i_sr) = opval; | |
2026 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2027 | } | |
2028 | } | |
2029 | ||
2030 | #undef FLD | |
2031 | } | |
2032 | NEXT (vpc); | |
2033 | ||
2034 | CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */ | |
2035 | { | |
2036 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2037 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2038 | #define FLD(f) abuf->fields.sfmt_ld24.f | |
2039 | int UNUSED written = 0; | |
2040 | IADDR UNUSED pc = abuf->addr; | |
2041 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2042 | ||
2043 | { | |
2044 | SI opval = FLD (i_uimm24); | |
2045 | * FLD (i_dr) = opval; | |
2046 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2047 | } | |
2048 | ||
2049 | #undef FLD | |
2050 | } | |
2051 | NEXT (vpc); | |
2052 | ||
2053 | CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */ | |
2054 | { | |
2055 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2056 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2057 | #define FLD(f) abuf->fields.sfmt_addi.f | |
2058 | int UNUSED written = 0; | |
2059 | IADDR UNUSED pc = abuf->addr; | |
2060 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2061 | ||
2062 | { | |
2063 | SI opval = FLD (f_simm8); | |
2064 | * FLD (i_dr) = opval; | |
2065 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2066 | } | |
2067 | ||
2068 | #undef FLD | |
2069 | } | |
2070 | NEXT (vpc); | |
2071 | ||
2072 | CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */ | |
2073 | { | |
2074 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2075 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2076 | #define FLD(f) abuf->fields.sfmt_add3.f | |
2077 | int UNUSED written = 0; | |
2078 | IADDR UNUSED pc = abuf->addr; | |
2079 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2080 | ||
2081 | { | |
2082 | SI opval = FLD (f_simm16); | |
2083 | * FLD (i_dr) = opval; | |
2084 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2085 | } | |
2086 | ||
2087 | #undef FLD | |
2088 | } | |
2089 | NEXT (vpc); | |
2090 | ||
2091 | CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */ | |
2092 | { | |
2093 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2094 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2095 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
2096 | int UNUSED written = 0; | |
2097 | IADDR UNUSED pc = abuf->addr; | |
2098 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2099 | ||
2100 | { | |
2101 | { | |
2102 | BI opval = 1; | |
2103 | CPU (h_lock) = opval; | |
2104 | TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); | |
2105 | } | |
2106 | { | |
2107 | SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); | |
2108 | * FLD (i_dr) = opval; | |
2109 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2110 | } | |
2111 | } | |
2112 | ||
2113 | #undef FLD | |
2114 | } | |
2115 | NEXT (vpc); | |
2116 | ||
2117 | CASE (sem, INSN_MACHI_A) : /* machi $src1,$src2,$acc */ | |
2118 | { | |
2119 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2120 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2121 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
2122 | int UNUSED written = 0; | |
2123 | IADDR UNUSED pc = abuf->addr; | |
2124 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2125 | ||
2126 | { | |
2127 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); | |
2128 | SET_H_ACCUMS (FLD (f_acc), opval); | |
2129 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2130 | } | |
2131 | ||
2132 | #undef FLD | |
2133 | } | |
2134 | NEXT (vpc); | |
2135 | ||
2136 | CASE (sem, INSN_MACLO_A) : /* maclo $src1,$src2,$acc */ | |
2137 | { | |
2138 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2139 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2140 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
2141 | int UNUSED written = 0; | |
2142 | IADDR UNUSED pc = abuf->addr; | |
2143 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2144 | ||
2145 | { | |
2146 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); | |
2147 | SET_H_ACCUMS (FLD (f_acc), opval); | |
2148 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2149 | } | |
2150 | ||
2151 | #undef FLD | |
2152 | } | |
2153 | NEXT (vpc); | |
2154 | ||
2155 | CASE (sem, INSN_MACWHI_A) : /* macwhi $src1,$src2,$acc */ | |
2156 | { | |
2157 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2158 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2159 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
2160 | int UNUSED written = 0; | |
2161 | IADDR UNUSED pc = abuf->addr; | |
2162 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2163 | ||
2164 | { | |
2165 | DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))); | |
2166 | SET_H_ACCUMS (FLD (f_acc), opval); | |
2167 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2168 | } | |
2169 | ||
2170 | #undef FLD | |
2171 | } | |
2172 | NEXT (vpc); | |
2173 | ||
2174 | CASE (sem, INSN_MACWLO_A) : /* macwlo $src1,$src2,$acc */ | |
2175 | { | |
2176 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2177 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2178 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
2179 | int UNUSED written = 0; | |
2180 | IADDR UNUSED pc = abuf->addr; | |
2181 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2182 | ||
2183 | { | |
2184 | DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))); | |
2185 | SET_H_ACCUMS (FLD (f_acc), opval); | |
2186 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2187 | } | |
2188 | ||
2189 | #undef FLD | |
2190 | } | |
2191 | NEXT (vpc); | |
2192 | ||
2193 | CASE (sem, INSN_MUL) : /* mul $dr,$sr */ | |
2194 | { | |
2195 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2196 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2197 | #define FLD(f) abuf->fields.sfmt_add.f | |
2198 | int UNUSED written = 0; | |
2199 | IADDR UNUSED pc = abuf->addr; | |
2200 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2201 | ||
2202 | { | |
2203 | SI opval = MULSI (* FLD (i_dr), * FLD (i_sr)); | |
2204 | * FLD (i_dr) = opval; | |
2205 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2206 | } | |
2207 | ||
2208 | #undef FLD | |
2209 | } | |
2210 | NEXT (vpc); | |
2211 | ||
2212 | CASE (sem, INSN_MULHI_A) : /* mulhi $src1,$src2,$acc */ | |
2213 | { | |
2214 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2215 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2216 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
2217 | int UNUSED written = 0; | |
2218 | IADDR UNUSED pc = abuf->addr; | |
2219 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2220 | ||
2221 | { | |
2222 | DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16); | |
2223 | SET_H_ACCUMS (FLD (f_acc), opval); | |
2224 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2225 | } | |
2226 | ||
2227 | #undef FLD | |
2228 | } | |
2229 | NEXT (vpc); | |
2230 | ||
2231 | CASE (sem, INSN_MULLO_A) : /* mullo $src1,$src2,$acc */ | |
2232 | { | |
2233 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2234 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2235 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
2236 | int UNUSED written = 0; | |
2237 | IADDR UNUSED pc = abuf->addr; | |
2238 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2239 | ||
2240 | { | |
2241 | DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16); | |
2242 | SET_H_ACCUMS (FLD (f_acc), opval); | |
2243 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2244 | } | |
2245 | ||
2246 | #undef FLD | |
2247 | } | |
2248 | NEXT (vpc); | |
2249 | ||
2250 | CASE (sem, INSN_MULWHI_A) : /* mulwhi $src1,$src2,$acc */ | |
2251 | { | |
2252 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2253 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2254 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
2255 | int UNUSED written = 0; | |
2256 | IADDR UNUSED pc = abuf->addr; | |
2257 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2258 | ||
2259 | { | |
2260 | DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))); | |
2261 | SET_H_ACCUMS (FLD (f_acc), opval); | |
2262 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2263 | } | |
2264 | ||
2265 | #undef FLD | |
2266 | } | |
2267 | NEXT (vpc); | |
2268 | ||
2269 | CASE (sem, INSN_MULWLO_A) : /* mulwlo $src1,$src2,$acc */ | |
2270 | { | |
2271 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2272 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2273 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
2274 | int UNUSED written = 0; | |
2275 | IADDR UNUSED pc = abuf->addr; | |
2276 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2277 | ||
2278 | { | |
2279 | DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))); | |
2280 | SET_H_ACCUMS (FLD (f_acc), opval); | |
2281 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2282 | } | |
2283 | ||
2284 | #undef FLD | |
2285 | } | |
2286 | NEXT (vpc); | |
2287 | ||
2288 | CASE (sem, INSN_MV) : /* mv $dr,$sr */ | |
2289 | { | |
2290 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2291 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2292 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
2293 | int UNUSED written = 0; | |
2294 | IADDR UNUSED pc = abuf->addr; | |
2295 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2296 | ||
2297 | { | |
2298 | SI opval = * FLD (i_sr); | |
2299 | * FLD (i_dr) = opval; | |
2300 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2301 | } | |
2302 | ||
2303 | #undef FLD | |
2304 | } | |
2305 | NEXT (vpc); | |
2306 | ||
2307 | CASE (sem, INSN_MVFACHI_A) : /* mvfachi $dr,$accs */ | |
2308 | { | |
2309 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2310 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2311 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f | |
2312 | int UNUSED written = 0; | |
2313 | IADDR UNUSED pc = abuf->addr; | |
2314 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2315 | ||
2316 | { | |
2317 | SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32)); | |
2318 | * FLD (i_dr) = opval; | |
2319 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2320 | } | |
2321 | ||
2322 | #undef FLD | |
2323 | } | |
2324 | NEXT (vpc); | |
2325 | ||
2326 | CASE (sem, INSN_MVFACLO_A) : /* mvfaclo $dr,$accs */ | |
2327 | { | |
2328 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2329 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2330 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f | |
2331 | int UNUSED written = 0; | |
2332 | IADDR UNUSED pc = abuf->addr; | |
2333 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2334 | ||
2335 | { | |
2336 | SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs))); | |
2337 | * FLD (i_dr) = opval; | |
2338 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2339 | } | |
2340 | ||
2341 | #undef FLD | |
2342 | } | |
2343 | NEXT (vpc); | |
2344 | ||
2345 | CASE (sem, INSN_MVFACMI_A) : /* mvfacmi $dr,$accs */ | |
2346 | { | |
2347 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2348 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2349 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f | |
2350 | int UNUSED written = 0; | |
2351 | IADDR UNUSED pc = abuf->addr; | |
2352 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2353 | ||
2354 | { | |
2355 | SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16)); | |
2356 | * FLD (i_dr) = opval; | |
2357 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2358 | } | |
2359 | ||
2360 | #undef FLD | |
2361 | } | |
2362 | NEXT (vpc); | |
2363 | ||
2364 | CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */ | |
2365 | { | |
2366 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2367 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2368 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
2369 | int UNUSED written = 0; | |
2370 | IADDR UNUSED pc = abuf->addr; | |
2371 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2372 | ||
2373 | { | |
2374 | SI opval = GET_H_CR (FLD (f_r2)); | |
2375 | * FLD (i_dr) = opval; | |
2376 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2377 | } | |
2378 | ||
2379 | #undef FLD | |
2380 | } | |
2381 | NEXT (vpc); | |
2382 | ||
2383 | CASE (sem, INSN_MVTACHI_A) : /* mvtachi $src1,$accs */ | |
2384 | { | |
2385 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2386 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2387 | #define FLD(f) abuf->fields.sfmt_mvtachi_a.f | |
2388 | int UNUSED written = 0; | |
2389 | IADDR UNUSED pc = abuf->addr; | |
2390 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2391 | ||
2392 | { | |
2393 | DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32)); | |
2394 | SET_H_ACCUMS (FLD (f_accs), opval); | |
2395 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2396 | } | |
2397 | ||
2398 | #undef FLD | |
2399 | } | |
2400 | NEXT (vpc); | |
2401 | ||
2402 | CASE (sem, INSN_MVTACLO_A) : /* mvtaclo $src1,$accs */ | |
2403 | { | |
2404 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2405 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2406 | #define FLD(f) abuf->fields.sfmt_mvtachi_a.f | |
2407 | int UNUSED written = 0; | |
2408 | IADDR UNUSED pc = abuf->addr; | |
2409 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2410 | ||
2411 | { | |
2412 | DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1))); | |
2413 | SET_H_ACCUMS (FLD (f_accs), opval); | |
2414 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2415 | } | |
2416 | ||
2417 | #undef FLD | |
2418 | } | |
2419 | NEXT (vpc); | |
2420 | ||
2421 | CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */ | |
2422 | { | |
2423 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2424 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2425 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
2426 | int UNUSED written = 0; | |
2427 | IADDR UNUSED pc = abuf->addr; | |
2428 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2429 | ||
2430 | { | |
2431 | USI opval = * FLD (i_sr); | |
2432 | SET_H_CR (FLD (f_r1), opval); | |
2433 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
2434 | } | |
2435 | ||
2436 | #undef FLD | |
2437 | } | |
2438 | NEXT (vpc); | |
2439 | ||
2440 | CASE (sem, INSN_NEG) : /* neg $dr,$sr */ | |
2441 | { | |
2442 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2443 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2444 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
2445 | int UNUSED written = 0; | |
2446 | IADDR UNUSED pc = abuf->addr; | |
2447 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2448 | ||
2449 | { | |
2450 | SI opval = NEGSI (* FLD (i_sr)); | |
2451 | * FLD (i_dr) = opval; | |
2452 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2453 | } | |
2454 | ||
2455 | #undef FLD | |
2456 | } | |
2457 | NEXT (vpc); | |
2458 | ||
2459 | CASE (sem, INSN_NOP) : /* nop */ | |
2460 | { | |
2461 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2462 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 2463 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
2464 | int UNUSED written = 0; |
2465 | IADDR UNUSED pc = abuf->addr; | |
2466 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2467 | ||
2468 | PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); | |
2469 | ||
2470 | #undef FLD | |
2471 | } | |
2472 | NEXT (vpc); | |
2473 | ||
2474 | CASE (sem, INSN_NOT) : /* not $dr,$sr */ | |
2475 | { | |
2476 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2477 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2478 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
2479 | int UNUSED written = 0; | |
2480 | IADDR UNUSED pc = abuf->addr; | |
2481 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2482 | ||
2483 | { | |
2484 | SI opval = INVSI (* FLD (i_sr)); | |
2485 | * FLD (i_dr) = opval; | |
2486 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2487 | } | |
2488 | ||
2489 | #undef FLD | |
2490 | } | |
2491 | NEXT (vpc); | |
2492 | ||
2493 | CASE (sem, INSN_RAC_DSI) : /* rac $accd,$accs,$imm1 */ | |
2494 | { | |
2495 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2496 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2497 | #define FLD(f) abuf->fields.sfmt_rac_dsi.f | |
2498 | int UNUSED written = 0; | |
2499 | IADDR UNUSED pc = abuf->addr; | |
2500 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2501 | ||
2502 | { | |
2503 | DI tmp_tmp1; | |
2504 | tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); | |
2505 | tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); | |
2506 | { | |
2507 | DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))); | |
2508 | SET_H_ACCUMS (FLD (f_accd), opval); | |
2509 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2510 | } | |
2511 | } | |
2512 | ||
2513 | #undef FLD | |
2514 | } | |
2515 | NEXT (vpc); | |
2516 | ||
2517 | CASE (sem, INSN_RACH_DSI) : /* rach $accd,$accs,$imm1 */ | |
2518 | { | |
2519 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2520 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2521 | #define FLD(f) abuf->fields.sfmt_rac_dsi.f | |
2522 | int UNUSED written = 0; | |
2523 | IADDR UNUSED pc = abuf->addr; | |
2524 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2525 | ||
2526 | { | |
2527 | DI tmp_tmp1; | |
2528 | tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); | |
2529 | tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000)); | |
2530 | { | |
2531 | DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0))); | |
2532 | SET_H_ACCUMS (FLD (f_accd), opval); | |
2533 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
2534 | } | |
2535 | } | |
2536 | ||
2537 | #undef FLD | |
2538 | } | |
2539 | NEXT (vpc); | |
2540 | ||
2541 | CASE (sem, INSN_RTE) : /* rte */ | |
2542 | { | |
2543 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2544 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 2545 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
2546 | int UNUSED written = 0; |
2547 | IADDR UNUSED pc = abuf->addr; | |
2548 | SEM_BRANCH_INIT | |
2549 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2550 | ||
2551 | { | |
2552 | { | |
2553 | USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4); | |
2554 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
2555 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
2556 | } | |
2557 | { | |
2558 | USI opval = GET_H_CR (((UINT) 14)); | |
2559 | SET_H_CR (((UINT) 6), opval); | |
2560 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
2561 | } | |
2562 | { | |
2563 | UQI opval = CPU (h_bpsw); | |
2564 | SET_H_PSW (opval); | |
2565 | TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); | |
2566 | } | |
2567 | { | |
2568 | UQI opval = CPU (h_bbpsw); | |
2569 | CPU (h_bpsw) = opval; | |
2570 | TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); | |
2571 | } | |
2572 | } | |
2573 | ||
2574 | SEM_BRANCH_FINI (vpc); | |
2575 | #undef FLD | |
2576 | } | |
2577 | NEXT (vpc); | |
2578 | ||
2579 | CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */ | |
2580 | { | |
2581 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2582 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2583 | #define FLD(f) abuf->fields.sfmt_seth.f | |
2584 | int UNUSED written = 0; | |
2585 | IADDR UNUSED pc = abuf->addr; | |
2586 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2587 | ||
2588 | { | |
2589 | SI opval = SLLSI (FLD (f_hi16), 16); | |
2590 | * FLD (i_dr) = opval; | |
2591 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2592 | } | |
2593 | ||
2594 | #undef FLD | |
2595 | } | |
2596 | NEXT (vpc); | |
2597 | ||
2598 | CASE (sem, INSN_SLL) : /* sll $dr,$sr */ | |
2599 | { | |
2600 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2601 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2602 | #define FLD(f) abuf->fields.sfmt_add.f | |
2603 | int UNUSED written = 0; | |
2604 | IADDR UNUSED pc = abuf->addr; | |
2605 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2606 | ||
2607 | { | |
2608 | SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); | |
2609 | * FLD (i_dr) = opval; | |
2610 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2611 | } | |
2612 | ||
2613 | #undef FLD | |
2614 | } | |
2615 | NEXT (vpc); | |
2616 | ||
2617 | CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */ | |
2618 | { | |
2619 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2620 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2621 | #define FLD(f) abuf->fields.sfmt_add3.f | |
2622 | int UNUSED written = 0; | |
2623 | IADDR UNUSED pc = abuf->addr; | |
2624 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2625 | ||
2626 | { | |
2627 | SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); | |
2628 | * FLD (i_dr) = opval; | |
2629 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2630 | } | |
2631 | ||
2632 | #undef FLD | |
2633 | } | |
2634 | NEXT (vpc); | |
2635 | ||
2636 | CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */ | |
2637 | { | |
2638 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2639 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2640 | #define FLD(f) abuf->fields.sfmt_slli.f | |
2641 | int UNUSED written = 0; | |
2642 | IADDR UNUSED pc = abuf->addr; | |
2643 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2644 | ||
2645 | { | |
2646 | SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5)); | |
2647 | * FLD (i_dr) = opval; | |
2648 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2649 | } | |
2650 | ||
2651 | #undef FLD | |
2652 | } | |
2653 | NEXT (vpc); | |
2654 | ||
2655 | CASE (sem, INSN_SRA) : /* sra $dr,$sr */ | |
2656 | { | |
2657 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2658 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2659 | #define FLD(f) abuf->fields.sfmt_add.f | |
2660 | int UNUSED written = 0; | |
2661 | IADDR UNUSED pc = abuf->addr; | |
2662 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2663 | ||
2664 | { | |
2665 | SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); | |
2666 | * FLD (i_dr) = opval; | |
2667 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2668 | } | |
2669 | ||
2670 | #undef FLD | |
2671 | } | |
2672 | NEXT (vpc); | |
2673 | ||
2674 | CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */ | |
2675 | { | |
2676 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2677 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2678 | #define FLD(f) abuf->fields.sfmt_add3.f | |
2679 | int UNUSED written = 0; | |
2680 | IADDR UNUSED pc = abuf->addr; | |
2681 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2682 | ||
2683 | { | |
2684 | SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); | |
2685 | * FLD (i_dr) = opval; | |
2686 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2687 | } | |
2688 | ||
2689 | #undef FLD | |
2690 | } | |
2691 | NEXT (vpc); | |
2692 | ||
2693 | CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */ | |
2694 | { | |
2695 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2696 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2697 | #define FLD(f) abuf->fields.sfmt_slli.f | |
2698 | int UNUSED written = 0; | |
2699 | IADDR UNUSED pc = abuf->addr; | |
2700 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2701 | ||
2702 | { | |
2703 | SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5)); | |
2704 | * FLD (i_dr) = opval; | |
2705 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2706 | } | |
2707 | ||
2708 | #undef FLD | |
2709 | } | |
2710 | NEXT (vpc); | |
2711 | ||
2712 | CASE (sem, INSN_SRL) : /* srl $dr,$sr */ | |
2713 | { | |
2714 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2715 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2716 | #define FLD(f) abuf->fields.sfmt_add.f | |
2717 | int UNUSED written = 0; | |
2718 | IADDR UNUSED pc = abuf->addr; | |
2719 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2720 | ||
2721 | { | |
2722 | SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); | |
2723 | * FLD (i_dr) = opval; | |
2724 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2725 | } | |
2726 | ||
2727 | #undef FLD | |
2728 | } | |
2729 | NEXT (vpc); | |
2730 | ||
2731 | CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */ | |
2732 | { | |
2733 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2734 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2735 | #define FLD(f) abuf->fields.sfmt_add3.f | |
2736 | int UNUSED written = 0; | |
2737 | IADDR UNUSED pc = abuf->addr; | |
2738 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2739 | ||
2740 | { | |
2741 | SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); | |
2742 | * FLD (i_dr) = opval; | |
2743 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2744 | } | |
2745 | ||
2746 | #undef FLD | |
2747 | } | |
2748 | NEXT (vpc); | |
2749 | ||
2750 | CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */ | |
2751 | { | |
2752 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2753 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2754 | #define FLD(f) abuf->fields.sfmt_slli.f | |
2755 | int UNUSED written = 0; | |
2756 | IADDR UNUSED pc = abuf->addr; | |
2757 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2758 | ||
2759 | { | |
2760 | SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5)); | |
2761 | * FLD (i_dr) = opval; | |
2762 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2763 | } | |
2764 | ||
2765 | #undef FLD | |
2766 | } | |
2767 | NEXT (vpc); | |
2768 | ||
2769 | CASE (sem, INSN_ST) : /* st $src1,@$src2 */ | |
2770 | { | |
2771 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2772 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2773 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2774 | int UNUSED written = 0; | |
2775 | IADDR UNUSED pc = abuf->addr; | |
2776 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2777 | ||
2778 | { | |
2779 | SI opval = * FLD (i_src1); | |
2780 | SETMEMSI (current_cpu, pc, * FLD (i_src2), opval); | |
2781 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2782 | } | |
2783 | ||
2784 | #undef FLD | |
2785 | } | |
2786 | NEXT (vpc); | |
2787 | ||
2788 | CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */ | |
2789 | { | |
2790 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2791 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2792 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
2793 | int UNUSED written = 0; | |
2794 | IADDR UNUSED pc = abuf->addr; | |
2795 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2796 | ||
2797 | { | |
2798 | SI opval = * FLD (i_src1); | |
2799 | SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); | |
2800 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2801 | } | |
2802 | ||
2803 | #undef FLD | |
2804 | } | |
2805 | NEXT (vpc); | |
2806 | ||
2807 | CASE (sem, INSN_STB) : /* stb $src1,@$src2 */ | |
2808 | { | |
2809 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2810 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2811 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2812 | int UNUSED written = 0; | |
2813 | IADDR UNUSED pc = abuf->addr; | |
2814 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2815 | ||
2816 | { | |
2817 | QI opval = * FLD (i_src1); | |
2818 | SETMEMQI (current_cpu, pc, * FLD (i_src2), opval); | |
2819 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2820 | } | |
2821 | ||
2822 | #undef FLD | |
2823 | } | |
2824 | NEXT (vpc); | |
2825 | ||
2826 | CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */ | |
2827 | { | |
2828 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2829 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2830 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
2831 | int UNUSED written = 0; | |
2832 | IADDR UNUSED pc = abuf->addr; | |
2833 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2834 | ||
2835 | { | |
2836 | QI opval = * FLD (i_src1); | |
2837 | SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); | |
2838 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2839 | } | |
2840 | ||
2841 | #undef FLD | |
2842 | } | |
2843 | NEXT (vpc); | |
2844 | ||
2845 | CASE (sem, INSN_STH) : /* sth $src1,@$src2 */ | |
2846 | { | |
2847 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2848 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2849 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2850 | int UNUSED written = 0; | |
2851 | IADDR UNUSED pc = abuf->addr; | |
2852 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2853 | ||
2854 | { | |
2855 | HI opval = * FLD (i_src1); | |
2856 | SETMEMHI (current_cpu, pc, * FLD (i_src2), opval); | |
2857 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2858 | } | |
2859 | ||
2860 | #undef FLD | |
2861 | } | |
2862 | NEXT (vpc); | |
2863 | ||
2864 | CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */ | |
2865 | { | |
2866 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2867 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2868 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
2869 | int UNUSED written = 0; | |
2870 | IADDR UNUSED pc = abuf->addr; | |
2871 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2872 | ||
2873 | { | |
2874 | HI opval = * FLD (i_src1); | |
2875 | SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); | |
2876 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2877 | } | |
2878 | ||
2879 | #undef FLD | |
2880 | } | |
2881 | NEXT (vpc); | |
2882 | ||
2883 | CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */ | |
2884 | { | |
2885 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2886 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2887 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2888 | int UNUSED written = 0; | |
2889 | IADDR UNUSED pc = abuf->addr; | |
2890 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2891 | ||
2892 | { | |
2893 | SI tmp_new_src2; | |
2894 | tmp_new_src2 = ADDSI (* FLD (i_src2), 4); | |
2895 | { | |
2896 | SI opval = * FLD (i_src1); | |
2897 | SETMEMSI (current_cpu, pc, tmp_new_src2, opval); | |
2898 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2899 | } | |
2900 | { | |
2901 | SI opval = tmp_new_src2; | |
2902 | * FLD (i_src2) = opval; | |
2903 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2904 | } | |
2905 | } | |
2906 | ||
2907 | #undef FLD | |
2908 | } | |
2909 | NEXT (vpc); | |
2910 | ||
2911 | CASE (sem, INSN_STH_PLUS) : /* sth $src1,@$src2+ */ | |
2912 | { | |
2913 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2914 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2915 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2916 | int UNUSED written = 0; | |
2917 | IADDR UNUSED pc = abuf->addr; | |
2918 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2919 | ||
2920 | { | |
e9c60591 DE |
2921 | SI tmp_new_src2; |
2922 | tmp_new_src2 = * FLD (i_src2); | |
16b47b25 NC |
2923 | { |
2924 | HI opval = * FLD (i_src1); | |
2925 | SETMEMHI (current_cpu, pc, tmp_new_src2, opval); | |
2926 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2927 | } | |
16b47b25 | 2928 | { |
e9c60591 | 2929 | SI opval = ADDSI (tmp_new_src2, 2); |
16b47b25 NC |
2930 | * FLD (i_src2) = opval; |
2931 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2932 | } | |
2933 | } | |
2934 | ||
2935 | #undef FLD | |
2936 | } | |
2937 | NEXT (vpc); | |
2938 | ||
2939 | CASE (sem, INSN_STB_PLUS) : /* stb $src1,@$src2+ */ | |
2940 | { | |
2941 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2942 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2943 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2944 | int UNUSED written = 0; | |
2945 | IADDR UNUSED pc = abuf->addr; | |
2946 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2947 | ||
2948 | { | |
e9c60591 DE |
2949 | SI tmp_new_src2; |
2950 | tmp_new_src2 = * FLD (i_src2); | |
16b47b25 NC |
2951 | { |
2952 | QI opval = * FLD (i_src1); | |
2953 | SETMEMQI (current_cpu, pc, tmp_new_src2, opval); | |
2954 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2955 | } | |
16b47b25 | 2956 | { |
e9c60591 | 2957 | SI opval = ADDSI (tmp_new_src2, 1); |
16b47b25 NC |
2958 | * FLD (i_src2) = opval; |
2959 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2960 | } | |
2961 | } | |
2962 | ||
2963 | #undef FLD | |
2964 | } | |
2965 | NEXT (vpc); | |
2966 | ||
2967 | CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */ | |
2968 | { | |
2969 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2970 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2971 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2972 | int UNUSED written = 0; | |
2973 | IADDR UNUSED pc = abuf->addr; | |
2974 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
2975 | ||
2976 | { | |
2977 | SI tmp_new_src2; | |
2978 | tmp_new_src2 = SUBSI (* FLD (i_src2), 4); | |
2979 | { | |
2980 | SI opval = * FLD (i_src1); | |
2981 | SETMEMSI (current_cpu, pc, tmp_new_src2, opval); | |
2982 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
2983 | } | |
2984 | { | |
2985 | SI opval = tmp_new_src2; | |
2986 | * FLD (i_src2) = opval; | |
2987 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
2988 | } | |
2989 | } | |
2990 | ||
2991 | #undef FLD | |
2992 | } | |
2993 | NEXT (vpc); | |
2994 | ||
2995 | CASE (sem, INSN_SUB) : /* sub $dr,$sr */ | |
2996 | { | |
2997 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2998 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2999 | #define FLD(f) abuf->fields.sfmt_add.f | |
3000 | int UNUSED written = 0; | |
3001 | IADDR UNUSED pc = abuf->addr; | |
3002 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3003 | ||
3004 | { | |
3005 | SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr)); | |
3006 | * FLD (i_dr) = opval; | |
3007 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3008 | } | |
3009 | ||
3010 | #undef FLD | |
3011 | } | |
3012 | NEXT (vpc); | |
3013 | ||
3014 | CASE (sem, INSN_SUBV) : /* subv $dr,$sr */ | |
3015 | { | |
3016 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3017 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3018 | #define FLD(f) abuf->fields.sfmt_add.f | |
3019 | int UNUSED written = 0; | |
3020 | IADDR UNUSED pc = abuf->addr; | |
3021 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3022 | ||
3023 | { | |
3024 | SI temp0;BI temp1; | |
3025 | temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr)); | |
3026 | temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0); | |
3027 | { | |
3028 | SI opval = temp0; | |
3029 | * FLD (i_dr) = opval; | |
3030 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3031 | } | |
3032 | { | |
3033 | BI opval = temp1; | |
3034 | CPU (h_cond) = opval; | |
3035 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
3036 | } | |
3037 | } | |
3038 | ||
3039 | #undef FLD | |
3040 | } | |
3041 | NEXT (vpc); | |
3042 | ||
3043 | CASE (sem, INSN_SUBX) : /* subx $dr,$sr */ | |
3044 | { | |
3045 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3046 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3047 | #define FLD(f) abuf->fields.sfmt_add.f | |
3048 | int UNUSED written = 0; | |
3049 | IADDR UNUSED pc = abuf->addr; | |
3050 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3051 | ||
3052 | { | |
3053 | SI temp0;BI temp1; | |
3054 | temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); | |
3055 | temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); | |
3056 | { | |
3057 | SI opval = temp0; | |
3058 | * FLD (i_dr) = opval; | |
3059 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3060 | } | |
3061 | { | |
3062 | BI opval = temp1; | |
3063 | CPU (h_cond) = opval; | |
3064 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
3065 | } | |
3066 | } | |
3067 | ||
3068 | #undef FLD | |
3069 | } | |
3070 | NEXT (vpc); | |
3071 | ||
3072 | CASE (sem, INSN_TRAP) : /* trap $uimm4 */ | |
3073 | { | |
3074 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3075 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3076 | #define FLD(f) abuf->fields.sfmt_trap.f | |
3077 | int UNUSED written = 0; | |
3078 | IADDR UNUSED pc = abuf->addr; | |
3079 | SEM_BRANCH_INIT | |
3080 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3081 | ||
3082 | { | |
3083 | { | |
3084 | USI opval = GET_H_CR (((UINT) 6)); | |
3085 | SET_H_CR (((UINT) 14), opval); | |
3086 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
3087 | } | |
3088 | { | |
3089 | USI opval = ADDSI (pc, 4); | |
3090 | SET_H_CR (((UINT) 6), opval); | |
3091 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
3092 | } | |
3093 | { | |
3094 | UQI opval = CPU (h_bpsw); | |
3095 | CPU (h_bbpsw) = opval; | |
3096 | TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval); | |
3097 | } | |
3098 | { | |
3099 | UQI opval = GET_H_PSW (); | |
3100 | CPU (h_bpsw) = opval; | |
3101 | TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); | |
3102 | } | |
3103 | { | |
3104 | UQI opval = ANDQI (GET_H_PSW (), 128); | |
3105 | SET_H_PSW (opval); | |
3106 | TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); | |
3107 | } | |
3108 | { | |
3109 | SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4)); | |
3110 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
3111 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
3112 | } | |
3113 | } | |
3114 | ||
3115 | SEM_BRANCH_FINI (vpc); | |
3116 | #undef FLD | |
3117 | } | |
3118 | NEXT (vpc); | |
3119 | ||
3120 | CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */ | |
3121 | { | |
3122 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3123 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3124 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
3125 | int UNUSED written = 0; | |
3126 | IADDR UNUSED pc = abuf->addr; | |
3127 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3128 | ||
3129 | { | |
3130 | if (CPU (h_lock)) { | |
3131 | { | |
3132 | SI opval = * FLD (i_src1); | |
3133 | SETMEMSI (current_cpu, pc, * FLD (i_src2), opval); | |
3134 | written |= (1 << 4); | |
3135 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3136 | } | |
3137 | } | |
3138 | { | |
3139 | BI opval = 0; | |
3140 | CPU (h_lock) = opval; | |
3141 | TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); | |
3142 | } | |
3143 | } | |
3144 | ||
3145 | abuf->written = written; | |
3146 | #undef FLD | |
3147 | } | |
3148 | NEXT (vpc); | |
3149 | ||
3150 | CASE (sem, INSN_SATB) : /* satb $dr,$sr */ | |
3151 | { | |
3152 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3153 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3154 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
3155 | int UNUSED written = 0; | |
3156 | IADDR UNUSED pc = abuf->addr; | |
3157 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3158 | ||
3159 | { | |
3160 | SI opval = (GESI (* FLD (i_sr), 127)) ? (127) : (LESI (* FLD (i_sr), -128)) ? (-128) : (* FLD (i_sr)); | |
3161 | * FLD (i_dr) = opval; | |
3162 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3163 | } | |
3164 | ||
3165 | #undef FLD | |
3166 | } | |
3167 | NEXT (vpc); | |
3168 | ||
3169 | CASE (sem, INSN_SATH) : /* sath $dr,$sr */ | |
3170 | { | |
3171 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3172 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3173 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
3174 | int UNUSED written = 0; | |
3175 | IADDR UNUSED pc = abuf->addr; | |
3176 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3177 | ||
3178 | { | |
3179 | SI opval = (GESI (* FLD (i_sr), 32767)) ? (32767) : (LESI (* FLD (i_sr), -32768)) ? (-32768) : (* FLD (i_sr)); | |
3180 | * FLD (i_dr) = opval; | |
3181 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3182 | } | |
3183 | ||
3184 | #undef FLD | |
3185 | } | |
3186 | NEXT (vpc); | |
3187 | ||
3188 | CASE (sem, INSN_SAT) : /* sat $dr,$sr */ | |
3189 | { | |
3190 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3191 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3192 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
3193 | int UNUSED written = 0; | |
3194 | IADDR UNUSED pc = abuf->addr; | |
3195 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3196 | ||
3197 | { | |
3198 | SI opval = ((CPU (h_cond)) ? (((LTSI (* FLD (i_sr), 0)) ? (2147483647) : (0x80000000))) : (* FLD (i_sr))); | |
3199 | * FLD (i_dr) = opval; | |
3200 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3201 | } | |
3202 | ||
3203 | #undef FLD | |
3204 | } | |
3205 | NEXT (vpc); | |
3206 | ||
3207 | CASE (sem, INSN_PCMPBZ) : /* pcmpbz $src2 */ | |
3208 | { | |
3209 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3210 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3211 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
3212 | int UNUSED written = 0; | |
3213 | IADDR UNUSED pc = abuf->addr; | |
3214 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3215 | ||
3216 | { | |
3217 | BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0); | |
3218 | CPU (h_cond) = opval; | |
3219 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
3220 | } | |
3221 | ||
3222 | #undef FLD | |
3223 | } | |
3224 | NEXT (vpc); | |
3225 | ||
3226 | CASE (sem, INSN_SADD) : /* sadd */ | |
3227 | { | |
3228 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3229 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 3230 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
3231 | int UNUSED written = 0; |
3232 | IADDR UNUSED pc = abuf->addr; | |
3233 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3234 | ||
3235 | { | |
3236 | DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0))); | |
3237 | SET_H_ACCUMS (((UINT) 0), opval); | |
3238 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
3239 | } | |
3240 | ||
3241 | #undef FLD | |
3242 | } | |
3243 | NEXT (vpc); | |
3244 | ||
3245 | CASE (sem, INSN_MACWU1) : /* macwu1 $src1,$src2 */ | |
3246 | { | |
3247 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3248 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3249 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
3250 | int UNUSED written = 0; | |
3251 | IADDR UNUSED pc = abuf->addr; | |
3252 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3253 | ||
3254 | { | |
3255 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8); | |
3256 | SET_H_ACCUMS (((UINT) 1), opval); | |
3257 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
3258 | } | |
3259 | ||
3260 | #undef FLD | |
3261 | } | |
3262 | NEXT (vpc); | |
3263 | ||
3264 | CASE (sem, INSN_MSBLO) : /* msblo $src1,$src2 */ | |
3265 | { | |
3266 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3267 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3268 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
3269 | int UNUSED written = 0; | |
3270 | IADDR UNUSED pc = abuf->addr; | |
3271 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3272 | ||
3273 | { | |
3274 | DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8); | |
3275 | SET_H_ACCUM (opval); | |
3276 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
3277 | } | |
3278 | ||
3279 | #undef FLD | |
3280 | } | |
3281 | NEXT (vpc); | |
3282 | ||
3283 | CASE (sem, INSN_MULWU1) : /* mulwu1 $src1,$src2 */ | |
3284 | { | |
3285 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3286 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3287 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
3288 | int UNUSED written = 0; | |
3289 | IADDR UNUSED pc = abuf->addr; | |
3290 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3291 | ||
3292 | { | |
3293 | DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16); | |
3294 | SET_H_ACCUMS (((UINT) 1), opval); | |
3295 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
3296 | } | |
3297 | ||
3298 | #undef FLD | |
3299 | } | |
3300 | NEXT (vpc); | |
3301 | ||
3302 | CASE (sem, INSN_MACLH1) : /* maclh1 $src1,$src2 */ | |
3303 | { | |
3304 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3305 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3306 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
3307 | int UNUSED written = 0; | |
3308 | IADDR UNUSED pc = abuf->addr; | |
3309 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3310 | ||
3311 | { | |
3312 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8); | |
3313 | SET_H_ACCUMS (((UINT) 1), opval); | |
3314 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
3315 | } | |
3316 | ||
3317 | #undef FLD | |
3318 | } | |
3319 | NEXT (vpc); | |
3320 | ||
3321 | CASE (sem, INSN_SC) : /* sc */ | |
3322 | { | |
3323 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3324 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 3325 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
3326 | int UNUSED written = 0; |
3327 | IADDR UNUSED pc = abuf->addr; | |
3328 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3329 | ||
3330 | if (ZEXTBISI (CPU (h_cond))) | |
3331 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
3332 | ||
3333 | #undef FLD | |
3334 | } | |
3335 | NEXT (vpc); | |
3336 | ||
3337 | CASE (sem, INSN_SNC) : /* snc */ | |
3338 | { | |
3339 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3340 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 3341 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
3342 | int UNUSED written = 0; |
3343 | IADDR UNUSED pc = abuf->addr; | |
3344 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3345 | ||
3346 | if (ZEXTBISI (NOTBI (CPU (h_cond)))) | |
3347 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
3348 | ||
3349 | #undef FLD | |
3350 | } | |
3351 | NEXT (vpc); | |
3352 | ||
3353 | CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */ | |
3354 | { | |
3355 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3356 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3357 | #define FLD(f) abuf->fields.sfmt_clrpsw.f | |
3358 | int UNUSED written = 0; | |
3359 | IADDR UNUSED pc = abuf->addr; | |
3360 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3361 | ||
3362 | { | |
e9c60591 | 3363 | USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280)); |
16b47b25 NC |
3364 | SET_H_CR (((UINT) 0), opval); |
3365 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
3366 | } | |
3367 | ||
3368 | #undef FLD | |
3369 | } | |
3370 | NEXT (vpc); | |
3371 | ||
3372 | CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */ | |
3373 | { | |
3374 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3375 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3376 | #define FLD(f) abuf->fields.sfmt_clrpsw.f | |
3377 | int UNUSED written = 0; | |
3378 | IADDR UNUSED pc = abuf->addr; | |
3379 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3380 | ||
3381 | { | |
e9c60591 | 3382 | USI opval = FLD (f_uimm8); |
16b47b25 NC |
3383 | SET_H_CR (((UINT) 0), opval); |
3384 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
3385 | } | |
3386 | ||
3387 | #undef FLD | |
3388 | } | |
3389 | NEXT (vpc); | |
3390 | ||
3391 | CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */ | |
3392 | { | |
3393 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3394 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3395 | #define FLD(f) abuf->fields.sfmt_bset.f | |
3396 | int UNUSED written = 0; | |
3397 | IADDR UNUSED pc = abuf->addr; | |
3398 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3399 | ||
3400 | { | |
e9c60591 | 3401 | QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLQI (1, SUBSI (7, FLD (f_uimm3)))); |
16b47b25 NC |
3402 | SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval); |
3403 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3404 | } | |
3405 | ||
3406 | #undef FLD | |
3407 | } | |
3408 | NEXT (vpc); | |
3409 | ||
3410 | CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */ | |
3411 | { | |
3412 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3413 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3414 | #define FLD(f) abuf->fields.sfmt_bset.f | |
3415 | int UNUSED written = 0; | |
3416 | IADDR UNUSED pc = abuf->addr; | |
3417 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3418 | ||
3419 | { | |
e9c60591 | 3420 | QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLQI (1, SUBSI (7, FLD (f_uimm3))))); |
16b47b25 NC |
3421 | SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval); |
3422 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
3423 | } | |
3424 | ||
3425 | #undef FLD | |
3426 | } | |
3427 | NEXT (vpc); | |
3428 | ||
3429 | CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */ | |
3430 | { | |
3431 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3432 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3433 | #define FLD(f) abuf->fields.sfmt_bset.f | |
3434 | int UNUSED written = 0; | |
3435 | IADDR UNUSED pc = abuf->addr; | |
3436 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3437 | ||
3438 | { | |
e9c60591 | 3439 | BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1); |
16b47b25 NC |
3440 | CPU (h_cond) = opval; |
3441 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
3442 | } | |
3443 | ||
3444 | #undef FLD | |
3445 | } | |
3446 | NEXT (vpc); | |
3447 | ||
3448 | CASE (sem, INSN_PAR_ADD) : /* add $dr,$sr */ | |
3449 | { | |
3450 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3451 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3452 | #define FLD(f) abuf->fields.sfmt_add.f | |
3453 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
3454 | int UNUSED written = 0; | |
3455 | IADDR UNUSED pc = abuf->addr; | |
3456 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3457 | ||
3458 | { | |
3459 | SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr)); | |
3460 | OPRND (dr) = opval; | |
3461 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3462 | } | |
3463 | ||
3464 | #undef OPRND | |
3465 | #undef FLD | |
3466 | } | |
3467 | NEXT (vpc); | |
3468 | ||
3469 | CASE (sem, INSN_WRITE_ADD) : /* add $dr,$sr */ | |
3470 | { | |
3471 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3472 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3473 | #define FLD(f) abuf->fields.sfmt_add.f | |
3474 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
3475 | int UNUSED written = abuf->written; | |
3476 | IADDR UNUSED pc = abuf->addr; | |
3477 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3478 | ||
3479 | * FLD (i_dr) = OPRND (dr); | |
3480 | ||
3481 | #undef OPRND | |
3482 | #undef FLD | |
3483 | } | |
3484 | NEXT (vpc); | |
3485 | ||
3486 | CASE (sem, INSN_PAR_AND) : /* and $dr,$sr */ | |
3487 | { | |
3488 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3489 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3490 | #define FLD(f) abuf->fields.sfmt_add.f | |
3491 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
3492 | int UNUSED written = 0; | |
3493 | IADDR UNUSED pc = abuf->addr; | |
3494 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3495 | ||
3496 | { | |
3497 | SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr)); | |
3498 | OPRND (dr) = opval; | |
3499 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3500 | } | |
3501 | ||
3502 | #undef OPRND | |
3503 | #undef FLD | |
3504 | } | |
3505 | NEXT (vpc); | |
3506 | ||
3507 | CASE (sem, INSN_WRITE_AND) : /* and $dr,$sr */ | |
3508 | { | |
3509 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3510 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3511 | #define FLD(f) abuf->fields.sfmt_add.f | |
3512 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
3513 | int UNUSED written = abuf->written; | |
3514 | IADDR UNUSED pc = abuf->addr; | |
3515 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3516 | ||
3517 | * FLD (i_dr) = OPRND (dr); | |
3518 | ||
3519 | #undef OPRND | |
3520 | #undef FLD | |
3521 | } | |
3522 | NEXT (vpc); | |
3523 | ||
3524 | CASE (sem, INSN_PAR_OR) : /* or $dr,$sr */ | |
3525 | { | |
3526 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3527 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3528 | #define FLD(f) abuf->fields.sfmt_add.f | |
3529 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
3530 | int UNUSED written = 0; | |
3531 | IADDR UNUSED pc = abuf->addr; | |
3532 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3533 | ||
3534 | { | |
3535 | SI opval = ORSI (* FLD (i_dr), * FLD (i_sr)); | |
3536 | OPRND (dr) = opval; | |
3537 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3538 | } | |
3539 | ||
3540 | #undef OPRND | |
3541 | #undef FLD | |
3542 | } | |
3543 | NEXT (vpc); | |
3544 | ||
3545 | CASE (sem, INSN_WRITE_OR) : /* or $dr,$sr */ | |
3546 | { | |
3547 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3548 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3549 | #define FLD(f) abuf->fields.sfmt_add.f | |
3550 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
3551 | int UNUSED written = abuf->written; | |
3552 | IADDR UNUSED pc = abuf->addr; | |
3553 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3554 | ||
3555 | * FLD (i_dr) = OPRND (dr); | |
3556 | ||
3557 | #undef OPRND | |
3558 | #undef FLD | |
3559 | } | |
3560 | NEXT (vpc); | |
3561 | ||
3562 | CASE (sem, INSN_PAR_XOR) : /* xor $dr,$sr */ | |
3563 | { | |
3564 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3565 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3566 | #define FLD(f) abuf->fields.sfmt_add.f | |
3567 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
3568 | int UNUSED written = 0; | |
3569 | IADDR UNUSED pc = abuf->addr; | |
3570 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3571 | ||
3572 | { | |
3573 | SI opval = XORSI (* FLD (i_dr), * FLD (i_sr)); | |
3574 | OPRND (dr) = opval; | |
3575 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3576 | } | |
3577 | ||
3578 | #undef OPRND | |
3579 | #undef FLD | |
3580 | } | |
3581 | NEXT (vpc); | |
3582 | ||
3583 | CASE (sem, INSN_WRITE_XOR) : /* xor $dr,$sr */ | |
3584 | { | |
3585 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3586 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3587 | #define FLD(f) abuf->fields.sfmt_add.f | |
3588 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
3589 | int UNUSED written = abuf->written; | |
3590 | IADDR UNUSED pc = abuf->addr; | |
3591 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3592 | ||
3593 | * FLD (i_dr) = OPRND (dr); | |
3594 | ||
3595 | #undef OPRND | |
3596 | #undef FLD | |
3597 | } | |
3598 | NEXT (vpc); | |
3599 | ||
3600 | CASE (sem, INSN_PAR_ADDI) : /* addi $dr,$simm8 */ | |
3601 | { | |
3602 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3603 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3604 | #define FLD(f) abuf->fields.sfmt_addi.f | |
3605 | #define OPRND(f) par_exec->operands.sfmt_addi.f | |
3606 | int UNUSED written = 0; | |
3607 | IADDR UNUSED pc = abuf->addr; | |
3608 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3609 | ||
3610 | { | |
3611 | SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8)); | |
3612 | OPRND (dr) = opval; | |
3613 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3614 | } | |
3615 | ||
3616 | #undef OPRND | |
3617 | #undef FLD | |
3618 | } | |
3619 | NEXT (vpc); | |
3620 | ||
3621 | CASE (sem, INSN_WRITE_ADDI) : /* addi $dr,$simm8 */ | |
3622 | { | |
3623 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3624 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3625 | #define FLD(f) abuf->fields.sfmt_addi.f | |
3626 | #define OPRND(f) par_exec->operands.sfmt_addi.f | |
3627 | int UNUSED written = abuf->written; | |
3628 | IADDR UNUSED pc = abuf->addr; | |
3629 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3630 | ||
3631 | * FLD (i_dr) = OPRND (dr); | |
3632 | ||
3633 | #undef OPRND | |
3634 | #undef FLD | |
3635 | } | |
3636 | NEXT (vpc); | |
3637 | ||
3638 | CASE (sem, INSN_PAR_ADDV) : /* addv $dr,$sr */ | |
3639 | { | |
3640 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3641 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3642 | #define FLD(f) abuf->fields.sfmt_add.f | |
3643 | #define OPRND(f) par_exec->operands.sfmt_addv.f | |
3644 | int UNUSED written = 0; | |
3645 | IADDR UNUSED pc = abuf->addr; | |
3646 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3647 | ||
3648 | { | |
3649 | SI temp0;BI temp1; | |
3650 | temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr)); | |
3651 | temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0); | |
3652 | { | |
3653 | SI opval = temp0; | |
3654 | OPRND (dr) = opval; | |
3655 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3656 | } | |
3657 | { | |
3658 | BI opval = temp1; | |
3659 | OPRND (condbit) = opval; | |
3660 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
3661 | } | |
3662 | } | |
3663 | ||
3664 | #undef OPRND | |
3665 | #undef FLD | |
3666 | } | |
3667 | NEXT (vpc); | |
3668 | ||
3669 | CASE (sem, INSN_WRITE_ADDV) : /* addv $dr,$sr */ | |
3670 | { | |
3671 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3672 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3673 | #define FLD(f) abuf->fields.sfmt_add.f | |
3674 | #define OPRND(f) par_exec->operands.sfmt_addv.f | |
3675 | int UNUSED written = abuf->written; | |
3676 | IADDR UNUSED pc = abuf->addr; | |
3677 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3678 | ||
3679 | CPU (h_cond) = OPRND (condbit); | |
3680 | * FLD (i_dr) = OPRND (dr); | |
3681 | ||
3682 | #undef OPRND | |
3683 | #undef FLD | |
3684 | } | |
3685 | NEXT (vpc); | |
3686 | ||
3687 | CASE (sem, INSN_PAR_ADDX) : /* addx $dr,$sr */ | |
3688 | { | |
3689 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3690 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3691 | #define FLD(f) abuf->fields.sfmt_add.f | |
3692 | #define OPRND(f) par_exec->operands.sfmt_addx.f | |
3693 | int UNUSED written = 0; | |
3694 | IADDR UNUSED pc = abuf->addr; | |
3695 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3696 | ||
3697 | { | |
3698 | SI temp0;BI temp1; | |
3699 | temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); | |
3700 | temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); | |
3701 | { | |
3702 | SI opval = temp0; | |
3703 | OPRND (dr) = opval; | |
3704 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3705 | } | |
3706 | { | |
3707 | BI opval = temp1; | |
3708 | OPRND (condbit) = opval; | |
3709 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
3710 | } | |
3711 | } | |
3712 | ||
3713 | #undef OPRND | |
3714 | #undef FLD | |
3715 | } | |
3716 | NEXT (vpc); | |
3717 | ||
3718 | CASE (sem, INSN_WRITE_ADDX) : /* addx $dr,$sr */ | |
3719 | { | |
3720 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3721 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3722 | #define FLD(f) abuf->fields.sfmt_add.f | |
3723 | #define OPRND(f) par_exec->operands.sfmt_addx.f | |
3724 | int UNUSED written = abuf->written; | |
3725 | IADDR UNUSED pc = abuf->addr; | |
3726 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3727 | ||
3728 | CPU (h_cond) = OPRND (condbit); | |
3729 | * FLD (i_dr) = OPRND (dr); | |
3730 | ||
3731 | #undef OPRND | |
3732 | #undef FLD | |
3733 | } | |
3734 | NEXT (vpc); | |
3735 | ||
3736 | CASE (sem, INSN_PAR_BC8) : /* bc.s $disp8 */ | |
3737 | { | |
3738 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3739 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3740 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
3741 | #define OPRND(f) par_exec->operands.sfmt_bc8.f | |
3742 | int UNUSED written = 0; | |
3743 | IADDR UNUSED pc = abuf->addr; | |
3744 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3745 | ||
3746 | if (CPU (h_cond)) { | |
3747 | { | |
3748 | USI opval = FLD (i_disp8); | |
3749 | OPRND (pc) = opval; | |
3750 | written |= (1 << 2); | |
3751 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
3752 | } | |
3753 | } | |
3754 | ||
3755 | abuf->written = written; | |
3756 | #undef OPRND | |
3757 | #undef FLD | |
3758 | } | |
3759 | NEXT (vpc); | |
3760 | ||
3761 | CASE (sem, INSN_WRITE_BC8) : /* bc.s $disp8 */ | |
3762 | { | |
3763 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3764 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3765 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
3766 | #define OPRND(f) par_exec->operands.sfmt_bc8.f | |
3767 | int UNUSED written = abuf->written; | |
3768 | IADDR UNUSED pc = abuf->addr; | |
3769 | SEM_BRANCH_INIT | |
3770 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3771 | ||
3772 | if (written & (1 << 2)) | |
3773 | { | |
3774 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
3775 | } | |
3776 | ||
3777 | SEM_BRANCH_FINI (vpc); | |
3778 | #undef OPRND | |
3779 | #undef FLD | |
3780 | } | |
3781 | NEXT (vpc); | |
3782 | ||
3783 | CASE (sem, INSN_PAR_BL8) : /* bl.s $disp8 */ | |
3784 | { | |
3785 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3786 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3787 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
3788 | #define OPRND(f) par_exec->operands.sfmt_bl8.f | |
3789 | int UNUSED written = 0; | |
3790 | IADDR UNUSED pc = abuf->addr; | |
3791 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3792 | ||
3793 | { | |
3794 | { | |
3795 | SI opval = ADDSI (ANDSI (pc, -4), 4); | |
3796 | OPRND (h_gr_SI_14) = opval; | |
3797 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3798 | } | |
3799 | { | |
3800 | USI opval = FLD (i_disp8); | |
3801 | OPRND (pc) = opval; | |
3802 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
3803 | } | |
3804 | } | |
3805 | ||
3806 | #undef OPRND | |
3807 | #undef FLD | |
3808 | } | |
3809 | NEXT (vpc); | |
3810 | ||
3811 | CASE (sem, INSN_WRITE_BL8) : /* bl.s $disp8 */ | |
3812 | { | |
3813 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3814 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3815 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
3816 | #define OPRND(f) par_exec->operands.sfmt_bl8.f | |
3817 | int UNUSED written = abuf->written; | |
3818 | IADDR UNUSED pc = abuf->addr; | |
3819 | SEM_BRANCH_INIT | |
3820 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3821 | ||
3822 | CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); | |
3823 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
3824 | ||
3825 | SEM_BRANCH_FINI (vpc); | |
3826 | #undef OPRND | |
3827 | #undef FLD | |
3828 | } | |
3829 | NEXT (vpc); | |
3830 | ||
3831 | CASE (sem, INSN_PAR_BCL8) : /* bcl.s $disp8 */ | |
3832 | { | |
3833 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3834 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3835 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
3836 | #define OPRND(f) par_exec->operands.sfmt_bcl8.f | |
3837 | int UNUSED written = 0; | |
3838 | IADDR UNUSED pc = abuf->addr; | |
3839 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3840 | ||
3841 | if (CPU (h_cond)) { | |
3842 | { | |
3843 | { | |
3844 | SI opval = ADDSI (ANDSI (pc, -4), 4); | |
3845 | OPRND (h_gr_SI_14) = opval; | |
3846 | written |= (1 << 3); | |
3847 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3848 | } | |
3849 | { | |
3850 | USI opval = FLD (i_disp8); | |
3851 | OPRND (pc) = opval; | |
3852 | written |= (1 << 4); | |
3853 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
3854 | } | |
3855 | } | |
3856 | } | |
3857 | ||
3858 | abuf->written = written; | |
3859 | #undef OPRND | |
3860 | #undef FLD | |
3861 | } | |
3862 | NEXT (vpc); | |
3863 | ||
3864 | CASE (sem, INSN_WRITE_BCL8) : /* bcl.s $disp8 */ | |
3865 | { | |
3866 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3867 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3868 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
3869 | #define OPRND(f) par_exec->operands.sfmt_bcl8.f | |
3870 | int UNUSED written = abuf->written; | |
3871 | IADDR UNUSED pc = abuf->addr; | |
3872 | SEM_BRANCH_INIT | |
3873 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3874 | ||
3875 | if (written & (1 << 3)) | |
3876 | { | |
3877 | CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); | |
3878 | } | |
3879 | if (written & (1 << 4)) | |
3880 | { | |
3881 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
3882 | } | |
3883 | ||
3884 | SEM_BRANCH_FINI (vpc); | |
3885 | #undef OPRND | |
3886 | #undef FLD | |
3887 | } | |
3888 | NEXT (vpc); | |
3889 | ||
3890 | CASE (sem, INSN_PAR_BNC8) : /* bnc.s $disp8 */ | |
3891 | { | |
3892 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3893 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3894 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
3895 | #define OPRND(f) par_exec->operands.sfmt_bc8.f | |
3896 | int UNUSED written = 0; | |
3897 | IADDR UNUSED pc = abuf->addr; | |
3898 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3899 | ||
3900 | if (NOTBI (CPU (h_cond))) { | |
3901 | { | |
3902 | USI opval = FLD (i_disp8); | |
3903 | OPRND (pc) = opval; | |
3904 | written |= (1 << 2); | |
3905 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
3906 | } | |
3907 | } | |
3908 | ||
3909 | abuf->written = written; | |
3910 | #undef OPRND | |
3911 | #undef FLD | |
3912 | } | |
3913 | NEXT (vpc); | |
3914 | ||
3915 | CASE (sem, INSN_WRITE_BNC8) : /* bnc.s $disp8 */ | |
3916 | { | |
3917 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3918 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3919 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
3920 | #define OPRND(f) par_exec->operands.sfmt_bc8.f | |
3921 | int UNUSED written = abuf->written; | |
3922 | IADDR UNUSED pc = abuf->addr; | |
3923 | SEM_BRANCH_INIT | |
3924 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3925 | ||
3926 | if (written & (1 << 2)) | |
3927 | { | |
3928 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
3929 | } | |
3930 | ||
3931 | SEM_BRANCH_FINI (vpc); | |
3932 | #undef OPRND | |
3933 | #undef FLD | |
3934 | } | |
3935 | NEXT (vpc); | |
3936 | ||
3937 | CASE (sem, INSN_PAR_BRA8) : /* bra.s $disp8 */ | |
3938 | { | |
3939 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3940 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3941 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
3942 | #define OPRND(f) par_exec->operands.sfmt_bra8.f | |
3943 | int UNUSED written = 0; | |
3944 | IADDR UNUSED pc = abuf->addr; | |
3945 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3946 | ||
3947 | { | |
3948 | USI opval = FLD (i_disp8); | |
3949 | OPRND (pc) = opval; | |
3950 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
3951 | } | |
3952 | ||
3953 | #undef OPRND | |
3954 | #undef FLD | |
3955 | } | |
3956 | NEXT (vpc); | |
3957 | ||
3958 | CASE (sem, INSN_WRITE_BRA8) : /* bra.s $disp8 */ | |
3959 | { | |
3960 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3961 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
3962 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
3963 | #define OPRND(f) par_exec->operands.sfmt_bra8.f | |
3964 | int UNUSED written = abuf->written; | |
3965 | IADDR UNUSED pc = abuf->addr; | |
3966 | SEM_BRANCH_INIT | |
3967 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
3968 | ||
3969 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
3970 | ||
3971 | SEM_BRANCH_FINI (vpc); | |
3972 | #undef OPRND | |
3973 | #undef FLD | |
3974 | } | |
3975 | NEXT (vpc); | |
3976 | ||
3977 | CASE (sem, INSN_PAR_BNCL8) : /* bncl.s $disp8 */ | |
3978 | { | |
3979 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
3980 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3981 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
3982 | #define OPRND(f) par_exec->operands.sfmt_bcl8.f | |
3983 | int UNUSED written = 0; | |
3984 | IADDR UNUSED pc = abuf->addr; | |
3985 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
3986 | ||
3987 | if (NOTBI (CPU (h_cond))) { | |
3988 | { | |
3989 | { | |
3990 | SI opval = ADDSI (ANDSI (pc, -4), 4); | |
3991 | OPRND (h_gr_SI_14) = opval; | |
3992 | written |= (1 << 3); | |
3993 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
3994 | } | |
3995 | { | |
3996 | USI opval = FLD (i_disp8); | |
3997 | OPRND (pc) = opval; | |
3998 | written |= (1 << 4); | |
3999 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
4000 | } | |
4001 | } | |
4002 | } | |
4003 | ||
4004 | abuf->written = written; | |
4005 | #undef OPRND | |
4006 | #undef FLD | |
4007 | } | |
4008 | NEXT (vpc); | |
4009 | ||
4010 | CASE (sem, INSN_WRITE_BNCL8) : /* bncl.s $disp8 */ | |
4011 | { | |
4012 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4013 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4014 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
4015 | #define OPRND(f) par_exec->operands.sfmt_bcl8.f | |
4016 | int UNUSED written = abuf->written; | |
4017 | IADDR UNUSED pc = abuf->addr; | |
4018 | SEM_BRANCH_INIT | |
4019 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4020 | ||
4021 | if (written & (1 << 3)) | |
4022 | { | |
4023 | CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); | |
4024 | } | |
4025 | if (written & (1 << 4)) | |
4026 | { | |
4027 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
4028 | } | |
4029 | ||
4030 | SEM_BRANCH_FINI (vpc); | |
4031 | #undef OPRND | |
4032 | #undef FLD | |
4033 | } | |
4034 | NEXT (vpc); | |
4035 | ||
4036 | CASE (sem, INSN_PAR_CMP) : /* cmp $src1,$src2 */ | |
4037 | { | |
4038 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4039 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4040 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
4041 | #define OPRND(f) par_exec->operands.sfmt_cmp.f | |
4042 | int UNUSED written = 0; | |
4043 | IADDR UNUSED pc = abuf->addr; | |
4044 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4045 | ||
4046 | { | |
4047 | BI opval = LTSI (* FLD (i_src1), * FLD (i_src2)); | |
4048 | OPRND (condbit) = opval; | |
4049 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
4050 | } | |
4051 | ||
4052 | #undef OPRND | |
4053 | #undef FLD | |
4054 | } | |
4055 | NEXT (vpc); | |
4056 | ||
4057 | CASE (sem, INSN_WRITE_CMP) : /* cmp $src1,$src2 */ | |
4058 | { | |
4059 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4060 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4061 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
4062 | #define OPRND(f) par_exec->operands.sfmt_cmp.f | |
4063 | int UNUSED written = abuf->written; | |
4064 | IADDR UNUSED pc = abuf->addr; | |
4065 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4066 | ||
4067 | CPU (h_cond) = OPRND (condbit); | |
4068 | ||
4069 | #undef OPRND | |
4070 | #undef FLD | |
4071 | } | |
4072 | NEXT (vpc); | |
4073 | ||
4074 | CASE (sem, INSN_PAR_CMPU) : /* cmpu $src1,$src2 */ | |
4075 | { | |
4076 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4077 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4078 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
4079 | #define OPRND(f) par_exec->operands.sfmt_cmp.f | |
4080 | int UNUSED written = 0; | |
4081 | IADDR UNUSED pc = abuf->addr; | |
4082 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4083 | ||
4084 | { | |
4085 | BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2)); | |
4086 | OPRND (condbit) = opval; | |
4087 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
4088 | } | |
4089 | ||
4090 | #undef OPRND | |
4091 | #undef FLD | |
4092 | } | |
4093 | NEXT (vpc); | |
4094 | ||
4095 | CASE (sem, INSN_WRITE_CMPU) : /* cmpu $src1,$src2 */ | |
4096 | { | |
4097 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4098 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4099 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
4100 | #define OPRND(f) par_exec->operands.sfmt_cmp.f | |
4101 | int UNUSED written = abuf->written; | |
4102 | IADDR UNUSED pc = abuf->addr; | |
4103 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4104 | ||
4105 | CPU (h_cond) = OPRND (condbit); | |
4106 | ||
4107 | #undef OPRND | |
4108 | #undef FLD | |
4109 | } | |
4110 | NEXT (vpc); | |
4111 | ||
4112 | CASE (sem, INSN_PAR_CMPEQ) : /* cmpeq $src1,$src2 */ | |
4113 | { | |
4114 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4115 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4116 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
4117 | #define OPRND(f) par_exec->operands.sfmt_cmp.f | |
4118 | int UNUSED written = 0; | |
4119 | IADDR UNUSED pc = abuf->addr; | |
4120 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4121 | ||
4122 | { | |
4123 | BI opval = EQSI (* FLD (i_src1), * FLD (i_src2)); | |
4124 | OPRND (condbit) = opval; | |
4125 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
4126 | } | |
4127 | ||
4128 | #undef OPRND | |
4129 | #undef FLD | |
4130 | } | |
4131 | NEXT (vpc); | |
4132 | ||
4133 | CASE (sem, INSN_WRITE_CMPEQ) : /* cmpeq $src1,$src2 */ | |
4134 | { | |
4135 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4136 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4137 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
4138 | #define OPRND(f) par_exec->operands.sfmt_cmp.f | |
4139 | int UNUSED written = abuf->written; | |
4140 | IADDR UNUSED pc = abuf->addr; | |
4141 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4142 | ||
4143 | CPU (h_cond) = OPRND (condbit); | |
4144 | ||
4145 | #undef OPRND | |
4146 | #undef FLD | |
4147 | } | |
4148 | NEXT (vpc); | |
4149 | ||
4150 | CASE (sem, INSN_PAR_CMPZ) : /* cmpz $src2 */ | |
4151 | { | |
4152 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4153 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4154 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
4155 | #define OPRND(f) par_exec->operands.sfmt_cmpz.f | |
4156 | int UNUSED written = 0; | |
4157 | IADDR UNUSED pc = abuf->addr; | |
4158 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4159 | ||
4160 | { | |
4161 | BI opval = EQSI (* FLD (i_src2), 0); | |
4162 | OPRND (condbit) = opval; | |
4163 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
4164 | } | |
4165 | ||
4166 | #undef OPRND | |
4167 | #undef FLD | |
4168 | } | |
4169 | NEXT (vpc); | |
4170 | ||
4171 | CASE (sem, INSN_WRITE_CMPZ) : /* cmpz $src2 */ | |
4172 | { | |
4173 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4174 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4175 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
4176 | #define OPRND(f) par_exec->operands.sfmt_cmpz.f | |
4177 | int UNUSED written = abuf->written; | |
4178 | IADDR UNUSED pc = abuf->addr; | |
4179 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4180 | ||
4181 | CPU (h_cond) = OPRND (condbit); | |
4182 | ||
4183 | #undef OPRND | |
4184 | #undef FLD | |
4185 | } | |
4186 | NEXT (vpc); | |
4187 | ||
4188 | CASE (sem, INSN_PAR_JC) : /* jc $sr */ | |
4189 | { | |
4190 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4191 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4192 | #define FLD(f) abuf->fields.sfmt_jl.f | |
4193 | #define OPRND(f) par_exec->operands.sfmt_jc.f | |
4194 | int UNUSED written = 0; | |
4195 | IADDR UNUSED pc = abuf->addr; | |
4196 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4197 | ||
4198 | if (CPU (h_cond)) { | |
4199 | { | |
4200 | USI opval = ANDSI (* FLD (i_sr), -4); | |
4201 | OPRND (pc) = opval; | |
4202 | written |= (1 << 2); | |
4203 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
4204 | } | |
4205 | } | |
4206 | ||
4207 | abuf->written = written; | |
4208 | #undef OPRND | |
4209 | #undef FLD | |
4210 | } | |
4211 | NEXT (vpc); | |
4212 | ||
4213 | CASE (sem, INSN_WRITE_JC) : /* jc $sr */ | |
4214 | { | |
4215 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4216 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4217 | #define FLD(f) abuf->fields.sfmt_jl.f | |
4218 | #define OPRND(f) par_exec->operands.sfmt_jc.f | |
4219 | int UNUSED written = abuf->written; | |
4220 | IADDR UNUSED pc = abuf->addr; | |
4221 | SEM_BRANCH_INIT | |
4222 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4223 | ||
4224 | if (written & (1 << 2)) | |
4225 | { | |
4226 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
4227 | } | |
4228 | ||
4229 | SEM_BRANCH_FINI (vpc); | |
4230 | #undef OPRND | |
4231 | #undef FLD | |
4232 | } | |
4233 | NEXT (vpc); | |
4234 | ||
4235 | CASE (sem, INSN_PAR_JNC) : /* jnc $sr */ | |
4236 | { | |
4237 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4238 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4239 | #define FLD(f) abuf->fields.sfmt_jl.f | |
4240 | #define OPRND(f) par_exec->operands.sfmt_jc.f | |
4241 | int UNUSED written = 0; | |
4242 | IADDR UNUSED pc = abuf->addr; | |
4243 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4244 | ||
4245 | if (NOTBI (CPU (h_cond))) { | |
4246 | { | |
4247 | USI opval = ANDSI (* FLD (i_sr), -4); | |
4248 | OPRND (pc) = opval; | |
4249 | written |= (1 << 2); | |
4250 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
4251 | } | |
4252 | } | |
4253 | ||
4254 | abuf->written = written; | |
4255 | #undef OPRND | |
4256 | #undef FLD | |
4257 | } | |
4258 | NEXT (vpc); | |
4259 | ||
4260 | CASE (sem, INSN_WRITE_JNC) : /* jnc $sr */ | |
4261 | { | |
4262 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4263 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4264 | #define FLD(f) abuf->fields.sfmt_jl.f | |
4265 | #define OPRND(f) par_exec->operands.sfmt_jc.f | |
4266 | int UNUSED written = abuf->written; | |
4267 | IADDR UNUSED pc = abuf->addr; | |
4268 | SEM_BRANCH_INIT | |
4269 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4270 | ||
4271 | if (written & (1 << 2)) | |
4272 | { | |
4273 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
4274 | } | |
4275 | ||
4276 | SEM_BRANCH_FINI (vpc); | |
4277 | #undef OPRND | |
4278 | #undef FLD | |
4279 | } | |
4280 | NEXT (vpc); | |
4281 | ||
4282 | CASE (sem, INSN_PAR_JL) : /* jl $sr */ | |
4283 | { | |
4284 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4285 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4286 | #define FLD(f) abuf->fields.sfmt_jl.f | |
4287 | #define OPRND(f) par_exec->operands.sfmt_jl.f | |
4288 | int UNUSED written = 0; | |
4289 | IADDR UNUSED pc = abuf->addr; | |
4290 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4291 | ||
4292 | { | |
4293 | SI temp0;USI temp1; | |
4294 | temp0 = ADDSI (ANDSI (pc, -4), 4); | |
4295 | temp1 = ANDSI (* FLD (i_sr), -4); | |
4296 | { | |
4297 | SI opval = temp0; | |
4298 | OPRND (h_gr_SI_14) = opval; | |
4299 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
4300 | } | |
4301 | { | |
4302 | USI opval = temp1; | |
4303 | OPRND (pc) = opval; | |
4304 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
4305 | } | |
4306 | } | |
4307 | ||
4308 | #undef OPRND | |
4309 | #undef FLD | |
4310 | } | |
4311 | NEXT (vpc); | |
4312 | ||
4313 | CASE (sem, INSN_WRITE_JL) : /* jl $sr */ | |
4314 | { | |
4315 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4316 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4317 | #define FLD(f) abuf->fields.sfmt_jl.f | |
4318 | #define OPRND(f) par_exec->operands.sfmt_jl.f | |
4319 | int UNUSED written = abuf->written; | |
4320 | IADDR UNUSED pc = abuf->addr; | |
4321 | SEM_BRANCH_INIT | |
4322 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4323 | ||
4324 | CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); | |
4325 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
4326 | ||
4327 | SEM_BRANCH_FINI (vpc); | |
4328 | #undef OPRND | |
4329 | #undef FLD | |
4330 | } | |
4331 | NEXT (vpc); | |
4332 | ||
4333 | CASE (sem, INSN_PAR_JMP) : /* jmp $sr */ | |
4334 | { | |
4335 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4336 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4337 | #define FLD(f) abuf->fields.sfmt_jl.f | |
4338 | #define OPRND(f) par_exec->operands.sfmt_jmp.f | |
4339 | int UNUSED written = 0; | |
4340 | IADDR UNUSED pc = abuf->addr; | |
4341 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4342 | ||
4343 | { | |
4344 | USI opval = ANDSI (* FLD (i_sr), -4); | |
4345 | OPRND (pc) = opval; | |
4346 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
4347 | } | |
4348 | ||
4349 | #undef OPRND | |
4350 | #undef FLD | |
4351 | } | |
4352 | NEXT (vpc); | |
4353 | ||
4354 | CASE (sem, INSN_WRITE_JMP) : /* jmp $sr */ | |
4355 | { | |
4356 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4357 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4358 | #define FLD(f) abuf->fields.sfmt_jl.f | |
4359 | #define OPRND(f) par_exec->operands.sfmt_jmp.f | |
4360 | int UNUSED written = abuf->written; | |
4361 | IADDR UNUSED pc = abuf->addr; | |
4362 | SEM_BRANCH_INIT | |
4363 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4364 | ||
4365 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
4366 | ||
4367 | SEM_BRANCH_FINI (vpc); | |
4368 | #undef OPRND | |
4369 | #undef FLD | |
4370 | } | |
4371 | NEXT (vpc); | |
4372 | ||
4373 | CASE (sem, INSN_PAR_LD) : /* ld $dr,@$sr */ | |
4374 | { | |
4375 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4376 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4377 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4378 | #define OPRND(f) par_exec->operands.sfmt_ld.f | |
4379 | int UNUSED written = 0; | |
4380 | IADDR UNUSED pc = abuf->addr; | |
4381 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4382 | ||
4383 | { | |
4384 | SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); | |
4385 | OPRND (dr) = opval; | |
4386 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
4387 | } | |
4388 | ||
4389 | #undef OPRND | |
4390 | #undef FLD | |
4391 | } | |
4392 | NEXT (vpc); | |
4393 | ||
4394 | CASE (sem, INSN_WRITE_LD) : /* ld $dr,@$sr */ | |
4395 | { | |
4396 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4397 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4398 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4399 | #define OPRND(f) par_exec->operands.sfmt_ld.f | |
4400 | int UNUSED written = abuf->written; | |
4401 | IADDR UNUSED pc = abuf->addr; | |
4402 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4403 | ||
4404 | * FLD (i_dr) = OPRND (dr); | |
4405 | ||
4406 | #undef OPRND | |
4407 | #undef FLD | |
4408 | } | |
4409 | NEXT (vpc); | |
4410 | ||
4411 | CASE (sem, INSN_PAR_LDB) : /* ldb $dr,@$sr */ | |
4412 | { | |
4413 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4414 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4415 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4416 | #define OPRND(f) par_exec->operands.sfmt_ldb.f | |
4417 | int UNUSED written = 0; | |
4418 | IADDR UNUSED pc = abuf->addr; | |
4419 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4420 | ||
4421 | { | |
4422 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); | |
4423 | OPRND (dr) = opval; | |
4424 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
4425 | } | |
4426 | ||
4427 | #undef OPRND | |
4428 | #undef FLD | |
4429 | } | |
4430 | NEXT (vpc); | |
4431 | ||
4432 | CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */ | |
4433 | { | |
4434 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4435 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4436 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4437 | #define OPRND(f) par_exec->operands.sfmt_ldb.f | |
4438 | int UNUSED written = abuf->written; | |
4439 | IADDR UNUSED pc = abuf->addr; | |
4440 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4441 | ||
4442 | * FLD (i_dr) = OPRND (dr); | |
4443 | ||
4444 | #undef OPRND | |
4445 | #undef FLD | |
4446 | } | |
4447 | NEXT (vpc); | |
4448 | ||
4449 | CASE (sem, INSN_PAR_LDH) : /* ldh $dr,@$sr */ | |
4450 | { | |
4451 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4452 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4453 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4454 | #define OPRND(f) par_exec->operands.sfmt_ldh.f | |
4455 | int UNUSED written = 0; | |
4456 | IADDR UNUSED pc = abuf->addr; | |
4457 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4458 | ||
4459 | { | |
4460 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); | |
4461 | OPRND (dr) = opval; | |
4462 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
4463 | } | |
4464 | ||
4465 | #undef OPRND | |
4466 | #undef FLD | |
4467 | } | |
4468 | NEXT (vpc); | |
4469 | ||
4470 | CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */ | |
4471 | { | |
4472 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4473 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4474 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4475 | #define OPRND(f) par_exec->operands.sfmt_ldh.f | |
4476 | int UNUSED written = abuf->written; | |
4477 | IADDR UNUSED pc = abuf->addr; | |
4478 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4479 | ||
4480 | * FLD (i_dr) = OPRND (dr); | |
4481 | ||
4482 | #undef OPRND | |
4483 | #undef FLD | |
4484 | } | |
4485 | NEXT (vpc); | |
4486 | ||
4487 | CASE (sem, INSN_PAR_LDUB) : /* ldub $dr,@$sr */ | |
4488 | { | |
4489 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4490 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4491 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4492 | #define OPRND(f) par_exec->operands.sfmt_ldb.f | |
4493 | int UNUSED written = 0; | |
4494 | IADDR UNUSED pc = abuf->addr; | |
4495 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4496 | ||
4497 | { | |
4498 | SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); | |
4499 | OPRND (dr) = opval; | |
4500 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
4501 | } | |
4502 | ||
4503 | #undef OPRND | |
4504 | #undef FLD | |
4505 | } | |
4506 | NEXT (vpc); | |
4507 | ||
4508 | CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */ | |
4509 | { | |
4510 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4511 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4512 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4513 | #define OPRND(f) par_exec->operands.sfmt_ldb.f | |
4514 | int UNUSED written = abuf->written; | |
4515 | IADDR UNUSED pc = abuf->addr; | |
4516 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4517 | ||
4518 | * FLD (i_dr) = OPRND (dr); | |
4519 | ||
4520 | #undef OPRND | |
4521 | #undef FLD | |
4522 | } | |
4523 | NEXT (vpc); | |
4524 | ||
4525 | CASE (sem, INSN_PAR_LDUH) : /* lduh $dr,@$sr */ | |
4526 | { | |
4527 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4528 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4529 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4530 | #define OPRND(f) par_exec->operands.sfmt_ldh.f | |
4531 | int UNUSED written = 0; | |
4532 | IADDR UNUSED pc = abuf->addr; | |
4533 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4534 | ||
4535 | { | |
4536 | SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); | |
4537 | OPRND (dr) = opval; | |
4538 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
4539 | } | |
4540 | ||
4541 | #undef OPRND | |
4542 | #undef FLD | |
4543 | } | |
4544 | NEXT (vpc); | |
4545 | ||
4546 | CASE (sem, INSN_WRITE_LDUH) : /* lduh $dr,@$sr */ | |
4547 | { | |
4548 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4549 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4550 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4551 | #define OPRND(f) par_exec->operands.sfmt_ldh.f | |
4552 | int UNUSED written = abuf->written; | |
4553 | IADDR UNUSED pc = abuf->addr; | |
4554 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4555 | ||
4556 | * FLD (i_dr) = OPRND (dr); | |
4557 | ||
4558 | #undef OPRND | |
4559 | #undef FLD | |
4560 | } | |
4561 | NEXT (vpc); | |
4562 | ||
4563 | CASE (sem, INSN_PAR_LD_PLUS) : /* ld $dr,@$sr+ */ | |
4564 | { | |
4565 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4566 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4567 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4568 | #define OPRND(f) par_exec->operands.sfmt_ld_plus.f | |
4569 | int UNUSED written = 0; | |
4570 | IADDR UNUSED pc = abuf->addr; | |
4571 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4572 | ||
4573 | { | |
4574 | SI temp0;SI temp1; | |
4575 | temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr)); | |
4576 | temp1 = ADDSI (* FLD (i_sr), 4); | |
4577 | { | |
4578 | SI opval = temp0; | |
4579 | OPRND (dr) = opval; | |
4580 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
4581 | } | |
4582 | { | |
4583 | SI opval = temp1; | |
4584 | OPRND (sr) = opval; | |
4585 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
4586 | } | |
4587 | } | |
4588 | ||
4589 | #undef OPRND | |
4590 | #undef FLD | |
4591 | } | |
4592 | NEXT (vpc); | |
4593 | ||
4594 | CASE (sem, INSN_WRITE_LD_PLUS) : /* ld $dr,@$sr+ */ | |
4595 | { | |
4596 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4597 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4598 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4599 | #define OPRND(f) par_exec->operands.sfmt_ld_plus.f | |
4600 | int UNUSED written = abuf->written; | |
4601 | IADDR UNUSED pc = abuf->addr; | |
4602 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4603 | ||
4604 | * FLD (i_dr) = OPRND (dr); | |
4605 | * FLD (i_sr) = OPRND (sr); | |
4606 | ||
4607 | #undef OPRND | |
4608 | #undef FLD | |
4609 | } | |
4610 | NEXT (vpc); | |
4611 | ||
4612 | CASE (sem, INSN_PAR_LDI8) : /* ldi8 $dr,$simm8 */ | |
4613 | { | |
4614 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4615 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4616 | #define FLD(f) abuf->fields.sfmt_addi.f | |
4617 | #define OPRND(f) par_exec->operands.sfmt_ldi8.f | |
4618 | int UNUSED written = 0; | |
4619 | IADDR UNUSED pc = abuf->addr; | |
4620 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4621 | ||
4622 | { | |
4623 | SI opval = FLD (f_simm8); | |
4624 | OPRND (dr) = opval; | |
4625 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
4626 | } | |
4627 | ||
4628 | #undef OPRND | |
4629 | #undef FLD | |
4630 | } | |
4631 | NEXT (vpc); | |
4632 | ||
4633 | CASE (sem, INSN_WRITE_LDI8) : /* ldi8 $dr,$simm8 */ | |
4634 | { | |
4635 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4636 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4637 | #define FLD(f) abuf->fields.sfmt_addi.f | |
4638 | #define OPRND(f) par_exec->operands.sfmt_ldi8.f | |
4639 | int UNUSED written = abuf->written; | |
4640 | IADDR UNUSED pc = abuf->addr; | |
4641 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4642 | ||
4643 | * FLD (i_dr) = OPRND (dr); | |
4644 | ||
4645 | #undef OPRND | |
4646 | #undef FLD | |
4647 | } | |
4648 | NEXT (vpc); | |
4649 | ||
4650 | CASE (sem, INSN_PAR_LOCK) : /* lock $dr,@$sr */ | |
4651 | { | |
4652 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4653 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4654 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4655 | #define OPRND(f) par_exec->operands.sfmt_lock.f | |
4656 | int UNUSED written = 0; | |
4657 | IADDR UNUSED pc = abuf->addr; | |
4658 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4659 | ||
4660 | { | |
4661 | { | |
4662 | BI opval = 1; | |
4663 | OPRND (h_lock_BI) = opval; | |
4664 | TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); | |
4665 | } | |
4666 | { | |
4667 | SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); | |
4668 | OPRND (dr) = opval; | |
4669 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
4670 | } | |
4671 | } | |
4672 | ||
4673 | #undef OPRND | |
4674 | #undef FLD | |
4675 | } | |
4676 | NEXT (vpc); | |
4677 | ||
4678 | CASE (sem, INSN_WRITE_LOCK) : /* lock $dr,@$sr */ | |
4679 | { | |
4680 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4681 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4682 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
4683 | #define OPRND(f) par_exec->operands.sfmt_lock.f | |
4684 | int UNUSED written = abuf->written; | |
4685 | IADDR UNUSED pc = abuf->addr; | |
4686 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4687 | ||
4688 | * FLD (i_dr) = OPRND (dr); | |
4689 | CPU (h_lock) = OPRND (h_lock_BI); | |
4690 | ||
4691 | #undef OPRND | |
4692 | #undef FLD | |
4693 | } | |
4694 | NEXT (vpc); | |
4695 | ||
4696 | CASE (sem, INSN_PAR_MACHI_A) : /* machi $src1,$src2,$acc */ | |
4697 | { | |
4698 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4699 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4700 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4701 | #define OPRND(f) par_exec->operands.sfmt_machi_a.f | |
4702 | int UNUSED written = 0; | |
4703 | IADDR UNUSED pc = abuf->addr; | |
4704 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4705 | ||
4706 | { | |
4707 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); | |
4708 | OPRND (acc) = opval; | |
4709 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
4710 | } | |
4711 | ||
4712 | #undef OPRND | |
4713 | #undef FLD | |
4714 | } | |
4715 | NEXT (vpc); | |
4716 | ||
4717 | CASE (sem, INSN_WRITE_MACHI_A) : /* machi $src1,$src2,$acc */ | |
4718 | { | |
4719 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4720 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4721 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4722 | #define OPRND(f) par_exec->operands.sfmt_machi_a.f | |
4723 | int UNUSED written = abuf->written; | |
4724 | IADDR UNUSED pc = abuf->addr; | |
4725 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4726 | ||
4727 | SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); | |
4728 | ||
4729 | #undef OPRND | |
4730 | #undef FLD | |
4731 | } | |
4732 | NEXT (vpc); | |
4733 | ||
4734 | CASE (sem, INSN_PAR_MACLO_A) : /* maclo $src1,$src2,$acc */ | |
4735 | { | |
4736 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4737 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4738 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4739 | #define OPRND(f) par_exec->operands.sfmt_machi_a.f | |
4740 | int UNUSED written = 0; | |
4741 | IADDR UNUSED pc = abuf->addr; | |
4742 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4743 | ||
4744 | { | |
4745 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); | |
4746 | OPRND (acc) = opval; | |
4747 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
4748 | } | |
4749 | ||
4750 | #undef OPRND | |
4751 | #undef FLD | |
4752 | } | |
4753 | NEXT (vpc); | |
4754 | ||
4755 | CASE (sem, INSN_WRITE_MACLO_A) : /* maclo $src1,$src2,$acc */ | |
4756 | { | |
4757 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4758 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4759 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4760 | #define OPRND(f) par_exec->operands.sfmt_machi_a.f | |
4761 | int UNUSED written = abuf->written; | |
4762 | IADDR UNUSED pc = abuf->addr; | |
4763 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4764 | ||
4765 | SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); | |
4766 | ||
4767 | #undef OPRND | |
4768 | #undef FLD | |
4769 | } | |
4770 | NEXT (vpc); | |
4771 | ||
4772 | CASE (sem, INSN_PAR_MACWHI_A) : /* macwhi $src1,$src2,$acc */ | |
4773 | { | |
4774 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4775 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4776 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4777 | #define OPRND(f) par_exec->operands.sfmt_machi_a.f | |
4778 | int UNUSED written = 0; | |
4779 | IADDR UNUSED pc = abuf->addr; | |
4780 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4781 | ||
4782 | { | |
4783 | DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))); | |
4784 | OPRND (acc) = opval; | |
4785 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
4786 | } | |
4787 | ||
4788 | #undef OPRND | |
4789 | #undef FLD | |
4790 | } | |
4791 | NEXT (vpc); | |
4792 | ||
4793 | CASE (sem, INSN_WRITE_MACWHI_A) : /* macwhi $src1,$src2,$acc */ | |
4794 | { | |
4795 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4796 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4797 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4798 | #define OPRND(f) par_exec->operands.sfmt_machi_a.f | |
4799 | int UNUSED written = abuf->written; | |
4800 | IADDR UNUSED pc = abuf->addr; | |
4801 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4802 | ||
4803 | SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); | |
4804 | ||
4805 | #undef OPRND | |
4806 | #undef FLD | |
4807 | } | |
4808 | NEXT (vpc); | |
4809 | ||
4810 | CASE (sem, INSN_PAR_MACWLO_A) : /* macwlo $src1,$src2,$acc */ | |
4811 | { | |
4812 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4813 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4814 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4815 | #define OPRND(f) par_exec->operands.sfmt_machi_a.f | |
4816 | int UNUSED written = 0; | |
4817 | IADDR UNUSED pc = abuf->addr; | |
4818 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4819 | ||
4820 | { | |
4821 | DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))); | |
4822 | OPRND (acc) = opval; | |
4823 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
4824 | } | |
4825 | ||
4826 | #undef OPRND | |
4827 | #undef FLD | |
4828 | } | |
4829 | NEXT (vpc); | |
4830 | ||
4831 | CASE (sem, INSN_WRITE_MACWLO_A) : /* macwlo $src1,$src2,$acc */ | |
4832 | { | |
4833 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4834 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4835 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4836 | #define OPRND(f) par_exec->operands.sfmt_machi_a.f | |
4837 | int UNUSED written = abuf->written; | |
4838 | IADDR UNUSED pc = abuf->addr; | |
4839 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4840 | ||
4841 | SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); | |
4842 | ||
4843 | #undef OPRND | |
4844 | #undef FLD | |
4845 | } | |
4846 | NEXT (vpc); | |
4847 | ||
4848 | CASE (sem, INSN_PAR_MUL) : /* mul $dr,$sr */ | |
4849 | { | |
4850 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4851 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4852 | #define FLD(f) abuf->fields.sfmt_add.f | |
4853 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
4854 | int UNUSED written = 0; | |
4855 | IADDR UNUSED pc = abuf->addr; | |
4856 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4857 | ||
4858 | { | |
4859 | SI opval = MULSI (* FLD (i_dr), * FLD (i_sr)); | |
4860 | OPRND (dr) = opval; | |
4861 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
4862 | } | |
4863 | ||
4864 | #undef OPRND | |
4865 | #undef FLD | |
4866 | } | |
4867 | NEXT (vpc); | |
4868 | ||
4869 | CASE (sem, INSN_WRITE_MUL) : /* mul $dr,$sr */ | |
4870 | { | |
4871 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4872 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4873 | #define FLD(f) abuf->fields.sfmt_add.f | |
4874 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
4875 | int UNUSED written = abuf->written; | |
4876 | IADDR UNUSED pc = abuf->addr; | |
4877 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4878 | ||
4879 | * FLD (i_dr) = OPRND (dr); | |
4880 | ||
4881 | #undef OPRND | |
4882 | #undef FLD | |
4883 | } | |
4884 | NEXT (vpc); | |
4885 | ||
4886 | CASE (sem, INSN_PAR_MULHI_A) : /* mulhi $src1,$src2,$acc */ | |
4887 | { | |
4888 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4889 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4890 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4891 | #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f | |
4892 | int UNUSED written = 0; | |
4893 | IADDR UNUSED pc = abuf->addr; | |
4894 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4895 | ||
4896 | { | |
4897 | DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16); | |
4898 | OPRND (acc) = opval; | |
4899 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
4900 | } | |
4901 | ||
4902 | #undef OPRND | |
4903 | #undef FLD | |
4904 | } | |
4905 | NEXT (vpc); | |
4906 | ||
4907 | CASE (sem, INSN_WRITE_MULHI_A) : /* mulhi $src1,$src2,$acc */ | |
4908 | { | |
4909 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4910 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4911 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4912 | #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f | |
4913 | int UNUSED written = abuf->written; | |
4914 | IADDR UNUSED pc = abuf->addr; | |
4915 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4916 | ||
4917 | SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); | |
4918 | ||
4919 | #undef OPRND | |
4920 | #undef FLD | |
4921 | } | |
4922 | NEXT (vpc); | |
4923 | ||
4924 | CASE (sem, INSN_PAR_MULLO_A) : /* mullo $src1,$src2,$acc */ | |
4925 | { | |
4926 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4927 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4928 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4929 | #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f | |
4930 | int UNUSED written = 0; | |
4931 | IADDR UNUSED pc = abuf->addr; | |
4932 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4933 | ||
4934 | { | |
4935 | DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16); | |
4936 | OPRND (acc) = opval; | |
4937 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
4938 | } | |
4939 | ||
4940 | #undef OPRND | |
4941 | #undef FLD | |
4942 | } | |
4943 | NEXT (vpc); | |
4944 | ||
4945 | CASE (sem, INSN_WRITE_MULLO_A) : /* mullo $src1,$src2,$acc */ | |
4946 | { | |
4947 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4948 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4949 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4950 | #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f | |
4951 | int UNUSED written = abuf->written; | |
4952 | IADDR UNUSED pc = abuf->addr; | |
4953 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4954 | ||
4955 | SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); | |
4956 | ||
4957 | #undef OPRND | |
4958 | #undef FLD | |
4959 | } | |
4960 | NEXT (vpc); | |
4961 | ||
4962 | CASE (sem, INSN_PAR_MULWHI_A) : /* mulwhi $src1,$src2,$acc */ | |
4963 | { | |
4964 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4965 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
4966 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4967 | #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f | |
4968 | int UNUSED written = 0; | |
4969 | IADDR UNUSED pc = abuf->addr; | |
4970 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
4971 | ||
4972 | { | |
4973 | DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))); | |
4974 | OPRND (acc) = opval; | |
4975 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
4976 | } | |
4977 | ||
4978 | #undef OPRND | |
4979 | #undef FLD | |
4980 | } | |
4981 | NEXT (vpc); | |
4982 | ||
4983 | CASE (sem, INSN_WRITE_MULWHI_A) : /* mulwhi $src1,$src2,$acc */ | |
4984 | { | |
4985 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
4986 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
4987 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
4988 | #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f | |
4989 | int UNUSED written = abuf->written; | |
4990 | IADDR UNUSED pc = abuf->addr; | |
4991 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
4992 | ||
4993 | SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); | |
4994 | ||
4995 | #undef OPRND | |
4996 | #undef FLD | |
4997 | } | |
4998 | NEXT (vpc); | |
4999 | ||
5000 | CASE (sem, INSN_PAR_MULWLO_A) : /* mulwlo $src1,$src2,$acc */ | |
5001 | { | |
5002 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5003 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5004 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
5005 | #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f | |
5006 | int UNUSED written = 0; | |
5007 | IADDR UNUSED pc = abuf->addr; | |
5008 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5009 | ||
5010 | { | |
5011 | DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))); | |
5012 | OPRND (acc) = opval; | |
5013 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
5014 | } | |
5015 | ||
5016 | #undef OPRND | |
5017 | #undef FLD | |
5018 | } | |
5019 | NEXT (vpc); | |
5020 | ||
5021 | CASE (sem, INSN_WRITE_MULWLO_A) : /* mulwlo $src1,$src2,$acc */ | |
5022 | { | |
5023 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5024 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5025 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
5026 | #define OPRND(f) par_exec->operands.sfmt_mulhi_a.f | |
5027 | int UNUSED written = abuf->written; | |
5028 | IADDR UNUSED pc = abuf->addr; | |
5029 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5030 | ||
5031 | SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); | |
5032 | ||
5033 | #undef OPRND | |
5034 | #undef FLD | |
5035 | } | |
5036 | NEXT (vpc); | |
5037 | ||
5038 | CASE (sem, INSN_PAR_MV) : /* mv $dr,$sr */ | |
5039 | { | |
5040 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5041 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5042 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
5043 | #define OPRND(f) par_exec->operands.sfmt_mv.f | |
5044 | int UNUSED written = 0; | |
5045 | IADDR UNUSED pc = abuf->addr; | |
5046 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5047 | ||
5048 | { | |
5049 | SI opval = * FLD (i_sr); | |
5050 | OPRND (dr) = opval; | |
5051 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5052 | } | |
5053 | ||
5054 | #undef OPRND | |
5055 | #undef FLD | |
5056 | } | |
5057 | NEXT (vpc); | |
5058 | ||
5059 | CASE (sem, INSN_WRITE_MV) : /* mv $dr,$sr */ | |
5060 | { | |
5061 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5062 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5063 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
5064 | #define OPRND(f) par_exec->operands.sfmt_mv.f | |
5065 | int UNUSED written = abuf->written; | |
5066 | IADDR UNUSED pc = abuf->addr; | |
5067 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5068 | ||
5069 | * FLD (i_dr) = OPRND (dr); | |
5070 | ||
5071 | #undef OPRND | |
5072 | #undef FLD | |
5073 | } | |
5074 | NEXT (vpc); | |
5075 | ||
5076 | CASE (sem, INSN_PAR_MVFACHI_A) : /* mvfachi $dr,$accs */ | |
5077 | { | |
5078 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5079 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5080 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f | |
5081 | #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f | |
5082 | int UNUSED written = 0; | |
5083 | IADDR UNUSED pc = abuf->addr; | |
5084 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5085 | ||
5086 | { | |
5087 | SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32)); | |
5088 | OPRND (dr) = opval; | |
5089 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5090 | } | |
5091 | ||
5092 | #undef OPRND | |
5093 | #undef FLD | |
5094 | } | |
5095 | NEXT (vpc); | |
5096 | ||
5097 | CASE (sem, INSN_WRITE_MVFACHI_A) : /* mvfachi $dr,$accs */ | |
5098 | { | |
5099 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5100 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5101 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f | |
5102 | #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f | |
5103 | int UNUSED written = abuf->written; | |
5104 | IADDR UNUSED pc = abuf->addr; | |
5105 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5106 | ||
5107 | * FLD (i_dr) = OPRND (dr); | |
5108 | ||
5109 | #undef OPRND | |
5110 | #undef FLD | |
5111 | } | |
5112 | NEXT (vpc); | |
5113 | ||
5114 | CASE (sem, INSN_PAR_MVFACLO_A) : /* mvfaclo $dr,$accs */ | |
5115 | { | |
5116 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5117 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5118 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f | |
5119 | #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f | |
5120 | int UNUSED written = 0; | |
5121 | IADDR UNUSED pc = abuf->addr; | |
5122 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5123 | ||
5124 | { | |
5125 | SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs))); | |
5126 | OPRND (dr) = opval; | |
5127 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5128 | } | |
5129 | ||
5130 | #undef OPRND | |
5131 | #undef FLD | |
5132 | } | |
5133 | NEXT (vpc); | |
5134 | ||
5135 | CASE (sem, INSN_WRITE_MVFACLO_A) : /* mvfaclo $dr,$accs */ | |
5136 | { | |
5137 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5138 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5139 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f | |
5140 | #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f | |
5141 | int UNUSED written = abuf->written; | |
5142 | IADDR UNUSED pc = abuf->addr; | |
5143 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5144 | ||
5145 | * FLD (i_dr) = OPRND (dr); | |
5146 | ||
5147 | #undef OPRND | |
5148 | #undef FLD | |
5149 | } | |
5150 | NEXT (vpc); | |
5151 | ||
5152 | CASE (sem, INSN_PAR_MVFACMI_A) : /* mvfacmi $dr,$accs */ | |
5153 | { | |
5154 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5155 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5156 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f | |
5157 | #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f | |
5158 | int UNUSED written = 0; | |
5159 | IADDR UNUSED pc = abuf->addr; | |
5160 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5161 | ||
5162 | { | |
5163 | SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16)); | |
5164 | OPRND (dr) = opval; | |
5165 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5166 | } | |
5167 | ||
5168 | #undef OPRND | |
5169 | #undef FLD | |
5170 | } | |
5171 | NEXT (vpc); | |
5172 | ||
5173 | CASE (sem, INSN_WRITE_MVFACMI_A) : /* mvfacmi $dr,$accs */ | |
5174 | { | |
5175 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5176 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5177 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f | |
5178 | #define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f | |
5179 | int UNUSED written = abuf->written; | |
5180 | IADDR UNUSED pc = abuf->addr; | |
5181 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5182 | ||
5183 | * FLD (i_dr) = OPRND (dr); | |
5184 | ||
5185 | #undef OPRND | |
5186 | #undef FLD | |
5187 | } | |
5188 | NEXT (vpc); | |
5189 | ||
5190 | CASE (sem, INSN_PAR_MVFC) : /* mvfc $dr,$scr */ | |
5191 | { | |
5192 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5193 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5194 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
5195 | #define OPRND(f) par_exec->operands.sfmt_mvfc.f | |
5196 | int UNUSED written = 0; | |
5197 | IADDR UNUSED pc = abuf->addr; | |
5198 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5199 | ||
5200 | { | |
5201 | SI opval = GET_H_CR (FLD (f_r2)); | |
5202 | OPRND (dr) = opval; | |
5203 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5204 | } | |
5205 | ||
5206 | #undef OPRND | |
5207 | #undef FLD | |
5208 | } | |
5209 | NEXT (vpc); | |
5210 | ||
5211 | CASE (sem, INSN_WRITE_MVFC) : /* mvfc $dr,$scr */ | |
5212 | { | |
5213 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5214 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5215 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
5216 | #define OPRND(f) par_exec->operands.sfmt_mvfc.f | |
5217 | int UNUSED written = abuf->written; | |
5218 | IADDR UNUSED pc = abuf->addr; | |
5219 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5220 | ||
5221 | * FLD (i_dr) = OPRND (dr); | |
5222 | ||
5223 | #undef OPRND | |
5224 | #undef FLD | |
5225 | } | |
5226 | NEXT (vpc); | |
5227 | ||
5228 | CASE (sem, INSN_PAR_MVTACHI_A) : /* mvtachi $src1,$accs */ | |
5229 | { | |
5230 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5231 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5232 | #define FLD(f) abuf->fields.sfmt_mvtachi_a.f | |
5233 | #define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f | |
5234 | int UNUSED written = 0; | |
5235 | IADDR UNUSED pc = abuf->addr; | |
5236 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5237 | ||
5238 | { | |
5239 | DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32)); | |
5240 | OPRND (accs) = opval; | |
5241 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
5242 | } | |
5243 | ||
5244 | #undef OPRND | |
5245 | #undef FLD | |
5246 | } | |
5247 | NEXT (vpc); | |
5248 | ||
5249 | CASE (sem, INSN_WRITE_MVTACHI_A) : /* mvtachi $src1,$accs */ | |
5250 | { | |
5251 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5252 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5253 | #define FLD(f) abuf->fields.sfmt_mvtachi_a.f | |
5254 | #define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f | |
5255 | int UNUSED written = abuf->written; | |
5256 | IADDR UNUSED pc = abuf->addr; | |
5257 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5258 | ||
5259 | SET_H_ACCUMS (FLD (f_accs), OPRND (accs)); | |
5260 | ||
5261 | #undef OPRND | |
5262 | #undef FLD | |
5263 | } | |
5264 | NEXT (vpc); | |
5265 | ||
5266 | CASE (sem, INSN_PAR_MVTACLO_A) : /* mvtaclo $src1,$accs */ | |
5267 | { | |
5268 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5269 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5270 | #define FLD(f) abuf->fields.sfmt_mvtachi_a.f | |
5271 | #define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f | |
5272 | int UNUSED written = 0; | |
5273 | IADDR UNUSED pc = abuf->addr; | |
5274 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5275 | ||
5276 | { | |
5277 | DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1))); | |
5278 | OPRND (accs) = opval; | |
5279 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
5280 | } | |
5281 | ||
5282 | #undef OPRND | |
5283 | #undef FLD | |
5284 | } | |
5285 | NEXT (vpc); | |
5286 | ||
5287 | CASE (sem, INSN_WRITE_MVTACLO_A) : /* mvtaclo $src1,$accs */ | |
5288 | { | |
5289 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5290 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5291 | #define FLD(f) abuf->fields.sfmt_mvtachi_a.f | |
5292 | #define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f | |
5293 | int UNUSED written = abuf->written; | |
5294 | IADDR UNUSED pc = abuf->addr; | |
5295 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5296 | ||
5297 | SET_H_ACCUMS (FLD (f_accs), OPRND (accs)); | |
5298 | ||
5299 | #undef OPRND | |
5300 | #undef FLD | |
5301 | } | |
5302 | NEXT (vpc); | |
5303 | ||
5304 | CASE (sem, INSN_PAR_MVTC) : /* mvtc $sr,$dcr */ | |
5305 | { | |
5306 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5307 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5308 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
5309 | #define OPRND(f) par_exec->operands.sfmt_mvtc.f | |
5310 | int UNUSED written = 0; | |
5311 | IADDR UNUSED pc = abuf->addr; | |
5312 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5313 | ||
5314 | { | |
5315 | USI opval = * FLD (i_sr); | |
5316 | OPRND (dcr) = opval; | |
5317 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
5318 | } | |
5319 | ||
5320 | #undef OPRND | |
5321 | #undef FLD | |
5322 | } | |
5323 | NEXT (vpc); | |
5324 | ||
5325 | CASE (sem, INSN_WRITE_MVTC) : /* mvtc $sr,$dcr */ | |
5326 | { | |
5327 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5328 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5329 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
5330 | #define OPRND(f) par_exec->operands.sfmt_mvtc.f | |
5331 | int UNUSED written = abuf->written; | |
5332 | IADDR UNUSED pc = abuf->addr; | |
5333 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5334 | ||
5335 | SET_H_CR (FLD (f_r1), OPRND (dcr)); | |
5336 | ||
5337 | #undef OPRND | |
5338 | #undef FLD | |
5339 | } | |
5340 | NEXT (vpc); | |
5341 | ||
5342 | CASE (sem, INSN_PAR_NEG) : /* neg $dr,$sr */ | |
5343 | { | |
5344 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5345 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5346 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
5347 | #define OPRND(f) par_exec->operands.sfmt_mv.f | |
5348 | int UNUSED written = 0; | |
5349 | IADDR UNUSED pc = abuf->addr; | |
5350 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5351 | ||
5352 | { | |
5353 | SI opval = NEGSI (* FLD (i_sr)); | |
5354 | OPRND (dr) = opval; | |
5355 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5356 | } | |
5357 | ||
5358 | #undef OPRND | |
5359 | #undef FLD | |
5360 | } | |
5361 | NEXT (vpc); | |
5362 | ||
5363 | CASE (sem, INSN_WRITE_NEG) : /* neg $dr,$sr */ | |
5364 | { | |
5365 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5366 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5367 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
5368 | #define OPRND(f) par_exec->operands.sfmt_mv.f | |
5369 | int UNUSED written = abuf->written; | |
5370 | IADDR UNUSED pc = abuf->addr; | |
5371 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5372 | ||
5373 | * FLD (i_dr) = OPRND (dr); | |
5374 | ||
5375 | #undef OPRND | |
5376 | #undef FLD | |
5377 | } | |
5378 | NEXT (vpc); | |
5379 | ||
5380 | CASE (sem, INSN_PAR_NOP) : /* nop */ | |
5381 | { | |
5382 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5383 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 5384 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
5385 | #define OPRND(f) par_exec->operands.sfmt_nop.f |
5386 | int UNUSED written = 0; | |
5387 | IADDR UNUSED pc = abuf->addr; | |
5388 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5389 | ||
5390 | PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); | |
5391 | ||
5392 | #undef OPRND | |
5393 | #undef FLD | |
5394 | } | |
5395 | NEXT (vpc); | |
5396 | ||
5397 | CASE (sem, INSN_WRITE_NOP) : /* nop */ | |
5398 | { | |
5399 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5400 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
2310652a | 5401 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
5402 | #define OPRND(f) par_exec->operands.sfmt_nop.f |
5403 | int UNUSED written = abuf->written; | |
5404 | IADDR UNUSED pc = abuf->addr; | |
5405 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5406 | ||
5407 | ||
5408 | #undef OPRND | |
5409 | #undef FLD | |
5410 | } | |
5411 | NEXT (vpc); | |
5412 | ||
5413 | CASE (sem, INSN_PAR_NOT) : /* not $dr,$sr */ | |
5414 | { | |
5415 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5416 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5417 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
5418 | #define OPRND(f) par_exec->operands.sfmt_mv.f | |
5419 | int UNUSED written = 0; | |
5420 | IADDR UNUSED pc = abuf->addr; | |
5421 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5422 | ||
5423 | { | |
5424 | SI opval = INVSI (* FLD (i_sr)); | |
5425 | OPRND (dr) = opval; | |
5426 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5427 | } | |
5428 | ||
5429 | #undef OPRND | |
5430 | #undef FLD | |
5431 | } | |
5432 | NEXT (vpc); | |
5433 | ||
5434 | CASE (sem, INSN_WRITE_NOT) : /* not $dr,$sr */ | |
5435 | { | |
5436 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5437 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5438 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
5439 | #define OPRND(f) par_exec->operands.sfmt_mv.f | |
5440 | int UNUSED written = abuf->written; | |
5441 | IADDR UNUSED pc = abuf->addr; | |
5442 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5443 | ||
5444 | * FLD (i_dr) = OPRND (dr); | |
5445 | ||
5446 | #undef OPRND | |
5447 | #undef FLD | |
5448 | } | |
5449 | NEXT (vpc); | |
5450 | ||
5451 | CASE (sem, INSN_PAR_RAC_DSI) : /* rac $accd,$accs,$imm1 */ | |
5452 | { | |
5453 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5454 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5455 | #define FLD(f) abuf->fields.sfmt_rac_dsi.f | |
5456 | #define OPRND(f) par_exec->operands.sfmt_rac_dsi.f | |
5457 | int UNUSED written = 0; | |
5458 | IADDR UNUSED pc = abuf->addr; | |
5459 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5460 | ||
5461 | { | |
5462 | DI tmp_tmp1; | |
5463 | tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); | |
5464 | tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); | |
5465 | { | |
5466 | DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))); | |
5467 | OPRND (accd) = opval; | |
5468 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
5469 | } | |
5470 | } | |
5471 | ||
5472 | #undef OPRND | |
5473 | #undef FLD | |
5474 | } | |
5475 | NEXT (vpc); | |
5476 | ||
5477 | CASE (sem, INSN_WRITE_RAC_DSI) : /* rac $accd,$accs,$imm1 */ | |
5478 | { | |
5479 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5480 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5481 | #define FLD(f) abuf->fields.sfmt_rac_dsi.f | |
5482 | #define OPRND(f) par_exec->operands.sfmt_rac_dsi.f | |
5483 | int UNUSED written = abuf->written; | |
5484 | IADDR UNUSED pc = abuf->addr; | |
5485 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5486 | ||
5487 | SET_H_ACCUMS (FLD (f_accd), OPRND (accd)); | |
5488 | ||
5489 | #undef OPRND | |
5490 | #undef FLD | |
5491 | } | |
5492 | NEXT (vpc); | |
5493 | ||
5494 | CASE (sem, INSN_PAR_RACH_DSI) : /* rach $accd,$accs,$imm1 */ | |
5495 | { | |
5496 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5497 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5498 | #define FLD(f) abuf->fields.sfmt_rac_dsi.f | |
5499 | #define OPRND(f) par_exec->operands.sfmt_rac_dsi.f | |
5500 | int UNUSED written = 0; | |
5501 | IADDR UNUSED pc = abuf->addr; | |
5502 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5503 | ||
5504 | { | |
5505 | DI tmp_tmp1; | |
5506 | tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); | |
5507 | tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000)); | |
5508 | { | |
5509 | DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0))); | |
5510 | OPRND (accd) = opval; | |
5511 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
5512 | } | |
5513 | } | |
5514 | ||
5515 | #undef OPRND | |
5516 | #undef FLD | |
5517 | } | |
5518 | NEXT (vpc); | |
5519 | ||
5520 | CASE (sem, INSN_WRITE_RACH_DSI) : /* rach $accd,$accs,$imm1 */ | |
5521 | { | |
5522 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5523 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5524 | #define FLD(f) abuf->fields.sfmt_rac_dsi.f | |
5525 | #define OPRND(f) par_exec->operands.sfmt_rac_dsi.f | |
5526 | int UNUSED written = abuf->written; | |
5527 | IADDR UNUSED pc = abuf->addr; | |
5528 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5529 | ||
5530 | SET_H_ACCUMS (FLD (f_accd), OPRND (accd)); | |
5531 | ||
5532 | #undef OPRND | |
5533 | #undef FLD | |
5534 | } | |
5535 | NEXT (vpc); | |
5536 | ||
5537 | CASE (sem, INSN_PAR_RTE) : /* rte */ | |
5538 | { | |
5539 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5540 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 5541 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
5542 | #define OPRND(f) par_exec->operands.sfmt_rte.f |
5543 | int UNUSED written = 0; | |
5544 | IADDR UNUSED pc = abuf->addr; | |
5545 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5546 | ||
5547 | { | |
5548 | { | |
5549 | USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4); | |
5550 | OPRND (pc) = opval; | |
5551 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
5552 | } | |
5553 | { | |
5554 | USI opval = GET_H_CR (((UINT) 14)); | |
5555 | OPRND (h_cr_USI_6) = opval; | |
5556 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
5557 | } | |
5558 | { | |
5559 | UQI opval = CPU (h_bpsw); | |
5560 | OPRND (h_psw_UQI) = opval; | |
5561 | TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); | |
5562 | } | |
5563 | { | |
5564 | UQI opval = CPU (h_bbpsw); | |
5565 | OPRND (h_bpsw_UQI) = opval; | |
5566 | TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); | |
5567 | } | |
5568 | } | |
5569 | ||
5570 | #undef OPRND | |
5571 | #undef FLD | |
5572 | } | |
5573 | NEXT (vpc); | |
5574 | ||
5575 | CASE (sem, INSN_WRITE_RTE) : /* rte */ | |
5576 | { | |
5577 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5578 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
2310652a | 5579 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
5580 | #define OPRND(f) par_exec->operands.sfmt_rte.f |
5581 | int UNUSED written = abuf->written; | |
5582 | IADDR UNUSED pc = abuf->addr; | |
5583 | SEM_BRANCH_INIT | |
5584 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5585 | ||
5586 | CPU (h_bpsw) = OPRND (h_bpsw_UQI); | |
5587 | SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6)); | |
5588 | SET_H_PSW (OPRND (h_psw_UQI)); | |
5589 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
5590 | ||
5591 | SEM_BRANCH_FINI (vpc); | |
5592 | #undef OPRND | |
5593 | #undef FLD | |
5594 | } | |
5595 | NEXT (vpc); | |
5596 | ||
5597 | CASE (sem, INSN_PAR_SLL) : /* sll $dr,$sr */ | |
5598 | { | |
5599 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5600 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5601 | #define FLD(f) abuf->fields.sfmt_add.f | |
5602 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
5603 | int UNUSED written = 0; | |
5604 | IADDR UNUSED pc = abuf->addr; | |
5605 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5606 | ||
5607 | { | |
5608 | SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); | |
5609 | OPRND (dr) = opval; | |
5610 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5611 | } | |
5612 | ||
5613 | #undef OPRND | |
5614 | #undef FLD | |
5615 | } | |
5616 | NEXT (vpc); | |
5617 | ||
5618 | CASE (sem, INSN_WRITE_SLL) : /* sll $dr,$sr */ | |
5619 | { | |
5620 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5621 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5622 | #define FLD(f) abuf->fields.sfmt_add.f | |
5623 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
5624 | int UNUSED written = abuf->written; | |
5625 | IADDR UNUSED pc = abuf->addr; | |
5626 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5627 | ||
5628 | * FLD (i_dr) = OPRND (dr); | |
5629 | ||
5630 | #undef OPRND | |
5631 | #undef FLD | |
5632 | } | |
5633 | NEXT (vpc); | |
5634 | ||
5635 | CASE (sem, INSN_PAR_SLLI) : /* slli $dr,$uimm5 */ | |
5636 | { | |
5637 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5638 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5639 | #define FLD(f) abuf->fields.sfmt_slli.f | |
5640 | #define OPRND(f) par_exec->operands.sfmt_slli.f | |
5641 | int UNUSED written = 0; | |
5642 | IADDR UNUSED pc = abuf->addr; | |
5643 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5644 | ||
5645 | { | |
5646 | SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5)); | |
5647 | OPRND (dr) = opval; | |
5648 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5649 | } | |
5650 | ||
5651 | #undef OPRND | |
5652 | #undef FLD | |
5653 | } | |
5654 | NEXT (vpc); | |
5655 | ||
5656 | CASE (sem, INSN_WRITE_SLLI) : /* slli $dr,$uimm5 */ | |
5657 | { | |
5658 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5659 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5660 | #define FLD(f) abuf->fields.sfmt_slli.f | |
5661 | #define OPRND(f) par_exec->operands.sfmt_slli.f | |
5662 | int UNUSED written = abuf->written; | |
5663 | IADDR UNUSED pc = abuf->addr; | |
5664 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5665 | ||
5666 | * FLD (i_dr) = OPRND (dr); | |
5667 | ||
5668 | #undef OPRND | |
5669 | #undef FLD | |
5670 | } | |
5671 | NEXT (vpc); | |
5672 | ||
5673 | CASE (sem, INSN_PAR_SRA) : /* sra $dr,$sr */ | |
5674 | { | |
5675 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5676 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5677 | #define FLD(f) abuf->fields.sfmt_add.f | |
5678 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
5679 | int UNUSED written = 0; | |
5680 | IADDR UNUSED pc = abuf->addr; | |
5681 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5682 | ||
5683 | { | |
5684 | SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); | |
5685 | OPRND (dr) = opval; | |
5686 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5687 | } | |
5688 | ||
5689 | #undef OPRND | |
5690 | #undef FLD | |
5691 | } | |
5692 | NEXT (vpc); | |
5693 | ||
5694 | CASE (sem, INSN_WRITE_SRA) : /* sra $dr,$sr */ | |
5695 | { | |
5696 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5697 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5698 | #define FLD(f) abuf->fields.sfmt_add.f | |
5699 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
5700 | int UNUSED written = abuf->written; | |
5701 | IADDR UNUSED pc = abuf->addr; | |
5702 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5703 | ||
5704 | * FLD (i_dr) = OPRND (dr); | |
5705 | ||
5706 | #undef OPRND | |
5707 | #undef FLD | |
5708 | } | |
5709 | NEXT (vpc); | |
5710 | ||
5711 | CASE (sem, INSN_PAR_SRAI) : /* srai $dr,$uimm5 */ | |
5712 | { | |
5713 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5714 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5715 | #define FLD(f) abuf->fields.sfmt_slli.f | |
5716 | #define OPRND(f) par_exec->operands.sfmt_slli.f | |
5717 | int UNUSED written = 0; | |
5718 | IADDR UNUSED pc = abuf->addr; | |
5719 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5720 | ||
5721 | { | |
5722 | SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5)); | |
5723 | OPRND (dr) = opval; | |
5724 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5725 | } | |
5726 | ||
5727 | #undef OPRND | |
5728 | #undef FLD | |
5729 | } | |
5730 | NEXT (vpc); | |
5731 | ||
5732 | CASE (sem, INSN_WRITE_SRAI) : /* srai $dr,$uimm5 */ | |
5733 | { | |
5734 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5735 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5736 | #define FLD(f) abuf->fields.sfmt_slli.f | |
5737 | #define OPRND(f) par_exec->operands.sfmt_slli.f | |
5738 | int UNUSED written = abuf->written; | |
5739 | IADDR UNUSED pc = abuf->addr; | |
5740 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5741 | ||
5742 | * FLD (i_dr) = OPRND (dr); | |
5743 | ||
5744 | #undef OPRND | |
5745 | #undef FLD | |
5746 | } | |
5747 | NEXT (vpc); | |
5748 | ||
5749 | CASE (sem, INSN_PAR_SRL) : /* srl $dr,$sr */ | |
5750 | { | |
5751 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5752 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5753 | #define FLD(f) abuf->fields.sfmt_add.f | |
5754 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
5755 | int UNUSED written = 0; | |
5756 | IADDR UNUSED pc = abuf->addr; | |
5757 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5758 | ||
5759 | { | |
5760 | SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); | |
5761 | OPRND (dr) = opval; | |
5762 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5763 | } | |
5764 | ||
5765 | #undef OPRND | |
5766 | #undef FLD | |
5767 | } | |
5768 | NEXT (vpc); | |
5769 | ||
5770 | CASE (sem, INSN_WRITE_SRL) : /* srl $dr,$sr */ | |
5771 | { | |
5772 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5773 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5774 | #define FLD(f) abuf->fields.sfmt_add.f | |
5775 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
5776 | int UNUSED written = abuf->written; | |
5777 | IADDR UNUSED pc = abuf->addr; | |
5778 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5779 | ||
5780 | * FLD (i_dr) = OPRND (dr); | |
5781 | ||
5782 | #undef OPRND | |
5783 | #undef FLD | |
5784 | } | |
5785 | NEXT (vpc); | |
5786 | ||
5787 | CASE (sem, INSN_PAR_SRLI) : /* srli $dr,$uimm5 */ | |
5788 | { | |
5789 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5790 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5791 | #define FLD(f) abuf->fields.sfmt_slli.f | |
5792 | #define OPRND(f) par_exec->operands.sfmt_slli.f | |
5793 | int UNUSED written = 0; | |
5794 | IADDR UNUSED pc = abuf->addr; | |
5795 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5796 | ||
5797 | { | |
5798 | SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5)); | |
5799 | OPRND (dr) = opval; | |
5800 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5801 | } | |
5802 | ||
5803 | #undef OPRND | |
5804 | #undef FLD | |
5805 | } | |
5806 | NEXT (vpc); | |
5807 | ||
5808 | CASE (sem, INSN_WRITE_SRLI) : /* srli $dr,$uimm5 */ | |
5809 | { | |
5810 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5811 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5812 | #define FLD(f) abuf->fields.sfmt_slli.f | |
5813 | #define OPRND(f) par_exec->operands.sfmt_slli.f | |
5814 | int UNUSED written = abuf->written; | |
5815 | IADDR UNUSED pc = abuf->addr; | |
5816 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5817 | ||
5818 | * FLD (i_dr) = OPRND (dr); | |
5819 | ||
5820 | #undef OPRND | |
5821 | #undef FLD | |
5822 | } | |
5823 | NEXT (vpc); | |
5824 | ||
5825 | CASE (sem, INSN_PAR_ST) : /* st $src1,@$src2 */ | |
5826 | { | |
5827 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5828 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5829 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
5830 | #define OPRND(f) par_exec->operands.sfmt_st.f | |
5831 | int UNUSED written = 0; | |
5832 | IADDR UNUSED pc = abuf->addr; | |
5833 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5834 | ||
5835 | { | |
5836 | SI opval = * FLD (i_src1); | |
5837 | OPRND (h_memory_SI_src2_idx) = * FLD (i_src2); | |
5838 | OPRND (h_memory_SI_src2) = opval; | |
5839 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
5840 | } | |
5841 | ||
5842 | #undef OPRND | |
5843 | #undef FLD | |
5844 | } | |
5845 | NEXT (vpc); | |
5846 | ||
5847 | CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */ | |
5848 | { | |
5849 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5850 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5851 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
5852 | #define OPRND(f) par_exec->operands.sfmt_st.f | |
5853 | int UNUSED written = abuf->written; | |
5854 | IADDR UNUSED pc = abuf->addr; | |
5855 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5856 | ||
5857 | SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2)); | |
5858 | ||
5859 | #undef OPRND | |
5860 | #undef FLD | |
5861 | } | |
5862 | NEXT (vpc); | |
5863 | ||
5864 | CASE (sem, INSN_PAR_STB) : /* stb $src1,@$src2 */ | |
5865 | { | |
5866 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5867 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5868 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
5869 | #define OPRND(f) par_exec->operands.sfmt_stb.f | |
5870 | int UNUSED written = 0; | |
5871 | IADDR UNUSED pc = abuf->addr; | |
5872 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5873 | ||
5874 | { | |
5875 | QI opval = * FLD (i_src1); | |
5876 | OPRND (h_memory_QI_src2_idx) = * FLD (i_src2); | |
5877 | OPRND (h_memory_QI_src2) = opval; | |
5878 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
5879 | } | |
5880 | ||
5881 | #undef OPRND | |
5882 | #undef FLD | |
5883 | } | |
5884 | NEXT (vpc); | |
5885 | ||
5886 | CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */ | |
5887 | { | |
5888 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5889 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5890 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
5891 | #define OPRND(f) par_exec->operands.sfmt_stb.f | |
5892 | int UNUSED written = abuf->written; | |
5893 | IADDR UNUSED pc = abuf->addr; | |
5894 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5895 | ||
5896 | SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_src2_idx), OPRND (h_memory_QI_src2)); | |
5897 | ||
5898 | #undef OPRND | |
5899 | #undef FLD | |
5900 | } | |
5901 | NEXT (vpc); | |
5902 | ||
5903 | CASE (sem, INSN_PAR_STH) : /* sth $src1,@$src2 */ | |
5904 | { | |
5905 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5906 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5907 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
5908 | #define OPRND(f) par_exec->operands.sfmt_sth.f | |
5909 | int UNUSED written = 0; | |
5910 | IADDR UNUSED pc = abuf->addr; | |
5911 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5912 | ||
5913 | { | |
5914 | HI opval = * FLD (i_src1); | |
5915 | OPRND (h_memory_HI_src2_idx) = * FLD (i_src2); | |
5916 | OPRND (h_memory_HI_src2) = opval; | |
5917 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
5918 | } | |
5919 | ||
5920 | #undef OPRND | |
5921 | #undef FLD | |
5922 | } | |
5923 | NEXT (vpc); | |
5924 | ||
5925 | CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */ | |
5926 | { | |
5927 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5928 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5929 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
5930 | #define OPRND(f) par_exec->operands.sfmt_sth.f | |
5931 | int UNUSED written = abuf->written; | |
5932 | IADDR UNUSED pc = abuf->addr; | |
5933 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5934 | ||
5935 | SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_src2_idx), OPRND (h_memory_HI_src2)); | |
5936 | ||
5937 | #undef OPRND | |
5938 | #undef FLD | |
5939 | } | |
5940 | NEXT (vpc); | |
5941 | ||
5942 | CASE (sem, INSN_PAR_ST_PLUS) : /* st $src1,@+$src2 */ | |
5943 | { | |
5944 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5945 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5946 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
5947 | #define OPRND(f) par_exec->operands.sfmt_st_plus.f | |
5948 | int UNUSED written = 0; | |
5949 | IADDR UNUSED pc = abuf->addr; | |
5950 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
5951 | ||
5952 | { | |
5953 | SI tmp_new_src2; | |
5954 | tmp_new_src2 = ADDSI (* FLD (i_src2), 4); | |
5955 | { | |
5956 | SI opval = * FLD (i_src1); | |
5957 | OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2; | |
5958 | OPRND (h_memory_SI_new_src2) = opval; | |
5959 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
5960 | } | |
5961 | { | |
5962 | SI opval = tmp_new_src2; | |
5963 | OPRND (src2) = opval; | |
5964 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
5965 | } | |
5966 | } | |
5967 | ||
5968 | #undef OPRND | |
5969 | #undef FLD | |
5970 | } | |
5971 | NEXT (vpc); | |
5972 | ||
5973 | CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */ | |
5974 | { | |
5975 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5976 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
5977 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
5978 | #define OPRND(f) par_exec->operands.sfmt_st_plus.f | |
5979 | int UNUSED written = abuf->written; | |
5980 | IADDR UNUSED pc = abuf->addr; | |
5981 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
5982 | ||
5983 | SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2)); | |
5984 | * FLD (i_src2) = OPRND (src2); | |
5985 | ||
5986 | #undef OPRND | |
5987 | #undef FLD | |
5988 | } | |
5989 | NEXT (vpc); | |
5990 | ||
5991 | CASE (sem, INSN_PAR_STH_PLUS) : /* sth $src1,@$src2+ */ | |
5992 | { | |
5993 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
5994 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
5995 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
5996 | #define OPRND(f) par_exec->operands.sfmt_sth_plus.f | |
5997 | int UNUSED written = 0; | |
5998 | IADDR UNUSED pc = abuf->addr; | |
5999 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6000 | ||
6001 | { | |
e9c60591 DE |
6002 | SI tmp_new_src2; |
6003 | tmp_new_src2 = * FLD (i_src2); | |
16b47b25 NC |
6004 | { |
6005 | HI opval = * FLD (i_src1); | |
6006 | OPRND (h_memory_HI_new_src2_idx) = tmp_new_src2; | |
6007 | OPRND (h_memory_HI_new_src2) = opval; | |
6008 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
6009 | } | |
16b47b25 | 6010 | { |
e9c60591 | 6011 | SI opval = ADDSI (tmp_new_src2, 2); |
16b47b25 NC |
6012 | OPRND (src2) = opval; |
6013 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
6014 | } | |
6015 | } | |
6016 | ||
6017 | #undef OPRND | |
6018 | #undef FLD | |
6019 | } | |
6020 | NEXT (vpc); | |
6021 | ||
6022 | CASE (sem, INSN_WRITE_STH_PLUS) : /* sth $src1,@$src2+ */ | |
6023 | { | |
6024 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6025 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6026 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6027 | #define OPRND(f) par_exec->operands.sfmt_sth_plus.f | |
6028 | int UNUSED written = abuf->written; | |
6029 | IADDR UNUSED pc = abuf->addr; | |
6030 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6031 | ||
6032 | SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_new_src2_idx), OPRND (h_memory_HI_new_src2)); | |
6033 | * FLD (i_src2) = OPRND (src2); | |
6034 | ||
6035 | #undef OPRND | |
6036 | #undef FLD | |
6037 | } | |
6038 | NEXT (vpc); | |
6039 | ||
6040 | CASE (sem, INSN_PAR_STB_PLUS) : /* stb $src1,@$src2+ */ | |
6041 | { | |
6042 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6043 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6044 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6045 | #define OPRND(f) par_exec->operands.sfmt_stb_plus.f | |
6046 | int UNUSED written = 0; | |
6047 | IADDR UNUSED pc = abuf->addr; | |
6048 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6049 | ||
6050 | { | |
e9c60591 DE |
6051 | SI tmp_new_src2; |
6052 | tmp_new_src2 = * FLD (i_src2); | |
16b47b25 NC |
6053 | { |
6054 | QI opval = * FLD (i_src1); | |
6055 | OPRND (h_memory_QI_new_src2_idx) = tmp_new_src2; | |
6056 | OPRND (h_memory_QI_new_src2) = opval; | |
6057 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
6058 | } | |
16b47b25 | 6059 | { |
e9c60591 | 6060 | SI opval = ADDSI (tmp_new_src2, 1); |
16b47b25 NC |
6061 | OPRND (src2) = opval; |
6062 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
6063 | } | |
6064 | } | |
6065 | ||
6066 | #undef OPRND | |
6067 | #undef FLD | |
6068 | } | |
6069 | NEXT (vpc); | |
6070 | ||
6071 | CASE (sem, INSN_WRITE_STB_PLUS) : /* stb $src1,@$src2+ */ | |
6072 | { | |
6073 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6074 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6075 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6076 | #define OPRND(f) par_exec->operands.sfmt_stb_plus.f | |
6077 | int UNUSED written = abuf->written; | |
6078 | IADDR UNUSED pc = abuf->addr; | |
6079 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6080 | ||
6081 | SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_new_src2_idx), OPRND (h_memory_QI_new_src2)); | |
6082 | * FLD (i_src2) = OPRND (src2); | |
6083 | ||
6084 | #undef OPRND | |
6085 | #undef FLD | |
6086 | } | |
6087 | NEXT (vpc); | |
6088 | ||
6089 | CASE (sem, INSN_PAR_ST_MINUS) : /* st $src1,@-$src2 */ | |
6090 | { | |
6091 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6092 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6093 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6094 | #define OPRND(f) par_exec->operands.sfmt_st_plus.f | |
6095 | int UNUSED written = 0; | |
6096 | IADDR UNUSED pc = abuf->addr; | |
6097 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6098 | ||
6099 | { | |
6100 | SI tmp_new_src2; | |
6101 | tmp_new_src2 = SUBSI (* FLD (i_src2), 4); | |
6102 | { | |
6103 | SI opval = * FLD (i_src1); | |
6104 | OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2; | |
6105 | OPRND (h_memory_SI_new_src2) = opval; | |
6106 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
6107 | } | |
6108 | { | |
6109 | SI opval = tmp_new_src2; | |
6110 | OPRND (src2) = opval; | |
6111 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
6112 | } | |
6113 | } | |
6114 | ||
6115 | #undef OPRND | |
6116 | #undef FLD | |
6117 | } | |
6118 | NEXT (vpc); | |
6119 | ||
6120 | CASE (sem, INSN_WRITE_ST_MINUS) : /* st $src1,@-$src2 */ | |
6121 | { | |
6122 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6123 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6124 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6125 | #define OPRND(f) par_exec->operands.sfmt_st_plus.f | |
6126 | int UNUSED written = abuf->written; | |
6127 | IADDR UNUSED pc = abuf->addr; | |
6128 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6129 | ||
6130 | SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2)); | |
6131 | * FLD (i_src2) = OPRND (src2); | |
6132 | ||
6133 | #undef OPRND | |
6134 | #undef FLD | |
6135 | } | |
6136 | NEXT (vpc); | |
6137 | ||
6138 | CASE (sem, INSN_PAR_SUB) : /* sub $dr,$sr */ | |
6139 | { | |
6140 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6141 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6142 | #define FLD(f) abuf->fields.sfmt_add.f | |
6143 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
6144 | int UNUSED written = 0; | |
6145 | IADDR UNUSED pc = abuf->addr; | |
6146 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6147 | ||
6148 | { | |
6149 | SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr)); | |
6150 | OPRND (dr) = opval; | |
6151 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
6152 | } | |
6153 | ||
6154 | #undef OPRND | |
6155 | #undef FLD | |
6156 | } | |
6157 | NEXT (vpc); | |
6158 | ||
6159 | CASE (sem, INSN_WRITE_SUB) : /* sub $dr,$sr */ | |
6160 | { | |
6161 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6162 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6163 | #define FLD(f) abuf->fields.sfmt_add.f | |
6164 | #define OPRND(f) par_exec->operands.sfmt_add.f | |
6165 | int UNUSED written = abuf->written; | |
6166 | IADDR UNUSED pc = abuf->addr; | |
6167 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6168 | ||
6169 | * FLD (i_dr) = OPRND (dr); | |
6170 | ||
6171 | #undef OPRND | |
6172 | #undef FLD | |
6173 | } | |
6174 | NEXT (vpc); | |
6175 | ||
6176 | CASE (sem, INSN_PAR_SUBV) : /* subv $dr,$sr */ | |
6177 | { | |
6178 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6179 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6180 | #define FLD(f) abuf->fields.sfmt_add.f | |
6181 | #define OPRND(f) par_exec->operands.sfmt_addv.f | |
6182 | int UNUSED written = 0; | |
6183 | IADDR UNUSED pc = abuf->addr; | |
6184 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6185 | ||
6186 | { | |
6187 | SI temp0;BI temp1; | |
6188 | temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr)); | |
6189 | temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0); | |
6190 | { | |
6191 | SI opval = temp0; | |
6192 | OPRND (dr) = opval; | |
6193 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
6194 | } | |
6195 | { | |
6196 | BI opval = temp1; | |
6197 | OPRND (condbit) = opval; | |
6198 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
6199 | } | |
6200 | } | |
6201 | ||
6202 | #undef OPRND | |
6203 | #undef FLD | |
6204 | } | |
6205 | NEXT (vpc); | |
6206 | ||
6207 | CASE (sem, INSN_WRITE_SUBV) : /* subv $dr,$sr */ | |
6208 | { | |
6209 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6210 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6211 | #define FLD(f) abuf->fields.sfmt_add.f | |
6212 | #define OPRND(f) par_exec->operands.sfmt_addv.f | |
6213 | int UNUSED written = abuf->written; | |
6214 | IADDR UNUSED pc = abuf->addr; | |
6215 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6216 | ||
6217 | CPU (h_cond) = OPRND (condbit); | |
6218 | * FLD (i_dr) = OPRND (dr); | |
6219 | ||
6220 | #undef OPRND | |
6221 | #undef FLD | |
6222 | } | |
6223 | NEXT (vpc); | |
6224 | ||
6225 | CASE (sem, INSN_PAR_SUBX) : /* subx $dr,$sr */ | |
6226 | { | |
6227 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6228 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6229 | #define FLD(f) abuf->fields.sfmt_add.f | |
6230 | #define OPRND(f) par_exec->operands.sfmt_addx.f | |
6231 | int UNUSED written = 0; | |
6232 | IADDR UNUSED pc = abuf->addr; | |
6233 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6234 | ||
6235 | { | |
6236 | SI temp0;BI temp1; | |
6237 | temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); | |
6238 | temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); | |
6239 | { | |
6240 | SI opval = temp0; | |
6241 | OPRND (dr) = opval; | |
6242 | TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); | |
6243 | } | |
6244 | { | |
6245 | BI opval = temp1; | |
6246 | OPRND (condbit) = opval; | |
6247 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
6248 | } | |
6249 | } | |
6250 | ||
6251 | #undef OPRND | |
6252 | #undef FLD | |
6253 | } | |
6254 | NEXT (vpc); | |
6255 | ||
6256 | CASE (sem, INSN_WRITE_SUBX) : /* subx $dr,$sr */ | |
6257 | { | |
6258 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6259 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6260 | #define FLD(f) abuf->fields.sfmt_add.f | |
6261 | #define OPRND(f) par_exec->operands.sfmt_addx.f | |
6262 | int UNUSED written = abuf->written; | |
6263 | IADDR UNUSED pc = abuf->addr; | |
6264 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6265 | ||
6266 | CPU (h_cond) = OPRND (condbit); | |
6267 | * FLD (i_dr) = OPRND (dr); | |
6268 | ||
6269 | #undef OPRND | |
6270 | #undef FLD | |
6271 | } | |
6272 | NEXT (vpc); | |
6273 | ||
6274 | CASE (sem, INSN_PAR_TRAP) : /* trap $uimm4 */ | |
6275 | { | |
6276 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6277 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6278 | #define FLD(f) abuf->fields.sfmt_trap.f | |
6279 | #define OPRND(f) par_exec->operands.sfmt_trap.f | |
6280 | int UNUSED written = 0; | |
6281 | IADDR UNUSED pc = abuf->addr; | |
6282 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6283 | ||
6284 | { | |
6285 | { | |
6286 | USI opval = GET_H_CR (((UINT) 6)); | |
6287 | OPRND (h_cr_USI_14) = opval; | |
6288 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
6289 | } | |
6290 | { | |
6291 | USI opval = ADDSI (pc, 4); | |
6292 | OPRND (h_cr_USI_6) = opval; | |
6293 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
6294 | } | |
6295 | { | |
6296 | UQI opval = CPU (h_bpsw); | |
6297 | OPRND (h_bbpsw_UQI) = opval; | |
6298 | TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval); | |
6299 | } | |
6300 | { | |
6301 | UQI opval = GET_H_PSW (); | |
6302 | OPRND (h_bpsw_UQI) = opval; | |
6303 | TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); | |
6304 | } | |
6305 | { | |
6306 | UQI opval = ANDQI (GET_H_PSW (), 128); | |
6307 | OPRND (h_psw_UQI) = opval; | |
6308 | TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); | |
6309 | } | |
6310 | { | |
6311 | SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4)); | |
6312 | OPRND (pc) = opval; | |
6313 | TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
6314 | } | |
6315 | } | |
6316 | ||
6317 | #undef OPRND | |
6318 | #undef FLD | |
6319 | } | |
6320 | NEXT (vpc); | |
6321 | ||
6322 | CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */ | |
6323 | { | |
6324 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6325 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6326 | #define FLD(f) abuf->fields.sfmt_trap.f | |
6327 | #define OPRND(f) par_exec->operands.sfmt_trap.f | |
6328 | int UNUSED written = abuf->written; | |
6329 | IADDR UNUSED pc = abuf->addr; | |
6330 | SEM_BRANCH_INIT | |
6331 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6332 | ||
6333 | CPU (h_bbpsw) = OPRND (h_bbpsw_UQI); | |
6334 | CPU (h_bpsw) = OPRND (h_bpsw_UQI); | |
6335 | SET_H_CR (((UINT) 14), OPRND (h_cr_USI_14)); | |
6336 | SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6)); | |
6337 | SET_H_PSW (OPRND (h_psw_UQI)); | |
6338 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); | |
6339 | ||
6340 | SEM_BRANCH_FINI (vpc); | |
6341 | #undef OPRND | |
6342 | #undef FLD | |
6343 | } | |
6344 | NEXT (vpc); | |
6345 | ||
6346 | CASE (sem, INSN_PAR_UNLOCK) : /* unlock $src1,@$src2 */ | |
6347 | { | |
6348 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6349 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6350 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6351 | #define OPRND(f) par_exec->operands.sfmt_unlock.f | |
6352 | int UNUSED written = 0; | |
6353 | IADDR UNUSED pc = abuf->addr; | |
6354 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6355 | ||
6356 | { | |
6357 | if (CPU (h_lock)) { | |
6358 | { | |
6359 | SI opval = * FLD (i_src1); | |
6360 | OPRND (h_memory_SI_src2_idx) = * FLD (i_src2); | |
6361 | OPRND (h_memory_SI_src2) = opval; | |
6362 | written |= (1 << 4); | |
6363 | TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
6364 | } | |
6365 | } | |
6366 | { | |
6367 | BI opval = 0; | |
6368 | OPRND (h_lock_BI) = opval; | |
6369 | TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); | |
6370 | } | |
6371 | } | |
6372 | ||
6373 | abuf->written = written; | |
6374 | #undef OPRND | |
6375 | #undef FLD | |
6376 | } | |
6377 | NEXT (vpc); | |
6378 | ||
6379 | CASE (sem, INSN_WRITE_UNLOCK) : /* unlock $src1,@$src2 */ | |
6380 | { | |
6381 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6382 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6383 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6384 | #define OPRND(f) par_exec->operands.sfmt_unlock.f | |
6385 | int UNUSED written = abuf->written; | |
6386 | IADDR UNUSED pc = abuf->addr; | |
6387 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6388 | ||
6389 | CPU (h_lock) = OPRND (h_lock_BI); | |
6390 | if (written & (1 << 4)) | |
6391 | { | |
6392 | SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2)); | |
6393 | } | |
6394 | ||
6395 | #undef OPRND | |
6396 | #undef FLD | |
6397 | } | |
6398 | NEXT (vpc); | |
6399 | ||
6400 | CASE (sem, INSN_PAR_PCMPBZ) : /* pcmpbz $src2 */ | |
6401 | { | |
6402 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6403 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6404 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6405 | #define OPRND(f) par_exec->operands.sfmt_cmpz.f | |
6406 | int UNUSED written = 0; | |
6407 | IADDR UNUSED pc = abuf->addr; | |
6408 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6409 | ||
6410 | { | |
6411 | BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0); | |
6412 | OPRND (condbit) = opval; | |
6413 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
6414 | } | |
6415 | ||
6416 | #undef OPRND | |
6417 | #undef FLD | |
6418 | } | |
6419 | NEXT (vpc); | |
6420 | ||
6421 | CASE (sem, INSN_WRITE_PCMPBZ) : /* pcmpbz $src2 */ | |
6422 | { | |
6423 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6424 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6425 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6426 | #define OPRND(f) par_exec->operands.sfmt_cmpz.f | |
6427 | int UNUSED written = abuf->written; | |
6428 | IADDR UNUSED pc = abuf->addr; | |
6429 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6430 | ||
6431 | CPU (h_cond) = OPRND (condbit); | |
6432 | ||
6433 | #undef OPRND | |
6434 | #undef FLD | |
6435 | } | |
6436 | NEXT (vpc); | |
6437 | ||
6438 | CASE (sem, INSN_PAR_SADD) : /* sadd */ | |
6439 | { | |
6440 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6441 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 6442 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
6443 | #define OPRND(f) par_exec->operands.sfmt_sadd.f |
6444 | int UNUSED written = 0; | |
6445 | IADDR UNUSED pc = abuf->addr; | |
6446 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6447 | ||
6448 | { | |
6449 | DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0))); | |
6450 | OPRND (h_accums_DI_0) = opval; | |
6451 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
6452 | } | |
6453 | ||
6454 | #undef OPRND | |
6455 | #undef FLD | |
6456 | } | |
6457 | NEXT (vpc); | |
6458 | ||
6459 | CASE (sem, INSN_WRITE_SADD) : /* sadd */ | |
6460 | { | |
6461 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6462 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
2310652a | 6463 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
6464 | #define OPRND(f) par_exec->operands.sfmt_sadd.f |
6465 | int UNUSED written = abuf->written; | |
6466 | IADDR UNUSED pc = abuf->addr; | |
6467 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6468 | ||
6469 | SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_DI_0)); | |
6470 | ||
6471 | #undef OPRND | |
6472 | #undef FLD | |
6473 | } | |
6474 | NEXT (vpc); | |
6475 | ||
6476 | CASE (sem, INSN_PAR_MACWU1) : /* macwu1 $src1,$src2 */ | |
6477 | { | |
6478 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6479 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6480 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6481 | #define OPRND(f) par_exec->operands.sfmt_macwu1.f | |
6482 | int UNUSED written = 0; | |
6483 | IADDR UNUSED pc = abuf->addr; | |
6484 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6485 | ||
6486 | { | |
6487 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8); | |
6488 | OPRND (h_accums_DI_1) = opval; | |
6489 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
6490 | } | |
6491 | ||
6492 | #undef OPRND | |
6493 | #undef FLD | |
6494 | } | |
6495 | NEXT (vpc); | |
6496 | ||
6497 | CASE (sem, INSN_WRITE_MACWU1) : /* macwu1 $src1,$src2 */ | |
6498 | { | |
6499 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6500 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6501 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6502 | #define OPRND(f) par_exec->operands.sfmt_macwu1.f | |
6503 | int UNUSED written = abuf->written; | |
6504 | IADDR UNUSED pc = abuf->addr; | |
6505 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6506 | ||
6507 | SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1)); | |
6508 | ||
6509 | #undef OPRND | |
6510 | #undef FLD | |
6511 | } | |
6512 | NEXT (vpc); | |
6513 | ||
6514 | CASE (sem, INSN_PAR_MSBLO) : /* msblo $src1,$src2 */ | |
6515 | { | |
6516 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6517 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6518 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6519 | #define OPRND(f) par_exec->operands.sfmt_msblo.f | |
6520 | int UNUSED written = 0; | |
6521 | IADDR UNUSED pc = abuf->addr; | |
6522 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6523 | ||
6524 | { | |
6525 | DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8); | |
6526 | OPRND (accum) = opval; | |
6527 | TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); | |
6528 | } | |
6529 | ||
6530 | #undef OPRND | |
6531 | #undef FLD | |
6532 | } | |
6533 | NEXT (vpc); | |
6534 | ||
6535 | CASE (sem, INSN_WRITE_MSBLO) : /* msblo $src1,$src2 */ | |
6536 | { | |
6537 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6538 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6539 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6540 | #define OPRND(f) par_exec->operands.sfmt_msblo.f | |
6541 | int UNUSED written = abuf->written; | |
6542 | IADDR UNUSED pc = abuf->addr; | |
6543 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6544 | ||
6545 | SET_H_ACCUM (OPRND (accum)); | |
6546 | ||
6547 | #undef OPRND | |
6548 | #undef FLD | |
6549 | } | |
6550 | NEXT (vpc); | |
6551 | ||
6552 | CASE (sem, INSN_PAR_MULWU1) : /* mulwu1 $src1,$src2 */ | |
6553 | { | |
6554 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6555 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6556 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6557 | #define OPRND(f) par_exec->operands.sfmt_mulwu1.f | |
6558 | int UNUSED written = 0; | |
6559 | IADDR UNUSED pc = abuf->addr; | |
6560 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6561 | ||
6562 | { | |
6563 | DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16); | |
6564 | OPRND (h_accums_DI_1) = opval; | |
6565 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
6566 | } | |
6567 | ||
6568 | #undef OPRND | |
6569 | #undef FLD | |
6570 | } | |
6571 | NEXT (vpc); | |
6572 | ||
6573 | CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */ | |
6574 | { | |
6575 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6576 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6577 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6578 | #define OPRND(f) par_exec->operands.sfmt_mulwu1.f | |
6579 | int UNUSED written = abuf->written; | |
6580 | IADDR UNUSED pc = abuf->addr; | |
6581 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6582 | ||
6583 | SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1)); | |
6584 | ||
6585 | #undef OPRND | |
6586 | #undef FLD | |
6587 | } | |
6588 | NEXT (vpc); | |
6589 | ||
6590 | CASE (sem, INSN_PAR_MACLH1) : /* maclh1 $src1,$src2 */ | |
6591 | { | |
6592 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6593 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6594 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6595 | #define OPRND(f) par_exec->operands.sfmt_macwu1.f | |
6596 | int UNUSED written = 0; | |
6597 | IADDR UNUSED pc = abuf->addr; | |
6598 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6599 | ||
6600 | { | |
6601 | DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8); | |
6602 | OPRND (h_accums_DI_1) = opval; | |
6603 | TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval); | |
6604 | } | |
6605 | ||
6606 | #undef OPRND | |
6607 | #undef FLD | |
6608 | } | |
6609 | NEXT (vpc); | |
6610 | ||
6611 | CASE (sem, INSN_WRITE_MACLH1) : /* maclh1 $src1,$src2 */ | |
6612 | { | |
6613 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6614 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6615 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
6616 | #define OPRND(f) par_exec->operands.sfmt_macwu1.f | |
6617 | int UNUSED written = abuf->written; | |
6618 | IADDR UNUSED pc = abuf->addr; | |
6619 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6620 | ||
6621 | SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1)); | |
6622 | ||
6623 | #undef OPRND | |
6624 | #undef FLD | |
6625 | } | |
6626 | NEXT (vpc); | |
6627 | ||
6628 | CASE (sem, INSN_PAR_SC) : /* sc */ | |
6629 | { | |
6630 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6631 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 6632 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
6633 | #define OPRND(f) par_exec->operands.sfmt_sc.f |
6634 | int UNUSED written = 0; | |
6635 | IADDR UNUSED pc = abuf->addr; | |
6636 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6637 | ||
6638 | if (ZEXTBISI (CPU (h_cond))) | |
6639 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
6640 | ||
6641 | #undef OPRND | |
6642 | #undef FLD | |
6643 | } | |
6644 | NEXT (vpc); | |
6645 | ||
6646 | CASE (sem, INSN_WRITE_SC) : /* sc */ | |
6647 | { | |
6648 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6649 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
2310652a | 6650 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
6651 | #define OPRND(f) par_exec->operands.sfmt_sc.f |
6652 | int UNUSED written = abuf->written; | |
6653 | IADDR UNUSED pc = abuf->addr; | |
6654 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6655 | ||
6656 | ||
6657 | #undef OPRND | |
6658 | #undef FLD | |
6659 | } | |
6660 | NEXT (vpc); | |
6661 | ||
6662 | CASE (sem, INSN_PAR_SNC) : /* snc */ | |
6663 | { | |
6664 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6665 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2310652a | 6666 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
6667 | #define OPRND(f) par_exec->operands.sfmt_sc.f |
6668 | int UNUSED written = 0; | |
6669 | IADDR UNUSED pc = abuf->addr; | |
6670 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6671 | ||
6672 | if (ZEXTBISI (NOTBI (CPU (h_cond)))) | |
6673 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
6674 | ||
6675 | #undef OPRND | |
6676 | #undef FLD | |
6677 | } | |
6678 | NEXT (vpc); | |
6679 | ||
6680 | CASE (sem, INSN_WRITE_SNC) : /* snc */ | |
6681 | { | |
6682 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6683 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
2310652a | 6684 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
6685 | #define OPRND(f) par_exec->operands.sfmt_sc.f |
6686 | int UNUSED written = abuf->written; | |
6687 | IADDR UNUSED pc = abuf->addr; | |
6688 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6689 | ||
6690 | ||
6691 | #undef OPRND | |
6692 | #undef FLD | |
6693 | } | |
6694 | NEXT (vpc); | |
6695 | ||
6696 | CASE (sem, INSN_PAR_CLRPSW) : /* clrpsw $uimm8 */ | |
6697 | { | |
6698 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6699 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6700 | #define FLD(f) abuf->fields.sfmt_clrpsw.f | |
6701 | #define OPRND(f) par_exec->operands.sfmt_clrpsw.f | |
6702 | int UNUSED written = 0; | |
6703 | IADDR UNUSED pc = abuf->addr; | |
6704 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6705 | ||
6706 | { | |
e9c60591 | 6707 | USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280)); |
16b47b25 NC |
6708 | OPRND (h_cr_USI_0) = opval; |
6709 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
6710 | } | |
6711 | ||
6712 | #undef OPRND | |
6713 | #undef FLD | |
6714 | } | |
6715 | NEXT (vpc); | |
6716 | ||
6717 | CASE (sem, INSN_WRITE_CLRPSW) : /* clrpsw $uimm8 */ | |
6718 | { | |
6719 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6720 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6721 | #define FLD(f) abuf->fields.sfmt_clrpsw.f | |
6722 | #define OPRND(f) par_exec->operands.sfmt_clrpsw.f | |
6723 | int UNUSED written = abuf->written; | |
6724 | IADDR UNUSED pc = abuf->addr; | |
6725 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6726 | ||
6727 | SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0)); | |
6728 | ||
6729 | #undef OPRND | |
6730 | #undef FLD | |
6731 | } | |
6732 | NEXT (vpc); | |
6733 | ||
6734 | CASE (sem, INSN_PAR_SETPSW) : /* setpsw $uimm8 */ | |
6735 | { | |
6736 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6737 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6738 | #define FLD(f) abuf->fields.sfmt_clrpsw.f | |
6739 | #define OPRND(f) par_exec->operands.sfmt_setpsw.f | |
6740 | int UNUSED written = 0; | |
6741 | IADDR UNUSED pc = abuf->addr; | |
6742 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6743 | ||
6744 | { | |
e9c60591 | 6745 | USI opval = FLD (f_uimm8); |
16b47b25 NC |
6746 | OPRND (h_cr_USI_0) = opval; |
6747 | TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); | |
6748 | } | |
6749 | ||
6750 | #undef OPRND | |
6751 | #undef FLD | |
6752 | } | |
6753 | NEXT (vpc); | |
6754 | ||
6755 | CASE (sem, INSN_WRITE_SETPSW) : /* setpsw $uimm8 */ | |
6756 | { | |
6757 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6758 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6759 | #define FLD(f) abuf->fields.sfmt_clrpsw.f | |
6760 | #define OPRND(f) par_exec->operands.sfmt_setpsw.f | |
6761 | int UNUSED written = abuf->written; | |
6762 | IADDR UNUSED pc = abuf->addr; | |
6763 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6764 | ||
6765 | SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0)); | |
6766 | ||
6767 | #undef OPRND | |
6768 | #undef FLD | |
6769 | } | |
6770 | NEXT (vpc); | |
6771 | ||
6772 | CASE (sem, INSN_PAR_BTST) : /* btst $uimm3,$sr */ | |
6773 | { | |
6774 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6775 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
6776 | #define FLD(f) abuf->fields.sfmt_bset.f | |
6777 | #define OPRND(f) par_exec->operands.sfmt_btst.f | |
6778 | int UNUSED written = 0; | |
6779 | IADDR UNUSED pc = abuf->addr; | |
6780 | vpc = SEM_NEXT_VPC (sem_arg, pc, 2); | |
6781 | ||
6782 | { | |
e9c60591 | 6783 | BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1); |
16b47b25 NC |
6784 | OPRND (condbit) = opval; |
6785 | TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); | |
6786 | } | |
6787 | ||
6788 | #undef OPRND | |
6789 | #undef FLD | |
6790 | } | |
6791 | NEXT (vpc); | |
6792 | ||
6793 | CASE (sem, INSN_WRITE_BTST) : /* btst $uimm3,$sr */ | |
6794 | { | |
6795 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
6796 | const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf; | |
6797 | #define FLD(f) abuf->fields.sfmt_bset.f | |
6798 | #define OPRND(f) par_exec->operands.sfmt_btst.f | |
6799 | int UNUSED written = abuf->written; | |
6800 | IADDR UNUSED pc = abuf->addr; | |
6801 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
6802 | ||
6803 | CPU (h_cond) = OPRND (condbit); | |
6804 | ||
6805 | #undef OPRND | |
6806 | #undef FLD | |
6807 | } | |
6808 | NEXT (vpc); | |
6809 | ||
6810 | ||
6811 | } | |
6812 | ENDSWITCH (sem) /* End of semantic switch. */ | |
6813 | ||
6814 | /* At this point `vpc' contains the next insn to execute. */ | |
6815 | } | |
6816 | ||
6817 | #undef DEFINE_SWITCH | |
6818 | #endif /* DEFINE_SWITCH */ |