]>
Commit | Line | Data |
---|---|---|
c906108c SS |
1 | /* m32r exception, interrupt, and trap (EIT) support |
2 | Copyright (C) 1998 Free Software Foundation, Inc. | |
3 | Contributed by Cygnus Solutions. | |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include "sim-main.h" | |
22 | #include "targ-vals.h" | |
23 | ||
24 | /* The semantic code invokes this for invalid (unrecognized) instructions. */ | |
25 | ||
26 | void | |
27 | sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia) | |
28 | { | |
29 | SIM_DESC sd = CPU_STATE (current_cpu); | |
30 | ||
31 | #if 0 | |
32 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) | |
33 | { | |
34 | h_bsm_set (current_cpu, h_sm_get (current_cpu)); | |
35 | h_bie_set (current_cpu, h_ie_get (current_cpu)); | |
36 | h_bcond_set (current_cpu, h_cond_get (current_cpu)); | |
37 | /* sm not changed */ | |
38 | h_ie_set (current_cpu, 0); | |
39 | h_cond_set (current_cpu, 0); | |
40 | ||
41 | h_bpc_set (current_cpu, cia); | |
42 | ||
43 | sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, | |
44 | EIT_RSVD_INSN_ADDR); | |
45 | } | |
46 | else | |
47 | #endif | |
48 | sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL); | |
49 | } | |
50 | ||
51 | /* Process an address exception. */ | |
52 | ||
53 | void | |
54 | m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, | |
55 | unsigned int map, int nr_bytes, address_word addr, | |
56 | transfer_type transfer, sim_core_signals sig) | |
57 | { | |
58 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) | |
59 | { | |
60 | a_m32r_h_cr_set (current_cpu, H_CR_BBPC, | |
61 | a_m32r_h_cr_get (current_cpu, H_CR_BPC)); | |
7a292a7a SS |
62 | if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R) |
63 | { | |
64 | m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu)); | |
65 | /* sm not changed */ | |
66 | m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80); | |
67 | } | |
68 | else | |
69 | { | |
70 | m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu)); | |
71 | /* sm not changed */ | |
72 | m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80); | |
73 | } | |
c906108c SS |
74 | a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia); |
75 | ||
76 | sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, | |
77 | EIT_ADDR_EXCP_ADDR); | |
78 | } | |
79 | else | |
80 | sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, | |
81 | transfer, sig); | |
82 | } | |
83 | \f | |
84 | /* Read/write functions for system call interface. */ | |
85 | ||
86 | static int | |
87 | syscall_read_mem (host_callback *cb, struct cb_syscall *sc, | |
88 | unsigned long taddr, char *buf, int bytes) | |
89 | { | |
90 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
91 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
92 | ||
93 | return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); | |
94 | } | |
95 | ||
96 | static int | |
97 | syscall_write_mem (host_callback *cb, struct cb_syscall *sc, | |
98 | unsigned long taddr, const char *buf, int bytes) | |
99 | { | |
100 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
101 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
102 | ||
103 | return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); | |
104 | } | |
105 | ||
106 | /* Trap support. | |
107 | The result is the pc address to continue at. | |
108 | Preprocessing like saving the various registers has already been done. */ | |
109 | ||
110 | USI | |
111 | m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num) | |
112 | { | |
113 | SIM_DESC sd = CPU_STATE (current_cpu); | |
114 | host_callback *cb = STATE_CALLBACK (sd); | |
115 | ||
116 | #ifdef SIM_HAVE_BREAKPOINTS | |
117 | /* Check for breakpoints "owned" by the simulator first, regardless | |
118 | of --environment. */ | |
119 | if (num == TRAP_BREAKPOINT) | |
120 | { | |
121 | /* First try sim-break.c. If it's a breakpoint the simulator "owns" | |
122 | it doesn't return. Otherwise it returns and let's us try. */ | |
123 | sim_handle_breakpoint (sd, current_cpu, pc); | |
124 | /* Fall through. */ | |
125 | } | |
126 | #endif | |
127 | ||
128 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) | |
129 | { | |
130 | /* The new pc is the trap vector entry. | |
131 | We assume there's a branch there to some handler. */ | |
132 | USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; | |
133 | return new_pc; | |
134 | } | |
135 | ||
136 | switch (num) | |
137 | { | |
138 | case TRAP_SYSCALL : | |
139 | { | |
140 | CB_SYSCALL s; | |
141 | ||
142 | CB_SYSCALL_INIT (&s); | |
143 | s.func = a_m32r_h_gr_get (current_cpu, 0); | |
144 | s.arg1 = a_m32r_h_gr_get (current_cpu, 1); | |
145 | s.arg2 = a_m32r_h_gr_get (current_cpu, 2); | |
146 | s.arg3 = a_m32r_h_gr_get (current_cpu, 3); | |
147 | ||
148 | if (s.func == TARGET_SYS_exit) | |
149 | { | |
150 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1); | |
151 | } | |
152 | ||
153 | s.p1 = (PTR) sd; | |
154 | s.p2 = (PTR) current_cpu; | |
155 | s.read_mem = syscall_read_mem; | |
156 | s.write_mem = syscall_write_mem; | |
157 | cb_syscall (cb, &s); | |
158 | a_m32r_h_gr_set (current_cpu, 2, s.errcode); | |
159 | a_m32r_h_gr_set (current_cpu, 0, s.result); | |
160 | a_m32r_h_gr_set (current_cpu, 1, s.result2); | |
161 | break; | |
162 | } | |
163 | ||
164 | case TRAP_BREAKPOINT: | |
165 | sim_engine_halt (sd, current_cpu, NULL, pc, | |
166 | sim_stopped, SIM_SIGTRAP); | |
167 | break; | |
168 | ||
169 | default : | |
170 | { | |
171 | USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; | |
172 | return new_pc; | |
173 | } | |
174 | } | |
175 | ||
176 | /* Fake an "rte" insn. */ | |
177 | /* FIXME: Should duplicate all of rte processing. */ | |
178 | return (pc & -4) + 4; | |
179 | } |