[thirdparty/binutils-gdb.git] / sim / m68hc11 / sim-main.h

/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   Copyright (C) 1999-2015 Free Software Foundation, Inc.
   Written by Stephane Carrez (stcarrez@nerim.fr)

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef _SIM_MAIN_H
#define _SIM_MAIN_H

#define WITH_MODULO_MEMORY 1
#define WITH_WATCHPOINTS 1
#define SIM_HANDLES_LMA 1

#include "sim-basics.h"
#include "sim-signal.h"
#include "sim-base.h"

#include "bfd.h"

#include "opcode/m68hc11.h"

#include "gdb/callback.h"
#include "gdb/remote-sim.h"
#include "opcode/m68hc11.h"
#include "sim-types.h"

typedef unsigned8 uint8;
typedef unsigned16 uint16;
typedef signed16 int16;
typedef unsigned32 uint32;
typedef signed32 int32;
typedef unsigned64 uint64;
typedef signed64 int64;

struct _sim_cpu;

#include "interrupts.h"
#include <setjmp.h>

/* Specifies the level of mapping for the IO, EEprom, nvram and external
   RAM.  IO registers are mapped over everything and the external RAM
   is last (ie, it can be hidden by everything above it in the list).  */
enum m68hc11_map_level
{
  M6811_IO_LEVEL,
  M6811_EEPROM_LEVEL,
  M6811_NVRAM_LEVEL,
  M6811_RAM_LEVEL
};

enum cpu_type
{
  CPU_M6811,
  CPU_M6812
};

#define X_REGNUM 	0
#define D_REGNUM	1
#define Y_REGNUM        2
#define SP_REGNUM 	3
#define PC_REGNUM 	4
#define A_REGNUM        5
#define B_REGNUM        6
#define PSW_REGNUM 	7
#define PAGE_REGNUM     8
#define Z_REGNUM        9

typedef struct m6811_regs {
    unsigned short      d;
    unsigned short      ix;
    unsigned short      iy;
    unsigned short      sp;
    unsigned short      pc;
    unsigned char       ccr;
  unsigned short      page;
} m6811_regs;


/* Description of 68HC11 IO registers.  Such description is only provided
   for the info command to display the current setting of IO registers
   from GDB.  */
struct io_reg_desc
{
  int        mask;
  const char *short_name;
  const char *long_name;
};
typedef struct io_reg_desc io_reg_desc;

extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
			       int mode);
extern void print_io_byte (SIM_DESC sd, const char *name,
			   io_reg_desc *desc, uint8 val, uint16 addr);
extern void print_io_word (SIM_DESC sd, const char *name,
			   io_reg_desc *desc, uint16 val, uint16 addr);


/* List of special 68HC11&68HC12 instructions that are not handled by the
   'gencode.c' generator.  These complex instructions are implemented
   by 'cpu_special'.  */
enum M6811_Special
{
  /* 68HC11 instructions.  */
  M6811_DAA,
  M6811_EMUL_SYSCALL,
  M6811_ILLEGAL,
  M6811_RTI,
  M6811_STOP,
  M6811_SWI,
  M6811_TEST,
  M6811_WAI,

  /* 68HC12 instructions.  */
  M6812_BGND,
  M6812_CALL,
  M6812_CALL_INDIRECT,
  M6812_IDIVS,
  M6812_EDIV,
  M6812_EDIVS,
  M6812_EMACS,
  M6812_EMUL,
  M6812_EMULS,
  M6812_ETBL,
  M6812_MEM,
  M6812_REV,
  M6812_REVW,
  M6812_RTC,
  M6812_RTI,
  M6812_WAV
};

#define M6811_MAX_PORTS (0x03f+1)
#define M6812_MAX_PORTS (0x3ff+1)
#define MAX_PORTS       (M6812_MAX_PORTS)

struct _sim_cpu;

typedef void (* cpu_interp) (struct _sim_cpu*);

struct _sim_cpu {
  /* CPU registers.  */
  struct m6811_regs     cpu_regs;

  /* CPU interrupts.  */
  struct interrupts     cpu_interrupts;

  /* Pointer to the interpretor routine.  */
  cpu_interp            cpu_interpretor;

  /* Pointer to the architecture currently configured in the simulator.  */
  const struct bfd_arch_info  *cpu_configured_arch;
  
  /* CPU absolute cycle time.  The cycle time is updated after
     each instruction, by the number of cycles taken by the instruction.
     It is cleared only when reset occurs.  */
  signed64              cpu_absolute_cycle;

  /* Number of cycles to increment after the current instruction.
     This is also the number of ticks for the generic event scheduler.  */
  uint8                 cpu_current_cycle;
  int                   cpu_emul_syscall;
  int                   cpu_is_initialized;
  int                   cpu_running;
  int                   cpu_check_memory;
  int                   cpu_stop_on_interrupt;

  /* When this is set, start execution of program at address specified
     in the ELF header.  This is used for testing some programs that do not
     have an interrupt table linked with them.  Programs created during the
     GCC validation are like this. A normal 68HC11 does not behave like
     this (unless there is some OS or downloadable feature).  */
  int                   cpu_use_elf_start;

  /* The starting address specified in ELF header.  */
  int                   cpu_elf_start;
  
  uint16                cpu_insn_pc;

  /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
     get the cycle time.  This is used for the timer rate and for the baud
     rate generation.  */
  unsigned long         cpu_frequency;

  /* The mode in which the CPU is configured (MODA and MODB pins).  */
  unsigned int          cpu_mode;
  const char*           cpu_start_mode;

  /* The cpu being configured.  */
  enum cpu_type         cpu_type;
  
  /* Initial value of the CONFIG register.  */
  uint8                 cpu_config;
  uint8                 cpu_use_local_config;
  
  uint8                 ios[MAX_PORTS];

  /* Memory bank parameters which describe how the memory bank window
     is mapped in memory and how to convert it in virtual address.  */
  uint16                bank_start;
  uint16                bank_end;
  address_word          bank_virtual;
  unsigned              bank_shift;
  

  struct hw            *hw_cpu;

  /* ... base type ... */
  sim_cpu_base base;
};

/* Returns the cpu absolute cycle time (A virtual counter incremented
   at each 68HC11 E clock).  */
#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
#define cpu_add_cycles(PROC,T)  ((PROC)->cpu_current_cycle += (signed64) (T))
#define cpu_is_running(PROC)    ((PROC)->cpu_running)

/* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
#define cpu_get_io_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
#define cpu_get_reg_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)

/* Returns the different CPU registers.  */
#define cpu_get_ccr(PROC)          ((PROC)->cpu_regs.ccr)
#define cpu_get_pc(PROC)           ((PROC)->cpu_regs.pc)
#define cpu_get_d(PROC)            ((PROC)->cpu_regs.d)
#define cpu_get_x(PROC)            ((PROC)->cpu_regs.ix)
#define cpu_get_y(PROC)            ((PROC)->cpu_regs.iy)
#define cpu_get_sp(PROC)           ((PROC)->cpu_regs.sp)
#define cpu_get_a(PROC)            ((PROC->cpu_regs.d >> 8) & 0x0FF)
#define cpu_get_b(PROC)            ((PROC->cpu_regs.d) & 0x0FF)
#define cpu_get_page(PROC)         ((PROC)->cpu_regs.page)

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_get_tmp3(PROC)         (0)
#define cpu_get_tmp2(PROC)         (0)

#define cpu_set_d(PROC,VAL)        (((PROC)->cpu_regs.d) = (VAL))
#define cpu_set_x(PROC,VAL)        (((PROC)->cpu_regs.ix) = (VAL))
#define cpu_set_y(PROC,VAL)        (((PROC)->cpu_regs.iy) = (VAL))
#define cpu_set_page(PROC,VAL)     (((PROC)->cpu_regs.page) = (VAL))

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_set_tmp3(PROC,VAL)     (0)
#define cpu_set_tmp2(PROC,VAL)     (void) (0)

#if 0
/* This is a function in m68hc11_sim.c to keep track of the frame.  */
#define cpu_set_sp(PROC,VAL)       (((PROC)->cpu_regs.sp) = (VAL))
#endif

#define cpu_set_pc(PROC,VAL)       (((PROC)->cpu_regs.pc) = (VAL))

#define cpu_set_a(PROC,VAL)  \
      cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
#define cpu_set_b(PROC,VAL)  \
      cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))

#define cpu_set_ccr(PROC,VAL)      ((PROC)->cpu_regs.ccr = (VAL))
#define cpu_get_ccr_H(PROC)        ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
#define cpu_get_ccr_X(PROC)        ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
#define cpu_get_ccr_S(PROC)        ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
#define cpu_get_ccr_N(PROC)        ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
#define cpu_get_ccr_V(PROC)        ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
#define cpu_get_ccr_C(PROC)        ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
#define cpu_get_ccr_Z(PROC)        ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
#define cpu_get_ccr_I(PROC)        ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)

#define cpu_set_ccr_flag(S,B,V) \
cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))

#define cpu_set_ccr_H(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
#define cpu_set_ccr_X(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
#define cpu_set_ccr_S(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
#define cpu_set_ccr_N(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
#define cpu_set_ccr_V(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
#define cpu_set_ccr_C(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
#define cpu_set_ccr_Z(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
#define cpu_set_ccr_I(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)

#undef inline
#define inline static __inline__

extern void cpu_memory_exception (struct _sim_cpu *proc,
                                  SIM_SIGNAL excep,
                                  uint16 addr,
                                  const char *message);

inline address_word
phys_to_virt (sim_cpu *cpu, address_word addr)
{
  if (addr >= cpu->bank_start && addr < cpu->bank_end)
    return ((address_word) (addr - cpu->bank_start)
            + (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
            + cpu->bank_virtual);
  else
    return (address_word) (addr);
}

inline uint8
memory_read8 (sim_cpu *cpu, uint16 addr)
{
  uint8 val;

  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return val;
}

inline void
memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
{
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}

inline uint16
memory_read16 (sim_cpu *cpu, uint16 addr)
{
  uint8 b[2];

  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
}

inline void
memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
{
  uint8 b[2];

  b[0] = val >> 8;
  b[1] = val;
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}
extern void
cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);

     inline void
cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_V (proc, 0);
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
}

     inline void
cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
{
  cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

     inline void
cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

inline void
cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}


inline void
cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}

inline void
cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

inline void
cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

/* Push and pop instructions for 68HC11 (next-available stack mode).  */
inline void
cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline void
cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp - 1;

  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline uint8
cpu_m68hc11_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc11_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Push and pop instructions for 68HC12 (last-used stack mode).  */
inline void
cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr --;
  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline void
cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr -= 2;
  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline uint8
cpu_m68hc12_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc12_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Fetch a 8/16 bit value and update the PC.  */
inline uint8
cpu_fetch8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.pc = addr + 1;
  return val;
}

inline uint16
cpu_fetch16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.pc = addr + 2;
  return val;
}

extern void cpu_call (sim_cpu* proc, uint16 addr);
extern void cpu_exg (sim_cpu* proc, uint8 code);
extern void cpu_dbcc (sim_cpu* proc);
extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
extern void cpu_move8 (sim_cpu *proc, uint8 op);
extern void cpu_move16 (sim_cpu *proc, uint8 op);

extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
extern void cpu_push_all (sim_cpu *proc);
extern void cpu_single_step (sim_cpu *proc);

extern void cpu_info (SIM_DESC sd, sim_cpu *proc);

extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);

/* Returns the address of a 68HC12 indexed operand.
   Pre and post modifications are handled on the source register.  */
extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);

extern void cpu_return (sim_cpu *cpu);
extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
extern int cpu_reset (sim_cpu *cpu);
extern int cpu_restart (sim_cpu *cpu);
extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
                              uint16 addr, const char *message, ...);
extern void emul_os (int op, sim_cpu *cpu);
extern void cpu_interp_m6811 (sim_cpu *cpu);
extern void cpu_interp_m6812 (sim_cpu *cpu);

extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
				      double ton, double toff,
				      signed64 repeat);
extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
				 unsigned addr, uint8 val);

/* The current state of the processor; registers, memory, etc.  */

struct sim_state {
  sim_cpu        *cpu[MAX_NR_PROCESSORS];
  device         *devices;
  sim_state_base base;
};

extern void sim_board_reset (SIM_DESC sd);

#define PRINT_TIME  0x01
#define PRINT_CYCLE 0x02
extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);

#endif
Commit	Line	Data
81e09ed8	1	/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
32d0add0	2	Copyright (C) 1999-2015 Free Software Foundation, Inc.
63f36def	3	Written by Stephane Carrez (stcarrez@nerim.fr)
e0709f50 AC	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
e0709f50 AC	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
e0709f50 AC	19
	20	#ifndef _SIM_MAIN_H
	21	#define _SIM_MAIN_H
	22
	23	#define WITH_MODULO_MEMORY 1
	24	#define WITH_WATCHPOINTS 1
	25	#define SIM_HANDLES_LMA 1
	26
	27	#include "sim-basics.h"
e0709f50 AC	28	#include "sim-signal.h"
	29	#include "sim-base.h"
	30
	31	#include "bfd.h"
	32
	33	#include "opcode/m68hc11.h"
	34
3c25f8c7 AC	35	#include "gdb/callback.h"
3c25f8c7 AC	36	#include "gdb/remote-sim.h"
e0709f50 AC	37	#include "opcode/m68hc11.h"
	38	#include "sim-types.h"
	39
	40	typedef unsigned8 uint8;
	41	typedef unsigned16 uint16;
	42	typedef signed16 int16;
	43	typedef unsigned32 uint32;
	44	typedef signed32 int32;
	45	typedef unsigned64 uint64;
	46	typedef signed64 int64;
	47
	48	struct _sim_cpu;
	49
	50	#include "interrupts.h"
	51	#include <setjmp.h>
	52
63348d04 SC	53	/* Specifies the level of mapping for the IO, EEprom, nvram and external
	54	RAM. IO registers are mapped over everything and the external RAM
	55	is last (ie, it can be hidden by everything above it in the list). */
	56	enum m68hc11_map_level
	57	{
	58	M6811_IO_LEVEL,
	59	M6811_EEPROM_LEVEL,
	60	M6811_NVRAM_LEVEL,
	61	M6811_RAM_LEVEL
	62	};
	63
81e09ed8 SC	64	enum cpu_type
	65	{
	66	CPU_M6811,
	67	CPU_M6812
	68	};
63348d04	69
e0709f50 AC	70	#define X_REGNUM 0
	71	#define D_REGNUM 1
	72	#define Y_REGNUM 2
	73	#define SP_REGNUM 3
	74	#define PC_REGNUM 4
	75	#define A_REGNUM 5
	76	#define B_REGNUM 6
	77	#define PSW_REGNUM 7
53b3cd22 SC	78	#define PAGE_REGNUM 8
53b3cd22 SC	79	#define Z_REGNUM 9
e0709f50 AC	80
	81	typedef struct m6811_regs {
	82	unsigned short d;
	83	unsigned short ix;
	84	unsigned short iy;
	85	unsigned short sp;
	86	unsigned short pc;
	87	unsigned char ccr;
63f36def	88	unsigned short page;
e0709f50 AC	89	} m6811_regs;
	90
	91
	92	/* Description of 68HC11 IO registers. Such description is only provided
	93	for the info command to display the current setting of IO registers
	94	from GDB. */
	95	struct io_reg_desc
	96	{
	97	int mask;
	98	const char *short_name;
	99	const char *long_name;
	100	};
	101	typedef struct io_reg_desc io_reg_desc;
	102
	103	extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
	104	int mode);
	105	extern void print_io_byte (SIM_DESC sd, const char *name,
	106	io_reg_desc *desc, uint8 val, uint16 addr);
962e9d85 SC	107	extern void print_io_word (SIM_DESC sd, const char *name,
962e9d85 SC	108	io_reg_desc *desc, uint16 val, uint16 addr);
e0709f50 AC	109
e0709f50 AC	110
81e09ed8	111	/* List of special 68HC11&68HC12 instructions that are not handled by the
e0709f50 AC	112	'gencode.c' generator. These complex instructions are implemented
	113	by 'cpu_special'. */
	114	enum M6811_Special
	115	{
81e09ed8 SC	116	/* 68HC11 instructions. */
	117	M6811_DAA,
	118	M6811_EMUL_SYSCALL,
	119	M6811_ILLEGAL,
e0709f50	120	M6811_RTI,
81e09ed8	121	M6811_STOP,
e0709f50 AC	122	M6811_SWI,
e0709f50 AC	123	M6811_TEST,
81e09ed8 SC	124	M6811_WAI,
	125
	126	/* 68HC12 instructions. */
	127	M6812_BGND,
	128	M6812_CALL,
63f36def	129	M6812_CALL_INDIRECT,
81e09ed8 SC	130	M6812_IDIVS,
	131	M6812_EDIV,
	132	M6812_EDIVS,
	133	M6812_EMACS,
	134	M6812_EMUL,
	135	M6812_EMULS,
	136	M6812_ETBL,
	137	M6812_MEM,
	138	M6812_REV,
	139	M6812_REVW,
	140	M6812_RTC,
	141	M6812_RTI,
	142	M6812_WAV
e0709f50 AC	143	};
e0709f50 AC	144
81e09ed8 SC	145	#define M6811_MAX_PORTS (0x03f+1)
	146	#define M6812_MAX_PORTS (0x3ff+1)
	147	#define MAX_PORTS (M6812_MAX_PORTS)
e0709f50	148
81e09ed8 SC	149	struct _sim_cpu;
	150
	151	typedef void (* cpu_interp) (struct _sim_cpu*);
	152
e0709f50 AC	153	struct _sim_cpu {
	154	/* CPU registers. */
	155	struct m6811_regs cpu_regs;
	156
	157	/* CPU interrupts. */
	158	struct interrupts cpu_interrupts;
	159
81e09ed8 SC	160	/* Pointer to the interpretor routine. */
	161	cpu_interp cpu_interpretor;
	162
	163	/* Pointer to the architecture currently configured in the simulator. */
	164	const struct bfd_arch_info *cpu_configured_arch;
	165
e0709f50 AC	166	/* CPU absolute cycle time. The cycle time is updated after
	167	each instruction, by the number of cycles taken by the instruction.
	168	It is cleared only when reset occurs. */
	169	signed64 cpu_absolute_cycle;
	170
	171	/* Number of cycles to increment after the current instruction.
	172	This is also the number of ticks for the generic event scheduler. */
	173	uint8 cpu_current_cycle;
	174	int cpu_emul_syscall;
	175	int cpu_is_initialized;
	176	int cpu_running;
	177	int cpu_check_memory;
	178	int cpu_stop_on_interrupt;
	179
	180	/* When this is set, start execution of program at address specified
	181	in the ELF header. This is used for testing some programs that do not
	182	have an interrupt table linked with them. Programs created during the
	183	GCC validation are like this. A normal 68HC11 does not behave like
	184	this (unless there is some OS or downloadable feature). */
	185	int cpu_use_elf_start;
	186
	187	/* The starting address specified in ELF header. */
	188	int cpu_elf_start;
	189
	190	uint16 cpu_insn_pc;
e0709f50 AC	191
	192	/* CPU frequency. This is the quartz frequency. It is divided by 4 to
	193	get the cycle time. This is used for the timer rate and for the baud
	194	rate generation. */
	195	unsigned long cpu_frequency;
	196
	197	/* The mode in which the CPU is configured (MODA and MODB pins). */
	198	unsigned int cpu_mode;
a685700c	199	const char* cpu_start_mode;
e0709f50	200
81e09ed8 SC	201	/* The cpu being configured. */
	202	enum cpu_type cpu_type;
	203
e0709f50 AC	204	/* Initial value of the CONFIG register. */
	205	uint8 cpu_config;
	206	uint8 cpu_use_local_config;
	207
81e09ed8	208	uint8 ios[MAX_PORTS];
827ec39a	209
77342e5e SC	210	/* Memory bank parameters which describe how the memory bank window
	211	is mapped in memory and how to convert it in virtual address. */
	212	uint16 bank_start;
	213	uint16 bank_end;
	214	address_word bank_virtual;
	215	unsigned bank_shift;
	216
	217
827ec39a SC	218	struct hw *hw_cpu;
827ec39a SC	219
e0709f50 AC	220	/* ... base type ... */
	221	sim_cpu_base base;
	222	};
	223
	224	/* Returns the cpu absolute cycle time (A virtual counter incremented
	225	at each 68HC11 E clock). */
	226	#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
	227	#define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
	228	#define cpu_is_running(PROC) ((PROC)->cpu_running)
	229
	230	/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
	231	#define cpu_get_io_base(PROC) \
	232	(((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
	233	#define cpu_get_reg_base(PROC) \
	234	(((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
	235
	236	/* Returns the different CPU registers. */
	237	#define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
	238	#define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
	239	#define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
	240	#define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
	241	#define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
	242	#define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
	243	#define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
	244	#define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
77342e5e	245	#define cpu_get_page(PROC) ((PROC)->cpu_regs.page)
e0709f50	246
81e09ed8 SC	247	/* 68HC12 specific and Motorola internal registers. */
	248	#define cpu_get_tmp3(PROC) (0)
	249	#define cpu_get_tmp2(PROC) (0)
	250
e0709f50 AC	251	#define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
	252	#define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
	253	#define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
77342e5e	254	#define cpu_set_page(PROC,VAL) (((PROC)->cpu_regs.page) = (VAL))
e0709f50	255
81e09ed8 SC	256	/* 68HC12 specific and Motorola internal registers. */
81e09ed8 SC	257	#define cpu_set_tmp3(PROC,VAL) (0)
63f36def	258	#define cpu_set_tmp2(PROC,VAL) (void) (0)
81e09ed8	259
e0709f50 AC	260	#if 0
	261	/* This is a function in m68hc11_sim.c to keep track of the frame. */
	262	#define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
	263	#endif
	264
	265	#define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
	266
	267	#define cpu_set_a(PROC,VAL) \
	268	cpu_set_d(PROC,((VAL) << 8) \| cpu_get_b(PROC))
	269	#define cpu_set_b(PROC,VAL) \
	270	cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)\|(VAL & 0x0FF))
	271
	272	#define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
	273	#define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
	274	#define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
	275	#define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
	276	#define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
	277	#define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
	278	#define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
	279	#define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
	280	#define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
	281
	282	#define cpu_set_ccr_flag(S,B,V) \
	283	cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) \| ((V) ? B : 0))
	284
	285	#define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
	286	#define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
	287	#define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
	288	#define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
	289	#define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
	290	#define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
	291	#define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
	292	#define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
	293
	294	#undef inline
	295	#define inline static __inline__
	296
	297	extern void cpu_memory_exception (struct _sim_cpu *proc,
	298	SIM_SIGNAL excep,
	299	uint16 addr,
	300	const char *message);
	301
63f36def SC	302	inline address_word
	303	phys_to_virt (sim_cpu *cpu, address_word addr)
	304	{
77342e5e SC	305	if (addr >= cpu->bank_start && addr < cpu->bank_end)
	306	return ((address_word) (addr - cpu->bank_start)
	307	+ (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
	308	+ cpu->bank_virtual);
63f36def SC	309	else
	310	return (address_word) (addr);
	311	}
	312
e0709f50 AC	313	inline uint8
	314	memory_read8 (sim_cpu *cpu, uint16 addr)
	315	{
	316	uint8 val;
63f36def	317
e0709f50 AC	318	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	319	{
	320	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	321	"Read error");
	322	}
	323	return val;
	324	}
	325
	326	inline void
	327	memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
	328	{
	329	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	330	{
	331	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	332	"Write error");
	333	}
	334	}
	335
	336	inline uint16
	337	memory_read16 (sim_cpu *cpu, uint16 addr)
	338	{
	339	uint8 b[2];
63f36def	340
e0709f50 AC	341	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
	342	{
	343	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	344	"Read error");
	345	}
	346	return (((uint16) (b[0])) << 8) \| ((uint16) b[1]);
	347	}
	348
	349	inline void
	350	memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
	351	{
	352	uint8 b[2];
	353
	354	b[0] = val >> 8;
	355	b[1] = val;
	356	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
	357	{
	358	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	359	"Write error");
	360	}
	361	}
	362	extern void
	363	cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
	364
	365	inline void
	366	cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
	367	{
	368	cpu_set_ccr_V (proc, 0);
	369	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
	370	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	371	}
	372
	373	inline void
	374	cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
	375	{
	376	cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
	377	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	378	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
	379	}
	380
	381	inline void
	382	cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
	383	{
	384	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
	385	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	386	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
	387	}
	388
	389	inline void
	390	cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
	391	{
	392	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x80 ? 1 : 0);
	393	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x80 ? 1 : 0);
	394	cpu_set_ccr_Z (proc, r == 0);
	395	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
	396	}
	397
	398
	399	inline void
	400	cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
	401	{
	402	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x80 ? 1 : 0);
	403	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x80 ? 1 : 0);
	404	cpu_set_ccr_Z (proc, r == 0);
405	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
406	}
407
408	inline void
409	cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
410	{
411	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x8000 ? 1 : 0);
412	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x8000 ? 1 : 0);
413	cpu_set_ccr_Z (proc, r == 0);
414	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
415	}
416
417	inline void
418	cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
419	{
420	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x8000 ? 1 : 0);
421	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x8000 ? 1 : 0);
422	cpu_set_ccr_Z (proc, r == 0);
423	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
424	}
425
81e09ed8	426	/* Push and pop instructions for 68HC11 (next-available stack mode). */
e0709f50	427	inline void
81e09ed8	428	cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
e0709f50 AC	429	{
	430	uint16 addr = proc->cpu_regs.sp;
	431
	432	memory_write8 (proc, addr, val);
	433	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	434	}
	435
	436	inline void
81e09ed8	437	cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
e0709f50 AC	438	{
	439	uint16 addr = proc->cpu_regs.sp - 1;
	440
	441	memory_write16 (proc, addr, val);
	442	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	443	}
	444
	445	inline uint8
81e09ed8	446	cpu_m68hc11_pop_uint8 (sim_cpu *proc)
e0709f50 AC	447	{
	448	uint16 addr = proc->cpu_regs.sp;
	449	uint8 val;
	450
	451	val = memory_read8 (proc, addr + 1);
	452	proc->cpu_regs.sp = addr + 1;
e0709f50 AC	453	return val;
	454	}
	455
	456	inline uint16
81e09ed8	457	cpu_m68hc11_pop_uint16 (sim_cpu *proc)
e0709f50 AC	458	{
	459	uint16 addr = proc->cpu_regs.sp;
	460	uint16 val;
	461
	462	val = memory_read16 (proc, addr + 1);
	463	proc->cpu_regs.sp = addr + 2;
e0709f50 AC	464	return val;
	465	}
	466
81e09ed8 SC	467	/* Push and pop instructions for 68HC12 (last-used stack mode). */
	468	inline void
	469	cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
	470	{
	471	uint16 addr = proc->cpu_regs.sp;
	472
	473	addr --;
	474	memory_write8 (proc, addr, val);
	475	proc->cpu_regs.sp = addr;
81e09ed8 SC	476	}
	477
	478	inline void
	479	cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
	480	{
	481	uint16 addr = proc->cpu_regs.sp;
	482
	483	addr -= 2;
	484	memory_write16 (proc, addr, val);
	485	proc->cpu_regs.sp = addr;
81e09ed8 SC	486	}
	487
	488	inline uint8
	489	cpu_m68hc12_pop_uint8 (sim_cpu *proc)
	490	{
	491	uint16 addr = proc->cpu_regs.sp;
	492	uint8 val;
	493
	494	val = memory_read8 (proc, addr);
	495	proc->cpu_regs.sp = addr + 1;
81e09ed8 SC	496	return val;
	497	}
	498
	499	inline uint16
	500	cpu_m68hc12_pop_uint16 (sim_cpu *proc)
	501	{
	502	uint16 addr = proc->cpu_regs.sp;
	503	uint16 val;
	504
	505	val = memory_read16 (proc, addr);
	506	proc->cpu_regs.sp = addr + 2;
81e09ed8 SC	507	return val;
	508	}
	509
	510	/* Fetch a 8/16 bit value and update the PC. */
e0709f50 AC	511	inline uint8
	512	cpu_fetch8 (sim_cpu *proc)
	513	{
	514	uint16 addr = proc->cpu_regs.pc;
	515	uint8 val;
	516
	517	val = memory_read8 (proc, addr);
	518	proc->cpu_regs.pc = addr + 1;
	519	return val;
	520	}
	521
	522	inline uint16
	523	cpu_fetch16 (sim_cpu *proc)
	524	{
	525	uint16 addr = proc->cpu_regs.pc;
	526	uint16 val;
	527
	528	val = memory_read16 (proc, addr);
	529	proc->cpu_regs.pc = addr + 2;
	530	return val;
	531	}
	532
	533	extern void cpu_call (sim_cpu* proc, uint16 addr);
81e09ed8 SC	534	extern void cpu_exg (sim_cpu* proc, uint8 code);
81e09ed8 SC	535	extern void cpu_dbcc (sim_cpu* proc);
e0709f50	536	extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
81e09ed8 SC	537	extern void cpu_move8 (sim_cpu *proc, uint8 op);
81e09ed8 SC	538	extern void cpu_move16 (sim_cpu *proc, uint8 op);
e0709f50 AC	539
e0709f50 AC	540	extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
81e09ed8	541	extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
e0709f50 AC	542	extern void cpu_push_all (sim_cpu *proc);
	543	extern void cpu_single_step (sim_cpu *proc);
	544
	545	extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
	546
	547	extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
	548
63f36def SC	549	/* Returns the address of a 68HC12 indexed operand.
63f36def SC	550	Pre and post modifications are handled on the source register. */
2b6ca062	551	extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
63f36def SC	552
63f36def SC	553	extern void cpu_return (sim_cpu *cpu);
e0709f50	554	extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
e0709f50 AC	555	extern int cpu_reset (sim_cpu *cpu);
	556	extern int cpu_restart (sim_cpu *cpu);
	557	extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
	558	uint16 addr, const char *message, ...);
	559	extern void emul_os (int op, sim_cpu *cpu);
81e09ed8 SC	560	extern void cpu_interp_m6811 (sim_cpu *cpu);
81e09ed8 SC	561	extern void cpu_interp_m6812 (sim_cpu *cpu);
e0709f50	562
827ec39a SC	563	extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
	564	double ton, double toff,
	565	signed64 repeat);
	566	extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
	567	extern void m68hc11cpu_set_port (struct hw me, sim_cpu cpu,
	568	unsigned addr, uint8 val);
	569
e0709f50 AC	570	/* The current state of the processor; registers, memory, etc. */
e0709f50 AC	571
e0709f50	572	struct sim_state {
bea3f671	573	sim_cpu *cpu[MAX_NR_PROCESSORS];
e0709f50 AC	574	device *devices;
	575	sim_state_base base;
	576	};
	577
e0709f50 AC	578	extern void sim_board_reset (SIM_DESC sd);
e0709f50 AC	579
a685700c SC	580	#define PRINT_TIME 0x01
	581	#define PRINT_CYCLE 0x02
	582	extern const char cycle_to_string (sim_cpu cpu, signed64 t, int flags);
2990a9f4	583
e0709f50 AC	584	#endif
	585
	586