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1d506c26 | 1 | /* Copyright 2009-2024 Free Software Foundation, Inc. |
7790fabe MF |
2 | |
3 | This file is part of the Xilinx MicroBlaze simulator. | |
4 | ||
5 | This library is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 3 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, see <http://www.gnu.org/licenses/>. */ | |
17 | ||
18 | #ifndef MICROBLAZE_SIM_H | |
19 | #define MICROBLAZE_SIM_H | |
20 | ||
21 | #include "microblaze.h" | |
22 | ||
23 | /* The machine state. | |
24 | This state is maintained in host byte order. The | |
25 | fetch/store register functions must translate between host | |
26 | byte order and the target processor byte order. | |
27 | Keeping this data in target byte order simplifies the register | |
28 | read/write functions. Keeping this data in native order improves | |
29 | the performance of the simulator. Simulation speed is deemed more | |
30 | important. */ | |
31 | ||
32 | /* The ordering of the microblaze_regset structure is matched in the | |
33 | gdb/config/microblaze/tm-microblaze.h file in the REGISTER_NAMES macro. */ | |
34 | struct microblaze_regset | |
35 | { | |
36 | signed_4 regs[32]; /* primary registers */ | |
37 | signed_4 spregs[2]; /* pc + msr */ | |
38 | int cycles; | |
39 | int insts; | |
40 | unsigned_1 imm_enable; | |
41 | signed_2 imm_high; | |
42 | }; | |
43 | ||
44 | #define MICROBLAZE_SIM_CPU(cpu) ((struct microblaze_regset *) CPU_ARCH_DATA (cpu)) | |
45 | ||
46 | #endif /* MICROBLAZE_SIM_H */ |