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* Makefile.in: Regenerate.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
20ae0098
CD		 12002-02-10 Chris Demetriou cgd@sibyte.com
2
3 * mips.igen (ADDI): Print immediate value.
4 (BREAK): Print code.
5 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
6 (SLL): Print "nop" specially, and don't run the code
7 that does the shift for the "nop" case.
8
9e52972e
FF		 92001-11-17 Fred Fish <fnf@redhat.com>
10
11 * sim-main.h (float_operation): Move enum declaration outside
12 of _sim_cpu struct declaration.
13
c0efbca4
JB		 142001-04-12 Jim Blandy <jimb@redhat.com>
15
16 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
17 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
18 set of the FCSR.
19 * sim-main.h (COCIDX): Remove definition; this isn't supported by
20 PENDING_FILL, and you can get the intended effect gracefully by
21 calling PENDING_SCHED directly.
22
fb891446
BE		 232001-02-23 Ben Elliston <bje@redhat.com>
24
25 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
26 already defined elsewhere.
27
8030f857
BE		 282001-02-19 Ben Elliston <bje@redhat.com>
29
30 * sim-main.h (sim_monitor): Return an int.
31 * interp.c (sim_monitor): Add return values.
32 (signal_exception): Handle error conditions from sim_monitor.
33
56b48a7a
CD		 342001-02-08 Ben Elliston <bje@redhat.com>
35
36 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
37 (store_memory): Likewise, pass cia to sim_core_write*.
38
d3ee60d9
FCE		 392000-10-19 Frank Ch. Eigler <fche@redhat.com>
40
41 On advice from Chris G. Demetriou <cgd@sibyte.com>:
42 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
43
071da002
AC		 44Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
45
46 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
47 * Makefile.in: Don't delete *.igen when cleaning directory.
48
a28c02cd
AC		 49Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
50
51 * m16.igen (break): Call SignalException not sim_engine_halt.
52
80ee11fa
AC		 53Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
54
55 From Jason Eckhardt:
56 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
57
673388c0
AC		 58Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
59
60 * mips.igen (MxC1, DMxC1): Fix printf formatting.
61
4c0deff4
NC		 622000-05-24 Michael Hayes <mhayes@cygnus.com>
63
64 * mips.igen (do_dmultx): Fix typo.
65
eb2d80b4
AC		 66Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
67
68 * configure: Regenerated to track ../common/aclocal.m4 changes.
69
dd37a34b
AC		 70Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
71
72 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
73
4c0deff4
NC		 742000-04-12 Frank Ch. Eigler <fche@redhat.com>
75
76 * sim-main.h (GPR_CLEAR): Define macro.
77
e30db738
AC		 78Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
79
80 * interp.c (decode_coproc): Output long using %lx and not %s.
81
cb7450ea
FCE		 822000-03-21 Frank Ch. Eigler <fche@redhat.com>
83
84 * interp.c (sim_open): Sort & extend dummy memory regions for
85 --board=jmr3904 for eCos.
86
a3027dd7
FCE		 872000-03-02 Frank Ch. Eigler <fche@redhat.com>
88
89 * configure: Regenerated.
90
91Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
92
93 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
94 calls, conditional on the simulator being in verbose mode.
95
dfcd3bfb
JM		 96Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
97
98 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
99 cache don't get ReservedInstruction traps.
100
c2d11a7d
JM		 1011999-11-29 Mark Salter <msalter@cygnus.com>
102
103 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
104 to clear status bits in sdisr register. This is how the hardware works.
105
106 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
107 being used by cygmon.
108
4ce44c66
JM		 1091999-11-11 Andrew Haley <aph@cygnus.com>
110
111 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
112 instructions.
113
cff3e48b
JM		 114Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
115
116 * mips.igen (MULT): Correct previous mis-applied patch.
117
d4f3574e
SS		 118Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
119
120 * mips.igen (delayslot32): Handle sequence like
121 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
122 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
123 (MULT): Actually pass the third register...
124
1251999-09-03 Mark Salter <msalter@cygnus.com>
126
127 * interp.c (sim_open): Added more memory aliases for additional
128 hardware being touched by cygmon on jmr3904 board.
129
130Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
131
132 * configure: Regenerated to track ../common/aclocal.m4 changes.
133
a0b3c4fd
JM		 134Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
135
136 * interp.c (sim_store_register): Handle case where client - GDB -
137 specifies that a 4 byte register is 8 bytes in size.
138 (sim_fetch_register): Ditto.
139
adf40b2e
JM		 1401999-07-14 Frank Ch. Eigler <fche@cygnus.com>
141
142 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
143 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
144 (idt_monitor_base): Base address for IDT monitor traps.
145 (pmon_monitor_base): Ditto for PMON.
146 (lsipmon_monitor_base): Ditto for LSI PMON.
147 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
148 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
149 (sim_firmware_command): New function.
150 (mips_option_handler): Call it for OPTION_FIRMWARE.
151 (sim_open): Allocate memory for idt_monitor region. If "--board"
152 option was given, add no monitor by default. Add BREAK hooks only if
153 monitors are also there.
154
43e526b9
JM		 155Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
156
157 * interp.c (sim_monitor): Flush output before reading input.
158
159Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
160
161 * tconfig.in (SIM_HANDLES_LMA): Always define.
162
163Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
164
165 From Mark Salter <msalter@cygnus.com>:
166 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
167 (sim_open): Add setup for BSP board.
168
9846de1b
JM		 169Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
170
171 * mips.igen (MULT, MULTU): Add syntax for two operand version.
172 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
173 them as unimplemented.
174
cd0fc7c3
SS		 1751999-05-08 Felix Lee <flee@cygnus.com>
176
177 * configure: Regenerated to track ../common/aclocal.m4 changes.
178
7a292a7a
SS		 1791999-04-21 Frank Ch. Eigler <fche@cygnus.com>
180
181 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
182
183Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
184
185 * configure.in: Any mips64vr5*-*-* target should have
186 -DTARGET_ENABLE_FR=1.
187 (default_endian): Any mips64vr*el-*-* target should default to
188 LITTLE_ENDIAN.
189 * configure: Re-generate.
190
1911999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
192
193 * mips.igen (ldl): Extend from _16_, not 32.
194
195Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
196
197 * interp.c (sim_store_register): Force registers written to by GDB
198 into an un-interpreted state.
199
c906108c
SS		 2001999-02-05 Frank Ch. Eigler <fche@cygnus.com>
201
202 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
203 CPU, start periodic background I/O polls.
204 (tx3904sio_poll): New function: periodic I/O poller.
205
2061998-12-30 Frank Ch. Eigler <fche@cygnus.com>
207
208 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
209
210Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
211
212 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
213 case statement.
214
2151998-12-29 Frank Ch. Eigler <fche@cygnus.com>
216
217 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
218 (load_word): Call SIM_CORE_SIGNAL hook on error.
219 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
220 starting. For exception dispatching, pass PC instead of NULL_CIA.
221 (decode_coproc): Use COP0_BADVADDR to store faulting address.
222 * sim-main.h (COP0_BADVADDR): Define.
223 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
224 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
225 (_sim_cpu): Add exc_* fields to store register value snapshots.
226 * mips.igen (*): Replace memory-related SignalException* calls
227 with references to SIM_CORE_SIGNAL hook.
228
229 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
230 fix.
231 * sim-main.c (*): Minor warning cleanups.
232
2331998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
234
235 * m16.igen (DADDIU5): Correct type-o.
236
237Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
238
239 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
240 variables.
241
242Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
243
244 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
245 to include path.
246 (interp.o): Add dependency on itable.h
247 (oengine.c, gencode): Delete remaining references.
248 (BUILT_SRC_FROM_GEN): Clean up.
249
2501998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
251
252 * vr4run.c: New.
253 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
254 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
255 tmp-run-hack) : New.
256 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
257 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
258 Drop the "64" qualifier to get the HACK generator working.
259 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
260 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
261 qualifier to get the hack generator working.
262 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
263 (DSLL): Use do_dsll.
264 (DSLLV): Use do_dsllv.
265 (DSRA): Use do_dsra.
266 (DSRL): Use do_dsrl.
267 (DSRLV): Use do_dsrlv.
268 (BC1): Move *vr4100 to get the HACK generator working.
269 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
270 get the HACK generator working.
271 (MACC) Rename to get the HACK generator working.
272 (DMACC,MACCS,DMACCS): Add the 64.
273
2741998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
275
276 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
277 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
278
2791998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
280
281 * mips/interp.c (DEBUG): Cleanups.
282
2831998-12-10 Frank Ch. Eigler <fche@cygnus.com>
284
285 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
286 (tx3904sio_tickle): fflush after a stdout character output.
287
2881998-12-03 Frank Ch. Eigler <fche@cygnus.com>
289
290 * interp.c (sim_close): Uninstall modules.
291
292Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
293
294 * sim-main.h, interp.c (sim_monitor): Change to global
295 function.
296
297Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
298
299 * configure.in (vr4100): Only include vr4100 instructions in
300 simulator.
301 * configure: Re-generate.
302 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
303
304Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
305
306 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
307 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
308 true alternative.
309
310 * configure.in (sim_default_gen, sim_use_gen): Replace with
311 sim_gen.
312 (--enable-sim-igen): Delete config option. Always using IGEN.
313 * configure: Re-generate.
314
315 * Makefile.in (gencode): Kill, kill, kill.
316 * gencode.c: Ditto.
317
318Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
319
320 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
321 bit mips16 igen simulator.
322 * configure: Re-generate.
323
324 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
325 as part of vr4100 ISA.
326 * vr.igen: Mark all instructions as 64 bit only.
327
328Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
329
330 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
331 Pacify GCC.
332
333Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
334
335 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
336 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
337 * configure: Re-generate.
338
339 * m16.igen (BREAK): Define breakpoint instruction.
340 (JALX32): Mark instruction as mips16 and not r3900.
341 * mips.igen (C.cond.fmt): Fix typo in instruction format.
342
343 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
344
345Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
346
347 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
348 insn as a debug breakpoint.
349
350 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
351 pending.slot_size.
352 (PENDING_SCHED): Clean up trace statement.
353 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
354 (PENDING_FILL): Delay write by only one cycle.
355 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
356
357 * sim-main.c (pending_tick): Clean up trace statements. Add trace
358 of pending writes.
359 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
360 32 & 64.
361 (pending_tick): Move incrementing of index to FOR statement.
362 (pending_tick): Only update PENDING_OUT after a write has occured.
363
364 * configure.in: Add explicit mips-lsi-* target. Use gencode to
365 build simulator.
366 * configure: Re-generate.
367
368 * interp.c (sim_engine_run OLD): Delete explicit call to
369 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
370
371Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
372
373 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
374 interrupt level number to match changed SignalExceptionInterrupt
375 macro.
376
377Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
378
379 * interp.c: #include "itable.h" if WITH_IGEN.
380 (get_insn_name): New function.
381 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
382 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
383
384Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
385
386 * configure: Rebuilt to inhale new common/aclocal.m4.
387
388Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
389
390 * dv-tx3904sio.c: Include sim-assert.h.
391
392Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
393
394 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
395 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
396 Reorganize target-specific sim-hardware checks.
397 * configure: rebuilt.
398 * interp.c (sim_open): For tx39 target boards, set
399 OPERATING_ENVIRONMENT, add tx3904sio devices.
400 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
401 ROM executables. Install dv-sockser into sim-modules list.
402
403 * dv-tx3904irc.c: Compiler warning clean-up.
404 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
405 frequent hw-trace messages.
406
407Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
408
409 * vr.igen (MulAcc): Identify as a vr4100 specific function.
410
411Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
412
413 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
414
415 * vr.igen: New file.
416 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
417 * mips.igen: Define vr4100 model. Include vr.igen.
418Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
419
420 * mips.igen (check_mf_hilo): Correct check.
421
422Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
423
424 * sim-main.h (interrupt_event): Add prototype.
425
426 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
427 register_ptr, register_value.
428 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
429
430 * sim-main.h (tracefh): Make extern.
431
432Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
433
434 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
435 Reduce unnecessarily high timer event frequency.
436 * dv-tx3904cpu.c: Ditto for interrupt event.
437
438Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
439
440 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
441 to allay warnings.
442 (interrupt_event): Made non-static.
443
444 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
445 interchange of configuration values for external vs. internal
446 clock dividers.
447
448Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
449
450 * mips.igen (BREAK): Moved code to here for
451 simulator-reserved break instructions.
452 * gencode.c (build_instruction): Ditto.
453 * interp.c (signal_exception): Code moved from here. Non-
454 reserved instructions now use exception vector, rather
455 than halting sim.
456 * sim-main.h: Moved magic constants to here.
457
458Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
459
460 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
461 register upon non-zero interrupt event level, clear upon zero
462 event value.
463 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
464 by passing zero event value.
465 (*_io_{read,write}_buffer): Endianness fixes.
466 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
467 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
468
469 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
470 serial I/O and timer module at base address 0xFFFF0000.
471
472Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
473
474 * mips.igen (SWC1) : Correct the handling of ReverseEndian
475 and BigEndianCPU.
476
477Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
478
479 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
480 parts.
481 * configure: Update.
482
483Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
484
485 * dv-tx3904tmr.c: New file - implements tx3904 timer.
486 * dv-tx3904{irc,cpu}.c: Mild reformatting.
487 * configure.in: Include tx3904tmr in hw_device list.
488 * configure: Rebuilt.
489 * interp.c (sim_open): Instantiate three timer instances.
490 Fix address typo of tx3904irc instance.
491
492Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
493
494 * interp.c (signal_exception): SystemCall exception now uses
495 the exception vector.
496
497Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
498
499 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
500 to allay warnings.
501
502Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
503
504 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
505
506Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
507
508 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
509
510 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
511 sim-main.h. Declare a struct hw_descriptor instead of struct
512 hw_device_descriptor.
513
514Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
515
516 * mips.igen (do_store_left, do_load_left): Compute nr of left and
517 right bits and then re-align left hand bytes to correct byte
518 lanes. Fix incorrect computation in do_store_left when loading
519 bytes from second word.
520
521Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
522
523 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
524 * interp.c (sim_open): Only create a device tree when HW is
525 enabled.
526
527 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
528 * interp.c (signal_exception): Ditto.
529
530Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
531
532 * gencode.c: Mark BEGEZALL as LIKELY.
533
534Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
535
536 * sim-main.h (ALU32_END): Sign extend 32 bit results.
537 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
538
539Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
540
541 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
542 modules. Recognize TX39 target with "mips*tx39" pattern.
543 * configure: Rebuilt.
544 * sim-main.h (*): Added many macros defining bits in
545 TX39 control registers.
546 (SignalInterrupt): Send actual PC instead of NULL.
547 (SignalNMIReset): New exception type.
548 * interp.c (board): New variable for future use to identify
549 a particular board being simulated.
550 (mips_option_handler,mips_options): Added "--board" option.
551 (interrupt_event): Send actual PC.
552 (sim_open): Make memory layout conditional on board setting.
553 (signal_exception): Initial implementation of hardware interrupt
554 handling. Accept another break instruction variant for simulator
555 exit.
556 (decode_coproc): Implement RFE instruction for TX39.
557 (mips.igen): Decode RFE instruction as such.
558 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
559 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
560 bbegin to implement memory map.
561 * dv-tx3904cpu.c: New file.
562 * dv-tx3904irc.c: New file.
563
564Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
565
566 * mips.igen (check_mt_hilo): Create a separate r3900 version.
567
568Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
569
570 * tx.igen (madd,maddu): Replace calls to check_op_hilo
571 with calls to check_div_hilo.
572
573Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
574
575 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
576 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
577 Add special r3900 version of do_mult_hilo.
578 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
579 with calls to check_mult_hilo.
580 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
581 with calls to check_div_hilo.
582
583Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
584
585 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
586 Document a replacement.
587
588Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
589
590 * interp.c (sim_monitor): Make mon_printf work.
591
592Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
593
594 * sim-main.h (INSN_NAME): New arg `cpu'.
595
596Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
597
598 * configure: Regenerated to track ../common/aclocal.m4 changes.
599
600Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
601
602 * configure: Regenerated to track ../common/aclocal.m4 changes.
603 * config.in: Ditto.
604
605Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
606
607 * acconfig.h: New file.
608 * configure.in: Reverted change of Apr 24; use sinclude again.
609
610Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
611
612 * configure: Regenerated to track ../common/aclocal.m4 changes.
613 * config.in: Ditto.
614
615Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
616
617 * configure.in: Don't call sinclude.
618
619Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
620
621 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
622
623Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
624
625 * mips.igen (ERET): Implement.
626
627 * interp.c (decode_coproc): Return sign-extended EPC.
628
629 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
630
631 * interp.c (signal_exception): Do not ignore Trap.
632 (signal_exception): On TRAP, restart at exception address.
633 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
634 (signal_exception): Update.
635 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
636 so that TRAP instructions are caught.
637
638Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
639
640 * sim-main.h (struct hilo_access, struct hilo_history): Define,
641 contains HI/LO access history.
642 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
643 (HIACCESS, LOACCESS): Delete, replace with
644 (HIHISTORY, LOHISTORY): New macros.
645 (CHECKHILO): Delete all, moved to mips.igen
646
647 * gencode.c (build_instruction): Do not generate checks for
648 correct HI/LO register usage.
649
650 * interp.c (old_engine_run): Delete checks for correct HI/LO
651 register usage.
652
653 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
654 check_mf_cycles): New functions.
655 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
656 do_divu, domultx, do_mult, do_multu): Use.
657
658 * tx.igen ("madd", "maddu"): Use.
659
660Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
661
662 * mips.igen (DSRAV): Use function do_dsrav.
663 (SRAV): Use new function do_srav.
664
665 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
666 (B): Sign extend 11 bit immediate.
667 (EXT-B*): Shift 16 bit immediate left by 1.
668 (ADDIU*): Don't sign extend immediate value.
669
670Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
671
672 * m16run.c (sim_engine_run): Restore CIA after handling an event.
673
674 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
675 functions.
676
677 * mips.igen (delayslot32, nullify_next_insn): New functions.
678 (m16.igen): Always include.
679 (do_*): Add more tracing.
680
681 * m16.igen (delayslot16): Add NIA argument, could be called by a
682 32 bit MIPS16 instruction.
683
684 * interp.c (ifetch16): Move function from here.
685 * sim-main.c (ifetch16): To here.
686
687 * sim-main.c (ifetch16, ifetch32): Update to match current
688 implementations of LH, LW.
689 (signal_exception): Don't print out incorrect hex value of illegal
690 instruction.
691
692Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
693
694 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
695 instruction.
696
697 * m16.igen: Implement MIPS16 instructions.
698
699 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
700 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
701 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
702 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
703 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
704 bodies of corresponding code from 32 bit insn to these. Also used
705 by MIPS16 versions of functions.
706
707 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
708 (IMEM16): Drop NR argument from macro.
709
710Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
711
712 * Makefile.in (SIM_OBJS): Add sim-main.o.
713
714 * sim-main.h (address_translation, load_memory, store_memory,
715 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
716 as INLINE_SIM_MAIN.
717 (pr_addr, pr_uword64): Declare.
718 (sim-main.c): Include when H_REVEALS_MODULE_P.
719
720 * interp.c (address_translation, load_memory, store_memory,
721 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
722 from here.
723 * sim-main.c: To here. Fix compilation problems.
724
725 * configure.in: Enable inlining.
726 * configure: Re-config.
727
728Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
729
730 * configure: Regenerated to track ../common/aclocal.m4 changes.
731
732Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
733
734 * mips.igen: Include tx.igen.
735 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
736 * tx.igen: New file, contains MADD and MADDU.
737
738 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
739 the hardwired constant `7'.
740 (store_memory): Ditto.
741 (LOADDRMASK): Move definition to sim-main.h.
742
743 mips.igen (MTC0): Enable for r3900.
744 (ADDU): Add trace.
745
746 mips.igen (do_load_byte): Delete.
747 (do_load, do_store, do_load_left, do_load_write, do_store_left,
748 do_store_right): New functions.
749 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
750
751 configure.in: Let the tx39 use igen again.
752 configure: Update.
753
754Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
755
756 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
757 not an address sized quantity. Return zero for cache sizes.
758
759Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
760
761 * mips.igen (r3900): r3900 does not support 64 bit integer
762 operations.
763
764Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
765
766 * configure.in (mipstx39*-*-*): Use gencode simulator rather
767 than igen one.
768 * configure : Rebuild.
769
770Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
771
772 * configure: Regenerated to track ../common/aclocal.m4 changes.
773
774Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
775
776 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
777
778Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
779
780 * configure: Regenerated to track ../common/aclocal.m4 changes.
781 * config.in: Regenerated to track ../common/aclocal.m4 changes.
782
783Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
784
785 * configure: Regenerated to track ../common/aclocal.m4 changes.
786
787Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
788
789 * interp.c (Max, Min): Comment out functions. Not yet used.
790
791Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
792
793 * configure: Regenerated to track ../common/aclocal.m4 changes.
794
795Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
796
797 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
798 configurable settings for stand-alone simulator.
799
800 * configure.in: Added X11 search, just in case.
801
802 * configure: Regenerated.
803
804Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
805
806 * interp.c (sim_write, sim_read, load_memory, store_memory):
807 Replace sim_core_*_map with read_map, write_map, exec_map resp.
808
809Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
810
811 * sim-main.h (GETFCC): Return an unsigned value.
812
813Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
814
815 * mips.igen (DIV): Fix check for -1 / MIN_INT.
816 (DADD): Result destination is RD not RT.
817
818Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
819
820 * sim-main.h (HIACCESS, LOACCESS): Always define.
821
822 * mdmx.igen (Maxi, Mini): Rename Max, Min.
823
824 * interp.c (sim_info): Delete.
825
826Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
827
828 * interp.c (DECLARE_OPTION_HANDLER): Use it.
829 (mips_option_handler): New argument `cpu'.
830 (sim_open): Update call to sim_add_option_table.
831
832Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
833
834 * mips.igen (CxC1): Add tracing.
835
836Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
837
838 * sim-main.h (Max, Min): Declare.
839
840 * interp.c (Max, Min): New functions.
841
842 * mips.igen (BC1): Add tracing.
843
844Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
845
846 * interp.c Added memory map for stack in vr4100
847
848Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
849
850 * interp.c (load_memory): Add missing "break"'s.
851
852Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
853
854 * interp.c (sim_store_register, sim_fetch_register): Pass in
855 length parameter. Return -1.
856
857Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
858
859 * interp.c: Added hardware init hook, fixed warnings.
860
861Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
862
863 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
864
865Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
866
867 * interp.c (ifetch16): New function.
868
869 * sim-main.h (IMEM32): Rename IMEM.
870 (IMEM16_IMMED): Define.
871 (IMEM16): Define.
872 (DELAY_SLOT): Update.
873
874 * m16run.c (sim_engine_run): New file.
875
876 * m16.igen: All instructions except LB.
877 (LB): Call do_load_byte.
878 * mips.igen (do_load_byte): New function.
879 (LB): Call do_load_byte.
880
881 * mips.igen: Move spec for insn bit size and high bit from here.
882 * Makefile.in (tmp-igen, tmp-m16): To here.
883
884 * m16.dc: New file, decode mips16 instructions.
885
886 * Makefile.in (SIM_NO_ALL): Define.
887 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
888
889Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
890
891 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
892 point unit to 32 bit registers.
893 * configure: Re-generate.
894
895Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
896
897 * configure.in (sim_use_gen): Make IGEN the default simulator
898 generator for generic 32 and 64 bit mips targets.
899 * configure: Re-generate.
900
901Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
902
903 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
904 bitsize.
905
906 * interp.c (sim_fetch_register, sim_store_register): Read/write
907 FGR from correct location.
908 (sim_open): Set size of FGR's according to
909 WITH_TARGET_FLOATING_POINT_BITSIZE.
910
911 * sim-main.h (FGR): Store floating point registers in a separate
912 array.
913
914Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
915
916 * configure: Regenerated to track ../common/aclocal.m4 changes.
917
918Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
919
920 * interp.c (ColdReset): Call PENDING_INVALIDATE.
921
922 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
923
924 * interp.c (pending_tick): New function. Deliver pending writes.
925
926 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
927 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
928 it can handle mixed sized quantites and single bits.
929
930Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
931
932 * interp.c (oengine.h): Do not include when building with IGEN.
933 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
934 (sim_info): Ditto for PROCESSOR_64BIT.
935 (sim_monitor): Replace ut_reg with unsigned_word.
936 (*): Ditto for t_reg.
937 (LOADDRMASK): Define.
938 (sim_open): Remove defunct check that host FP is IEEE compliant,
939 using software to emulate floating point.
940 (value_fpr, ...): Always compile, was conditional on HASFPU.
941
942Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
943
944 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
945 size.
946
947 * interp.c (SD, CPU): Define.
948 (mips_option_handler): Set flags in each CPU.
949 (interrupt_event): Assume CPU 0 is the one being iterrupted.
950 (sim_close): Do not clear STATE, deleted anyway.
951 (sim_write, sim_read): Assume CPU zero's vm should be used for
952 data transfers.
953 (sim_create_inferior): Set the PC for all processors.
954 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
955 argument.
956 (mips16_entry): Pass correct nr of args to store_word, load_word.
957 (ColdReset): Cold reset all cpu's.
958 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
959 (sim_monitor, load_memory, store_memory, signal_exception): Use
960 `CPU' instead of STATE_CPU.
961
962
963 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
964 SD or CPU_.
965
966 * sim-main.h (signal_exception): Add sim_cpu arg.
967 (SignalException*): Pass both SD and CPU to signal_exception.
968 * interp.c (signal_exception): Update.
969
970 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
971 Ditto
972 (sync_operation, prefetch, cache_op, store_memory, load_memory,
973 address_translation): Ditto
974 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
975
976Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
977
978 * configure: Regenerated to track ../common/aclocal.m4 changes.
979
980Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
981
982 * interp.c (sim_engine_run): Add `nr_cpus' argument.
983
984 * mips.igen (model): Map processor names onto BFD name.
985
986 * sim-main.h (CPU_CIA): Delete.
987 (SET_CIA, GET_CIA): Define
988
989Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
990
991 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
992 regiser.
993
994 * configure.in (default_endian): Configure a big-endian simulator
995 by default.
996 * configure: Re-generate.
997
998Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
999
1000 * configure: Regenerated to track ../common/aclocal.m4 changes.
1001
1002Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1003
1004 * interp.c (sim_monitor): Handle Densan monitor outbyte
1005 and inbyte functions.
1006
10071997-12-29 Felix Lee <flee@cygnus.com>
1008
1009 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1010
1011Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1012
1013 * Makefile.in (tmp-igen): Arrange for $zero to always be
1014 reset to zero after every instruction.
1015
1016Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1017
1018 * configure: Regenerated to track ../common/aclocal.m4 changes.
1019 * config.in: Ditto.
1020
1021Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1022
1023 * mips.igen (MSUB): Fix to work like MADD.
1024 * gencode.c (MSUB): Similarly.
1025
1026Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1027
1028 * configure: Regenerated to track ../common/aclocal.m4 changes.
1029
1030Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1031
1032 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1033
1034Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1035
1036 * sim-main.h (sim-fpu.h): Include.
1037
1038 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1039 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1040 using host independant sim_fpu module.
1041
1042Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1043
1044 * interp.c (signal_exception): Report internal errors with SIGABRT
1045 not SIGQUIT.
1046
1047 * sim-main.h (C0_CONFIG): New register.
1048 (signal.h): No longer include.
1049
1050 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1051
1052Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1053
1054 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1055
1056Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1057
1058 * mips.igen: Tag vr5000 instructions.
1059 (ANDI): Was missing mipsIV model, fix assembler syntax.
1060 (do_c_cond_fmt): New function.
1061 (C.cond.fmt): Handle mips I-III which do not support CC field
1062 separatly.
1063 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1064 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1065 in IV3.2 spec.
1066 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1067 vr5000 which saves LO in a GPR separatly.
1068
1069 * configure.in (enable-sim-igen): For vr5000, select vr5000
1070 specific instructions.
1071 * configure: Re-generate.
1072
1073Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1074
1075 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1076
1077 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1078 fmt_uninterpreted_64 bit cases to switch. Convert to
1079 fmt_formatted,
1080
1081 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1082
1083 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1084 as specified in IV3.2 spec.
1085 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1086
1087Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1088
1089 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1090 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1091 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1092 PENDING_FILL versions of instructions. Simplify.
1093 (X): New function.
1094 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1095 instructions.
1096 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1097 a signed value.
1098 (MTHI, MFHI): Disable code checking HI-LO.
1099
1100 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1101 global.
1102 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1103
1104Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1105
1106 * gencode.c (build_mips16_operands): Replace IPC with cia.
1107
1108 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1109 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1110 IPC to `cia'.
1111 (UndefinedResult): Replace function with macro/function
1112 combination.
1113 (sim_engine_run): Don't save PC in IPC.
1114
1115 * sim-main.h (IPC): Delete.
1116
1117
1118 * interp.c (signal_exception, store_word, load_word,
1119 address_translation, load_memory, store_memory, cache_op,
1120 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1121 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1122 current instruction address - cia - argument.
1123 (sim_read, sim_write): Call address_translation directly.
1124 (sim_engine_run): Rename variable vaddr to cia.
1125 (signal_exception): Pass cia to sim_monitor
1126
1127 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1128 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1129 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1130
1131 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1132 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1133 SIM_ASSERT.
1134
1135 * interp.c (signal_exception): Pass restart address to
1136 sim_engine_restart.
1137
1138 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1139 idecode.o): Add dependency.
1140
1141 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1142 Delete definitions
1143 (DELAY_SLOT): Update NIA not PC with branch address.
1144 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1145
1146 * mips.igen: Use CIA not PC in branch calculations.
1147 (illegal): Call SignalException.
1148 (BEQ, ADDIU): Fix assembler.
1149
1150Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1151
1152 * m16.igen (JALX): Was missing.
1153
1154 * configure.in (enable-sim-igen): New configuration option.
1155 * configure: Re-generate.
1156
1157 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1158
1159 * interp.c (load_memory, store_memory): Delete parameter RAW.
1160 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1161 bypassing {load,store}_memory.
1162
1163 * sim-main.h (ByteSwapMem): Delete definition.
1164
1165 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1166
1167 * interp.c (sim_do_command, sim_commands): Delete mips specific
1168 commands. Handled by module sim-options.
1169
1170 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1171 (WITH_MODULO_MEMORY): Define.
1172
1173 * interp.c (sim_info): Delete code printing memory size.
1174
1175 * interp.c (mips_size): Nee sim_size, delete function.
1176 (power2): Delete.
1177 (monitor, monitor_base, monitor_size): Delete global variables.
1178 (sim_open, sim_close): Delete code creating monitor and other
1179 memory regions. Use sim-memopts module, via sim_do_commandf, to
1180 manage memory regions.
1181 (load_memory, store_memory): Use sim-core for memory model.
1182
1183 * interp.c (address_translation): Delete all memory map code
1184 except line forcing 32 bit addresses.
1185
1186Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1187
1188 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1189 trace options.
1190
1191 * interp.c (logfh, logfile): Delete globals.
1192 (sim_open, sim_close): Delete code opening & closing log file.
1193 (mips_option_handler): Delete -l and -n options.
1194 (OPTION mips_options): Ditto.
1195
1196 * interp.c (OPTION mips_options): Rename option trace to dinero.
1197 (mips_option_handler): Update.
1198
1199Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1200
1201 * interp.c (fetch_str): New function.
1202 (sim_monitor): Rewrite using sim_read & sim_write.
1203 (sim_open): Check magic number.
1204 (sim_open): Write monitor vectors into memory using sim_write.
1205 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1206 (sim_read, sim_write): Simplify - transfer data one byte at a
1207 time.
1208 (load_memory, store_memory): Clarify meaning of parameter RAW.
1209
1210 * sim-main.h (isHOST): Defete definition.
1211 (isTARGET): Mark as depreciated.
1212 (address_translation): Delete parameter HOST.
1213
1214 * interp.c (address_translation): Delete parameter HOST.
1215
1216Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1217
1218 * mips.igen:
1219
1220 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1221 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1222
1223Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1224
1225 * mips.igen: Add model filter field to records.
1226
1227Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1228
1229 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1230
1231 interp.c (sim_engine_run): Do not compile function sim_engine_run
1232 when WITH_IGEN == 1.
1233
1234 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1235 target architecture.
1236
1237 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1238 igen. Replace with configuration variables sim_igen_flags /
1239 sim_m16_flags.
1240
1241 * m16.igen: New file. Copy mips16 insns here.
1242 * mips.igen: From here.
1243
1244Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1245
1246 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1247 to top.
1248 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1249
1250Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1251
1252 * gencode.c (build_instruction): Follow sim_write's lead in using
1253 BigEndianMem instead of !ByteSwapMem.
1254
1255Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1256
1257 * configure.in (sim_gen): Dependent on target, select type of
1258 generator. Always select old style generator.
1259
1260 configure: Re-generate.
1261
1262 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1263 targets.
1264 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1265 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1266 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1267 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1268 SIM_@sim_gen@_*, set by autoconf.
1269
1270Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1271
1272 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1273
1274 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1275 CURRENT_FLOATING_POINT instead.
1276
1277 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1278 (address_translation): Raise exception InstructionFetch when
1279 translation fails and isINSTRUCTION.
1280
1281 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1282 sim_engine_run): Change type of of vaddr and paddr to
1283 address_word.
1284 (address_translation, prefetch, load_memory, store_memory,
1285 cache_op): Change type of vAddr and pAddr to address_word.
1286
1287 * gencode.c (build_instruction): Change type of vaddr and paddr to
1288 address_word.
1289
1290Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1291
1292 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1293 macro to obtain result of ALU op.
1294
1295Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1296
1297 * interp.c (sim_info): Call profile_print.
1298
1299Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1300
1301 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1302
1303 * sim-main.h (WITH_PROFILE): Do not define, defined in
1304 common/sim-config.h. Use sim-profile module.
1305 (simPROFILE): Delete defintion.
1306
1307 * interp.c (PROFILE): Delete definition.
1308 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1309 (sim_close): Delete code writing profile histogram.
1310 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1311 Delete.
1312 (sim_engine_run): Delete code profiling the PC.
1313
1314Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1315
1316 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1317
1318 * interp.c (sim_monitor): Make register pointers of type
1319 unsigned_word*.
1320
1321 * sim-main.h: Make registers of type unsigned_word not
1322 signed_word.
1323
1324Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1325
1326 * interp.c (sync_operation): Rename from SyncOperation, make
1327 global, add SD argument.
1328 (prefetch): Rename from Prefetch, make global, add SD argument.
1329 (decode_coproc): Make global.
1330
1331 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1332
1333 * gencode.c (build_instruction): Generate DecodeCoproc not
1334 decode_coproc calls.
1335
1336 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1337 (SizeFGR): Move to sim-main.h
1338 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1339 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1340 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1341 sim-main.h.
1342 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1343 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1344 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1345 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1346 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1347 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1348
1349 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1350 exception.
1351 (sim-alu.h): Include.
1352 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1353 (sim_cia): Typedef to instruction_address.
1354
1355Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1356
1357 * Makefile.in (interp.o): Rename generated file engine.c to
1358 oengine.c.
1359
1360 * interp.c: Update.
1361
1362Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1363
1364 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1365
1366Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1367
1368 * gencode.c (build_instruction): For "FPSQRT", output correct
1369 number of arguments to Recip.
1370
1371Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1372
1373 * Makefile.in (interp.o): Depends on sim-main.h
1374
1375 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1376
1377 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1378 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1379 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1380 STATE, DSSTATE): Define
1381 (GPR, FGRIDX, ..): Define.
1382
1383 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1384 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1385 (GPR, FGRIDX, ...): Delete macros.
1386
1387 * interp.c: Update names to match defines from sim-main.h
1388
1389Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1390
1391 * interp.c (sim_monitor): Add SD argument.
1392 (sim_warning): Delete. Replace calls with calls to
1393 sim_io_eprintf.
1394 (sim_error): Delete. Replace calls with sim_io_error.
1395 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1396 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1397 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1398 argument.
1399 (mips_size): Rename from sim_size. Add SD argument.
1400
1401 * interp.c (simulator): Delete global variable.
1402 (callback): Delete global variable.
1403 (mips_option_handler, sim_open, sim_write, sim_read,
1404 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1405 sim_size,sim_monitor): Use sim_io_* not callback->*.
1406 (sim_open): ZALLOC simulator struct.
1407 (PROFILE): Do not define.
1408
1409Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1410
1411 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1412 support.h with corresponding code.
1413
1414 * sim-main.h (word64, uword64), support.h: Move definition to
1415 sim-main.h.
1416 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1417
1418 * support.h: Delete
1419 * Makefile.in: Update dependencies
1420 * interp.c: Do not include.
1421
1422Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1423
1424 * interp.c (address_translation, load_memory, store_memory,
1425 cache_op): Rename to from AddressTranslation et.al., make global,
1426 add SD argument
1427
1428 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1429 CacheOp): Define.
1430
1431 * interp.c (SignalException): Rename to signal_exception, make
1432 global.
1433
1434 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1435
1436 * sim-main.h (SignalException, SignalExceptionInterrupt,
1437 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1438 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1439 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1440 Define.
1441
1442 * interp.c, support.h: Use.
1443
1444Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1445
1446 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1447 to value_fpr / store_fpr. Add SD argument.
1448 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1449 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1450
1451 * sim-main.h (ValueFPR, StoreFPR): Define.
1452
1453Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1454
1455 * interp.c (sim_engine_run): Check consistency between configure
1456 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1457 and HASFPU.
1458
1459 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1460 (mips_fpu): Configure WITH_FLOATING_POINT.
1461 (mips_endian): Configure WITH_TARGET_ENDIAN.
1462 * configure: Update.
1463
1464Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1465
1466 * configure: Regenerated to track ../common/aclocal.m4 changes.
1467
1468Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1469
1470 * configure: Regenerated.
1471
1472Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1473
1474 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1475
1476Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1477
1478 * gencode.c (print_igen_insn_models): Assume certain architectures
1479 include all mips* instructions.
1480 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1481 instruction.
1482
1483 * Makefile.in (tmp.igen): Add target. Generate igen input from
1484 gencode file.
1485
1486 * gencode.c (FEATURE_IGEN): Define.
1487 (main): Add --igen option. Generate output in igen format.
1488 (process_instructions): Format output according to igen option.
1489 (print_igen_insn_format): New function.
1490 (print_igen_insn_models): New function.
1491 (process_instructions): Only issue warnings and ignore
1492 instructions when no FEATURE_IGEN.
1493
1494Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1495
1496 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1497 MIPS targets.
1498
1499Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1500
1501 * configure: Regenerated to track ../common/aclocal.m4 changes.
1502
1503Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1504
1505 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1506 SIM_RESERVED_BITS): Delete, moved to common.
1507 (SIM_EXTRA_CFLAGS): Update.
1508
1509Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1510
1511 * configure.in: Configure non-strict memory alignment.
1512 * configure: Regenerated to track ../common/aclocal.m4 changes.
1513
1514Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1515
1516 * configure: Regenerated to track ../common/aclocal.m4 changes.
1517
1518Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1519
1520 * gencode.c (SDBBP,DERET): Added (3900) insns.
1521 (RFE): Turn on for 3900.
1522 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1523 (dsstate): Made global.
1524 (SUBTARGET_R3900): Added.
1525 (CANCELDELAYSLOT): New.
1526 (SignalException): Ignore SystemCall rather than ignore and
1527 terminate. Add DebugBreakPoint handling.
1528 (decode_coproc): New insns RFE, DERET; and new registers Debug
1529 and DEPC protected by SUBTARGET_R3900.
1530 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1531 bits explicitly.
1532 * Makefile.in,configure.in: Add mips subtarget option.
1533 * configure: Update.
1534
1535Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1536
1537 * gencode.c: Add r3900 (tx39).
1538
1539
1540Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1541
1542 * gencode.c (build_instruction): Don't need to subtract 4 for
1543 JALR, just 2.
1544
1545Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1546
1547 * interp.c: Correct some HASFPU problems.
1548
1549Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1550
1551 * configure: Regenerated to track ../common/aclocal.m4 changes.
1552
1553Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1554
1555 * interp.c (mips_options): Fix samples option short form, should
1556 be `x'.
1557
1558Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1559
1560 * interp.c (sim_info): Enable info code. Was just returning.
1561
1562Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1563
1564 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1565 MFC0.
1566
1567Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1568
1569 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1570 constants.
1571 (build_instruction): Ditto for LL.
1572
1573Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1574
1575 * configure: Regenerated to track ../common/aclocal.m4 changes.
1576
1577Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1578
1579 * configure: Regenerated to track ../common/aclocal.m4 changes.
1580 * config.in: Ditto.
1581
1582Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1583
1584 * interp.c (sim_open): Add call to sim_analyze_program, update
1585 call to sim_config.
1586
1587Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1588
1589 * interp.c (sim_kill): Delete.
1590 (sim_create_inferior): Add ABFD argument. Set PC from same.
1591 (sim_load): Move code initializing trap handlers from here.
1592 (sim_open): To here.
1593 (sim_load): Delete, use sim-hload.c.
1594
1595 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1596
1597Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1598
1599 * configure: Regenerated to track ../common/aclocal.m4 changes.
1600 * config.in: Ditto.
1601
1602Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1603
1604 * interp.c (sim_open): Add ABFD argument.
1605 (sim_load): Move call to sim_config from here.
1606 (sim_open): To here. Check return status.
1607
1608Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1609
1610 * gencode.c (build_instruction): Two arg MADD should
1611 not assign result to $0.
1612
1613Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1614
1615 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1616 * sim/mips/configure.in: Regenerate.
1617
1618Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1619
1620 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1621 signed8, unsigned8 et.al. types.
1622
1623 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1624 hosts when selecting subreg.
1625
1626Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1627
1628 * interp.c (sim_engine_run): Reset the ZERO register to zero
1629 regardless of FEATURE_WARN_ZERO.
1630 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1631
1632Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1633
1634 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1635 (SignalException): For BreakPoints ignore any mode bits and just
1636 save the PC.
1637 (SignalException): Always set the CAUSE register.
1638
1639Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1640
1641 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1642 exception has been taken.
1643
1644 * interp.c: Implement the ERET and mt/f sr instructions.
1645
1646Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1647
1648 * interp.c (SignalException): Don't bother restarting an
1649 interrupt.
1650
1651Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1652
1653 * interp.c (SignalException): Really take an interrupt.
1654 (interrupt_event): Only deliver interrupts when enabled.
1655
1656Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1657
1658 * interp.c (sim_info): Only print info when verbose.
1659 (sim_info) Use sim_io_printf for output.
1660
1661Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1662
1663 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1664 mips architectures.
1665
1666Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1667
1668 * interp.c (sim_do_command): Check for common commands if a
1669 simulator specific command fails.
1670
1671Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1672
1673 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1674 and simBE when DEBUG is defined.
1675
1676Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1677
1678 * interp.c (interrupt_event): New function. Pass exception event
1679 onto exception handler.
1680
1681 * configure.in: Check for stdlib.h.
1682 * configure: Regenerate.
1683
1684 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1685 variable declaration.
1686 (build_instruction): Initialize memval1.
1687 (build_instruction): Add UNUSED attribute to byte, bigend,
1688 reverse.
1689 (build_operands): Ditto.
1690
1691 * interp.c: Fix GCC warnings.
1692 (sim_get_quit_code): Delete.
1693
1694 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1695 * Makefile.in: Ditto.
1696 * configure: Re-generate.
1697
1698 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1699
1700Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1701
1702 * interp.c (mips_option_handler): New function parse argumes using
1703 sim-options.
1704 (myname): Replace with STATE_MY_NAME.
1705 (sim_open): Delete check for host endianness - performed by
1706 sim_config.
1707 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1708 (sim_open): Move much of the initialization from here.
1709 (sim_load): To here. After the image has been loaded and
1710 endianness set.
1711 (sim_open): Move ColdReset from here.
1712 (sim_create_inferior): To here.
1713 (sim_open): Make FP check less dependant on host endianness.
1714
1715 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1716 run.
1717 * interp.c (sim_set_callbacks): Delete.
1718
1719 * interp.c (membank, membank_base, membank_size): Replace with
1720 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1721 (sim_open): Remove call to callback->init. gdb/run do this.
1722
1723 * interp.c: Update
1724
1725 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1726
1727 * interp.c (big_endian_p): Delete, replaced by
1728 current_target_byte_order.
1729
1730Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1731
1732 * interp.c (host_read_long, host_read_word, host_swap_word,
1733 host_swap_long): Delete. Using common sim-endian.
1734 (sim_fetch_register, sim_store_register): Use H2T.
1735 (pipeline_ticks): Delete. Handled by sim-events.
1736 (sim_info): Update.
1737 (sim_engine_run): Update.
1738
1739Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1740
1741 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1742 reason from here.
1743 (SignalException): To here. Signal using sim_engine_halt.
1744 (sim_stop_reason): Delete, moved to common.
1745
1746Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1747
1748 * interp.c (sim_open): Add callback argument.
1749 (sim_set_callbacks): Delete SIM_DESC argument.
1750 (sim_size): Ditto.
1751
1752Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1753
1754 * Makefile.in (SIM_OBJS): Add common modules.
1755
1756 * interp.c (sim_set_callbacks): Also set SD callback.
1757 (set_endianness, xfer_*, swap_*): Delete.
1758 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1759 Change to functions using sim-endian macros.
1760 (control_c, sim_stop): Delete, use common version.
1761 (simulate): Convert into.
1762 (sim_engine_run): This function.
1763 (sim_resume): Delete.
1764
1765 * interp.c (simulation): New variable - the simulator object.
1766 (sim_kind): Delete global - merged into simulation.
1767 (sim_load): Cleanup. Move PC assignment from here.
1768 (sim_create_inferior): To here.
1769
1770 * sim-main.h: New file.
1771 * interp.c (sim-main.h): Include.
1772
1773Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1774
1775 * configure: Regenerated to track ../common/aclocal.m4 changes.
1776
1777Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1778
1779 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1780
1781Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1782
1783 * gencode.c (build_instruction): DIV instructions: check
1784 for division by zero and integer overflow before using
1785 host's division operation.
1786
1787Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1788
1789 * Makefile.in (SIM_OBJS): Add sim-load.o.
1790 * interp.c: #include bfd.h.
1791 (target_byte_order): Delete.
1792 (sim_kind, myname, big_endian_p): New static locals.
1793 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1794 after argument parsing. Recognize -E arg, set endianness accordingly.
1795 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1796 load file into simulator. Set PC from bfd.
1797 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1798 (set_endianness): Use big_endian_p instead of target_byte_order.
1799
1800Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1801
1802 * interp.c (sim_size): Delete prototype - conflicts with
1803 definition in remote-sim.h. Correct definition.
1804
1805Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1806
1807 * configure: Regenerated to track ../common/aclocal.m4 changes.
1808 * config.in: Ditto.
1809
1810Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1811
1812 * interp.c (sim_open): New arg `kind'.
1813
1814 * configure: Regenerated to track ../common/aclocal.m4 changes.
1815
1816Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1817
1818 * configure: Regenerated to track ../common/aclocal.m4 changes.
1819
1820Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1821
1822 * interp.c (sim_open): Set optind to 0 before calling getopt.
1823
1824Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1825
1826 * configure: Regenerated to track ../common/aclocal.m4 changes.
1827
1828Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1829
1830 * interp.c : Replace uses of pr_addr with pr_uword64
1831 where the bit length is always 64 independent of SIM_ADDR.
1832 (pr_uword64) : added.
1833
1834Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1835
1836 * configure: Re-generate.
1837
1838Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1839
1840 * configure: Regenerate to track ../common/aclocal.m4 changes.
1841
1842Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1843
1844 * interp.c (sim_open): New SIM_DESC result. Argument is now
1845 in argv form.
1846 (other sim_*): New SIM_DESC argument.
1847
1848Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1849
1850 * interp.c: Fix printing of addresses for non-64-bit targets.
1851 (pr_addr): Add function to print address based on size.
1852
1853Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1854
1855 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1856
1857Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1858
1859 * gencode.c (build_mips16_operands): Correct computation of base
1860 address for extended PC relative instruction.
1861
1862Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1863
1864 * interp.c (mips16_entry): Add support for floating point cases.
1865 (SignalException): Pass floating point cases to mips16_entry.
1866 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1867 registers.
1868 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1869 or fmt_word.
1870 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1871 and then set the state to fmt_uninterpreted.
1872 (COP_SW): Temporarily set the state to fmt_word while calling
1873 ValueFPR.
1874
1875Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1876
1877 * gencode.c (build_instruction): The high order may be set in the
1878 comparison flags at any ISA level, not just ISA 4.
1879
1880Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1881
1882 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1883 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1884 * configure.in: sinclude ../common/aclocal.m4.
1885 * configure: Regenerated.
1886
1887Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1888
1889 * configure: Rebuild after change to aclocal.m4.
1890
1891Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1892
1893 * configure configure.in Makefile.in: Update to new configure
1894 scheme which is more compatible with WinGDB builds.
1895 * configure.in: Improve comment on how to run autoconf.
1896 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1897 * Makefile.in: Use autoconf substitution to install common
1898 makefile fragment.
1899
1900Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1901
1902 * gencode.c (build_instruction): Use BigEndianCPU instead of
1903 ByteSwapMem.
1904
1905Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1906
1907 * interp.c (sim_monitor): Make output to stdout visible in
1908 wingdb's I/O log window.
1909
1910Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1911
1912 * support.h: Undo previous change to SIGTRAP
1913 and SIGQUIT values.
1914
1915Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1916
1917 * interp.c (store_word, load_word): New static functions.
1918 (mips16_entry): New static function.
1919 (SignalException): Look for mips16 entry and exit instructions.
1920 (simulate): Use the correct index when setting fpr_state after
1921 doing a pending move.
1922
1923Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1924
1925 * interp.c: Fix byte-swapping code throughout to work on
1926 both little- and big-endian hosts.
1927
1928Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1929
1930 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1931 with gdb/config/i386/xm-windows.h.
1932
1933Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1934
1935 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1936 that messes up arithmetic shifts.
1937
1938Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1939
1940 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1941 SIGTRAP and SIGQUIT for _WIN32.
1942
1943Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1944
1945 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1946 force a 64 bit multiplication.
1947 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1948 destination register is 0, since that is the default mips16 nop
1949 instruction.
1950
1951Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1952
1953 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1954 (build_endian_shift): Don't check proc64.
1955 (build_instruction): Always set memval to uword64. Cast op2 to
1956 uword64 when shifting it left in memory instructions. Always use
1957 the same code for stores--don't special case proc64.
1958
1959 * gencode.c (build_mips16_operands): Fix base PC value for PC
1960 relative operands.
1961 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1962 jal instruction.
1963 * interp.c (simJALDELAYSLOT): Define.
1964 (JALDELAYSLOT): Define.
1965 (INDELAYSLOT, INJALDELAYSLOT): Define.
1966 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1967
1968Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1969
1970 * interp.c (sim_open): add flush_cache as a PMON routine
1971 (sim_monitor): handle flush_cache by ignoring it
1972
1973Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1974
1975 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1976 BigEndianMem.
1977 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1978 (BigEndianMem): Rename to ByteSwapMem and change sense.
1979 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1980 BigEndianMem references to !ByteSwapMem.
1981 (set_endianness): New function, with prototype.
1982 (sim_open): Call set_endianness.
1983 (sim_info): Use simBE instead of BigEndianMem.
1984 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1985 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1986 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1987 ifdefs, keeping the prototype declaration.
1988 (swap_word): Rewrite correctly.
1989 (ColdReset): Delete references to CONFIG. Delete endianness related
1990 code; moved to set_endianness.
1991
1992Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1993
1994 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1995 * interp.c (CHECKHILO): Define away.
1996 (simSIGINT): New macro.
1997 (membank_size): Increase from 1MB to 2MB.
1998 (control_c): New function.
1999 (sim_resume): Rename parameter signal to signal_number. Add local
2000 variable prev. Call signal before and after simulate.
2001 (sim_stop_reason): Add simSIGINT support.
2002 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2003 functions always.
2004 (sim_warning): Delete call to SignalException. Do call printf_filtered
2005 if logfh is NULL.
2006 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2007 a call to sim_warning.
2008
2009Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2010
2011 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2012 16 bit instructions.
2013
2014Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2015
2016 Add support for mips16 (16 bit MIPS implementation):
2017 * gencode.c (inst_type): Add mips16 instruction encoding types.
2018 (GETDATASIZEINSN): Define.
2019 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2020 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2021 mtlo.
2022 (MIPS16_DECODE): New table, for mips16 instructions.
2023 (bitmap_val): New static function.
2024 (struct mips16_op): Define.
2025 (mips16_op_table): New table, for mips16 operands.
2026 (build_mips16_operands): New static function.
2027 (process_instructions): If PC is odd, decode a mips16
2028 instruction. Break out instruction handling into new
2029 build_instruction function.
2030 (build_instruction): New static function, broken out of
2031 process_instructions. Check modifiers rather than flags for SHIFT
2032 bit count and m[ft]{hi,lo} direction.
2033 (usage): Pass program name to fprintf.
2034 (main): Remove unused variable this_option_optind. Change
2035 ``*loptarg++'' to ``loptarg++''.
2036 (my_strtoul): Parenthesize && within ||.
2037 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2038 (simulate): If PC is odd, fetch a 16 bit instruction, and
2039 increment PC by 2 rather than 4.
2040 * configure.in: Add case for mips16*-*-*.
2041 * configure: Rebuild.
2042
2043Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2044
2045 * interp.c: Allow -t to enable tracing in standalone simulator.
2046 Fix garbage output in trace file and error messages.
2047
2048Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2049
2050 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2051 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2052 * configure.in: Simplify using macros in ../common/aclocal.m4.
2053 * configure: Regenerated.
2054 * tconfig.in: New file.
2055
2056Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2057
2058 * interp.c: Fix bugs in 64-bit port.
2059 Use ansi function declarations for msvc compiler.
2060 Initialize and test file pointer in trace code.
2061 Prevent duplicate definition of LAST_EMED_REGNUM.
2062
2063Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2064
2065 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2066
2067Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2068
2069 * interp.c (SignalException): Check for explicit terminating
2070 breakpoint value.
2071 * gencode.c: Pass instruction value through SignalException()
2072 calls for Trap, Breakpoint and Syscall.
2073
2074Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2075
2076 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2077 only used on those hosts that provide it.
2078 * configure.in: Add sqrt() to list of functions to be checked for.
2079 * config.in: Re-generated.
2080 * configure: Re-generated.
2081
2082Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2083
2084 * gencode.c (process_instructions): Call build_endian_shift when
2085 expanding STORE RIGHT, to fix swr.
2086 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2087 clear the high bits.
2088 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2089 Fix float to int conversions to produce signed values.
2090
2091Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2092
2093 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2094 (process_instructions): Correct handling of nor instruction.
2095 Correct shift count for 32 bit shift instructions. Correct sign
2096 extension for arithmetic shifts to not shift the number of bits in
2097 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2098 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2099 Fix madd.
2100 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2101 It's OK to have a mult follow a mult. What's not OK is to have a
2102 mult follow an mfhi.
2103 (Convert): Comment out incorrect rounding code.
2104
2105Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2106
2107 * interp.c (sim_monitor): Improved monitor printf
2108 simulation. Tidied up simulator warnings, and added "--log" option
2109 for directing warning message output.
2110 * gencode.c: Use sim_warning() rather than WARNING macro.
2111
2112Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2113
2114 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2115 getopt1.o, rather than on gencode.c. Link objects together.
2116 Don't link against -liberty.
2117 (gencode.o, getopt.o, getopt1.o): New targets.
2118 * gencode.c: Include <ctype.h> and "ansidecl.h".
2119 (AND): Undefine after including "ansidecl.h".
2120 (ULONG_MAX): Define if not defined.
2121 (OP_*): Don't define macros; now defined in opcode/mips.h.
2122 (main): Call my_strtoul rather than strtoul.
2123 (my_strtoul): New static function.
2124
2125Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2126
2127 * gencode.c (process_instructions): Generate word64 and uword64
2128 instead of `long long' and `unsigned long long' data types.
2129 * interp.c: #include sysdep.h to get signals, and define default
2130 for SIGBUS.
2131 * (Convert): Work around for Visual-C++ compiler bug with type
2132 conversion.
2133 * support.h: Make things compile under Visual-C++ by using
2134 __int64 instead of `long long'. Change many refs to long long
2135 into word64/uword64 typedefs.
2136
2137Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2138
2139 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2140 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2141 (docdir): Removed.
2142 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2143 (AC_PROG_INSTALL): Added.
2144 (AC_PROG_CC): Moved to before configure.host call.
2145 * configure: Rebuilt.
2146
2147Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2148
2149 * configure.in: Define @SIMCONF@ depending on mips target.
2150 * configure: Rebuild.
2151 * Makefile.in (run): Add @SIMCONF@ to control simulator
2152 construction.
2153 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2154 * interp.c: Remove some debugging, provide more detailed error
2155 messages, update memory accesses to use LOADDRMASK.
2156
2157Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2158
2159 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2160 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2161 stamp-h.
2162 * configure: Rebuild.
2163 * config.in: New file, generated by autoheader.
2164 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2165 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2166 HAVE_ANINT and HAVE_AINT, as appropriate.
2167 * Makefile.in (run): Use @LIBS@ rather than -lm.
2168 (interp.o): Depend upon config.h.
2169 (Makefile): Just rebuild Makefile.
2170 (clean): Remove stamp-h.
2171 (mostlyclean): Make the same as clean, not as distclean.
2172 (config.h, stamp-h): New targets.
2173
2174Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2175
2176 * interp.c (ColdReset): Fix boolean test. Make all simulator
2177 globals static.
2178
2179Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2180
2181 * interp.c (xfer_direct_word, xfer_direct_long,
2182 swap_direct_word, swap_direct_long, xfer_big_word,
2183 xfer_big_long, xfer_little_word, xfer_little_long,
2184 swap_word,swap_long): Added.
2185 * interp.c (ColdReset): Provide function indirection to
2186 host<->simulated_target transfer routines.
2187 * interp.c (sim_store_register, sim_fetch_register): Updated to
2188 make use of indirected transfer routines.
2189
2190Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2191
2192 * gencode.c (process_instructions): Ensure FP ABS instruction
2193 recognised.
2194 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2195 system call support.
2196
2197Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2198
2199 * interp.c (sim_do_command): Complain if callback structure not
2200 initialised.
2201
2202Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2203
2204 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2205 support for Sun hosts.
2206 * Makefile.in (gencode): Ensure the host compiler and libraries
2207 used for cross-hosted build.
2208
2209Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2210
2211 * interp.c, gencode.c: Some more (TODO) tidying.
2212
2213Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2214
2215 * gencode.c, interp.c: Replaced explicit long long references with
2216 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2217 * support.h (SET64LO, SET64HI): Macros added.
2218
2219Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2220
2221 * configure: Regenerate with autoconf 2.7.
2222
2223Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2224
2225 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2226 * support.h: Remove superfluous "1" from #if.
2227 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2228
2229Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2230
2231 * interp.c (StoreFPR): Control UndefinedResult() call on
2232 WARN_RESULT manifest.
2233
2234Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2235
2236 * gencode.c: Tidied instruction decoding, and added FP instruction
2237 support.
2238
2239 * interp.c: Added dineroIII, and BSD profiling support. Also
2240 run-time FP handling.
2241
2242Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2243
2244 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2245 gencode.c, interp.c, support.h: created.
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