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sim: unify various library testing logic
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
07490bf8
MF		 12021-06-19 Mike Frysinger <vapier@gentoo.org>
2
3 * configure.ac: Delete AC_CHECK_LIB calls.
4 * configure: Regenerate.
5
47ce766a
MF		 62021-06-18 Mike Frysinger <vapier@gentoo.org>
7
8 * aclocal.m4, configure: Regenerate.
9
982c3a65
MF		 102021-06-18 Mike Frysinger <vapier@gentoo.org>
11
12 * Makefile.in (SIM_WERROR_CFLAGS): New variable.
13 * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
14 * configure: Regenerate.
15
1fef66b0
MF		 162021-06-18 Mike Frysinger <vapier@gentoo.org>
17
18 * interp.c: Include sim-signal.h.
19
f9a4d543
MF		 202021-06-17 Mike Frysinger <vapier@gentoo.org>
21
22 * configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
23 * aclocal.m4, configure: Regenerate.
24
b80d4475
MF		 252021-06-16 Mike Frysinger <vapier@gentoo.org>
26
27 * interp.c (dotrace): Make comment const.
28 * sim-main.h (dotrace): Likewise. Add ATTRIBUTE_PRINTF.
29
6828a302
MF		 302021-06-16 Mike Frysinger <vapier@gentoo.org>
31
32 * interp.c (sim_monitor): Change ap type to address_word*.
33 (_P, P): New macros. Rewrite dynamic printf logic to use these.
34
df32b446
MF		 352021-06-16 Mike Frysinger <vapier@gentoo.org>
36
37 * dv-tx3904sio.c (tx3904sio_fifo_push): Change next_buf to
38 unsigned_1.
39
7b2298cb
MF		 402021-06-16 Mike Frysinger <vapier@gentoo.org>
41
42 * dv-tx3904irc.c (tx3904irc_io_write_buffer): Initialize
43 register_value to 0.
44
a8a3d907
MF		 452021-06-16 Mike Frysinger <vapier@gentoo.org>
46
47 * configure: Regenerate.
48
dae666c9
MF		 492021-06-16 Mike Frysinger <vapier@gentoo.org>
50
51 * interp.c (sim_open): Change %lx to %x and PRIx macros.
52
52d37d2c
MF		 532021-06-16 Mike Frysinger <vapier@gentoo.org>
54
55 * configure: Regenerate.
56 * config.in: Removed.
57
bcaa61f7
MF		 582021-06-15 Mike Frysinger <vapier@gentoo.org>
59
60 * config.in, configure: Regenerate.
61
ba307cdd
MF		 622021-06-12 Mike Frysinger <vapier@gentoo.org>
63
64 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
65
dba333c1
MF		 662021-06-12 Mike Frysinger <vapier@gentoo.org>
67
68 * aclocal.m4, config.in, configure: Regenerate.
69
b15c5d7a
MF		 702021-06-12 Mike Frysinger <vapier@gentoo.org>
71
72 * configure.ac: Delete call to AC_CHECK_FUNCS.
73 * config.in, configure: Regenerate.
74
a55b92be
MF		 752021-06-08 Mike Frysinger <vapier@gentoo.org>
76
77 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
78 with $(IGEN).
79
8ea881d9
MF		 802021-05-29 Mike Frysinger <vapier@gentoo.org>
81
82 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
83
b312488f
FS		 842021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
85
168671c1
FS		 86 * interp.c (sim_open): Add shadow mappings from 32-bit
87 address space to 64-bit sign-extended address space.
88
892021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
90
b312488f
FS		 91 * interp.c (sim_create_inferior): Only truncate sign extension
92 bits for 32-bit target models.
93
f4fdd845
MF		 942021-05-17 Mike Frysinger <vapier@gentoo.org>
95
96 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
97
8ea7241c
MF		 982021-05-17 Mike Frysinger <vapier@gentoo.org>
99
100 * interp.c (sim_open): Switch to sim_state_alloc_extra.
101 * micromips.igen: Change SD to mips_sim_state.
102 * micromipsrun.c (sim_engine_run): Likewise.
103 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
104 (watch_options_install): Delete.
105 (struct swatch): Delete.
106 (struct sim_state): Delete.
107 (struct mips_sim_state): New struct.
108 (MIPS_SIM_STATE): Define.
109
6df01ab8
MF		 1102021-05-16 Mike Frysinger <vapier@gentoo.org>
111
112 * interp.c: Replace config.h include with defs.h.
113 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
114 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
115 Include defs.h.
116
79633c12
MF		 1172021-05-16 Mike Frysinger <vapier@gentoo.org>
118
119 * config.in, configure: Regenerate.
120
df68e12b
MF		 1212021-05-14 Mike Frysinger <vapier@gentoo.org>
122
123 * interp.c: Update include path.
124
77c0fdb7
MF		 1252021-05-04 Mike Frysinger <vapier@gentoo.org>
126
127 * dv-tx3904sio.c: Include stdlib.h.
128
9b1af85c
MF		 1292021-05-04 Mike Frysinger <vapier@gentoo.org>
130
131 * configure.ac (hw_extra_devices): Inline contents into
132 SIM_AC_OPTION_HARDWARE and delete.
133 * configure: Regenerate.
134
d97ba9c6
MF		 1352021-05-04 Mike Frysinger <vapier@gentoo.org>
136
137 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
138 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
139 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
140 * configure: Regenerate.
141
4df817de
MF		 1422021-05-04 Mike Frysinger <vapier@gentoo.org>
143
144 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
145
aa0fca16
MF		 1462021-05-04 Mike Frysinger <vapier@gentoo.org>
147
148 * configure: Regenerate.
149
adbaa7b8
MF		 1502021-05-01 Mike Frysinger <vapier@gentoo.org>
151
152 * cp1.c (store_fcr): Mark static.
153
fe348617
MF		 1542021-05-01 Mike Frysinger <vapier@gentoo.org>
155
156 * config.in, configure: Regenerate.
157
9d903352
MF		 1582021-04-23 Mike Frysinger <vapier@gentoo.org>
159
160 * configure.ac (hw_enabled): Delete.
161 (SIM_AC_OPTION_HARDWARE): Delete first two args.
162 * configure: Regenerate.
163
19f6a43c
TT		 1642021-04-22 Tom Tromey <tom@tromey.com>
165
166 * configure, config.in: Rebuild.
167
e7d8f1da
TT		 1682021-04-22 Tom Tromey <tom@tromey.com>
169
170 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
171 Remove.
172 (SIM_EXTRA_DEPS): New variable.
173
efd82ac7
TT		 1742021-04-22 Tom Tromey <tom@tromey.com>
175
176 * configure: Rebuild.
177
2662c237
MF		 1782021-04-21 Mike Frysinger <vapier@gentoo.org>
179
180 * aclocal.m4: Regenerate.
181
1f195bc3
SM		 1822021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
183
184 * configure: Regenerate.
185
37e9f182
MF		 1862021-04-18 Mike Frysinger <vapier@gentoo.org>
187
188 * configure: Regenerate.
189
d5a71b11
MF		 1902021-04-12 Mike Frysinger <vapier@gentoo.org>
191
192 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
193
2b8d134b
SM		 1942021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
195
196 * Makefile.in: Set ASAN_OPTIONS when running igen.
197
5c6f091a
FS		 1982021-04-04 Steve Ellcey <sellcey@mips.com>
199 Faraz Shahbazker <fshahbazker@wavecomp.com>
200
201 * interp.c (sim_monitor): Add switch entries for unlink (13),
202 lseek (14), and stat (15).
203
b6b1c790
MF		 2042021-04-02 Mike Frysinger <vapier@gentoo.org>
205
206 * Makefile.in (../igen/igen): Delete rule.
207 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
208
c2783492
MF		 2092021-04-02 Mike Frysinger <vapier@gentoo.org>
210
211 * aclocal.m4, configure: Regenerate.
212
ebe9564b
MF		 2132021-02-28 Mike Frysinger <vapier@gentoo.org>
214
215 * configure: Regenerate.
216
f8069d55
MF		 2172021-02-27 Mike Frysinger <vapier@gentoo.org>
218
219 * Makefile.in (SIM_EXTRA_ALL): Delete.
220 (all): New target.
221
760b3e8b
MF		 2222021-02-21 Mike Frysinger <vapier@gentoo.org>
223
224 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
225 * aclocal.m4, configure: Regenerate.
226
136da8cd
MF		 2272021-02-13 Mike Frysinger <vapier@gentoo.org>
228
229 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
230 * aclocal.m4, configure: Regenerate.
231
4c0d76b9
MF		 2322021-02-06 Mike Frysinger <vapier@gentoo.org>
233
234 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
235
aa09469f
MF		 2362021-02-06 Mike Frysinger <vapier@gentoo.org>
237
238 * configure: Regenerate.
239
d4e3adda
MF		 2402021-01-30 Mike Frysinger <vapier@gentoo.org>
241
242 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
243
68ed2854
MF		 2442021-01-11 Mike Frysinger <vapier@gentoo.org>
245
246 * config.in, configure: Regenerate.
247 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
248 and strings.h include.
249
50df264d
MF		 2502021-01-09 Mike Frysinger <vapier@gentoo.org>
251
252 * configure: Regenerate.
253
bf470982
MF		 2542021-01-09 Mike Frysinger <vapier@gentoo.org>
255
256 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
257 * configure: Regenerate.
258
46f900c0
MF		 2592021-01-08 Mike Frysinger <vapier@gentoo.org>
260
261 * configure: Regenerate.
262
dfb856ba
MF		 2632021-01-04 Mike Frysinger <vapier@gentoo.org>
264
265 * configure: Regenerate.
266
382bc56b
PK		 2672020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
268
269 * sim-main.c: Include <stdlib.h>.
270
ad9675dd
PK		 2712020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
272
273 * cp1.c: Include <stdlib.h>.
274
f693213d
SM		 2752020-07-29 Simon Marchi <simon.marchi@efficios.com>
276
277 * configure: Re-generate.
278
5c887dd5
JB		 2792017-09-06 John Baldwin <jhb@FreeBSD.org>
280
281 * configure: Regenerate.
282
91588b3a
MF		 2832016-11-11 Mike Frysinger <vapier@gentoo.org>
284
6cb2202b 285 PR sim/20808
91588b3a
MF		 286 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
287 and SD to sd.
288
e04659e8
MF		 2892016-11-11 Mike Frysinger <vapier@gentoo.org>
290
6cb2202b 291 PR sim/20809
e04659e8
MF		 292 * mips.igen (check_u64): Enable for `r3900'.
293
1554f758
MF		 2942016-02-05 Mike Frysinger <vapier@gentoo.org>
295
296 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
297 STATE_PROG_BFD (sd).
298 * configure: Regenerate.
299
3d304f48
AB		 3002016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
301 Maciej W. Rozycki <macro@imgtec.com>
302
303 PR sim/19441
304 * micromips.igen (delayslot_micromips): Enable for `micromips32',
305 `micromips64' and `micromipsdsp' only.
306 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
307 (do_micromips_jalr, do_micromips_jal): Likewise.
308 (compute_movep_src_reg): Likewise.
309 (compute_andi16_imm): Likewise.
310 (convert_fmt_micromips): Likewise.
311 (convert_fmt_micromips_cvt_d): Likewise.
312 (convert_fmt_micromips_cvt_s): Likewise.
313 (FMT_MICROMIPS): Likewise.
314 (FMT_MICROMIPS_CVT_D): Likewise.
315 (FMT_MICROMIPS_CVT_S): Likewise.
316
b36d953b
MF		 3172016-01-12 Mike Frysinger <vapier@gentoo.org>
318
319 * interp.c: Include elf-bfd.h.
320 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
321 ELFCLASS32.
322
ce39bd38
MF		 3232016-01-10 Mike Frysinger <vapier@gentoo.org>
324
325 * config.in, configure: Regenerate.
326
99d8e879
MF		 3272016-01-10 Mike Frysinger <vapier@gentoo.org>
328
329 * configure: Regenerate.
330
35656e95
MF		 3312016-01-10 Mike Frysinger <vapier@gentoo.org>
332
333 * configure: Regenerate.
334
16f7876d
MF		 3352016-01-10 Mike Frysinger <vapier@gentoo.org>
336
337 * configure: Regenerate.
338
e19418e0
MF		 3392016-01-10 Mike Frysinger <vapier@gentoo.org>
340
341 * configure: Regenerate.
342
6d90347b
MF		 3432016-01-10 Mike Frysinger <vapier@gentoo.org>
344
345 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
346 * configure: Regenerate.
347
347fe5bb
MF		 3482016-01-10 Mike Frysinger <vapier@gentoo.org>
349
350 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
351 * configure: Regenerate.
352
22be3fbe
MF		 3532016-01-10 Mike Frysinger <vapier@gentoo.org>
354
355 * configure: Regenerate.
356
0dc73ef7
MF		 3572016-01-10 Mike Frysinger <vapier@gentoo.org>
358
359 * configure: Regenerate.
360
936df756
MF		 3612016-01-09 Mike Frysinger <vapier@gentoo.org>
362
363 * config.in, configure: Regenerate.
364
2e3d4f4d
MF		 3652016-01-06 Mike Frysinger <vapier@gentoo.org>
366
367 * interp.c (sim_open): Mark argv const.
368 (sim_create_inferior): Mark argv and env const.
369
9bbf6f91
MF		 3702016-01-04 Mike Frysinger <vapier@gentoo.org>
371
372 * configure: Regenerate.
373
77cf2ef5
MF		 3742016-01-03 Mike Frysinger <vapier@gentoo.org>
375
376 * interp.c (sim_open): Update sim_parse_args comment.
377
0cb8d851
MF		 3782016-01-03 Mike Frysinger <vapier@gentoo.org>
379
380 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
381 * configure: Regenerate.
382
1ac72f06
MF		 3832016-01-02 Mike Frysinger <vapier@gentoo.org>
384
385 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
386 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
387 * configure: Regenerate.
388 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
389
d47f5b30
MF		 3902016-01-02 Mike Frysinger <vapier@gentoo.org>
391
392 * dv-tx3904cpu.c (CPU, SD): Delete.
393
e1211e55
MF		 3942015-12-30 Mike Frysinger <vapier@gentoo.org>
395
396 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
397 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
398 (sim_store_register): Rename to ...
399 (mips_reg_store): ... this. Delete local cpu var.
400 Update sim_io_eprintf calls.
401 (sim_fetch_register): Rename to ...
402 (mips_reg_fetch): ... this. Delete local cpu var.
403 Update sim_io_eprintf calls.
404
5e744ef8
MF		 4052015-12-27 Mike Frysinger <vapier@gentoo.org>
406
407 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
408
1b393626
MF		 4092015-12-26 Mike Frysinger <vapier@gentoo.org>
410
411 * config.in, configure: Regenerate.
412
26f8bf63
MF		 4132015-12-26 Mike Frysinger <vapier@gentoo.org>
414
415 * interp.c (sim_write, sim_read): Delete.
416 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
417 (load_word): Likewise.
418 * micromips.igen (cache): Likewise.
419 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
420 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
421 do_store_left, do_store_right, do_load_double, do_store_double):
422 Likewise.
423 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
424 (do_prefx): Likewise.
425 * sim-main.c (address_translation, prefetch): Delete.
426 (ifetch32, ifetch16): Delete call to AddressTranslation and set
427 paddr=vaddr.
428 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
429 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
430 (LoadMemory, StoreMemory): Delete CCA arg.
431
ef04e371
MF		 4322015-12-24 Mike Frysinger <vapier@gentoo.org>
433
434 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
435 * configure: Regenerated.
436
cb379ede
MF		 4372015-12-24 Mike Frysinger <vapier@gentoo.org>
438
439 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
440 * tconfig.h: Delete.
441
26936211
MF		 4422015-12-24 Mike Frysinger <vapier@gentoo.org>
443
444 * tconfig.h (SIM_HANDLES_LMA): Delete.
445
84e8e361
MF		 4462015-12-24 Mike Frysinger <vapier@gentoo.org>
447
448 * sim-main.h (WITH_WATCHPOINTS): Delete.
449
3cabaf66
MF		 4502015-12-24 Mike Frysinger <vapier@gentoo.org>
451
452 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
453
8abe6c66
MF		 4542015-12-24 Mike Frysinger <vapier@gentoo.org>
455
456 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
457
1d19cae7
DV		 4582015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
459
460 * micromips.igen (process_isa_mode): Fix left shift of negative
461 value.
462
cdf850e9
MF		 4632015-11-17 Mike Frysinger <vapier@gentoo.org>
464
465 * sim-main.h (WITH_MODULO_MEMORY): Delete.
466
797eee42
MF		 4672015-11-15 Mike Frysinger <vapier@gentoo.org>
468
469 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
470
6e4f085c
MF		 4712015-11-14 Mike Frysinger <vapier@gentoo.org>
472
473 * interp.c (sim_close): Rename to ...
474 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
475 sim_io_shutdown.
476 * sim-main.h (mips_sim_close): Declare.
477 (SIM_CLOSE_HOOK): Define.
478
8e394ffc
AB		 4792015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
480 Ali Lown <ali.lown@imgtec.com>
481
482 * Makefile.in (tmp-micromips): New rule.
483 (tmp-mach-multi): Add support for micromips.
484 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
485 that works for both mips64 and micromips64.
486 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
487 micromips32.
488 Add build support for micromips.
489 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
490 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
491 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
492 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
493 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
494 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
495 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
496 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
497 Refactored instruction code to use these functions.
498 * dsp2.igen: Refactored instruction code to use the new functions.
499 * interp.c (decode_coproc): Refactored to work with any instruction
500 encoding.
501 (isa_mode): New variable
502 (RSVD_INSTRUCTION): Changed to 0x00000039.
503 * m16.igen (BREAK16): Refactored instruction to use do_break16.
504 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
505 * micromips.dc: New file.
506 * micromips.igen: New file.
507 * micromips16.dc: New file.
508 * micromipsdsp.igen: New file.
509 * micromipsrun.c: New file.
510 * mips.igen (do_swc1): Changed to work with any instruction encoding.
511 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
512 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
513 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
514 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
515 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
516 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
517 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
518 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
519 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
520 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
521 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
522 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
523 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
524 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
525 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
526 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
527 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
528 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
529 instructions.
530 Refactored instruction code to use these functions.
531 (RSVD): Changed to use new reserved instruction.
532 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
533 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
534 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
535 do_store_double): Added micromips32 and micromips64 models.
536 Added include for micromips.igen and micromipsdsp.igen
537 Add micromips32 and micromips64 models.
538 (DecodeCoproc): Updated to use new macro definition.
539 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
540 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
541 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
542 Refactored instruction code to use these functions.
543 * sim-main.h (CP0_operation): New enum.
544 (DecodeCoproc): Updated macro.
545 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
546 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
547 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
548 ISA_MODE_MICROMIPS): New defines.
549 (sim_state): Add isa_mode field.
550
8d0978fb
MF		 5512015-06-23 Mike Frysinger <vapier@gentoo.org>
552
553 * configure: Regenerate.
554
306f4178
MF		 5552015-06-12 Mike Frysinger <vapier@gentoo.org>
556
557 * configure.ac: Change configure.in to configure.ac.
558 * configure: Regenerate.
559
a3487082
MF		 5602015-06-12 Mike Frysinger <vapier@gentoo.org>
561
562 * configure: Regenerate.
563
29bc024d
MF		 5642015-06-12 Mike Frysinger <vapier@gentoo.org>
565
566 * interp.c [TRACE]: Delete.
567 (TRACE): Change to WITH_TRACE_ANY_P.
568 [!WITH_TRACE_ANY_P] (open_trace): Define.
569 (mips_option_handler, open_trace, sim_close, dotrace):
570 Change defined(TRACE) to WITH_TRACE_ANY_P.
571 (sim_open): Delete TRACE ifdef check.
572 * sim-main.c (load_memory): Delete TRACE ifdef check.
573 (store_memory): Likewise.
574 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
575 [!WITH_TRACE_ANY_P] (dotrace): Define.
576
3ebe2863
MF		 5772015-04-18 Mike Frysinger <vapier@gentoo.org>
578
579 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
580 comments.
581
20bca71d
MF		 5822015-04-18 Mike Frysinger <vapier@gentoo.org>
583
584 * sim-main.h (SIM_CPU): Delete.
585
7e83aa92
MF		 5862015-04-18 Mike Frysinger <vapier@gentoo.org>
587
588 * sim-main.h (sim_cia): Delete.
589
034685f9
MF		 5902015-04-17 Mike Frysinger <vapier@gentoo.org>
591
592 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
593 PU_PC_GET.
594 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
595 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
596 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
597 CIA_SET to CPU_PC_SET.
598 * sim-main.h (CIA_GET, CIA_SET): Delete.
599
78e9aa70
MF		 6002015-04-15 Mike Frysinger <vapier@gentoo.org>
601
602 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
603 * sim-main.h (STATE_CPU): Delete.
604
bf12d44e
MF		 6052015-04-13 Mike Frysinger <vapier@gentoo.org>
606
607 * configure: Regenerate.
608
7bebb329
MF		 6092015-04-13 Mike Frysinger <vapier@gentoo.org>
610
611 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
612 * interp.c (mips_pc_get, mips_pc_set): New functions.
613 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
614 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
615 (sim_pc_get): Delete.
616 * sim-main.h (SIM_CPU): Define.
617 (struct sim_state): Change cpu to an array of pointers.
618 (STATE_CPU): Drop &.
619
8ac57fbd
MF		 6202015-04-13 Mike Frysinger <vapier@gentoo.org>
621
622 * interp.c (mips_option_handler, open_trace, sim_close,
623 sim_write, sim_read, sim_store_register, sim_fetch_register,
624 sim_create_inferior, pr_addr, pr_uword64): Convert old style
625 prototypes.
626 (sim_open): Convert old style prototype. Change casts with
627 sim_write to unsigned char *.
628 (fetch_str): Change null to unsigned char, and change cast to
629 unsigned char *.
630 (sim_monitor): Change c & ch to unsigned char. Change cast to
631 unsigned char *.
632
e787f858
MF		 6332015-04-12 Mike Frysinger <vapier@gentoo.org>
634
635 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
636
122bbfb5
MF		 6372015-04-06 Mike Frysinger <vapier@gentoo.org>
638
639 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
640
0fe84f3f
MF		 6412015-04-01 Mike Frysinger <vapier@gentoo.org>
642
643 * tconfig.h (SIM_HAVE_PROFILE): Delete.
644
aadc9410
MF		 6452015-03-31 Mike Frysinger <vapier@gentoo.org>
646
647 * config.in, configure: Regenerate.
648
05f53ed6
MF		 6492015-03-24 Mike Frysinger <vapier@gentoo.org>
650
651 * interp.c (sim_pc_get): New function.
652
c0931f26
MF		 6532015-03-24 Mike Frysinger <vapier@gentoo.org>
654
655 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
656 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
657
30452bbe
MF		 6582015-03-24 Mike Frysinger <vapier@gentoo.org>
659
660 * configure: Regenerate.
661
64dd13df
MF		 6622015-03-23 Mike Frysinger <vapier@gentoo.org>
663
664 * configure: Regenerate.
665
49cd1634
MF		 6662015-03-23 Mike Frysinger <vapier@gentoo.org>
667
668 * configure: Regenerate.
669 * configure.ac (mips_extra_objs): Delete.
670 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
671 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
672
3649cb06
MF		 6732015-03-23 Mike Frysinger <vapier@gentoo.org>
674
675 * configure: Regenerate.
676 * configure.ac: Delete sim_hw checks for dv-sockser.
677
ae7d0cac
MF		 6782015-03-16 Mike Frysinger <vapier@gentoo.org>
679
680 * config.in, configure: Regenerate.
681 * tconfig.in: Rename file ...
682 * tconfig.h: ... here.
683
8406bb59
MF		 6842015-03-15 Mike Frysinger <vapier@gentoo.org>
685
686 * tconfig.in: Delete includes.
687 [HAVE_DV_SOCKSER]: Delete.
688
465fb143
MF		 6892015-03-14 Mike Frysinger <vapier@gentoo.org>
690
691 * Makefile.in (SIM_RUN_OBJS): Delete.
692
5cddc23a
MF		 6932015-03-14 Mike Frysinger <vapier@gentoo.org>
694
695 * configure.ac (AC_CHECK_HEADERS): Delete.
696 * aclocal.m4, configure: Regenerate.
697
2974be62
AM		 6982014-08-19 Alan Modra <amodra@gmail.com>
699
700 * configure: Regenerate.
701
faa743bb
RM		 7022014-08-15 Roland McGrath <mcgrathr@google.com>
703
704 * configure: Regenerate.
705 * config.in: Regenerate.
706
1a8a700e
MF		 7072014-03-04 Mike Frysinger <vapier@gentoo.org>
708
709 * configure: Regenerate.
710
bf3d9781
AM		 7112013-09-23 Alan Modra <amodra@gmail.com>
712
713 * configure: Regenerate.
714
31e6ad7d
MF		 7152013-06-03 Mike Frysinger <vapier@gentoo.org>
716
717 * aclocal.m4, configure: Regenerate.
718
d3685d60
TT		 7192013-05-10 Freddie Chopin <freddie_chopin@op.pl>
720
721 * configure: Rebuild.
722
1517bd27
MF		 7232013-03-26 Mike Frysinger <vapier@gentoo.org>
724
725 * configure: Regenerate.
726
3be31516
JS		 7272013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
728
729 * configure.ac: Address use of dv-sockser.o.
730 * tconfig.in: Conditionalize use of dv_sockser_install.
731 * configure: Regenerated.
732 * config.in: Regenerated.
733
37cb8f8e
SE		 7342012-10-04 Chao-ying Fu <fu@mips.com>
735 Steve Ellcey <sellcey@mips.com>
736
737 * mips/mips3264r2.igen (rdhwr): New.
738
87c8644f
JS		 7392012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
740
741 * configure.ac: Always link against dv-sockser.o.
742 * configure: Regenerate.
743
5f3ef9d0
JB		 7442012-06-15 Joel Brobecker <brobecker@adacore.com>
745
746 * config.in, configure: Regenerate.
747
a6ff997c
NC		 7482012-05-18 Nick Clifton <nickc@redhat.com>
749
750 PR 14072
751 * interp.c: Include config.h before system header files.
752
2232061b
MF		 7532012-03-24 Mike Frysinger <vapier@gentoo.org>
754
755 * aclocal.m4, config.in, configure: Regenerate.
756
db2e4d67
MF		 7572011-12-03 Mike Frysinger <vapier@gentoo.org>
758
759 * aclocal.m4: New file.
760 * configure: Regenerate.
761
4399a56b
MF		 7622011-10-19 Mike Frysinger <vapier@gentoo.org>
763
764 * configure: Regenerate after common/acinclude.m4 update.
765
9c082ca8
MF		 7662011-10-17 Mike Frysinger <vapier@gentoo.org>
767
768 * configure.ac: Change include to common/acinclude.m4.
769
6ffe910a
MF		 7702011-10-17 Mike Frysinger <vapier@gentoo.org>
771
772 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
773 call. Replace common.m4 include with SIM_AC_COMMON.
774 * configure: Regenerate.
775
31b28250
HPN		 7762011-07-08 Hans-Peter Nilsson <hp@axis.com>
777
3faa01e3
HPN		 778 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
779 $(SIM_EXTRA_DEPS).
780 (tmp-mach-multi): Exit early when igen fails.
31b28250 781
2419798b
MF		 7822011-07-05 Mike Frysinger <vapier@gentoo.org>
783
784 * interp.c (sim_do_command): Delete.
785
d79fe0d6
MF		 7862011-02-14 Mike Frysinger <vapier@gentoo.org>
787
788 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
789 (tx3904sio_fifo_reset): Likewise.
790 * interp.c (sim_monitor): Likewise.
791
5558e7e6
MF		 7922010-04-14 Mike Frysinger <vapier@gentoo.org>
793
794 * interp.c (sim_write): Add const to buffer arg.
795
35aafff4
JB		 7962010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
797
798 * interp.c: Don't include sysdep.h
799
3725885a
RW		 8002010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
801
802 * configure: Regenerate.
803
d6416cdc
RW		 8042009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
805
81ecdfbb
RW		 806 * config.in: Regenerate.
807 * configure: Likewise.
808
d6416cdc
RW		 809 * configure: Regenerate.
810
b5bd9624
HPN		 8112008-07-11 Hans-Peter Nilsson <hp@axis.com>
812
813 * configure: Regenerate to track ../common/common.m4 changes.
814 * config.in: Ditto.
815
6efef468 8162008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 817 Daniel Jacobowitz <dan@codesourcery.com>
818 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 819
820 * configure: Regenerate.
821
60dc88db
RS		 8222007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
823
824 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
825 that unconditionally allows fmt_ps.
826 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
827 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
828 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
829 filter from 64,f to 32,f.
830 (PREFX): Change filter from 64 to 32.
831 (LDXC1, LUXC1): Provide separate mips32r2 implementations
832 that use do_load_double instead of do_load. Make both LUXC1
833 versions unpredictable if SizeFGR () != 64.
834 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
835 instead of do_store. Remove unused variable. Make both SUXC1
836 versions unpredictable if SizeFGR () != 64.
837
599ca73e
RS		 8382007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
839
840 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
841 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
842 shifts for that case.
843
2525df03
NC		 8442007-09-04 Nick Clifton <nickc@redhat.com>
845
846 * interp.c (options enum): Add OPTION_INFO_MEMORY.
847 (display_mem_info): New static variable.
848 (mips_option_handler): Handle OPTION_INFO_MEMORY.
849 (mips_options): Add info-memory and memory-info.
850 (sim_open): After processing the command line and board
851 specification, check display_mem_info. If it is set then
852 call the real handler for the --memory-info command line
853 switch.
854
35ee6e1e
JB		 8552007-08-24 Joel Brobecker <brobecker@adacore.com>
856
857 * configure.ac: Change license of multi-run.c to GPL version 3.
858 * configure: Regenerate.
859
d5fb0879
RS		 8602007-06-28 Richard Sandiford <richard@codesourcery.com>
861
862 * configure.ac, configure: Revert last patch.
863
2a2ce21b
RS		 8642007-06-26 Richard Sandiford <richard@codesourcery.com>
865
866 * configure.ac (sim_mipsisa3264_configs): New variable.
867 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
868 every configuration support all four targets, using the triplet to
869 determine the default.
870 * configure: Regenerate.
871
efdcccc9
RS		 8722007-06-25 Richard Sandiford <richard@codesourcery.com>
873
0a7692b2 874 * Makefile.in (m16run.o): New rule.
efdcccc9 875
f532a356
TS		 8762007-05-15 Thiemo Seufer <ths@mips.com>
877
878 * mips3264r2.igen (DSHD): Fix compile warning.
879
bfe9c90b
TS		 8802007-05-14 Thiemo Seufer <ths@mips.com>
881
882 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
883 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
884 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
885 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
886 for mips32r2.
887
53f4826b
TS		 8882007-03-01 Thiemo Seufer <ths@mips.com>
889
890 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
891 and mips64.
892
8bf3ddc8
TS		 8932007-02-20 Thiemo Seufer <ths@mips.com>
894
895 * dsp.igen: Update copyright notice.
896 * dsp2.igen: Fix copyright notice.
897
8b082fb1 8982007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 899 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 900
901 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
902 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
903 Add dsp2 to sim_igen_machine.
904 * configure: Regenerate.
905 * dsp.igen (do_ph_op): Add MUL support when op = 2.
906 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
907 (mulq_rs.ph): Use do_ph_mulq.
908 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
909 * mips.igen: Add dsp2 model and include dsp2.igen.
910 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
911 for *mips32r2, *mips64r2, *dsp.
912 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
913 for *mips32r2, *mips64r2, *dsp2.
914 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
915
b1004875 9162007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 917 Nigel Stephens <nigel@mips.com>
b1004875
TS		 918
919 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
920 jumps with hazard barrier.
921
f8df4c77 9222007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 923 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 924
925 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
926 after each call to sim_io_write.
927
b1004875 9282007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 929 Nigel Stephens <nigel@mips.com>
b1004875
TS		 930
931 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
932 supported by this simulator.
07802d98
TS		 933 (decode_coproc): Recognise additional CP0 Config registers
934 correctly.
935
14fb6c5a 9362007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 937 Nigel Stephens <nigel@mips.com>
938 David Ung <davidu@mips.com>
14fb6c5a
TS		 939
940 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
941 uninterpreted formats. If fmt is one of the uninterpreted types
942 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
943 fmt_word, and fmt_uninterpreted_64 like fmt_long.
944 (store_fpr): When writing an invalid odd register, set the
945 matching even register to fmt_unknown, not the following register.
946 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
947 the the memory window at offset 0 set by --memory-size command
948 line option.
949 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
950 point register.
951 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
952 register.
953 (sim_monitor): When returning the memory size to the MIPS
954 application, use the value in STATE_MEM_SIZE, not an arbitrary
955 hardcoded value.
956 (cop_lw): Don' mess around with FPR_STATE, just pass
957 fmt_uninterpreted_32 to StoreFPR.
958 (cop_sw): Similarly.
959 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
960 (cop_sd): Similarly.
961 * mips.igen (not_word_value): Single version for mips32, mips64
962 and mips16.
963
c8847145 9642007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 965 Nigel Stephens <nigel@mips.com>
c8847145
TS		 966
967 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
968 MBytes.
969
4b5d35ee
TS		 9702007-02-17 Thiemo Seufer <ths@mips.com>
971
972 * configure.ac (mips*-sde-elf*): Move in front of generic machine
973 configuration.
974 * configure: Regenerate.
975
3669427c
TS		 9762007-02-17 Thiemo Seufer <ths@mips.com>
977
978 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
979 Add mdmx to sim_igen_machine.
980 (mipsisa64*-*-*): Likewise. Remove dsp.
981 (mipsisa32*-*-*): Remove dsp.
982 * configure: Regenerate.
983
109ad085
TS		 9842007-02-13 Thiemo Seufer <ths@mips.com>
985
986 * configure.ac: Add mips*-sde-elf* target.
987 * configure: Regenerate.
988
921d7ad3
HPN		 9892006-12-21 Hans-Peter Nilsson <hp@axis.com>
990
991 * acconfig.h: Remove.
992 * config.in, configure: Regenerate.
993
02f97da7
TS		 9942006-11-07 Thiemo Seufer <ths@mips.com>
995
996 * dsp.igen (do_w_op): Fix compiler warning.
997
2d2733fc 9982006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 999 David Ung <davidu@mips.com>
2d2733fc
TS		 1000
1001 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
1002 sim_igen_machine.
1003 * configure: Regenerate.
1004 * mips.igen (model): Add smartmips.
1005 (MADDU): Increment ACX if carry.
1006 (do_mult): Clear ACX.
1007 (ROR,RORV): Add smartmips.
72f4393d 1008 (include): Include smartmips.igen.
2d2733fc
TS		 1009 * sim-main.h (ACX): Set to REGISTERS[89].
1010 * smartmips.igen: New file.
1011
d85c3a10 10122006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 1013 David Ung <davidu@mips.com>
d85c3a10
TS		 1014
1015 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
1016 mips3264r2.igen. Add missing dependency rules.
1017 * m16e.igen: Support for mips16e save/restore instructions.
1018
e85e3205
RE		 10192006-06-13 Richard Earnshaw <rearnsha@arm.com>
1020
1021 * configure: Regenerated.
1022
2f0122dc
DJ		 10232006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
1024
1025 * configure: Regenerated.
1026
20e95c23
DJ		 10272006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
1028
1029 * configure: Regenerated.
1030
69088b17
CF		 10312006-05-15 Chao-ying Fu <fu@mips.com>
1032
1033 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
1034
0275de4e
NC		 10352006-04-18 Nick Clifton <nickc@redhat.com>
1036
1037 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
1038 statement.
1039
b3a3ffef
HPN		 10402006-03-29 Hans-Peter Nilsson <hp@axis.com>
1041
1042 * configure: Regenerate.
1043
40a5538e
CF		 10442005-12-14 Chao-ying Fu <fu@mips.com>
1045
1046 * Makefile.in (SIM_OBJS): Add dsp.o.
1047 (dsp.o): New dependency.
1048 (IGEN_INCLUDE): Add dsp.igen.
1049 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
1050 mipsisa64*-*-*): Add dsp to sim_igen_machine.
1051 * configure: Regenerate.
1052 * mips.igen: Add dsp model and include dsp.igen.
1053 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
1054 because these instructions are extended in DSP ASE.
1055 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
1056 adding 6 DSP accumulator registers and 1 DSP control register.
1057 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
1058 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
1059 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
1060 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
1061 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
1062 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
1063 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
1064 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
1065 DSPCR_CCOND_SMASK): New define.
1066 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
1067 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
1068
21d14896
ILT		 10692005-07-08 Ian Lance Taylor <ian@airs.com>
1070
1071 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
1072
b16d63da 10732005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1074 Nigel Stephens <nigel@mips.com>
1075
1076 * mips.igen: New mips16e model and include m16e.igen.
1077 (check_u64): Add mips16e tag.
1078 * m16e.igen: New file for MIPS16e instructions.
1079 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1080 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1081 models.
1082 * configure: Regenerate.
b16d63da 1083
e70cb6cd 10842005-05-26 David Ung <davidu@mips.com>
72f4393d 1085
e70cb6cd
CD		 1086 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1087 tags to all instructions which are applicable to the new ISAs.
1088 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1089 vr.igen.
1090 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1091 instructions.
e70cb6cd
CD		 1092 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1093 to mips.igen.
1094 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1095 * configure: Regenerate.
72f4393d 1096
2b193c4a
MK		 10972005-03-23 Mark Kettenis <kettenis@gnu.org>
1098
1099 * configure: Regenerate.
1100
35695fd6
AC		 11012005-01-14 Andrew Cagney <cagney@gnu.org>
1102
1103 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1104 explicit call to AC_CONFIG_HEADER.
1105 * configure: Regenerate.
1106
f0569246
AC		 11072005-01-12 Andrew Cagney <cagney@gnu.org>
1108
1109 * configure.ac: Update to use ../common/common.m4.
1110 * configure: Re-generate.
1111
38f48d72
AC		 11122005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1113
1114 * configure: Regenerated to track ../common/aclocal.m4 changes.
1115
b7026657
AC		 11162005-01-07 Andrew Cagney <cagney@gnu.org>
1117
1118 * configure.ac: Rename configure.in, require autoconf 2.59.
1119 * configure: Re-generate.
1120
379832de
HPN		 11212004-12-08 Hans-Peter Nilsson <hp@axis.com>
1122
1123 * configure: Regenerate for ../common/aclocal.m4 update.
1124
cd62154c 11252004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1126
cd62154c
AC		 1127 Committed by Andrew Cagney.
1128 * m16.igen (CMP, CMPI): Fix assembler.
1129
e5da76ec
CD		 11302004-08-18 Chris Demetriou <cgd@broadcom.com>
1131
1132 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1133 * configure: Regenerate.
1134
139181c8
CD		 11352004-06-25 Chris Demetriou <cgd@broadcom.com>
1136
1137 * configure.in (sim_m16_machine): Include mipsIII.
1138 * configure: Regenerate.
1139
1a27f959
CD		 11402004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1141
72f4393d 1142 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1143 from COP0_BADVADDR.
1144 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1145
5dbb7b5a
CD		 11462004-04-10 Chris Demetriou <cgd@broadcom.com>
1147
1148 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1149
14234056
CD		 11502004-04-09 Chris Demetriou <cgd@broadcom.com>
1151
1152 * mips.igen (check_fmt): Remove.
1153 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1154 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1155 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1156 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1157 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1158 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1159 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1160 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1161 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1162 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1163
c6f9085c
CD		 11642004-04-09 Chris Demetriou <cgd@broadcom.com>
1165
1166 * sb1.igen (check_sbx): New function.
1167 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1168
11d66e66 11692004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1170 Richard Sandiford <rsandifo@redhat.com>
1171
1172 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1173 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1174 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1175 separate implementations for mipsIV and mipsV. Use new macros to
1176 determine whether the restrictions apply.
1177
b3208fb8
CD		 11782004-01-19 Chris Demetriou <cgd@broadcom.com>
1179
1180 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1181 (check_mult_hilo): Improve comments.
1182 (check_div_hilo): Likewise. Also, fork off a new version
1183 to handle mips32/mips64 (since there are no hazards to check
1184 in MIPS32/MIPS64).
1185
9a1d84fb
CD		 11862003-06-17 Richard Sandiford <rsandifo@redhat.com>
1187
1188 * mips.igen (do_dmultx): Fix check for negative operands.
1189
ae451ac6
ILT		 11902003-05-16 Ian Lance Taylor <ian@airs.com>
1191
1192 * Makefile.in (SHELL): Make sure this is defined.
1193 (various): Use $(SHELL) whenever we invoke move-if-change.
1194
dd69d292
CD		 11952003-05-03 Chris Demetriou <cgd@broadcom.com>
1196
1197 * cp1.c: Tweak attribution slightly.
1198 * cp1.h: Likewise.
1199 * mdmx.c: Likewise.
1200 * mdmx.igen: Likewise.
1201 * mips3d.igen: Likewise.
1202 * sb1.igen: Likewise.
1203
bcd0068e
CD		 12042003-04-15 Richard Sandiford <rsandifo@redhat.com>
1205
1206 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1207 unsigned operands.
1208
6b4a8935
AC		 12092003-02-27 Andrew Cagney <cagney@redhat.com>
1210
601da316
AC		 1211 * interp.c (sim_open): Rename _bfd to bfd.
1212 (sim_create_inferior): Ditto.
6b4a8935 1213
d29e330f
CD		 12142003-01-14 Chris Demetriou <cgd@broadcom.com>
1215
1216 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1217
a2353a08
CD		 12182003-01-14 Chris Demetriou <cgd@broadcom.com>
1219
1220 * mips.igen (EI, DI): Remove.
1221
80551777
CD		 12222003-01-05 Richard Sandiford <rsandifo@redhat.com>
1223
1224 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1225
4c54fc26
CD		 12262003-01-04 Richard Sandiford <rsandifo@redhat.com>
1227 Andrew Cagney <ac131313@redhat.com>
1228 Gavin Romig-Koch <gavin@redhat.com>
1229 Graydon Hoare <graydon@redhat.com>
1230 Aldy Hernandez <aldyh@redhat.com>
1231 Dave Brolley <brolley@redhat.com>
1232 Chris Demetriou <cgd@broadcom.com>
1233
1234 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1235 (sim_mach_default): New variable.
1236 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1237 Add a new simulator generator, MULTI.
1238 * configure: Regenerate.
1239 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1240 (multi-run.o): New dependency.
1241 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1242 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1243 (tmp-multi): Combine them.
1244 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1245 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1246 (distclean-extra): New rule.
1247 * sim-main.h: Include bfd.h.
1248 (MIPS_MACH): New macro.
1249 * mips.igen (vr4120, vr5400, vr5500): New models.
1250 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1251 * vr.igen: Replace with new version.
1252
e6c674b8
CD		 12532003-01-04 Chris Demetriou <cgd@broadcom.com>
1254
1255 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1256 * configure: Regenerate.
1257
28f50ac8
CD		 12582002-12-31 Chris Demetriou <cgd@broadcom.com>
1259
1260 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1261 * mips.igen: Remove all invocations of check_branch_bug and
1262 mark_branch_bug.
1263
5071ffe6
CD		 12642002-12-16 Chris Demetriou <cgd@broadcom.com>
1265
72f4393d 1266 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1267
06e7837e
CD		 12682002-07-30 Chris Demetriou <cgd@broadcom.com>
1269
1270 * mips.igen (do_load_double, do_store_double): New functions.
1271 (LDC1, SDC1): Rename to...
1272 (LDC1b, SDC1b): respectively.
1273 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1274
2265c243
MS		 12752002-07-29 Michael Snyder <msnyder@redhat.com>
1276
1277 * cp1.c (fp_recip2): Modify initialization expression so that
1278 GCC will recognize it as constant.
1279
a2f8b4f3
CD		 12802002-06-18 Chris Demetriou <cgd@broadcom.com>
1281
1282 * mdmx.c (SD_): Delete.
1283 (Unpredictable): Re-define, for now, to directly invoke
1284 unpredictable_action().
1285 (mdmx_acc_op): Fix error in .ob immediate handling.
1286
b4b6c939
AC		 12872002-06-18 Andrew Cagney <cagney@redhat.com>
1288
1289 * interp.c (sim_firmware_command): Initialize `address'.
1290
c8cca39f
AC		 12912002-06-16 Andrew Cagney <ac131313@redhat.com>
1292
1293 * configure: Regenerated to track ../common/aclocal.m4 changes.
1294
e7e81181 12952002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1296 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1297
1298 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1299 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1300 * mips.igen: Include mips3d.igen.
1301 (mips3d): New model name for MIPS-3D ASE instructions.
1302 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1303 instructions.
e7e81181
CD		 1304 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1305 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1306 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1307 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1308 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1309 (RSquareRoot1, RSquareRoot2): New macros.
1310 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1311 (fp_rsqrt2): New functions.
1312 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1313 * configure: Regenerate.
1314
3a2b820e 13152002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1316 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1317
1318 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1319 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1320 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1321 (convert): Note that this function is not used for paired-single
1322 format conversions.
1323 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1324 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1325 (check_fmt_p): Enable paired-single support.
1326 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1327 (PUU.PS): New instructions.
1328 (CVT.S.fmt): Don't use this instruction for paired-single format
1329 destinations.
1330 * sim-main.h (FP_formats): New value 'fmt_ps.'
1331 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1332 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1333
d18ea9c2
CD		 13342002-06-12 Chris Demetriou <cgd@broadcom.com>
1335
1336 * mips.igen: Fix formatting of function calls in
1337 many FP operations.
1338
95fd5cee
CD		 13392002-06-12 Chris Demetriou <cgd@broadcom.com>
1340
1341 * mips.igen (MOVN, MOVZ): Trace result.
1342 (TNEI): Print "tnei" as the opcode name in traces.
1343 (CEIL.W): Add disassembly string for traces.
1344 (RSQRT.fmt): Make location of disassembly string consistent
1345 with other instructions.
1346
4f0d55ae
CD		 13472002-06-12 Chris Demetriou <cgd@broadcom.com>
1348
1349 * mips.igen (X): Delete unused function.
1350
3c25f8c7
AC		 13512002-06-08 Andrew Cagney <cagney@redhat.com>
1352
1353 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1354
f3c08b7e 13552002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1356 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1357
1358 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1359 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1360 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1361 (fp_nmsub): New prototypes.
1362 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1363 (NegMultiplySub): New defines.
1364 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1365 (MADD.D, MADD.S): Replace with...
1366 (MADD.fmt): New instruction.
1367 (MSUB.D, MSUB.S): Replace with...
1368 (MSUB.fmt): New instruction.
1369 (NMADD.D, NMADD.S): Replace with...
1370 (NMADD.fmt): New instruction.
1371 (NMSUB.D, MSUB.S): Replace with...
1372 (NMSUB.fmt): New instruction.
1373
52714ff9 13742002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1375 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1376
1377 * cp1.c: Fix more comment spelling and formatting.
1378 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1379 (denorm_mode): New function.
1380 (fpu_unary, fpu_binary): Round results after operation, collect
1381 status from rounding operations, and update the FCSR.
1382 (convert): Collect status from integer conversions and rounding
1383 operations, and update the FCSR. Adjust NaN values that result
1384 from conversions. Convert to use sim_io_eprintf rather than
1385 fprintf, and remove some debugging code.
1386 * cp1.h (fenr_FS): New define.
1387
577d8c4b
CD		 13882002-06-07 Chris Demetriou <cgd@broadcom.com>
1389
1390 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1391 rounding mode to sim FP rounding mode flag conversion code into...
1392 (rounding_mode): New function.
1393
196496ed
CD		 13942002-06-07 Chris Demetriou <cgd@broadcom.com>
1395
1396 * cp1.c: Clean up formatting of a few comments.
1397 (value_fpr): Reformat switch statement.
1398
cfe9ea23 13992002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1400 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1401
1402 * cp1.h: New file.
1403 * sim-main.h: Include cp1.h.
1404 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1405 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1406 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1407 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1408 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1409 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1410 * cp1.c: Don't include sim-fpu.h; already included by
1411 sim-main.h. Clean up formatting of some comments.
1412 (NaN, Equal, Less): Remove.
1413 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1414 (fp_cmp): New functions.
1415 * mips.igen (do_c_cond_fmt): Remove.
1416 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1417 Compare. Add result tracing.
1418 (CxC1): Remove, replace with...
1419 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1420 (DMxC1): Remove, replace with...
1421 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1422 (MxC1): Remove, replace with...
1423 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1424
ee7254b0
CD		 14252002-06-04 Chris Demetriou <cgd@broadcom.com>
1426
1427 * sim-main.h (FGRIDX): Remove, replace all uses with...
1428 (FGR_BASE): New macro.
1429 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1430 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1431 (NR_FGR, FGR): Likewise.
1432 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1433 * mips.igen: Likewise.
1434
d3eb724f
CD		 14352002-06-04 Chris Demetriou <cgd@broadcom.com>
1436
1437 * cp1.c: Add an FSF Copyright notice to this file.
1438
ba46ddd0 14392002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1440 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1441
1442 * cp1.c (Infinity): Remove.
1443 * sim-main.h (Infinity): Likewise.
1444
1445 * cp1.c (fp_unary, fp_binary): New functions.
1446 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1447 (fp_sqrt): New functions, implemented in terms of the above.
1448 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1449 (Recip, SquareRoot): Remove (replaced by functions above).
1450 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1451 (fp_recip, fp_sqrt): New prototypes.
1452 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1453 (Recip, SquareRoot): Replace prototypes with #defines which
1454 invoke the functions above.
72f4393d 1455
18d8a52d
CD		 14562002-06-03 Chris Demetriou <cgd@broadcom.com>
1457
1458 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1459 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1460 file, remove PARAMS from prototypes.
1461 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1462 simulator state arguments.
1463 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1464 pass simulator state arguments.
1465 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1466 (store_fpr, convert): Remove 'sd' argument.
1467 (value_fpr): Likewise. Convert to use 'SD' instead.
1468
0f154cbd
CD		 14692002-06-03 Chris Demetriou <cgd@broadcom.com>
1470
1471 * cp1.c (Min, Max): Remove #if 0'd functions.
1472 * sim-main.h (Min, Max): Remove.
1473
e80fc152
CD		 14742002-06-03 Chris Demetriou <cgd@broadcom.com>
1475
1476 * cp1.c: fix formatting of switch case and default labels.
1477 * interp.c: Likewise.
1478 * sim-main.c: Likewise.
1479
bad673a9
CD		 14802002-06-03 Chris Demetriou <cgd@broadcom.com>
1481
1482 * cp1.c: Clean up comments which describe FP formats.
1483 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1484
7cbea089 14852002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1486 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1487
1488 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1489 Broadcom SiByte SB-1 processor configurations.
1490 * configure: Regenerate.
1491 * sb1.igen: New file.
1492 * mips.igen: Include sb1.igen.
1493 (sb1): New model.
1494 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1495 * mdmx.igen: Add "sb1" model to all appropriate functions and
1496 instructions.
1497 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1498 (ob_func, ob_acc): Reference the above.
1499 (qh_acc): Adjust to keep the same size as ob_acc.
1500 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1501 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1502
909daa82
CD		 15032002-06-03 Chris Demetriou <cgd@broadcom.com>
1504
1505 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1506
f4f1b9f1 15072002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1508 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1509
1510 * mips.igen (mdmx): New (pseudo-)model.
1511 * mdmx.c, mdmx.igen: New files.
1512 * Makefile.in (SIM_OBJS): Add mdmx.o.
1513 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1514 New typedefs.
1515 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1516 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1517 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1518 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1519 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1520 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1521 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1522 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1523 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1524 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1525 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1526 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1527 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1528 (qh_fmtsel): New macros.
1529 (_sim_cpu): New member "acc".
1530 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1531 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1532
5accf1ff
CD		 15332002-05-01 Chris Demetriou <cgd@broadcom.com>
1534
1535 * interp.c: Use 'deprecated' rather than 'depreciated.'
1536 * sim-main.h: Likewise.
1537
402586aa
CD		 15382002-05-01 Chris Demetriou <cgd@broadcom.com>
1539
1540 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1541 which wouldn't compile anyway.
1542 * sim-main.h (unpredictable_action): New function prototype.
1543 (Unpredictable): Define to call igen function unpredictable().
1544 (NotWordValue): New macro to call igen function not_word_value().
1545 (UndefinedResult): Remove.
1546 * interp.c (undefined_result): Remove.
1547 (unpredictable_action): New function.
1548 * mips.igen (not_word_value, unpredictable): New functions.
1549 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1550 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1551 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1552 NotWordValue() to check for unpredictable inputs, then
1553 Unpredictable() to handle them.
1554
c9b9995a
CD		 15552002-02-24 Chris Demetriou <cgd@broadcom.com>
1556
1557 * mips.igen: Fix formatting of calls to Unpredictable().
1558
e1015982
AC		 15592002-04-20 Andrew Cagney <ac131313@redhat.com>
1560
1561 * interp.c (sim_open): Revert previous change.
1562
b882a66b
AO		 15632002-04-18 Alexandre Oliva <aoliva@redhat.com>
1564
1565 * interp.c (sim_open): Disable chunk of code that wrote code in
1566 vector table entries.
1567
c429b7dd
CD		 15682002-03-19 Chris Demetriou <cgd@broadcom.com>
1569
1570 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1571 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1572 unused definitions.
1573
37d146fa
CD		 15742002-03-19 Chris Demetriou <cgd@broadcom.com>
1575
1576 * cp1.c: Fix many formatting issues.
1577
07892c0b
CD		 15782002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1579
1580 * cp1.c (fpu_format_name): New function to replace...
1581 (DOFMT): This. Delete, and update all callers.
1582 (fpu_rounding_mode_name): New function to replace...
1583 (RMMODE): This. Delete, and update all callers.
1584
487f79b7
CD		 15852002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1586
1587 * interp.c: Move FPU support routines from here to...
1588 * cp1.c: Here. New file.
1589 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1590 (cp1.o): New target.
1591
1e799e28
CD		 15922002-03-12 Chris Demetriou <cgd@broadcom.com>
1593
1594 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1595 * mips.igen (mips32, mips64): New models, add to all instructions
1596 and functions as appropriate.
1597 (loadstore_ea, check_u64): New variant for model mips64.
1598 (check_fmt_p): New variant for models mipsV and mips64, remove
1599 mipsV model marking fro other variant.
1600 (SLL) Rename to...
1601 (SLLa) this.
1602 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1603 for mips32 and mips64.
1604 (DCLO, DCLZ): New instructions for mips64.
1605
82f728db
CD		 16062002-03-07 Chris Demetriou <cgd@broadcom.com>
1607
1608 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1609 immediate or code as a hex value with the "%#lx" format.
1610 (ANDI): Likewise, and fix printed instruction name.
1611
b96e7ef1
CD		 16122002-03-05 Chris Demetriou <cgd@broadcom.com>
1613
1614 * sim-main.h (UndefinedResult, Unpredictable): New macros
1615 which currently do nothing.
1616
d35d4f70
CD		 16172002-03-05 Chris Demetriou <cgd@broadcom.com>
1618
1619 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1620 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1621 (status_CU3): New definitions.
1622
1623 * sim-main.h (ExceptionCause): Add new values for MIPS32
1624 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1625 for DebugBreakPoint and NMIReset to note their status in
1626 MIPS32 and MIPS64.
1627 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1628 (SignalExceptionCacheErr): New exception macros.
1629
3ad6f714
CD		 16302002-03-05 Chris Demetriou <cgd@broadcom.com>
1631
1632 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1633 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1634 is always enabled.
1635 (SignalExceptionCoProcessorUnusable): Take as argument the
1636 unusable coprocessor number.
1637
86b77b47
CD		 16382002-03-05 Chris Demetriou <cgd@broadcom.com>
1639
1640 * mips.igen: Fix formatting of all SignalException calls.
1641
97a88e93 16422002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1643
1644 * sim-main.h (SIGNEXTEND): Remove.
1645
97a88e93 16462002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1647
1648 * mips.igen: Remove gencode comment from top of file, fix
1649 spelling in another comment.
1650
97a88e93 16512002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1652
1653 * mips.igen (check_fmt, check_fmt_p): New functions to check
1654 whether specific floating point formats are usable.
1655 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1656 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1657 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1658 Use the new functions.
1659 (do_c_cond_fmt): Remove format checks...
1660 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1661
97a88e93 16622002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1663
1664 * mips.igen: Fix formatting of check_fpu calls.
1665
41774c9d
CD		 16662002-03-03 Chris Demetriou <cgd@broadcom.com>
1667
1668 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1669
4a0bd876
CD		 16702002-03-03 Chris Demetriou <cgd@broadcom.com>
1671
1672 * mips.igen: Remove whitespace at end of lines.
1673
09297648
CD		 16742002-03-02 Chris Demetriou <cgd@broadcom.com>
1675
1676 * mips.igen (loadstore_ea): New function to do effective
1677 address calculations.
1678 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1679 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1680 CACHE): Use loadstore_ea to do effective address computations.
1681
043b7057
CD		 16822002-03-02 Chris Demetriou <cgd@broadcom.com>
1683
1684 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1685 * mips.igen (LL, CxC1, MxC1): Likewise.
1686
c1e8ada4
CD		 16872002-03-02 Chris Demetriou <cgd@broadcom.com>
1688
1689 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1690 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1691 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1692 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1693 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1694 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1695 Don't split opcode fields by hand, use the opcode field values
1696 provided by igen.
1697
3e1dca16
CD		 16982002-03-01 Chris Demetriou <cgd@broadcom.com>
1699
1700 * mips.igen (do_divu): Fix spacing.
1701
1702 * mips.igen (do_dsllv): Move to be right before DSLLV,
1703 to match the rest of the do_<shift> functions.
1704
fff8d27d
CD		 17052002-03-01 Chris Demetriou <cgd@broadcom.com>
1706
1707 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1708 DSRL32, do_dsrlv): Trace inputs and results.
1709
0d3e762b
CD		 17102002-03-01 Chris Demetriou <cgd@broadcom.com>
1711
1712 * mips.igen (CACHE): Provide instruction-printing string.
1713
1714 * interp.c (signal_exception): Comment tokens after #endif.
1715
eb5fcf93
CD		 17162002-02-28 Chris Demetriou <cgd@broadcom.com>
1717
1718 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1719 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1720 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1721 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1722 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1723 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1724 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1725 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1726
bb22bd7d
CD		 17272002-02-28 Chris Demetriou <cgd@broadcom.com>
1728
1729 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1730 instruction-printing string.
1731 (LWU): Use '64' as the filter flag.
1732
91a177cf
CD		 17332002-02-28 Chris Demetriou <cgd@broadcom.com>
1734
1735 * mips.igen (SDXC1): Fix instruction-printing string.
1736
387f484a
CD		 17372002-02-28 Chris Demetriou <cgd@broadcom.com>
1738
1739 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1740 filter flags "32,f".
1741
3d81f391
CD		 17422002-02-27 Chris Demetriou <cgd@broadcom.com>
1743
1744 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1745 as the filter flag.
1746
af5107af
CD		 17472002-02-27 Chris Demetriou <cgd@broadcom.com>
1748
1749 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1750 add a comma) so that it more closely match the MIPS ISA
1751 documentation opcode partitioning.
1752 (PREF): Put useful names on opcode fields, and include
1753 instruction-printing string.
1754
ca971540
CD		 17552002-02-27 Chris Demetriou <cgd@broadcom.com>
1756
1757 * mips.igen (check_u64): New function which in the future will
1758 check whether 64-bit instructions are usable and signal an
1759 exception if not. Currently a no-op.
1760 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1761 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1762 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1763 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1764
1765 * mips.igen (check_fpu): New function which in the future will
1766 check whether FPU instructions are usable and signal an exception
1767 if not. Currently a no-op.
1768 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1769 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1770 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1771 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1772 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1773 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1774 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1775 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1776
1c47a468
CD		 17772002-02-27 Chris Demetriou <cgd@broadcom.com>
1778
1779 * mips.igen (do_load_left, do_load_right): Move to be immediately
1780 following do_load.
1781 (do_store_left, do_store_right): Move to be immediately following
1782 do_store.
1783
603a98e7
CD		 17842002-02-27 Chris Demetriou <cgd@broadcom.com>
1785
1786 * mips.igen (mipsV): New model name. Also, add it to
1787 all instructions and functions where it is appropriate.
1788
c5d00cc7
CD		 17892002-02-18 Chris Demetriou <cgd@broadcom.com>
1790
1791 * mips.igen: For all functions and instructions, list model
1792 names that support that instruction one per line.
1793
074e9cb8
CD		 17942002-02-11 Chris Demetriou <cgd@broadcom.com>
1795
1796 * mips.igen: Add some additional comments about supported
1797 models, and about which instructions go where.
1798 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1799 order as is used in the rest of the file.
1800
9805e229
CD		 18012002-02-11 Chris Demetriou <cgd@broadcom.com>
1802
1803 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1804 indicating that ALU32_END or ALU64_END are there to check
1805 for overflow.
1806 (DADD): Likewise, but also remove previous comment about
1807 overflow checking.
1808
f701dad2
CD		 18092002-02-10 Chris Demetriou <cgd@broadcom.com>
1810
1811 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1812 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1813 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1814 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1815 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1816 fields (i.e., add and move commas) so that they more closely
1817 match the MIPS ISA documentation opcode partitioning.
1818
18192002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1820
72f4393d
L		 1821 * mips.igen (ADDI): Print immediate value.
1822 (BREAK): Print code.
1823 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1824 (SLL): Print "nop" specially, and don't run the code
1825 that does the shift for the "nop" case.
20ae0098 1826
9e52972e
FF		 18272001-11-17 Fred Fish <fnf@redhat.com>
1828
1829 * sim-main.h (float_operation): Move enum declaration outside
1830 of _sim_cpu struct declaration.
1831
c0efbca4
JB		 18322001-04-12 Jim Blandy <jimb@redhat.com>
1833
1834 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1835 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1836 set of the FCSR.
1837 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1838 PENDING_FILL, and you can get the intended effect gracefully by
1839 calling PENDING_SCHED directly.
1840
fb891446
BE		 18412001-02-23 Ben Elliston <bje@redhat.com>
1842
1843 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1844 already defined elsewhere.
1845
8030f857
BE		 18462001-02-19 Ben Elliston <bje@redhat.com>
1847
1848 * sim-main.h (sim_monitor): Return an int.
1849 * interp.c (sim_monitor): Add return values.
1850 (signal_exception): Handle error conditions from sim_monitor.
1851
56b48a7a
CD		 18522001-02-08 Ben Elliston <bje@redhat.com>
1853
1854 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1855 (store_memory): Likewise, pass cia to sim_core_write*.
1856
d3ee60d9
FCE		 18572000-10-19 Frank Ch. Eigler <fche@redhat.com>
1858
1859 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1860 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1861
071da002
AC		 1862Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1863
1864 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1865 * Makefile.in: Don't delete *.igen when cleaning directory.
1866
a28c02cd
AC		 1867Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1868
1869 * m16.igen (break): Call SignalException not sim_engine_halt.
1870
80ee11fa
AC		 1871Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1872
1873 From Jason Eckhardt:
1874 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1875
673388c0
AC		 1876Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1877
1878 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1879
4c0deff4
NC		 18802000-05-24 Michael Hayes <mhayes@cygnus.com>
1881
1882 * mips.igen (do_dmultx): Fix typo.
1883
eb2d80b4
AC		 1884Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1885
1886 * configure: Regenerated to track ../common/aclocal.m4 changes.
1887
dd37a34b
AC		 1888Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1889
1890 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1891
4c0deff4
NC		 18922000-04-12 Frank Ch. Eigler <fche@redhat.com>
1893
1894 * sim-main.h (GPR_CLEAR): Define macro.
1895
e30db738
AC		 1896Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1897
1898 * interp.c (decode_coproc): Output long using %lx and not %s.
1899
cb7450ea
FCE		 19002000-03-21 Frank Ch. Eigler <fche@redhat.com>
1901
1902 * interp.c (sim_open): Sort & extend dummy memory regions for
1903 --board=jmr3904 for eCos.
1904
a3027dd7
FCE		 19052000-03-02 Frank Ch. Eigler <fche@redhat.com>
1906
1907 * configure: Regenerated.
1908
1909Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1910
1911 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1912 calls, conditional on the simulator being in verbose mode.
1913
dfcd3bfb
JM		 1914Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1915
1916 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1917 cache don't get ReservedInstruction traps.
1918
c2d11a7d
JM		 19191999-11-29 Mark Salter <msalter@cygnus.com>
1920
1921 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1922 to clear status bits in sdisr register. This is how the hardware works.
1923
1924 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1925 being used by cygmon.
1926
4ce44c66
JM		 19271999-11-11 Andrew Haley <aph@cygnus.com>
1928
1929 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1930 instructions.
1931
cff3e48b
JM		 1932Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1933
1934 * mips.igen (MULT): Correct previous mis-applied patch.
1935
d4f3574e
SS		 1936Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1937
1938 * mips.igen (delayslot32): Handle sequence like
1939 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1940 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1941 (MULT): Actually pass the third register...
1942
19431999-09-03 Mark Salter <msalter@cygnus.com>
1944
1945 * interp.c (sim_open): Added more memory aliases for additional
1946 hardware being touched by cygmon on jmr3904 board.
1947
1948Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1949
1950 * configure: Regenerated to track ../common/aclocal.m4 changes.
1951
a0b3c4fd
JM		 1952Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1953
1954 * interp.c (sim_store_register): Handle case where client - GDB -
1955 specifies that a 4 byte register is 8 bytes in size.
1956 (sim_fetch_register): Ditto.
72f4393d 1957
adf40b2e
JM		 19581999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1959
1960 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1961 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1962 (idt_monitor_base): Base address for IDT monitor traps.
1963 (pmon_monitor_base): Ditto for PMON.
1964 (lsipmon_monitor_base): Ditto for LSI PMON.
1965 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1966 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1967 (sim_firmware_command): New function.
1968 (mips_option_handler): Call it for OPTION_FIRMWARE.
1969 (sim_open): Allocate memory for idt_monitor region. If "--board"
1970 option was given, add no monitor by default. Add BREAK hooks only if
1971 monitors are also there.
72f4393d 1972
43e526b9
JM		 1973Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1974
1975 * interp.c (sim_monitor): Flush output before reading input.
1976
1977Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1978
1979 * tconfig.in (SIM_HANDLES_LMA): Always define.
1980
1981Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1982
1983 From Mark Salter <msalter@cygnus.com>:
1984 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1985 (sim_open): Add setup for BSP board.
1986
9846de1b
JM		 1987Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1988
1989 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1990 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1991 them as unimplemented.
1992
cd0fc7c3
SS		 19931999-05-08 Felix Lee <flee@cygnus.com>
1994
1995 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1996
7a292a7a
SS		 19971999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1998
1999 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
2000
2001Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
2002
2003 * configure.in: Any mips64vr5*-*-* target should have
2004 -DTARGET_ENABLE_FR=1.
2005 (default_endian): Any mips64vr*el-*-* target should default to
2006 LITTLE_ENDIAN.
2007 * configure: Re-generate.
2008
20091999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
2010
2011 * mips.igen (ldl): Extend from _16_, not 32.
2012
2013Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
2014
2015 * interp.c (sim_store_register): Force registers written to by GDB
2016 into an un-interpreted state.
2017
c906108c
SS		 20181999-02-05 Frank Ch. Eigler <fche@cygnus.com>
2019
2020 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
2021 CPU, start periodic background I/O polls.
72f4393d 2022 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 2023
20241998-12-30 Frank Ch. Eigler <fche@cygnus.com>
2025
2026 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 2027
c906108c
SS		 2028Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
2029
2030 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
2031 case statement.
2032
20331998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 2034
2035 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 2036 (load_word): Call SIM_CORE_SIGNAL hook on error.
2037 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
2038 starting. For exception dispatching, pass PC instead of NULL_CIA.
2039 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 2040 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 2041 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
2042 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 2043 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 2044 * mips.igen (*): Replace memory-related SignalException* calls
2045 with references to SIM_CORE_SIGNAL hook.
72f4393d 2046
c906108c
SS		 2047 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
2048 fix.
2049 * sim-main.c (*): Minor warning cleanups.
72f4393d 2050
c906108c
SS		 20511998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
2052
2053 * m16.igen (DADDIU5): Correct type-o.
2054
2055Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
2056
2057 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
2058 variables.
2059
2060Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
2061
2062 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
2063 to include path.
2064 (interp.o): Add dependency on itable.h
2065 (oengine.c, gencode): Delete remaining references.
2066 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 2067
c906108c 20681998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 2069
c906108c
SS		 2070 * vr4run.c: New.
2071 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
2072 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
2073 tmp-run-hack) : New.
2074 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2075 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2076 Drop the "64" qualifier to get the HACK generator working.
2077 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2078 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2079 qualifier to get the hack generator working.
2080 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2081 (DSLL): Use do_dsll.
2082 (DSLLV): Use do_dsllv.
2083 (DSRA): Use do_dsra.
2084 (DSRL): Use do_dsrl.
2085 (DSRLV): Use do_dsrlv.
2086 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2087 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2088 get the HACK generator working.
2089 (MACC) Rename to get the HACK generator working.
2090 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2091
c906108c
SS		 20921998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2093
2094 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2095 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2096
c906108c
SS		 20971998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2098
2099 * mips/interp.c (DEBUG): Cleanups.
2100
21011998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2102
2103 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2104 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2105
c906108c
SS		 21061998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2107
2108 * interp.c (sim_close): Uninstall modules.
2109
2110Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2111
2112 * sim-main.h, interp.c (sim_monitor): Change to global
2113 function.
2114
2115Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2116
2117 * configure.in (vr4100): Only include vr4100 instructions in
2118 simulator.
2119 * configure: Re-generate.
2120 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2121
2122Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2123
2124 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2125 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2126 true alternative.
2127
2128 * configure.in (sim_default_gen, sim_use_gen): Replace with
2129 sim_gen.
2130 (--enable-sim-igen): Delete config option. Always using IGEN.
2131 * configure: Re-generate.
72f4393d 2132
c906108c
SS		 2133 * Makefile.in (gencode): Kill, kill, kill.
2134 * gencode.c: Ditto.
72f4393d 2135
c906108c
SS		 2136Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2137
2138 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2139 bit mips16 igen simulator.
2140 * configure: Re-generate.
2141
2142 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2143 as part of vr4100 ISA.
2144 * vr.igen: Mark all instructions as 64 bit only.
2145
2146Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2147
2148 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2149 Pacify GCC.
2150
2151Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2152
2153 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2154 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2155 * configure: Re-generate.
2156
2157 * m16.igen (BREAK): Define breakpoint instruction.
2158 (JALX32): Mark instruction as mips16 and not r3900.
2159 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2160
2161 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2162
2163Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2164
2165 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2166 insn as a debug breakpoint.
2167
2168 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2169 pending.slot_size.
2170 (PENDING_SCHED): Clean up trace statement.
2171 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2172 (PENDING_FILL): Delay write by only one cycle.
2173 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2174
2175 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2176 of pending writes.
2177 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2178 32 & 64.
2179 (pending_tick): Move incrementing of index to FOR statement.
2180 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2181
c906108c
SS		 2182 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2183 build simulator.
2184 * configure: Re-generate.
72f4393d 2185
c906108c
SS		 2186 * interp.c (sim_engine_run OLD): Delete explicit call to
2187 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2188
c906108c
SS		 2189Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2190
2191 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2192 interrupt level number to match changed SignalExceptionInterrupt
2193 macro.
2194
2195Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2196
2197 * interp.c: #include "itable.h" if WITH_IGEN.
2198 (get_insn_name): New function.
2199 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2200 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2201
2202Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2203
2204 * configure: Rebuilt to inhale new common/aclocal.m4.
2205
2206Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2207
2208 * dv-tx3904sio.c: Include sim-assert.h.
2209
2210Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2211
2212 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2213 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2214 Reorganize target-specific sim-hardware checks.
2215 * configure: rebuilt.
2216 * interp.c (sim_open): For tx39 target boards, set
2217 OPERATING_ENVIRONMENT, add tx3904sio devices.
2218 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2219 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2220
c906108c
SS		 2221 * dv-tx3904irc.c: Compiler warning clean-up.
2222 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2223 frequent hw-trace messages.
2224
2225Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2226
2227 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2228
2229Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2230
2231 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2232
2233 * vr.igen: New file.
2234 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2235 * mips.igen: Define vr4100 model. Include vr.igen.
2236Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2237
2238 * mips.igen (check_mf_hilo): Correct check.
2239
2240Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2241
2242 * sim-main.h (interrupt_event): Add prototype.
2243
2244 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2245 register_ptr, register_value.
2246 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2247
2248 * sim-main.h (tracefh): Make extern.
2249
2250Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2251
2252 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2253 Reduce unnecessarily high timer event frequency.
c906108c 2254 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2255
c906108c
SS		 2256Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2257
2258 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2259 to allay warnings.
2260 (interrupt_event): Made non-static.
72f4393d 2261
c906108c
SS		 2262 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2263 interchange of configuration values for external vs. internal
2264 clock dividers.
72f4393d 2265
c906108c
SS		 2266Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2267
72f4393d 2268 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2269 simulator-reserved break instructions.
2270 * gencode.c (build_instruction): Ditto.
2271 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2272 reserved instructions now use exception vector, rather
c906108c
SS		 2273 than halting sim.
2274 * sim-main.h: Moved magic constants to here.
2275
2276Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2277
2278 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2279 register upon non-zero interrupt event level, clear upon zero
2280 event value.
2281 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2282 by passing zero event value.
2283 (*_io_{read,write}_buffer): Endianness fixes.
2284 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2285 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2286
2287 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2288 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2289
c906108c
SS		 2290Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2291
72f4393d 2292 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2293 and BigEndianCPU.
2294
2295Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2296
2297 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2298 parts.
2299 * configure: Update.
2300
2301Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2302
2303 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2304 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2305 * configure.in: Include tx3904tmr in hw_device list.
2306 * configure: Rebuilt.
2307 * interp.c (sim_open): Instantiate three timer instances.
2308 Fix address typo of tx3904irc instance.
2309
2310Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2311
2312 * interp.c (signal_exception): SystemCall exception now uses
2313 the exception vector.
2314
2315Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2316
2317 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2318 to allay warnings.
2319
2320Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2321
2322 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2323
2324Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2325
2326 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2327
2328 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2329 sim-main.h. Declare a struct hw_descriptor instead of struct
2330 hw_device_descriptor.
2331
2332Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2333
2334 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2335 right bits and then re-align left hand bytes to correct byte
2336 lanes. Fix incorrect computation in do_store_left when loading
2337 bytes from second word.
2338
2339Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2340
2341 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2342 * interp.c (sim_open): Only create a device tree when HW is
2343 enabled.
2344
2345 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2346 * interp.c (signal_exception): Ditto.
2347
2348Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2349
2350 * gencode.c: Mark BEGEZALL as LIKELY.
2351
2352Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2353
2354 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2355 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2356
c906108c
SS		 2357Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2358
2359 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2360 modules. Recognize TX39 target with "mips*tx39" pattern.
2361 * configure: Rebuilt.
2362 * sim-main.h (*): Added many macros defining bits in
2363 TX39 control registers.
2364 (SignalInterrupt): Send actual PC instead of NULL.
2365 (SignalNMIReset): New exception type.
2366 * interp.c (board): New variable for future use to identify
2367 a particular board being simulated.
2368 (mips_option_handler,mips_options): Added "--board" option.
2369 (interrupt_event): Send actual PC.
2370 (sim_open): Make memory layout conditional on board setting.
2371 (signal_exception): Initial implementation of hardware interrupt
2372 handling. Accept another break instruction variant for simulator
2373 exit.
2374 (decode_coproc): Implement RFE instruction for TX39.
2375 (mips.igen): Decode RFE instruction as such.
2376 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2377 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2378 bbegin to implement memory map.
2379 * dv-tx3904cpu.c: New file.
2380 * dv-tx3904irc.c: New file.
2381
2382Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2383
2384 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2385
2386Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2387
2388 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2389 with calls to check_div_hilo.
2390
2391Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2392
2393 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2394 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2395 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2396 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2397 with calls to check_mult_hilo.
2398 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2399 with calls to check_div_hilo.
2400
2401Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2402
2403 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2404 Document a replacement.
2405
2406Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2407
2408 * interp.c (sim_monitor): Make mon_printf work.
2409
2410Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2411
2412 * sim-main.h (INSN_NAME): New arg `cpu'.
2413
2414Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2415
72f4393d 2416 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2417
2418Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2419
2420 * configure: Regenerated to track ../common/aclocal.m4 changes.
2421 * config.in: Ditto.
2422
2423Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2424
2425 * acconfig.h: New file.
2426 * configure.in: Reverted change of Apr 24; use sinclude again.
2427
2428Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2429
2430 * configure: Regenerated to track ../common/aclocal.m4 changes.
2431 * config.in: Ditto.
2432
2433Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2434
2435 * configure.in: Don't call sinclude.
2436
2437Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2438
2439 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2440
2441Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2442
2443 * mips.igen (ERET): Implement.
2444
2445 * interp.c (decode_coproc): Return sign-extended EPC.
2446
2447 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2448
2449 * interp.c (signal_exception): Do not ignore Trap.
2450 (signal_exception): On TRAP, restart at exception address.
2451 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2452 (signal_exception): Update.
2453 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2454 so that TRAP instructions are caught.
2455
2456Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2457
2458 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2459 contains HI/LO access history.
2460 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2461 (HIACCESS, LOACCESS): Delete, replace with
2462 (HIHISTORY, LOHISTORY): New macros.
2463 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2464
c906108c
SS		 2465 * gencode.c (build_instruction): Do not generate checks for
2466 correct HI/LO register usage.
2467
2468 * interp.c (old_engine_run): Delete checks for correct HI/LO
2469 register usage.
2470
2471 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2472 check_mf_cycles): New functions.
2473 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2474 do_divu, domultx, do_mult, do_multu): Use.
2475
2476 * tx.igen ("madd", "maddu"): Use.
72f4393d 2477
c906108c
SS		 2478Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2479
2480 * mips.igen (DSRAV): Use function do_dsrav.
2481 (SRAV): Use new function do_srav.
2482
2483 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2484 (B): Sign extend 11 bit immediate.
2485 (EXT-B*): Shift 16 bit immediate left by 1.
2486 (ADDIU*): Don't sign extend immediate value.
2487
2488Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2489
2490 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2491
2492 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2493 functions.
2494
2495 * mips.igen (delayslot32, nullify_next_insn): New functions.
2496 (m16.igen): Always include.
2497 (do_*): Add more tracing.
2498
2499 * m16.igen (delayslot16): Add NIA argument, could be called by a
2500 32 bit MIPS16 instruction.
72f4393d 2501
c906108c
SS		 2502 * interp.c (ifetch16): Move function from here.
2503 * sim-main.c (ifetch16): To here.
72f4393d 2504
c906108c
SS		 2505 * sim-main.c (ifetch16, ifetch32): Update to match current
2506 implementations of LH, LW.
2507 (signal_exception): Don't print out incorrect hex value of illegal
2508 instruction.
2509
2510Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2511
2512 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2513 instruction.
2514
2515 * m16.igen: Implement MIPS16 instructions.
72f4393d 2516
c906108c
SS		 2517 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2518 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2519 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2520 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2521 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2522 bodies of corresponding code from 32 bit insn to these. Also used
2523 by MIPS16 versions of functions.
72f4393d 2524
c906108c
SS		 2525 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2526 (IMEM16): Drop NR argument from macro.
2527
2528Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2529
2530 * Makefile.in (SIM_OBJS): Add sim-main.o.
2531
2532 * sim-main.h (address_translation, load_memory, store_memory,
2533 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2534 as INLINE_SIM_MAIN.
2535 (pr_addr, pr_uword64): Declare.
2536 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2537
c906108c
SS		 2538 * interp.c (address_translation, load_memory, store_memory,
2539 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2540 from here.
2541 * sim-main.c: To here. Fix compilation problems.
72f4393d 2542
c906108c
SS		 2543 * configure.in: Enable inlining.
2544 * configure: Re-config.
2545
2546Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2547
2548 * configure: Regenerated to track ../common/aclocal.m4 changes.
2549
2550Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2551
2552 * mips.igen: Include tx.igen.
2553 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2554 * tx.igen: New file, contains MADD and MADDU.
2555
2556 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2557 the hardwired constant `7'.
2558 (store_memory): Ditto.
2559 (LOADDRMASK): Move definition to sim-main.h.
2560
2561 mips.igen (MTC0): Enable for r3900.
2562 (ADDU): Add trace.
2563
2564 mips.igen (do_load_byte): Delete.
2565 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2566 do_store_right): New functions.
2567 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2568
2569 configure.in: Let the tx39 use igen again.
2570 configure: Update.
72f4393d 2571
c906108c
SS		 2572Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2573
2574 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2575 not an address sized quantity. Return zero for cache sizes.
2576
2577Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2578
2579 * mips.igen (r3900): r3900 does not support 64 bit integer
2580 operations.
2581
2582Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2583
2584 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2585 than igen one.
2586 * configure : Rebuild.
72f4393d 2587
c906108c
SS		 2588Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2589
2590 * configure: Regenerated to track ../common/aclocal.m4 changes.
2591
2592Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2593
2594 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2595
2596Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2597
2598 * configure: Regenerated to track ../common/aclocal.m4 changes.
2599 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2600
2601Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2602
2603 * configure: Regenerated to track ../common/aclocal.m4 changes.
2604
2605Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2606
2607 * interp.c (Max, Min): Comment out functions. Not yet used.
2608
2609Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2610
2611 * configure: Regenerated to track ../common/aclocal.m4 changes.
2612
2613Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2614
2615 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2616 configurable settings for stand-alone simulator.
72f4393d 2617
c906108c 2618 * configure.in: Added X11 search, just in case.
72f4393d 2619
c906108c
SS		 2620 * configure: Regenerated.
2621
2622Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2623
2624 * interp.c (sim_write, sim_read, load_memory, store_memory):
2625 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2626
2627Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2628
2629 * sim-main.h (GETFCC): Return an unsigned value.
2630
2631Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2632
2633 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2634 (DADD): Result destination is RD not RT.
2635
2636Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2637
2638 * sim-main.h (HIACCESS, LOACCESS): Always define.
2639
2640 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2641
2642 * interp.c (sim_info): Delete.
2643
2644Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2645
2646 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2647 (mips_option_handler): New argument `cpu'.
2648 (sim_open): Update call to sim_add_option_table.
2649
2650Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2651
2652 * mips.igen (CxC1): Add tracing.
2653
2654Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2655
2656 * sim-main.h (Max, Min): Declare.
2657
2658 * interp.c (Max, Min): New functions.
2659
2660 * mips.igen (BC1): Add tracing.
72f4393d 2661
c906108c 2662Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2663
c906108c 2664 * interp.c Added memory map for stack in vr4100
72f4393d 2665
c906108c
SS		 2666Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2667
2668 * interp.c (load_memory): Add missing "break"'s.
2669
2670Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2671
2672 * interp.c (sim_store_register, sim_fetch_register): Pass in
2673 length parameter. Return -1.
2674
2675Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2676
2677 * interp.c: Added hardware init hook, fixed warnings.
2678
2679Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2680
2681 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2682
2683Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2684
2685 * interp.c (ifetch16): New function.
2686
2687 * sim-main.h (IMEM32): Rename IMEM.
2688 (IMEM16_IMMED): Define.
2689 (IMEM16): Define.
2690 (DELAY_SLOT): Update.
72f4393d 2691
c906108c 2692 * m16run.c (sim_engine_run): New file.
72f4393d 2693
c906108c
SS		 2694 * m16.igen: All instructions except LB.
2695 (LB): Call do_load_byte.
2696 * mips.igen (do_load_byte): New function.
2697 (LB): Call do_load_byte.
2698
2699 * mips.igen: Move spec for insn bit size and high bit from here.
2700 * Makefile.in (tmp-igen, tmp-m16): To here.
2701
2702 * m16.dc: New file, decode mips16 instructions.
2703
2704 * Makefile.in (SIM_NO_ALL): Define.
2705 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2706
2707Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2708
2709 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2710 point unit to 32 bit registers.
2711 * configure: Re-generate.
2712
2713Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2714
2715 * configure.in (sim_use_gen): Make IGEN the default simulator
2716 generator for generic 32 and 64 bit mips targets.
2717 * configure: Re-generate.
2718
2719Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2720
2721 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2722 bitsize.
2723
2724 * interp.c (sim_fetch_register, sim_store_register): Read/write
2725 FGR from correct location.
2726 (sim_open): Set size of FGR's according to
2727 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2728
c906108c
SS		 2729 * sim-main.h (FGR): Store floating point registers in a separate
2730 array.
2731
2732Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2733
2734 * configure: Regenerated to track ../common/aclocal.m4 changes.
2735
2736Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2737
2738 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2739
2740 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2741
2742 * interp.c (pending_tick): New function. Deliver pending writes.
2743
2744 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2745 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2746 it can handle mixed sized quantites and single bits.
72f4393d 2747
c906108c
SS		 2748Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2749
2750 * interp.c (oengine.h): Do not include when building with IGEN.
2751 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2752 (sim_info): Ditto for PROCESSOR_64BIT.
2753 (sim_monitor): Replace ut_reg with unsigned_word.
2754 (*): Ditto for t_reg.
2755 (LOADDRMASK): Define.
2756 (sim_open): Remove defunct check that host FP is IEEE compliant,
2757 using software to emulate floating point.
2758 (value_fpr, ...): Always compile, was conditional on HASFPU.
2759
2760Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2761
2762 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2763 size.
2764
2765 * interp.c (SD, CPU): Define.
2766 (mips_option_handler): Set flags in each CPU.
2767 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2768 (sim_close): Do not clear STATE, deleted anyway.
2769 (sim_write, sim_read): Assume CPU zero's vm should be used for
2770 data transfers.
2771 (sim_create_inferior): Set the PC for all processors.
2772 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2773 argument.
2774 (mips16_entry): Pass correct nr of args to store_word, load_word.
2775 (ColdReset): Cold reset all cpu's.
2776 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2777 (sim_monitor, load_memory, store_memory, signal_exception): Use
2778 `CPU' instead of STATE_CPU.
2779
2780
2781 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2782 SD or CPU_.
72f4393d 2783
c906108c
SS		 2784 * sim-main.h (signal_exception): Add sim_cpu arg.
2785 (SignalException*): Pass both SD and CPU to signal_exception.
2786 * interp.c (signal_exception): Update.
72f4393d 2787
c906108c
SS		 2788 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2789 Ditto
2790 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2791 address_translation): Ditto
2792 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2793
c906108c
SS		 2794Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2795
2796 * configure: Regenerated to track ../common/aclocal.m4 changes.
2797
2798Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2799
2800 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2801
72f4393d 2802 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2803
2804 * sim-main.h (CPU_CIA): Delete.
2805 (SET_CIA, GET_CIA): Define
2806
2807Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2808
2809 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2810 regiser.
2811
2812 * configure.in (default_endian): Configure a big-endian simulator
2813 by default.
2814 * configure: Re-generate.
72f4393d 2815
c906108c
SS		 2816Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2817
2818 * configure: Regenerated to track ../common/aclocal.m4 changes.
2819
2820Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2821
2822 * interp.c (sim_monitor): Handle Densan monitor outbyte
2823 and inbyte functions.
2824
28251997-12-29 Felix Lee <flee@cygnus.com>
2826
2827 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2828
2829Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2830
2831 * Makefile.in (tmp-igen): Arrange for $zero to always be
2832 reset to zero after every instruction.
2833
2834Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2835
2836 * configure: Regenerated to track ../common/aclocal.m4 changes.
2837 * config.in: Ditto.
2838
2839Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2840
2841 * mips.igen (MSUB): Fix to work like MADD.
2842 * gencode.c (MSUB): Similarly.
2843
2844Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2845
2846 * configure: Regenerated to track ../common/aclocal.m4 changes.
2847
2848Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2849
2850 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2851
2852Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2853
2854 * sim-main.h (sim-fpu.h): Include.
2855
2856 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2857 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2858 using host independant sim_fpu module.
2859
2860Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2861
2862 * interp.c (signal_exception): Report internal errors with SIGABRT
2863 not SIGQUIT.
2864
2865 * sim-main.h (C0_CONFIG): New register.
2866 (signal.h): No longer include.
2867
2868 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2869
2870Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2871
2872 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2873
2874Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2875
2876 * mips.igen: Tag vr5000 instructions.
2877 (ANDI): Was missing mipsIV model, fix assembler syntax.
2878 (do_c_cond_fmt): New function.
2879 (C.cond.fmt): Handle mips I-III which do not support CC field
2880 separatly.
2881 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2882 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2883 in IV3.2 spec.
2884 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2885 vr5000 which saves LO in a GPR separatly.
72f4393d 2886
c906108c
SS		 2887 * configure.in (enable-sim-igen): For vr5000, select vr5000
2888 specific instructions.
2889 * configure: Re-generate.
72f4393d 2890
c906108c
SS		 2891Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2892
2893 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2894
2895 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2896 fmt_uninterpreted_64 bit cases to switch. Convert to
2897 fmt_formatted,
2898
2899 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2900
2901 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2902 as specified in IV3.2 spec.
2903 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2904
2905Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2906
2907 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2908 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2909 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2910 PENDING_FILL versions of instructions. Simplify.
2911 (X): New function.
2912 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2913 instructions.
2914 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2915 a signed value.
2916 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2917
c906108c
SS		 2918 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2919 global.
2920 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2921
2922Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2923
2924 * gencode.c (build_mips16_operands): Replace IPC with cia.
2925
2926 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2927 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2928 IPC to `cia'.
2929 (UndefinedResult): Replace function with macro/function
2930 combination.
2931 (sim_engine_run): Don't save PC in IPC.
2932
2933 * sim-main.h (IPC): Delete.
2934
2935
2936 * interp.c (signal_exception, store_word, load_word,
2937 address_translation, load_memory, store_memory, cache_op,
2938 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2939 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2940 current instruction address - cia - argument.
2941 (sim_read, sim_write): Call address_translation directly.
2942 (sim_engine_run): Rename variable vaddr to cia.
2943 (signal_exception): Pass cia to sim_monitor
72f4393d 2944
c906108c
SS		 2945 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2946 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2947 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2948
2949 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2950 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2951 SIM_ASSERT.
72f4393d 2952
c906108c
SS		 2953 * interp.c (signal_exception): Pass restart address to
2954 sim_engine_restart.
2955
2956 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2957 idecode.o): Add dependency.
2958
2959 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2960 Delete definitions
2961 (DELAY_SLOT): Update NIA not PC with branch address.
2962 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2963
2964 * mips.igen: Use CIA not PC in branch calculations.
2965 (illegal): Call SignalException.
2966 (BEQ, ADDIU): Fix assembler.
2967
2968Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2969
2970 * m16.igen (JALX): Was missing.
2971
2972 * configure.in (enable-sim-igen): New configuration option.
2973 * configure: Re-generate.
72f4393d 2974
c906108c
SS		 2975 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2976
2977 * interp.c (load_memory, store_memory): Delete parameter RAW.
2978 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2979 bypassing {load,store}_memory.
2980
2981 * sim-main.h (ByteSwapMem): Delete definition.
2982
2983 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2984
2985 * interp.c (sim_do_command, sim_commands): Delete mips specific
2986 commands. Handled by module sim-options.
72f4393d 2987
c906108c
SS		 2988 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2989 (WITH_MODULO_MEMORY): Define.
2990
2991 * interp.c (sim_info): Delete code printing memory size.
2992
2993 * interp.c (mips_size): Nee sim_size, delete function.
2994 (power2): Delete.
2995 (monitor, monitor_base, monitor_size): Delete global variables.
2996 (sim_open, sim_close): Delete code creating monitor and other
2997 memory regions. Use sim-memopts module, via sim_do_commandf, to
2998 manage memory regions.
2999 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 3000
c906108c
SS		 3001 * interp.c (address_translation): Delete all memory map code
3002 except line forcing 32 bit addresses.
3003
3004Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
3005
3006 * sim-main.h (WITH_TRACE): Delete definition. Enables common
3007 trace options.
3008
3009 * interp.c (logfh, logfile): Delete globals.
3010 (sim_open, sim_close): Delete code opening & closing log file.
3011 (mips_option_handler): Delete -l and -n options.
3012 (OPTION mips_options): Ditto.
3013
3014 * interp.c (OPTION mips_options): Rename option trace to dinero.
3015 (mips_option_handler): Update.
3016
3017Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3018
3019 * interp.c (fetch_str): New function.
3020 (sim_monitor): Rewrite using sim_read & sim_write.
3021 (sim_open): Check magic number.
3022 (sim_open): Write monitor vectors into memory using sim_write.
3023 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
3024 (sim_read, sim_write): Simplify - transfer data one byte at a
3025 time.
3026 (load_memory, store_memory): Clarify meaning of parameter RAW.
3027
3028 * sim-main.h (isHOST): Defete definition.
3029 (isTARGET): Mark as depreciated.
3030 (address_translation): Delete parameter HOST.
3031
3032 * interp.c (address_translation): Delete parameter HOST.
3033
3034Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3035
72f4393d 3036 * mips.igen:
c906108c
SS		 3037
3038 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
3039 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
3040
3041Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
3042
3043 * mips.igen: Add model filter field to records.
3044
3045Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3046
3047 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 3048
c906108c
SS		 3049 interp.c (sim_engine_run): Do not compile function sim_engine_run
3050 when WITH_IGEN == 1.
3051
3052 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
3053 target architecture.
3054
3055 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
3056 igen. Replace with configuration variables sim_igen_flags /
3057 sim_m16_flags.
3058
3059 * m16.igen: New file. Copy mips16 insns here.
3060 * mips.igen: From here.
3061
3062Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3063
3064 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
3065 to top.
3066 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
3067
3068Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
3069
3070 * gencode.c (build_instruction): Follow sim_write's lead in using
3071 BigEndianMem instead of !ByteSwapMem.
3072
3073Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3074
3075 * configure.in (sim_gen): Dependent on target, select type of
3076 generator. Always select old style generator.
3077
3078 configure: Re-generate.
3079
3080 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3081 targets.
3082 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3083 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3084 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3085 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3086 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3087
c906108c
SS		 3088Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3089
3090 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3091
3092 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3093 CURRENT_FLOATING_POINT instead.
3094
3095 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3096 (address_translation): Raise exception InstructionFetch when
3097 translation fails and isINSTRUCTION.
72f4393d 3098
c906108c
SS		 3099 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3100 sim_engine_run): Change type of of vaddr and paddr to
3101 address_word.
3102 (address_translation, prefetch, load_memory, store_memory,
3103 cache_op): Change type of vAddr and pAddr to address_word.
3104
3105 * gencode.c (build_instruction): Change type of vaddr and paddr to
3106 address_word.
3107
3108Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3109
3110 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3111 macro to obtain result of ALU op.
3112
3113Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3114
3115 * interp.c (sim_info): Call profile_print.
3116
3117Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3118
3119 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3120
3121 * sim-main.h (WITH_PROFILE): Do not define, defined in
3122 common/sim-config.h. Use sim-profile module.
3123 (simPROFILE): Delete defintion.
3124
3125 * interp.c (PROFILE): Delete definition.
3126 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3127 (sim_close): Delete code writing profile histogram.
3128 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3129 Delete.
3130 (sim_engine_run): Delete code profiling the PC.
3131
3132Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3133
3134 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3135
3136 * interp.c (sim_monitor): Make register pointers of type
3137 unsigned_word*.
3138
3139 * sim-main.h: Make registers of type unsigned_word not
3140 signed_word.
3141
3142Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3143
3144 * interp.c (sync_operation): Rename from SyncOperation, make
3145 global, add SD argument.
3146 (prefetch): Rename from Prefetch, make global, add SD argument.
3147 (decode_coproc): Make global.
3148
3149 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3150
3151 * gencode.c (build_instruction): Generate DecodeCoproc not
3152 decode_coproc calls.
3153
3154 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3155 (SizeFGR): Move to sim-main.h
3156 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3157 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3158 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3159 sim-main.h.
3160 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3161 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3162 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3163 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3164 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3165 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3166
c906108c
SS		 3167 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3168 exception.
3169 (sim-alu.h): Include.
3170 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3171 (sim_cia): Typedef to instruction_address.
72f4393d 3172
c906108c
SS		 3173Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3174
3175 * Makefile.in (interp.o): Rename generated file engine.c to
3176 oengine.c.
72f4393d 3177
c906108c 3178 * interp.c: Update.
72f4393d 3179
c906108c
SS		 3180Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3181
3182 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3183
c906108c
SS		 3184Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3185
3186 * gencode.c (build_instruction): For "FPSQRT", output correct
3187 number of arguments to Recip.
72f4393d 3188
c906108c
SS		 3189Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3190
3191 * Makefile.in (interp.o): Depends on sim-main.h
3192
3193 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3194
3195 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3196 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3197 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3198 STATE, DSSTATE): Define
3199 (GPR, FGRIDX, ..): Define.
3200
3201 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3202 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3203 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3204
c906108c 3205 * interp.c: Update names to match defines from sim-main.h
72f4393d 3206
c906108c
SS		 3207Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3208
3209 * interp.c (sim_monitor): Add SD argument.
3210 (sim_warning): Delete. Replace calls with calls to
3211 sim_io_eprintf.
3212 (sim_error): Delete. Replace calls with sim_io_error.
3213 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3214 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3215 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3216 argument.
3217 (mips_size): Rename from sim_size. Add SD argument.
3218
3219 * interp.c (simulator): Delete global variable.
3220 (callback): Delete global variable.
3221 (mips_option_handler, sim_open, sim_write, sim_read,
3222 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3223 sim_size,sim_monitor): Use sim_io_* not callback->*.
3224 (sim_open): ZALLOC simulator struct.
3225 (PROFILE): Do not define.
3226
3227Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3228
3229 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3230 support.h with corresponding code.
3231
3232 * sim-main.h (word64, uword64), support.h: Move definition to
3233 sim-main.h.
3234 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3235
3236 * support.h: Delete
3237 * Makefile.in: Update dependencies
3238 * interp.c: Do not include.
72f4393d 3239
c906108c
SS		 3240Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3241
3242 * interp.c (address_translation, load_memory, store_memory,
3243 cache_op): Rename to from AddressTranslation et.al., make global,
3244 add SD argument
72f4393d 3245
c906108c
SS		 3246 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3247 CacheOp): Define.
72f4393d 3248
c906108c
SS		 3249 * interp.c (SignalException): Rename to signal_exception, make
3250 global.
3251
3252 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3253
c906108c
SS		 3254 * sim-main.h (SignalException, SignalExceptionInterrupt,
3255 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3256 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3257 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3258 Define.
72f4393d 3259
c906108c 3260 * interp.c, support.h: Use.
72f4393d 3261
c906108c
SS		 3262Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3263
3264 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3265 to value_fpr / store_fpr. Add SD argument.
3266 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3267 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3268
3269 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3270
c906108c
SS		 3271Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3272
3273 * interp.c (sim_engine_run): Check consistency between configure
3274 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3275 and HASFPU.
3276
3277 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3278 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3279 (mips_endian): Configure WITH_TARGET_ENDIAN.
3280 * configure: Update.
3281
3282Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3283
3284 * configure: Regenerated to track ../common/aclocal.m4 changes.
3285
3286Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3287
3288 * configure: Regenerated.
3289
3290Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3291
3292 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3293
3294Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3295
3296 * gencode.c (print_igen_insn_models): Assume certain architectures
3297 include all mips* instructions.
3298 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3299 instruction.
3300
3301 * Makefile.in (tmp.igen): Add target. Generate igen input from
3302 gencode file.
3303
3304 * gencode.c (FEATURE_IGEN): Define.
3305 (main): Add --igen option. Generate output in igen format.
3306 (process_instructions): Format output according to igen option.
3307 (print_igen_insn_format): New function.
3308 (print_igen_insn_models): New function.
3309 (process_instructions): Only issue warnings and ignore
3310 instructions when no FEATURE_IGEN.
3311
3312Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3313
3314 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3315 MIPS targets.
3316
3317Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3318
3319 * configure: Regenerated to track ../common/aclocal.m4 changes.
3320
3321Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3322
3323 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3324 SIM_RESERVED_BITS): Delete, moved to common.
3325 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3326
c906108c
SS		 3327Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3328
3329 * configure.in: Configure non-strict memory alignment.
3330 * configure: Regenerated to track ../common/aclocal.m4 changes.
3331
3332Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3333
3334 * configure: Regenerated to track ../common/aclocal.m4 changes.
3335
3336Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3337
3338 * gencode.c (SDBBP,DERET): Added (3900) insns.
3339 (RFE): Turn on for 3900.
3340 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3341 (dsstate): Made global.
3342 (SUBTARGET_R3900): Added.
3343 (CANCELDELAYSLOT): New.
3344 (SignalException): Ignore SystemCall rather than ignore and
3345 terminate. Add DebugBreakPoint handling.
3346 (decode_coproc): New insns RFE, DERET; and new registers Debug
3347 and DEPC protected by SUBTARGET_R3900.
3348 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3349 bits explicitly.
3350 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3351 * configure: Update.
c906108c
SS		 3352
3353Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3354
3355 * gencode.c: Add r3900 (tx39).
72f4393d 3356
c906108c
SS		 3357
3358Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3359
3360 * gencode.c (build_instruction): Don't need to subtract 4 for
3361 JALR, just 2.
3362
3363Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3364
3365 * interp.c: Correct some HASFPU problems.
3366
3367Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3368
3369 * configure: Regenerated to track ../common/aclocal.m4 changes.
3370
3371Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3372
3373 * interp.c (mips_options): Fix samples option short form, should
3374 be `x'.
3375
3376Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3377
3378 * interp.c (sim_info): Enable info code. Was just returning.
3379
3380Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3381
3382 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3383 MFC0.
3384
3385Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3386
3387 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3388 constants.
3389 (build_instruction): Ditto for LL.
3390
3391Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3392
3393 * configure: Regenerated to track ../common/aclocal.m4 changes.
3394
3395Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3396
3397 * configure: Regenerated to track ../common/aclocal.m4 changes.
3398 * config.in: Ditto.
3399
3400Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3401
3402 * interp.c (sim_open): Add call to sim_analyze_program, update
3403 call to sim_config.
3404
3405Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3406
3407 * interp.c (sim_kill): Delete.
3408 (sim_create_inferior): Add ABFD argument. Set PC from same.
3409 (sim_load): Move code initializing trap handlers from here.
3410 (sim_open): To here.
3411 (sim_load): Delete, use sim-hload.c.
3412
3413 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3414
3415Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3416
3417 * configure: Regenerated to track ../common/aclocal.m4 changes.
3418 * config.in: Ditto.
3419
3420Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3421
3422 * interp.c (sim_open): Add ABFD argument.
3423 (sim_load): Move call to sim_config from here.
3424 (sim_open): To here. Check return status.
3425
3426Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3427
c906108c
SS		 3428 * gencode.c (build_instruction): Two arg MADD should
3429 not assign result to $0.
72f4393d 3430
c906108c
SS		 3431Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3432
3433 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3434 * sim/mips/configure.in: Regenerate.
3435
3436Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3437
3438 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3439 signed8, unsigned8 et.al. types.
3440
3441 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3442 hosts when selecting subreg.
3443
3444Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3445
3446 * interp.c (sim_engine_run): Reset the ZERO register to zero
3447 regardless of FEATURE_WARN_ZERO.
3448 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3449
3450Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3451
3452 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3453 (SignalException): For BreakPoints ignore any mode bits and just
3454 save the PC.
3455 (SignalException): Always set the CAUSE register.
3456
3457Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3458
3459 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3460 exception has been taken.
3461
3462 * interp.c: Implement the ERET and mt/f sr instructions.
3463
3464Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3465
3466 * interp.c (SignalException): Don't bother restarting an
3467 interrupt.
3468
3469Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3470
3471 * interp.c (SignalException): Really take an interrupt.
3472 (interrupt_event): Only deliver interrupts when enabled.
3473
3474Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3475
3476 * interp.c (sim_info): Only print info when verbose.
3477 (sim_info) Use sim_io_printf for output.
72f4393d 3478
c906108c
SS		 3479Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3480
3481 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3482 mips architectures.
3483
3484Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3485
3486 * interp.c (sim_do_command): Check for common commands if a
3487 simulator specific command fails.
3488
3489Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3490
3491 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3492 and simBE when DEBUG is defined.
3493
3494Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3495
3496 * interp.c (interrupt_event): New function. Pass exception event
3497 onto exception handler.
3498
3499 * configure.in: Check for stdlib.h.
3500 * configure: Regenerate.
3501
3502 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3503 variable declaration.
3504 (build_instruction): Initialize memval1.
3505 (build_instruction): Add UNUSED attribute to byte, bigend,
3506 reverse.
3507 (build_operands): Ditto.
3508
3509 * interp.c: Fix GCC warnings.
3510 (sim_get_quit_code): Delete.
3511
3512 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3513 * Makefile.in: Ditto.
3514 * configure: Re-generate.
72f4393d 3515
c906108c
SS		 3516 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3517
3518Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3519
3520 * interp.c (mips_option_handler): New function parse argumes using
3521 sim-options.
3522 (myname): Replace with STATE_MY_NAME.
3523 (sim_open): Delete check for host endianness - performed by
3524 sim_config.
3525 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3526 (sim_open): Move much of the initialization from here.
3527 (sim_load): To here. After the image has been loaded and
3528 endianness set.
3529 (sim_open): Move ColdReset from here.
3530 (sim_create_inferior): To here.
3531 (sim_open): Make FP check less dependant on host endianness.
3532
3533 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3534 run.
3535 * interp.c (sim_set_callbacks): Delete.
3536
3537 * interp.c (membank, membank_base, membank_size): Replace with
3538 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3539 (sim_open): Remove call to callback->init. gdb/run do this.
3540
3541 * interp.c: Update
3542
3543 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3544
3545 * interp.c (big_endian_p): Delete, replaced by
3546 current_target_byte_order.
3547
3548Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3549
3550 * interp.c (host_read_long, host_read_word, host_swap_word,
3551 host_swap_long): Delete. Using common sim-endian.
3552 (sim_fetch_register, sim_store_register): Use H2T.
3553 (pipeline_ticks): Delete. Handled by sim-events.
3554 (sim_info): Update.
3555 (sim_engine_run): Update.
3556
3557Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3558
3559 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3560 reason from here.
3561 (SignalException): To here. Signal using sim_engine_halt.
3562 (sim_stop_reason): Delete, moved to common.
72f4393d 3563
c906108c
SS		 3564Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3565
3566 * interp.c (sim_open): Add callback argument.
3567 (sim_set_callbacks): Delete SIM_DESC argument.
3568 (sim_size): Ditto.
3569
3570Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3571
3572 * Makefile.in (SIM_OBJS): Add common modules.
3573
3574 * interp.c (sim_set_callbacks): Also set SD callback.
3575 (set_endianness, xfer_*, swap_*): Delete.
3576 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3577 Change to functions using sim-endian macros.
3578 (control_c, sim_stop): Delete, use common version.
3579 (simulate): Convert into.
3580 (sim_engine_run): This function.
3581 (sim_resume): Delete.
72f4393d 3582
c906108c
SS		 3583 * interp.c (simulation): New variable - the simulator object.
3584 (sim_kind): Delete global - merged into simulation.
3585 (sim_load): Cleanup. Move PC assignment from here.
3586 (sim_create_inferior): To here.
3587
3588 * sim-main.h: New file.
3589 * interp.c (sim-main.h): Include.
72f4393d 3590
c906108c
SS		 3591Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3592
3593 * configure: Regenerated to track ../common/aclocal.m4 changes.
3594
3595Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3596
3597 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3598
3599Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3600
72f4393d
L		 3601 * gencode.c (build_instruction): DIV instructions: check
3602 for division by zero and integer overflow before using
c906108c
SS		 3603 host's division operation.
3604
3605Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3606
3607 * Makefile.in (SIM_OBJS): Add sim-load.o.
3608 * interp.c: #include bfd.h.
3609 (target_byte_order): Delete.
3610 (sim_kind, myname, big_endian_p): New static locals.
3611 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3612 after argument parsing. Recognize -E arg, set endianness accordingly.
3613 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3614 load file into simulator. Set PC from bfd.
3615 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3616 (set_endianness): Use big_endian_p instead of target_byte_order.
3617
3618Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3619
3620 * interp.c (sim_size): Delete prototype - conflicts with
3621 definition in remote-sim.h. Correct definition.
3622
3623Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3624
3625 * configure: Regenerated to track ../common/aclocal.m4 changes.
3626 * config.in: Ditto.
3627
3628Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3629
3630 * interp.c (sim_open): New arg `kind'.
3631
3632 * configure: Regenerated to track ../common/aclocal.m4 changes.
3633
3634Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3635
3636 * configure: Regenerated to track ../common/aclocal.m4 changes.
3637
3638Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3639
3640 * interp.c (sim_open): Set optind to 0 before calling getopt.
3641
3642Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3643
3644 * configure: Regenerated to track ../common/aclocal.m4 changes.
3645
3646Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3647
3648 * interp.c : Replace uses of pr_addr with pr_uword64
3649 where the bit length is always 64 independent of SIM_ADDR.
3650 (pr_uword64) : added.
3651
3652Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3653
3654 * configure: Re-generate.
3655
3656Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3657
3658 * configure: Regenerate to track ../common/aclocal.m4 changes.
3659
3660Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3661
3662 * interp.c (sim_open): New SIM_DESC result. Argument is now
3663 in argv form.
3664 (other sim_*): New SIM_DESC argument.
3665
3666Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3667
3668 * interp.c: Fix printing of addresses for non-64-bit targets.
3669 (pr_addr): Add function to print address based on size.
3670
3671Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3672
3673 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3674
3675Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3676
3677 * gencode.c (build_mips16_operands): Correct computation of base
3678 address for extended PC relative instruction.
3679
3680Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3681
3682 * interp.c (mips16_entry): Add support for floating point cases.
3683 (SignalException): Pass floating point cases to mips16_entry.
3684 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3685 registers.
3686 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3687 or fmt_word.
3688 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3689 and then set the state to fmt_uninterpreted.
3690 (COP_SW): Temporarily set the state to fmt_word while calling
3691 ValueFPR.
3692
3693Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3694
3695 * gencode.c (build_instruction): The high order may be set in the
3696 comparison flags at any ISA level, not just ISA 4.
3697
3698Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3699
3700 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3701 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3702 * configure.in: sinclude ../common/aclocal.m4.
3703 * configure: Regenerated.
3704
3705Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3706
3707 * configure: Rebuild after change to aclocal.m4.
3708
3709Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3710
3711 * configure configure.in Makefile.in: Update to new configure
3712 scheme which is more compatible with WinGDB builds.
3713 * configure.in: Improve comment on how to run autoconf.
3714 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3715 * Makefile.in: Use autoconf substitution to install common
3716 makefile fragment.
3717
3718Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3719
3720 * gencode.c (build_instruction): Use BigEndianCPU instead of
3721 ByteSwapMem.
3722
3723Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3724
3725 * interp.c (sim_monitor): Make output to stdout visible in
3726 wingdb's I/O log window.
3727
3728Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3729
3730 * support.h: Undo previous change to SIGTRAP
3731 and SIGQUIT values.
3732
3733Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3734
3735 * interp.c (store_word, load_word): New static functions.
3736 (mips16_entry): New static function.
3737 (SignalException): Look for mips16 entry and exit instructions.
3738 (simulate): Use the correct index when setting fpr_state after
3739 doing a pending move.
3740
3741Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3742
3743 * interp.c: Fix byte-swapping code throughout to work on
3744 both little- and big-endian hosts.
3745
3746Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3747
3748 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3749 with gdb/config/i386/xm-windows.h.
3750
3751Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3752
3753 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3754 that messes up arithmetic shifts.
3755
3756Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3757
3758 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3759 SIGTRAP and SIGQUIT for _WIN32.
3760
3761Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3762
3763 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3764 force a 64 bit multiplication.
3765 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3766 destination register is 0, since that is the default mips16 nop
3767 instruction.
3768
3769Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3770
3771 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3772 (build_endian_shift): Don't check proc64.
3773 (build_instruction): Always set memval to uword64. Cast op2 to
3774 uword64 when shifting it left in memory instructions. Always use
3775 the same code for stores--don't special case proc64.
3776
3777 * gencode.c (build_mips16_operands): Fix base PC value for PC
3778 relative operands.
3779 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3780 jal instruction.
3781 * interp.c (simJALDELAYSLOT): Define.
3782 (JALDELAYSLOT): Define.
3783 (INDELAYSLOT, INJALDELAYSLOT): Define.
3784 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3785
3786Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3787
3788 * interp.c (sim_open): add flush_cache as a PMON routine
3789 (sim_monitor): handle flush_cache by ignoring it
3790
3791Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3792
3793 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3794 BigEndianMem.
3795 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3796 (BigEndianMem): Rename to ByteSwapMem and change sense.
3797 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3798 BigEndianMem references to !ByteSwapMem.
3799 (set_endianness): New function, with prototype.
3800 (sim_open): Call set_endianness.
3801 (sim_info): Use simBE instead of BigEndianMem.
3802 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3803 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3804 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3805 ifdefs, keeping the prototype declaration.
3806 (swap_word): Rewrite correctly.
3807 (ColdReset): Delete references to CONFIG. Delete endianness related
3808 code; moved to set_endianness.
72f4393d 3809
c906108c
SS		 3810Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3811
3812 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3813 * interp.c (CHECKHILO): Define away.
3814 (simSIGINT): New macro.
3815 (membank_size): Increase from 1MB to 2MB.
3816 (control_c): New function.
3817 (sim_resume): Rename parameter signal to signal_number. Add local
3818 variable prev. Call signal before and after simulate.
3819 (sim_stop_reason): Add simSIGINT support.
3820 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3821 functions always.
3822 (sim_warning): Delete call to SignalException. Do call printf_filtered
3823 if logfh is NULL.
3824 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3825 a call to sim_warning.
3826
3827Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3828
3829 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3830 16 bit instructions.
3831
3832Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3833
3834 Add support for mips16 (16 bit MIPS implementation):
3835 * gencode.c (inst_type): Add mips16 instruction encoding types.
3836 (GETDATASIZEINSN): Define.
3837 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3838 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3839 mtlo.
3840 (MIPS16_DECODE): New table, for mips16 instructions.
3841 (bitmap_val): New static function.
3842 (struct mips16_op): Define.
3843 (mips16_op_table): New table, for mips16 operands.
3844 (build_mips16_operands): New static function.
3845 (process_instructions): If PC is odd, decode a mips16
3846 instruction. Break out instruction handling into new
3847 build_instruction function.
3848 (build_instruction): New static function, broken out of
3849 process_instructions. Check modifiers rather than flags for SHIFT
3850 bit count and m[ft]{hi,lo} direction.
3851 (usage): Pass program name to fprintf.
3852 (main): Remove unused variable this_option_optind. Change
3853 ``*loptarg++'' to ``loptarg++''.
3854 (my_strtoul): Parenthesize && within ||.
3855 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3856 (simulate): If PC is odd, fetch a 16 bit instruction, and
3857 increment PC by 2 rather than 4.
3858 * configure.in: Add case for mips16*-*-*.
3859 * configure: Rebuild.
3860
3861Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3862
3863 * interp.c: Allow -t to enable tracing in standalone simulator.
3864 Fix garbage output in trace file and error messages.
3865
3866Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3867
3868 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3869 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3870 * configure.in: Simplify using macros in ../common/aclocal.m4.
3871 * configure: Regenerated.
3872 * tconfig.in: New file.
3873
3874Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3875
3876 * interp.c: Fix bugs in 64-bit port.
3877 Use ansi function declarations for msvc compiler.
3878 Initialize and test file pointer in trace code.
3879 Prevent duplicate definition of LAST_EMED_REGNUM.
3880
3881Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3882
3883 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3884
3885Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3886
3887 * interp.c (SignalException): Check for explicit terminating
3888 breakpoint value.
3889 * gencode.c: Pass instruction value through SignalException()
3890 calls for Trap, Breakpoint and Syscall.
3891
3892Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3893
3894 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3895 only used on those hosts that provide it.
3896 * configure.in: Add sqrt() to list of functions to be checked for.
3897 * config.in: Re-generated.
3898 * configure: Re-generated.
3899
3900Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3901
3902 * gencode.c (process_instructions): Call build_endian_shift when
3903 expanding STORE RIGHT, to fix swr.
3904 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3905 clear the high bits.
3906 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3907 Fix float to int conversions to produce signed values.
3908
3909Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3910
3911 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3912 (process_instructions): Correct handling of nor instruction.
3913 Correct shift count for 32 bit shift instructions. Correct sign
3914 extension for arithmetic shifts to not shift the number of bits in
3915 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3916 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3917 Fix madd.
3918 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3919 It's OK to have a mult follow a mult. What's not OK is to have a
3920 mult follow an mfhi.
3921 (Convert): Comment out incorrect rounding code.
3922
3923Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3924
3925 * interp.c (sim_monitor): Improved monitor printf
3926 simulation. Tidied up simulator warnings, and added "--log" option
3927 for directing warning message output.
3928 * gencode.c: Use sim_warning() rather than WARNING macro.
3929
3930Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3931
3932 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3933 getopt1.o, rather than on gencode.c. Link objects together.
3934 Don't link against -liberty.
3935 (gencode.o, getopt.o, getopt1.o): New targets.
3936 * gencode.c: Include <ctype.h> and "ansidecl.h".
3937 (AND): Undefine after including "ansidecl.h".
3938 (ULONG_MAX): Define if not defined.
3939 (OP_*): Don't define macros; now defined in opcode/mips.h.
3940 (main): Call my_strtoul rather than strtoul.
3941 (my_strtoul): New static function.
3942
3943Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3944
3945 * gencode.c (process_instructions): Generate word64 and uword64
3946 instead of `long long' and `unsigned long long' data types.
3947 * interp.c: #include sysdep.h to get signals, and define default
3948 for SIGBUS.
3949 * (Convert): Work around for Visual-C++ compiler bug with type
3950 conversion.
3951 * support.h: Make things compile under Visual-C++ by using
3952 __int64 instead of `long long'. Change many refs to long long
3953 into word64/uword64 typedefs.
3954
3955Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3956
72f4393d
L		 3957 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3958 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3959 (docdir): Removed.
3960 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3961 (AC_PROG_INSTALL): Added.
c906108c 3962 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3963 * configure: Rebuilt.
3964
c906108c
SS		 3965Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3966
3967 * configure.in: Define @SIMCONF@ depending on mips target.
3968 * configure: Rebuild.
3969 * Makefile.in (run): Add @SIMCONF@ to control simulator
3970 construction.
3971 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3972 * interp.c: Remove some debugging, provide more detailed error
3973 messages, update memory accesses to use LOADDRMASK.
72f4393d 3974
c906108c
SS		 3975Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3976
3977 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3978 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3979 stamp-h.
3980 * configure: Rebuild.
3981 * config.in: New file, generated by autoheader.
3982 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3983 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3984 HAVE_ANINT and HAVE_AINT, as appropriate.
3985 * Makefile.in (run): Use @LIBS@ rather than -lm.
3986 (interp.o): Depend upon config.h.
3987 (Makefile): Just rebuild Makefile.
3988 (clean): Remove stamp-h.
3989 (mostlyclean): Make the same as clean, not as distclean.
3990 (config.h, stamp-h): New targets.
3991
3992Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3993
3994 * interp.c (ColdReset): Fix boolean test. Make all simulator
3995 globals static.
3996
3997Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3998
3999 * interp.c (xfer_direct_word, xfer_direct_long,
4000 swap_direct_word, swap_direct_long, xfer_big_word,
4001 xfer_big_long, xfer_little_word, xfer_little_long,
4002 swap_word,swap_long): Added.
4003 * interp.c (ColdReset): Provide function indirection to
4004 host<->simulated_target transfer routines.
4005 * interp.c (sim_store_register, sim_fetch_register): Updated to
4006 make use of indirected transfer routines.
4007
4008Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
4009
4010 * gencode.c (process_instructions): Ensure FP ABS instruction
4011 recognised.
4012 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
4013 system call support.
4014
4015Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
4016
4017 * interp.c (sim_do_command): Complain if callback structure not
4018 initialised.
4019
4020Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
4021
4022 * interp.c (Convert): Provide round-to-nearest and round-to-zero
4023 support for Sun hosts.
4024 * Makefile.in (gencode): Ensure the host compiler and libraries
4025 used for cross-hosted build.
4026
4027Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
4028
4029 * interp.c, gencode.c: Some more (TODO) tidying.
4030
4031Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
4032
4033 * gencode.c, interp.c: Replaced explicit long long references with
4034 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
4035 * support.h (SET64LO, SET64HI): Macros added.
4036
4037Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
4038
4039 * configure: Regenerate with autoconf 2.7.
4040
4041Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
4042
4043 * interp.c (LoadMemory): Enclose text following #endif in /* */.
4044 * support.h: Remove superfluous "1" from #if.
4045 * support.h (CHECKSIM): Remove stray 'a' at end of line.
4046
4047Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
4048
4049 * interp.c (StoreFPR): Control UndefinedResult() call on
4050 WARN_RESULT manifest.
4051
4052Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
4053
4054 * gencode.c: Tidied instruction decoding, and added FP instruction
4055 support.
4056
4057 * interp.c: Added dineroIII, and BSD profiling support. Also
4058 run-time FP handling.
4059
4060Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
4061
4062 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
4063 gencode.c, interp.c, support.h: created.
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