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[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
1e799e28
CD		 12002-03-12 Chris Demetriou <cgd@broadcom.com>
2
3 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
4 * mips.igen (mips32, mips64): New models, add to all instructions
5 and functions as appropriate.
6 (loadstore_ea, check_u64): New variant for model mips64.
7 (check_fmt_p): New variant for models mipsV and mips64, remove
8 mipsV model marking fro other variant.
9 (SLL) Rename to...
10 (SLLa) this.
11 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
12 for mips32 and mips64.
13 (DCLO, DCLZ): New instructions for mips64.
14
82f728db
CD		 152002-03-07 Chris Demetriou <cgd@broadcom.com>
16
17 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
18 immediate or code as a hex value with the "%#lx" format.
19 (ANDI): Likewise, and fix printed instruction name.
20
b96e7ef1
CD		 212002-03-05 Chris Demetriou <cgd@broadcom.com>
22
23 * sim-main.h (UndefinedResult, Unpredictable): New macros
24 which currently do nothing.
25
d35d4f70
CD		 262002-03-05 Chris Demetriou <cgd@broadcom.com>
27
28 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
29 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
30 (status_CU3): New definitions.
31
32 * sim-main.h (ExceptionCause): Add new values for MIPS32
33 and MIPS64: MDMX, MCheck, CacheErr. Update comments
34 for DebugBreakPoint and NMIReset to note their status in
35 MIPS32 and MIPS64.
36 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
37 (SignalExceptionCacheErr): New exception macros.
38
3ad6f714
CD		 392002-03-05 Chris Demetriou <cgd@broadcom.com>
40
41 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
42 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
43 is always enabled.
44 (SignalExceptionCoProcessorUnusable): Take as argument the
45 unusable coprocessor number.
46
86b77b47
CD		 472002-03-05 Chris Demetriou <cgd@broadcom.com>
48
49 * mips.igen: Fix formatting of all SignalException calls.
50
97a88e93 512002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 52
53 * sim-main.h (SIGNEXTEND): Remove.
54
97a88e93 552002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 56
57 * mips.igen: Remove gencode comment from top of file, fix
58 spelling in another comment.
59
97a88e93 602002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 61
62 * mips.igen (check_fmt, check_fmt_p): New functions to check
63 whether specific floating point formats are usable.
64 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
65 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
66 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
67 Use the new functions.
68 (do_c_cond_fmt): Remove format checks...
69 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
70
97a88e93 712002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 72
73 * mips.igen: Fix formatting of check_fpu calls.
74
41774c9d
CD		 752002-03-03 Chris Demetriou <cgd@broadcom.com>
76
77 * mips.igen (FLOOR.L.fmt): Store correct destination register.
78
4a0bd876
CD		 792002-03-03 Chris Demetriou <cgd@broadcom.com>
80
81 * mips.igen: Remove whitespace at end of lines.
82
09297648
CD		 832002-03-02 Chris Demetriou <cgd@broadcom.com>
84
85 * mips.igen (loadstore_ea): New function to do effective
86 address calculations.
87 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
88 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
89 CACHE): Use loadstore_ea to do effective address computations.
90
043b7057
CD		 912002-03-02 Chris Demetriou <cgd@broadcom.com>
92
93 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
94 * mips.igen (LL, CxC1, MxC1): Likewise.
95
c1e8ada4
CD		 962002-03-02 Chris Demetriou <cgd@broadcom.com>
97
98 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
99 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
100 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
101 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
102 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
103 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
104 Don't split opcode fields by hand, use the opcode field values
105 provided by igen.
106
3e1dca16
CD		 1072002-03-01 Chris Demetriou <cgd@broadcom.com>
108
109 * mips.igen (do_divu): Fix spacing.
110
111 * mips.igen (do_dsllv): Move to be right before DSLLV,
112 to match the rest of the do_<shift> functions.
113
fff8d27d
CD		 1142002-03-01 Chris Demetriou <cgd@broadcom.com>
115
116 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
117 DSRL32, do_dsrlv): Trace inputs and results.
118
0d3e762b
CD		 1192002-03-01 Chris Demetriou <cgd@broadcom.com>
120
121 * mips.igen (CACHE): Provide instruction-printing string.
122
123 * interp.c (signal_exception): Comment tokens after #endif.
124
eb5fcf93
CD		 1252002-02-28 Chris Demetriou <cgd@broadcom.com>
126
127 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
128 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
129 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
130 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
131 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
132 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
133 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
134 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
135
bb22bd7d
CD		 1362002-02-28 Chris Demetriou <cgd@broadcom.com>
137
138 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
139 instruction-printing string.
140 (LWU): Use '64' as the filter flag.
141
91a177cf
CD		 1422002-02-28 Chris Demetriou <cgd@broadcom.com>
143
144 * mips.igen (SDXC1): Fix instruction-printing string.
145
387f484a
CD		 1462002-02-28 Chris Demetriou <cgd@broadcom.com>
147
148 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
149 filter flags "32,f".
150
3d81f391
CD		 1512002-02-27 Chris Demetriou <cgd@broadcom.com>
152
153 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
154 as the filter flag.
155
af5107af
CD		 1562002-02-27 Chris Demetriou <cgd@broadcom.com>
157
158 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
159 add a comma) so that it more closely match the MIPS ISA
160 documentation opcode partitioning.
161 (PREF): Put useful names on opcode fields, and include
162 instruction-printing string.
163
ca971540
CD		 1642002-02-27 Chris Demetriou <cgd@broadcom.com>
165
166 * mips.igen (check_u64): New function which in the future will
167 check whether 64-bit instructions are usable and signal an
168 exception if not. Currently a no-op.
169 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
170 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
171 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
172 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
173
174 * mips.igen (check_fpu): New function which in the future will
175 check whether FPU instructions are usable and signal an exception
176 if not. Currently a no-op.
177 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
178 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
179 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
180 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
181 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
182 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
183 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
184 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
185
1c47a468
CD		 1862002-02-27 Chris Demetriou <cgd@broadcom.com>
187
188 * mips.igen (do_load_left, do_load_right): Move to be immediately
189 following do_load.
190 (do_store_left, do_store_right): Move to be immediately following
191 do_store.
192
603a98e7
CD		 1932002-02-27 Chris Demetriou <cgd@broadcom.com>
194
195 * mips.igen (mipsV): New model name. Also, add it to
196 all instructions and functions where it is appropriate.
197
c5d00cc7
CD		 1982002-02-18 Chris Demetriou <cgd@broadcom.com>
199
200 * mips.igen: For all functions and instructions, list model
201 names that support that instruction one per line.
202
074e9cb8
CD		 2032002-02-11 Chris Demetriou <cgd@broadcom.com>
204
205 * mips.igen: Add some additional comments about supported
206 models, and about which instructions go where.
207 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
208 order as is used in the rest of the file.
209
9805e229
CD		 2102002-02-11 Chris Demetriou <cgd@broadcom.com>
211
212 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
213 indicating that ALU32_END or ALU64_END are there to check
214 for overflow.
215 (DADD): Likewise, but also remove previous comment about
216 overflow checking.
217
f701dad2
CD		 2182002-02-10 Chris Demetriou <cgd@broadcom.com>
219
220 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
221 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
222 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
223 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
224 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
225 fields (i.e., add and move commas) so that they more closely
226 match the MIPS ISA documentation opcode partitioning.
227
2282002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 229
230 * mips.igen (ADDI): Print immediate value.
231 (BREAK): Print code.
232 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
233 (SLL): Print "nop" specially, and don't run the code
234 that does the shift for the "nop" case.
235
9e52972e
FF		 2362001-11-17 Fred Fish <fnf@redhat.com>
237
238 * sim-main.h (float_operation): Move enum declaration outside
239 of _sim_cpu struct declaration.
240
c0efbca4
JB		 2412001-04-12 Jim Blandy <jimb@redhat.com>
242
243 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
244 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
245 set of the FCSR.
246 * sim-main.h (COCIDX): Remove definition; this isn't supported by
247 PENDING_FILL, and you can get the intended effect gracefully by
248 calling PENDING_SCHED directly.
249
fb891446
BE		 2502001-02-23 Ben Elliston <bje@redhat.com>
251
252 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
253 already defined elsewhere.
254
8030f857
BE		 2552001-02-19 Ben Elliston <bje@redhat.com>
256
257 * sim-main.h (sim_monitor): Return an int.
258 * interp.c (sim_monitor): Add return values.
259 (signal_exception): Handle error conditions from sim_monitor.
260
56b48a7a
CD		 2612001-02-08 Ben Elliston <bje@redhat.com>
262
263 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
264 (store_memory): Likewise, pass cia to sim_core_write*.
265
d3ee60d9
FCE		 2662000-10-19 Frank Ch. Eigler <fche@redhat.com>
267
268 On advice from Chris G. Demetriou <cgd@sibyte.com>:
269 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
270
071da002
AC		 271Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
272
273 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
274 * Makefile.in: Don't delete *.igen when cleaning directory.
275
a28c02cd
AC		 276Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
277
278 * m16.igen (break): Call SignalException not sim_engine_halt.
279
80ee11fa
AC		 280Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
281
282 From Jason Eckhardt:
283 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
284
673388c0
AC		 285Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
286
287 * mips.igen (MxC1, DMxC1): Fix printf formatting.
288
4c0deff4
NC		 2892000-05-24 Michael Hayes <mhayes@cygnus.com>
290
291 * mips.igen (do_dmultx): Fix typo.
292
eb2d80b4
AC		 293Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
294
295 * configure: Regenerated to track ../common/aclocal.m4 changes.
296
dd37a34b
AC		 297Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
298
299 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
300
4c0deff4
NC		 3012000-04-12 Frank Ch. Eigler <fche@redhat.com>
302
303 * sim-main.h (GPR_CLEAR): Define macro.
304
e30db738
AC		 305Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
306
307 * interp.c (decode_coproc): Output long using %lx and not %s.
308
cb7450ea
FCE		 3092000-03-21 Frank Ch. Eigler <fche@redhat.com>
310
311 * interp.c (sim_open): Sort & extend dummy memory regions for
312 --board=jmr3904 for eCos.
313
a3027dd7
FCE		 3142000-03-02 Frank Ch. Eigler <fche@redhat.com>
315
316 * configure: Regenerated.
317
318Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
319
320 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
321 calls, conditional on the simulator being in verbose mode.
322
dfcd3bfb
JM		 323Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
324
325 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
326 cache don't get ReservedInstruction traps.
327
c2d11a7d
JM		 3281999-11-29 Mark Salter <msalter@cygnus.com>
329
330 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
331 to clear status bits in sdisr register. This is how the hardware works.
332
333 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
334 being used by cygmon.
335
4ce44c66
JM		 3361999-11-11 Andrew Haley <aph@cygnus.com>
337
338 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
339 instructions.
340
cff3e48b
JM		 341Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
342
343 * mips.igen (MULT): Correct previous mis-applied patch.
344
d4f3574e
SS		 345Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
346
347 * mips.igen (delayslot32): Handle sequence like
348 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
349 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
350 (MULT): Actually pass the third register...
351
3521999-09-03 Mark Salter <msalter@cygnus.com>
353
354 * interp.c (sim_open): Added more memory aliases for additional
355 hardware being touched by cygmon on jmr3904 board.
356
357Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
358
359 * configure: Regenerated to track ../common/aclocal.m4 changes.
360
a0b3c4fd
JM		 361Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
362
363 * interp.c (sim_store_register): Handle case where client - GDB -
364 specifies that a 4 byte register is 8 bytes in size.
365 (sim_fetch_register): Ditto.
366
adf40b2e
JM		 3671999-07-14 Frank Ch. Eigler <fche@cygnus.com>
368
369 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
370 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
371 (idt_monitor_base): Base address for IDT monitor traps.
372 (pmon_monitor_base): Ditto for PMON.
373 (lsipmon_monitor_base): Ditto for LSI PMON.
374 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
375 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
376 (sim_firmware_command): New function.
377 (mips_option_handler): Call it for OPTION_FIRMWARE.
378 (sim_open): Allocate memory for idt_monitor region. If "--board"
379 option was given, add no monitor by default. Add BREAK hooks only if
380 monitors are also there.
381
43e526b9
JM		 382Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
383
384 * interp.c (sim_monitor): Flush output before reading input.
385
386Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
387
388 * tconfig.in (SIM_HANDLES_LMA): Always define.
389
390Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
391
392 From Mark Salter <msalter@cygnus.com>:
393 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
394 (sim_open): Add setup for BSP board.
395
9846de1b
JM		 396Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
397
398 * mips.igen (MULT, MULTU): Add syntax for two operand version.
399 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
400 them as unimplemented.
401
cd0fc7c3
SS		 4021999-05-08 Felix Lee <flee@cygnus.com>
403
404 * configure: Regenerated to track ../common/aclocal.m4 changes.
405
7a292a7a
SS		 4061999-04-21 Frank Ch. Eigler <fche@cygnus.com>
407
408 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
409
410Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
411
412 * configure.in: Any mips64vr5*-*-* target should have
413 -DTARGET_ENABLE_FR=1.
414 (default_endian): Any mips64vr*el-*-* target should default to
415 LITTLE_ENDIAN.
416 * configure: Re-generate.
417
4181999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
419
420 * mips.igen (ldl): Extend from _16_, not 32.
421
422Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
423
424 * interp.c (sim_store_register): Force registers written to by GDB
425 into an un-interpreted state.
426
c906108c
SS		 4271999-02-05 Frank Ch. Eigler <fche@cygnus.com>
428
429 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
430 CPU, start periodic background I/O polls.
431 (tx3904sio_poll): New function: periodic I/O poller.
432
4331998-12-30 Frank Ch. Eigler <fche@cygnus.com>
434
435 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
436
437Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
438
439 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
440 case statement.
441
4421998-12-29 Frank Ch. Eigler <fche@cygnus.com>
443
444 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
445 (load_word): Call SIM_CORE_SIGNAL hook on error.
446 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
447 starting. For exception dispatching, pass PC instead of NULL_CIA.
448 (decode_coproc): Use COP0_BADVADDR to store faulting address.
449 * sim-main.h (COP0_BADVADDR): Define.
450 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
451 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
452 (_sim_cpu): Add exc_* fields to store register value snapshots.
453 * mips.igen (*): Replace memory-related SignalException* calls
454 with references to SIM_CORE_SIGNAL hook.
455
456 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
457 fix.
458 * sim-main.c (*): Minor warning cleanups.
459
4601998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
461
462 * m16.igen (DADDIU5): Correct type-o.
463
464Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
465
466 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
467 variables.
468
469Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
470
471 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
472 to include path.
473 (interp.o): Add dependency on itable.h
474 (oengine.c, gencode): Delete remaining references.
475 (BUILT_SRC_FROM_GEN): Clean up.
476
4771998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
478
479 * vr4run.c: New.
480 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
481 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
482 tmp-run-hack) : New.
483 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
484 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
485 Drop the "64" qualifier to get the HACK generator working.
486 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
487 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
488 qualifier to get the hack generator working.
489 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
490 (DSLL): Use do_dsll.
491 (DSLLV): Use do_dsllv.
492 (DSRA): Use do_dsra.
493 (DSRL): Use do_dsrl.
494 (DSRLV): Use do_dsrlv.
495 (BC1): Move *vr4100 to get the HACK generator working.
496 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
497 get the HACK generator working.
498 (MACC) Rename to get the HACK generator working.
499 (DMACC,MACCS,DMACCS): Add the 64.
500
5011998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
502
503 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
504 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
505
5061998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
507
508 * mips/interp.c (DEBUG): Cleanups.
509
5101998-12-10 Frank Ch. Eigler <fche@cygnus.com>
511
512 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
513 (tx3904sio_tickle): fflush after a stdout character output.
514
5151998-12-03 Frank Ch. Eigler <fche@cygnus.com>
516
517 * interp.c (sim_close): Uninstall modules.
518
519Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
520
521 * sim-main.h, interp.c (sim_monitor): Change to global
522 function.
523
524Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
525
526 * configure.in (vr4100): Only include vr4100 instructions in
527 simulator.
528 * configure: Re-generate.
529 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
530
531Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
532
533 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
534 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
535 true alternative.
536
537 * configure.in (sim_default_gen, sim_use_gen): Replace with
538 sim_gen.
539 (--enable-sim-igen): Delete config option. Always using IGEN.
540 * configure: Re-generate.
541
542 * Makefile.in (gencode): Kill, kill, kill.
543 * gencode.c: Ditto.
544
545Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
546
547 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
548 bit mips16 igen simulator.
549 * configure: Re-generate.
550
551 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
552 as part of vr4100 ISA.
553 * vr.igen: Mark all instructions as 64 bit only.
554
555Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
556
557 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
558 Pacify GCC.
559
560Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
561
562 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
563 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
564 * configure: Re-generate.
565
566 * m16.igen (BREAK): Define breakpoint instruction.
567 (JALX32): Mark instruction as mips16 and not r3900.
568 * mips.igen (C.cond.fmt): Fix typo in instruction format.
569
570 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
571
572Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
573
574 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
575 insn as a debug breakpoint.
576
577 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
578 pending.slot_size.
579 (PENDING_SCHED): Clean up trace statement.
580 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
581 (PENDING_FILL): Delay write by only one cycle.
582 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
583
584 * sim-main.c (pending_tick): Clean up trace statements. Add trace
585 of pending writes.
586 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
587 32 & 64.
588 (pending_tick): Move incrementing of index to FOR statement.
589 (pending_tick): Only update PENDING_OUT after a write has occured.
590
591 * configure.in: Add explicit mips-lsi-* target. Use gencode to
592 build simulator.
593 * configure: Re-generate.
594
595 * interp.c (sim_engine_run OLD): Delete explicit call to
596 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
597
598Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
599
600 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
601 interrupt level number to match changed SignalExceptionInterrupt
602 macro.
603
604Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
605
606 * interp.c: #include "itable.h" if WITH_IGEN.
607 (get_insn_name): New function.
608 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
609 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
610
611Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
612
613 * configure: Rebuilt to inhale new common/aclocal.m4.
614
615Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
616
617 * dv-tx3904sio.c: Include sim-assert.h.
618
619Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
620
621 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
622 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
623 Reorganize target-specific sim-hardware checks.
624 * configure: rebuilt.
625 * interp.c (sim_open): For tx39 target boards, set
626 OPERATING_ENVIRONMENT, add tx3904sio devices.
627 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
628 ROM executables. Install dv-sockser into sim-modules list.
629
630 * dv-tx3904irc.c: Compiler warning clean-up.
631 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
632 frequent hw-trace messages.
633
634Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
635
636 * vr.igen (MulAcc): Identify as a vr4100 specific function.
637
638Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
639
640 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
641
642 * vr.igen: New file.
643 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
644 * mips.igen: Define vr4100 model. Include vr.igen.
645Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
646
647 * mips.igen (check_mf_hilo): Correct check.
648
649Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
650
651 * sim-main.h (interrupt_event): Add prototype.
652
653 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
654 register_ptr, register_value.
655 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
656
657 * sim-main.h (tracefh): Make extern.
658
659Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
660
661 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
662 Reduce unnecessarily high timer event frequency.
663 * dv-tx3904cpu.c: Ditto for interrupt event.
664
665Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
666
667 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
668 to allay warnings.
669 (interrupt_event): Made non-static.
670
671 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
672 interchange of configuration values for external vs. internal
673 clock dividers.
674
675Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
676
677 * mips.igen (BREAK): Moved code to here for
678 simulator-reserved break instructions.
679 * gencode.c (build_instruction): Ditto.
680 * interp.c (signal_exception): Code moved from here. Non-
681 reserved instructions now use exception vector, rather
682 than halting sim.
683 * sim-main.h: Moved magic constants to here.
684
685Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
686
687 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
688 register upon non-zero interrupt event level, clear upon zero
689 event value.
690 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
691 by passing zero event value.
692 (*_io_{read,write}_buffer): Endianness fixes.
693 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
694 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
695
696 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
697 serial I/O and timer module at base address 0xFFFF0000.
698
699Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
700
701 * mips.igen (SWC1) : Correct the handling of ReverseEndian
702 and BigEndianCPU.
703
704Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
705
706 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
707 parts.
708 * configure: Update.
709
710Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
711
712 * dv-tx3904tmr.c: New file - implements tx3904 timer.
713 * dv-tx3904{irc,cpu}.c: Mild reformatting.
714 * configure.in: Include tx3904tmr in hw_device list.
715 * configure: Rebuilt.
716 * interp.c (sim_open): Instantiate three timer instances.
717 Fix address typo of tx3904irc instance.
718
719Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
720
721 * interp.c (signal_exception): SystemCall exception now uses
722 the exception vector.
723
724Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
725
726 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
727 to allay warnings.
728
729Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
730
731 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
732
733Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
734
735 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
736
737 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
738 sim-main.h. Declare a struct hw_descriptor instead of struct
739 hw_device_descriptor.
740
741Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
742
743 * mips.igen (do_store_left, do_load_left): Compute nr of left and
744 right bits and then re-align left hand bytes to correct byte
745 lanes. Fix incorrect computation in do_store_left when loading
746 bytes from second word.
747
748Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
749
750 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
751 * interp.c (sim_open): Only create a device tree when HW is
752 enabled.
753
754 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
755 * interp.c (signal_exception): Ditto.
756
757Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
758
759 * gencode.c: Mark BEGEZALL as LIKELY.
760
761Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
762
763 * sim-main.h (ALU32_END): Sign extend 32 bit results.
764 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
765
766Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
767
768 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
769 modules. Recognize TX39 target with "mips*tx39" pattern.
770 * configure: Rebuilt.
771 * sim-main.h (*): Added many macros defining bits in
772 TX39 control registers.
773 (SignalInterrupt): Send actual PC instead of NULL.
774 (SignalNMIReset): New exception type.
775 * interp.c (board): New variable for future use to identify
776 a particular board being simulated.
777 (mips_option_handler,mips_options): Added "--board" option.
778 (interrupt_event): Send actual PC.
779 (sim_open): Make memory layout conditional on board setting.
780 (signal_exception): Initial implementation of hardware interrupt
781 handling. Accept another break instruction variant for simulator
782 exit.
783 (decode_coproc): Implement RFE instruction for TX39.
784 (mips.igen): Decode RFE instruction as such.
785 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
786 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
787 bbegin to implement memory map.
788 * dv-tx3904cpu.c: New file.
789 * dv-tx3904irc.c: New file.
790
791Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
792
793 * mips.igen (check_mt_hilo): Create a separate r3900 version.
794
795Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
796
797 * tx.igen (madd,maddu): Replace calls to check_op_hilo
798 with calls to check_div_hilo.
799
800Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
801
802 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
803 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
804 Add special r3900 version of do_mult_hilo.
805 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
806 with calls to check_mult_hilo.
807 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
808 with calls to check_div_hilo.
809
810Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
811
812 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
813 Document a replacement.
814
815Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
816
817 * interp.c (sim_monitor): Make mon_printf work.
818
819Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
820
821 * sim-main.h (INSN_NAME): New arg `cpu'.
822
823Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
824
825 * configure: Regenerated to track ../common/aclocal.m4 changes.
826
827Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
828
829 * configure: Regenerated to track ../common/aclocal.m4 changes.
830 * config.in: Ditto.
831
832Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
833
834 * acconfig.h: New file.
835 * configure.in: Reverted change of Apr 24; use sinclude again.
836
837Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
838
839 * configure: Regenerated to track ../common/aclocal.m4 changes.
840 * config.in: Ditto.
841
842Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
843
844 * configure.in: Don't call sinclude.
845
846Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
847
848 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
849
850Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
851
852 * mips.igen (ERET): Implement.
853
854 * interp.c (decode_coproc): Return sign-extended EPC.
855
856 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
857
858 * interp.c (signal_exception): Do not ignore Trap.
859 (signal_exception): On TRAP, restart at exception address.
860 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
861 (signal_exception): Update.
862 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
863 so that TRAP instructions are caught.
864
865Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
866
867 * sim-main.h (struct hilo_access, struct hilo_history): Define,
868 contains HI/LO access history.
869 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
870 (HIACCESS, LOACCESS): Delete, replace with
871 (HIHISTORY, LOHISTORY): New macros.
872 (CHECKHILO): Delete all, moved to mips.igen
873
874 * gencode.c (build_instruction): Do not generate checks for
875 correct HI/LO register usage.
876
877 * interp.c (old_engine_run): Delete checks for correct HI/LO
878 register usage.
879
880 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
881 check_mf_cycles): New functions.
882 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
883 do_divu, domultx, do_mult, do_multu): Use.
884
885 * tx.igen ("madd", "maddu"): Use.
886
887Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
888
889 * mips.igen (DSRAV): Use function do_dsrav.
890 (SRAV): Use new function do_srav.
891
892 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
893 (B): Sign extend 11 bit immediate.
894 (EXT-B*): Shift 16 bit immediate left by 1.
895 (ADDIU*): Don't sign extend immediate value.
896
897Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
898
899 * m16run.c (sim_engine_run): Restore CIA after handling an event.
900
901 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
902 functions.
903
904 * mips.igen (delayslot32, nullify_next_insn): New functions.
905 (m16.igen): Always include.
906 (do_*): Add more tracing.
907
908 * m16.igen (delayslot16): Add NIA argument, could be called by a
909 32 bit MIPS16 instruction.
910
911 * interp.c (ifetch16): Move function from here.
912 * sim-main.c (ifetch16): To here.
913
914 * sim-main.c (ifetch16, ifetch32): Update to match current
915 implementations of LH, LW.
916 (signal_exception): Don't print out incorrect hex value of illegal
917 instruction.
918
919Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
920
921 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
922 instruction.
923
924 * m16.igen: Implement MIPS16 instructions.
925
926 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
927 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
928 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
929 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
930 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
931 bodies of corresponding code from 32 bit insn to these. Also used
932 by MIPS16 versions of functions.
933
934 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
935 (IMEM16): Drop NR argument from macro.
936
937Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
938
939 * Makefile.in (SIM_OBJS): Add sim-main.o.
940
941 * sim-main.h (address_translation, load_memory, store_memory,
942 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
943 as INLINE_SIM_MAIN.
944 (pr_addr, pr_uword64): Declare.
945 (sim-main.c): Include when H_REVEALS_MODULE_P.
946
947 * interp.c (address_translation, load_memory, store_memory,
948 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
949 from here.
950 * sim-main.c: To here. Fix compilation problems.
951
952 * configure.in: Enable inlining.
953 * configure: Re-config.
954
955Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
956
957 * configure: Regenerated to track ../common/aclocal.m4 changes.
958
959Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
960
961 * mips.igen: Include tx.igen.
962 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
963 * tx.igen: New file, contains MADD and MADDU.
964
965 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
966 the hardwired constant `7'.
967 (store_memory): Ditto.
968 (LOADDRMASK): Move definition to sim-main.h.
969
970 mips.igen (MTC0): Enable for r3900.
971 (ADDU): Add trace.
972
973 mips.igen (do_load_byte): Delete.
974 (do_load, do_store, do_load_left, do_load_write, do_store_left,
975 do_store_right): New functions.
976 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
977
978 configure.in: Let the tx39 use igen again.
979 configure: Update.
980
981Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
982
983 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
984 not an address sized quantity. Return zero for cache sizes.
985
986Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
987
988 * mips.igen (r3900): r3900 does not support 64 bit integer
989 operations.
990
991Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
992
993 * configure.in (mipstx39*-*-*): Use gencode simulator rather
994 than igen one.
995 * configure : Rebuild.
996
997Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
998
999 * configure: Regenerated to track ../common/aclocal.m4 changes.
1000
1001Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1002
1003 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1004
1005Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1006
1007 * configure: Regenerated to track ../common/aclocal.m4 changes.
1008 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1009
1010Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1011
1012 * configure: Regenerated to track ../common/aclocal.m4 changes.
1013
1014Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1015
1016 * interp.c (Max, Min): Comment out functions. Not yet used.
1017
1018Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1019
1020 * configure: Regenerated to track ../common/aclocal.m4 changes.
1021
1022Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1023
1024 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1025 configurable settings for stand-alone simulator.
1026
1027 * configure.in: Added X11 search, just in case.
1028
1029 * configure: Regenerated.
1030
1031Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1032
1033 * interp.c (sim_write, sim_read, load_memory, store_memory):
1034 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1035
1036Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1037
1038 * sim-main.h (GETFCC): Return an unsigned value.
1039
1040Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1041
1042 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1043 (DADD): Result destination is RD not RT.
1044
1045Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1046
1047 * sim-main.h (HIACCESS, LOACCESS): Always define.
1048
1049 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1050
1051 * interp.c (sim_info): Delete.
1052
1053Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1054
1055 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1056 (mips_option_handler): New argument `cpu'.
1057 (sim_open): Update call to sim_add_option_table.
1058
1059Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1060
1061 * mips.igen (CxC1): Add tracing.
1062
1063Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1064
1065 * sim-main.h (Max, Min): Declare.
1066
1067 * interp.c (Max, Min): New functions.
1068
1069 * mips.igen (BC1): Add tracing.
1070
1071Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1072
1073 * interp.c Added memory map for stack in vr4100
1074
1075Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1076
1077 * interp.c (load_memory): Add missing "break"'s.
1078
1079Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1080
1081 * interp.c (sim_store_register, sim_fetch_register): Pass in
1082 length parameter. Return -1.
1083
1084Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1085
1086 * interp.c: Added hardware init hook, fixed warnings.
1087
1088Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1089
1090 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1091
1092Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1093
1094 * interp.c (ifetch16): New function.
1095
1096 * sim-main.h (IMEM32): Rename IMEM.
1097 (IMEM16_IMMED): Define.
1098 (IMEM16): Define.
1099 (DELAY_SLOT): Update.
1100
1101 * m16run.c (sim_engine_run): New file.
1102
1103 * m16.igen: All instructions except LB.
1104 (LB): Call do_load_byte.
1105 * mips.igen (do_load_byte): New function.
1106 (LB): Call do_load_byte.
1107
1108 * mips.igen: Move spec for insn bit size and high bit from here.
1109 * Makefile.in (tmp-igen, tmp-m16): To here.
1110
1111 * m16.dc: New file, decode mips16 instructions.
1112
1113 * Makefile.in (SIM_NO_ALL): Define.
1114 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1115
1116Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1117
1118 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1119 point unit to 32 bit registers.
1120 * configure: Re-generate.
1121
1122Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1123
1124 * configure.in (sim_use_gen): Make IGEN the default simulator
1125 generator for generic 32 and 64 bit mips targets.
1126 * configure: Re-generate.
1127
1128Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1129
1130 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1131 bitsize.
1132
1133 * interp.c (sim_fetch_register, sim_store_register): Read/write
1134 FGR from correct location.
1135 (sim_open): Set size of FGR's according to
1136 WITH_TARGET_FLOATING_POINT_BITSIZE.
1137
1138 * sim-main.h (FGR): Store floating point registers in a separate
1139 array.
1140
1141Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1142
1143 * configure: Regenerated to track ../common/aclocal.m4 changes.
1144
1145Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1146
1147 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1148
1149 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1150
1151 * interp.c (pending_tick): New function. Deliver pending writes.
1152
1153 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1154 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1155 it can handle mixed sized quantites and single bits.
1156
1157Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1158
1159 * interp.c (oengine.h): Do not include when building with IGEN.
1160 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1161 (sim_info): Ditto for PROCESSOR_64BIT.
1162 (sim_monitor): Replace ut_reg with unsigned_word.
1163 (*): Ditto for t_reg.
1164 (LOADDRMASK): Define.
1165 (sim_open): Remove defunct check that host FP is IEEE compliant,
1166 using software to emulate floating point.
1167 (value_fpr, ...): Always compile, was conditional on HASFPU.
1168
1169Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1170
1171 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1172 size.
1173
1174 * interp.c (SD, CPU): Define.
1175 (mips_option_handler): Set flags in each CPU.
1176 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1177 (sim_close): Do not clear STATE, deleted anyway.
1178 (sim_write, sim_read): Assume CPU zero's vm should be used for
1179 data transfers.
1180 (sim_create_inferior): Set the PC for all processors.
1181 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1182 argument.
1183 (mips16_entry): Pass correct nr of args to store_word, load_word.
1184 (ColdReset): Cold reset all cpu's.
1185 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1186 (sim_monitor, load_memory, store_memory, signal_exception): Use
1187 `CPU' instead of STATE_CPU.
1188
1189
1190 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1191 SD or CPU_.
1192
1193 * sim-main.h (signal_exception): Add sim_cpu arg.
1194 (SignalException*): Pass both SD and CPU to signal_exception.
1195 * interp.c (signal_exception): Update.
1196
1197 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1198 Ditto
1199 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1200 address_translation): Ditto
1201 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1202
1203Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1204
1205 * configure: Regenerated to track ../common/aclocal.m4 changes.
1206
1207Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1208
1209 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1210
1211 * mips.igen (model): Map processor names onto BFD name.
1212
1213 * sim-main.h (CPU_CIA): Delete.
1214 (SET_CIA, GET_CIA): Define
1215
1216Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1217
1218 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1219 regiser.
1220
1221 * configure.in (default_endian): Configure a big-endian simulator
1222 by default.
1223 * configure: Re-generate.
1224
1225Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1226
1227 * configure: Regenerated to track ../common/aclocal.m4 changes.
1228
1229Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1230
1231 * interp.c (sim_monitor): Handle Densan monitor outbyte
1232 and inbyte functions.
1233
12341997-12-29 Felix Lee <flee@cygnus.com>
1235
1236 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1237
1238Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1239
1240 * Makefile.in (tmp-igen): Arrange for $zero to always be
1241 reset to zero after every instruction.
1242
1243Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1244
1245 * configure: Regenerated to track ../common/aclocal.m4 changes.
1246 * config.in: Ditto.
1247
1248Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1249
1250 * mips.igen (MSUB): Fix to work like MADD.
1251 * gencode.c (MSUB): Similarly.
1252
1253Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1254
1255 * configure: Regenerated to track ../common/aclocal.m4 changes.
1256
1257Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1258
1259 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1260
1261Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1262
1263 * sim-main.h (sim-fpu.h): Include.
1264
1265 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1266 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1267 using host independant sim_fpu module.
1268
1269Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1270
1271 * interp.c (signal_exception): Report internal errors with SIGABRT
1272 not SIGQUIT.
1273
1274 * sim-main.h (C0_CONFIG): New register.
1275 (signal.h): No longer include.
1276
1277 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1278
1279Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1280
1281 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1282
1283Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1284
1285 * mips.igen: Tag vr5000 instructions.
1286 (ANDI): Was missing mipsIV model, fix assembler syntax.
1287 (do_c_cond_fmt): New function.
1288 (C.cond.fmt): Handle mips I-III which do not support CC field
1289 separatly.
1290 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1291 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1292 in IV3.2 spec.
1293 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1294 vr5000 which saves LO in a GPR separatly.
1295
1296 * configure.in (enable-sim-igen): For vr5000, select vr5000
1297 specific instructions.
1298 * configure: Re-generate.
1299
1300Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1301
1302 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1303
1304 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1305 fmt_uninterpreted_64 bit cases to switch. Convert to
1306 fmt_formatted,
1307
1308 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1309
1310 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1311 as specified in IV3.2 spec.
1312 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1313
1314Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1315
1316 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1317 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1318 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1319 PENDING_FILL versions of instructions. Simplify.
1320 (X): New function.
1321 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1322 instructions.
1323 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1324 a signed value.
1325 (MTHI, MFHI): Disable code checking HI-LO.
1326
1327 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1328 global.
1329 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1330
1331Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1332
1333 * gencode.c (build_mips16_operands): Replace IPC with cia.
1334
1335 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1336 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1337 IPC to `cia'.
1338 (UndefinedResult): Replace function with macro/function
1339 combination.
1340 (sim_engine_run): Don't save PC in IPC.
1341
1342 * sim-main.h (IPC): Delete.
1343
1344
1345 * interp.c (signal_exception, store_word, load_word,
1346 address_translation, load_memory, store_memory, cache_op,
1347 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1348 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1349 current instruction address - cia - argument.
1350 (sim_read, sim_write): Call address_translation directly.
1351 (sim_engine_run): Rename variable vaddr to cia.
1352 (signal_exception): Pass cia to sim_monitor
1353
1354 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1355 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1356 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1357
1358 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1359 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1360 SIM_ASSERT.
1361
1362 * interp.c (signal_exception): Pass restart address to
1363 sim_engine_restart.
1364
1365 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1366 idecode.o): Add dependency.
1367
1368 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1369 Delete definitions
1370 (DELAY_SLOT): Update NIA not PC with branch address.
1371 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1372
1373 * mips.igen: Use CIA not PC in branch calculations.
1374 (illegal): Call SignalException.
1375 (BEQ, ADDIU): Fix assembler.
1376
1377Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1378
1379 * m16.igen (JALX): Was missing.
1380
1381 * configure.in (enable-sim-igen): New configuration option.
1382 * configure: Re-generate.
1383
1384 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1385
1386 * interp.c (load_memory, store_memory): Delete parameter RAW.
1387 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1388 bypassing {load,store}_memory.
1389
1390 * sim-main.h (ByteSwapMem): Delete definition.
1391
1392 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1393
1394 * interp.c (sim_do_command, sim_commands): Delete mips specific
1395 commands. Handled by module sim-options.
1396
1397 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1398 (WITH_MODULO_MEMORY): Define.
1399
1400 * interp.c (sim_info): Delete code printing memory size.
1401
1402 * interp.c (mips_size): Nee sim_size, delete function.
1403 (power2): Delete.
1404 (monitor, monitor_base, monitor_size): Delete global variables.
1405 (sim_open, sim_close): Delete code creating monitor and other
1406 memory regions. Use sim-memopts module, via sim_do_commandf, to
1407 manage memory regions.
1408 (load_memory, store_memory): Use sim-core for memory model.
1409
1410 * interp.c (address_translation): Delete all memory map code
1411 except line forcing 32 bit addresses.
1412
1413Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1414
1415 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1416 trace options.
1417
1418 * interp.c (logfh, logfile): Delete globals.
1419 (sim_open, sim_close): Delete code opening & closing log file.
1420 (mips_option_handler): Delete -l and -n options.
1421 (OPTION mips_options): Ditto.
1422
1423 * interp.c (OPTION mips_options): Rename option trace to dinero.
1424 (mips_option_handler): Update.
1425
1426Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1427
1428 * interp.c (fetch_str): New function.
1429 (sim_monitor): Rewrite using sim_read & sim_write.
1430 (sim_open): Check magic number.
1431 (sim_open): Write monitor vectors into memory using sim_write.
1432 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1433 (sim_read, sim_write): Simplify - transfer data one byte at a
1434 time.
1435 (load_memory, store_memory): Clarify meaning of parameter RAW.
1436
1437 * sim-main.h (isHOST): Defete definition.
1438 (isTARGET): Mark as depreciated.
1439 (address_translation): Delete parameter HOST.
1440
1441 * interp.c (address_translation): Delete parameter HOST.
1442
1443Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1444
1445 * mips.igen:
1446
1447 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1448 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1449
1450Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1451
1452 * mips.igen: Add model filter field to records.
1453
1454Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1455
1456 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1457
1458 interp.c (sim_engine_run): Do not compile function sim_engine_run
1459 when WITH_IGEN == 1.
1460
1461 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1462 target architecture.
1463
1464 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1465 igen. Replace with configuration variables sim_igen_flags /
1466 sim_m16_flags.
1467
1468 * m16.igen: New file. Copy mips16 insns here.
1469 * mips.igen: From here.
1470
1471Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1472
1473 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1474 to top.
1475 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1476
1477Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1478
1479 * gencode.c (build_instruction): Follow sim_write's lead in using
1480 BigEndianMem instead of !ByteSwapMem.
1481
1482Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1483
1484 * configure.in (sim_gen): Dependent on target, select type of
1485 generator. Always select old style generator.
1486
1487 configure: Re-generate.
1488
1489 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1490 targets.
1491 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1492 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1493 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1494 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1495 SIM_@sim_gen@_*, set by autoconf.
1496
1497Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1498
1499 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1500
1501 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1502 CURRENT_FLOATING_POINT instead.
1503
1504 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1505 (address_translation): Raise exception InstructionFetch when
1506 translation fails and isINSTRUCTION.
1507
1508 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1509 sim_engine_run): Change type of of vaddr and paddr to
1510 address_word.
1511 (address_translation, prefetch, load_memory, store_memory,
1512 cache_op): Change type of vAddr and pAddr to address_word.
1513
1514 * gencode.c (build_instruction): Change type of vaddr and paddr to
1515 address_word.
1516
1517Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1518
1519 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1520 macro to obtain result of ALU op.
1521
1522Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1523
1524 * interp.c (sim_info): Call profile_print.
1525
1526Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1527
1528 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1529
1530 * sim-main.h (WITH_PROFILE): Do not define, defined in
1531 common/sim-config.h. Use sim-profile module.
1532 (simPROFILE): Delete defintion.
1533
1534 * interp.c (PROFILE): Delete definition.
1535 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1536 (sim_close): Delete code writing profile histogram.
1537 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1538 Delete.
1539 (sim_engine_run): Delete code profiling the PC.
1540
1541Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1542
1543 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1544
1545 * interp.c (sim_monitor): Make register pointers of type
1546 unsigned_word*.
1547
1548 * sim-main.h: Make registers of type unsigned_word not
1549 signed_word.
1550
1551Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1552
1553 * interp.c (sync_operation): Rename from SyncOperation, make
1554 global, add SD argument.
1555 (prefetch): Rename from Prefetch, make global, add SD argument.
1556 (decode_coproc): Make global.
1557
1558 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1559
1560 * gencode.c (build_instruction): Generate DecodeCoproc not
1561 decode_coproc calls.
1562
1563 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1564 (SizeFGR): Move to sim-main.h
1565 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1566 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1567 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1568 sim-main.h.
1569 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1570 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1571 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1572 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1573 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1574 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1575
1576 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1577 exception.
1578 (sim-alu.h): Include.
1579 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1580 (sim_cia): Typedef to instruction_address.
1581
1582Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1583
1584 * Makefile.in (interp.o): Rename generated file engine.c to
1585 oengine.c.
1586
1587 * interp.c: Update.
1588
1589Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1590
1591 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1592
1593Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1594
1595 * gencode.c (build_instruction): For "FPSQRT", output correct
1596 number of arguments to Recip.
1597
1598Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1599
1600 * Makefile.in (interp.o): Depends on sim-main.h
1601
1602 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1603
1604 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1605 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1606 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1607 STATE, DSSTATE): Define
1608 (GPR, FGRIDX, ..): Define.
1609
1610 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1611 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1612 (GPR, FGRIDX, ...): Delete macros.
1613
1614 * interp.c: Update names to match defines from sim-main.h
1615
1616Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1617
1618 * interp.c (sim_monitor): Add SD argument.
1619 (sim_warning): Delete. Replace calls with calls to
1620 sim_io_eprintf.
1621 (sim_error): Delete. Replace calls with sim_io_error.
1622 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1623 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1624 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1625 argument.
1626 (mips_size): Rename from sim_size. Add SD argument.
1627
1628 * interp.c (simulator): Delete global variable.
1629 (callback): Delete global variable.
1630 (mips_option_handler, sim_open, sim_write, sim_read,
1631 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1632 sim_size,sim_monitor): Use sim_io_* not callback->*.
1633 (sim_open): ZALLOC simulator struct.
1634 (PROFILE): Do not define.
1635
1636Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1637
1638 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1639 support.h with corresponding code.
1640
1641 * sim-main.h (word64, uword64), support.h: Move definition to
1642 sim-main.h.
1643 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1644
1645 * support.h: Delete
1646 * Makefile.in: Update dependencies
1647 * interp.c: Do not include.
1648
1649Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * interp.c (address_translation, load_memory, store_memory,
1652 cache_op): Rename to from AddressTranslation et.al., make global,
1653 add SD argument
1654
1655 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1656 CacheOp): Define.
1657
1658 * interp.c (SignalException): Rename to signal_exception, make
1659 global.
1660
1661 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1662
1663 * sim-main.h (SignalException, SignalExceptionInterrupt,
1664 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1665 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1666 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1667 Define.
1668
1669 * interp.c, support.h: Use.
1670
1671Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1672
1673 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1674 to value_fpr / store_fpr. Add SD argument.
1675 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1676 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1677
1678 * sim-main.h (ValueFPR, StoreFPR): Define.
1679
1680Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1681
1682 * interp.c (sim_engine_run): Check consistency between configure
1683 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1684 and HASFPU.
1685
1686 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1687 (mips_fpu): Configure WITH_FLOATING_POINT.
1688 (mips_endian): Configure WITH_TARGET_ENDIAN.
1689 * configure: Update.
1690
1691Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1692
1693 * configure: Regenerated to track ../common/aclocal.m4 changes.
1694
1695Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1696
1697 * configure: Regenerated.
1698
1699Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1700
1701 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1702
1703Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1704
1705 * gencode.c (print_igen_insn_models): Assume certain architectures
1706 include all mips* instructions.
1707 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1708 instruction.
1709
1710 * Makefile.in (tmp.igen): Add target. Generate igen input from
1711 gencode file.
1712
1713 * gencode.c (FEATURE_IGEN): Define.
1714 (main): Add --igen option. Generate output in igen format.
1715 (process_instructions): Format output according to igen option.
1716 (print_igen_insn_format): New function.
1717 (print_igen_insn_models): New function.
1718 (process_instructions): Only issue warnings and ignore
1719 instructions when no FEATURE_IGEN.
1720
1721Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1722
1723 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1724 MIPS targets.
1725
1726Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1727
1728 * configure: Regenerated to track ../common/aclocal.m4 changes.
1729
1730Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1731
1732 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1733 SIM_RESERVED_BITS): Delete, moved to common.
1734 (SIM_EXTRA_CFLAGS): Update.
1735
1736Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1737
1738 * configure.in: Configure non-strict memory alignment.
1739 * configure: Regenerated to track ../common/aclocal.m4 changes.
1740
1741Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1742
1743 * configure: Regenerated to track ../common/aclocal.m4 changes.
1744
1745Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1746
1747 * gencode.c (SDBBP,DERET): Added (3900) insns.
1748 (RFE): Turn on for 3900.
1749 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1750 (dsstate): Made global.
1751 (SUBTARGET_R3900): Added.
1752 (CANCELDELAYSLOT): New.
1753 (SignalException): Ignore SystemCall rather than ignore and
1754 terminate. Add DebugBreakPoint handling.
1755 (decode_coproc): New insns RFE, DERET; and new registers Debug
1756 and DEPC protected by SUBTARGET_R3900.
1757 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1758 bits explicitly.
1759 * Makefile.in,configure.in: Add mips subtarget option.
1760 * configure: Update.
1761
1762Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1763
1764 * gencode.c: Add r3900 (tx39).
1765
1766
1767Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1768
1769 * gencode.c (build_instruction): Don't need to subtract 4 for
1770 JALR, just 2.
1771
1772Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1773
1774 * interp.c: Correct some HASFPU problems.
1775
1776Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1777
1778 * configure: Regenerated to track ../common/aclocal.m4 changes.
1779
1780Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1781
1782 * interp.c (mips_options): Fix samples option short form, should
1783 be `x'.
1784
1785Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1786
1787 * interp.c (sim_info): Enable info code. Was just returning.
1788
1789Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1790
1791 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1792 MFC0.
1793
1794Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1795
1796 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1797 constants.
1798 (build_instruction): Ditto for LL.
1799
1800Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1801
1802 * configure: Regenerated to track ../common/aclocal.m4 changes.
1803
1804Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1805
1806 * configure: Regenerated to track ../common/aclocal.m4 changes.
1807 * config.in: Ditto.
1808
1809Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1810
1811 * interp.c (sim_open): Add call to sim_analyze_program, update
1812 call to sim_config.
1813
1814Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1815
1816 * interp.c (sim_kill): Delete.
1817 (sim_create_inferior): Add ABFD argument. Set PC from same.
1818 (sim_load): Move code initializing trap handlers from here.
1819 (sim_open): To here.
1820 (sim_load): Delete, use sim-hload.c.
1821
1822 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1823
1824Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1825
1826 * configure: Regenerated to track ../common/aclocal.m4 changes.
1827 * config.in: Ditto.
1828
1829Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1830
1831 * interp.c (sim_open): Add ABFD argument.
1832 (sim_load): Move call to sim_config from here.
1833 (sim_open): To here. Check return status.
1834
1835Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1836
1837 * gencode.c (build_instruction): Two arg MADD should
1838 not assign result to $0.
1839
1840Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1841
1842 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1843 * sim/mips/configure.in: Regenerate.
1844
1845Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1846
1847 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1848 signed8, unsigned8 et.al. types.
1849
1850 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1851 hosts when selecting subreg.
1852
1853Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1854
1855 * interp.c (sim_engine_run): Reset the ZERO register to zero
1856 regardless of FEATURE_WARN_ZERO.
1857 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1858
1859Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1860
1861 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1862 (SignalException): For BreakPoints ignore any mode bits and just
1863 save the PC.
1864 (SignalException): Always set the CAUSE register.
1865
1866Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1867
1868 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1869 exception has been taken.
1870
1871 * interp.c: Implement the ERET and mt/f sr instructions.
1872
1873Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1874
1875 * interp.c (SignalException): Don't bother restarting an
1876 interrupt.
1877
1878Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1879
1880 * interp.c (SignalException): Really take an interrupt.
1881 (interrupt_event): Only deliver interrupts when enabled.
1882
1883Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1884
1885 * interp.c (sim_info): Only print info when verbose.
1886 (sim_info) Use sim_io_printf for output.
1887
1888Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1889
1890 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1891 mips architectures.
1892
1893Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1894
1895 * interp.c (sim_do_command): Check for common commands if a
1896 simulator specific command fails.
1897
1898Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1899
1900 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1901 and simBE when DEBUG is defined.
1902
1903Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1904
1905 * interp.c (interrupt_event): New function. Pass exception event
1906 onto exception handler.
1907
1908 * configure.in: Check for stdlib.h.
1909 * configure: Regenerate.
1910
1911 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1912 variable declaration.
1913 (build_instruction): Initialize memval1.
1914 (build_instruction): Add UNUSED attribute to byte, bigend,
1915 reverse.
1916 (build_operands): Ditto.
1917
1918 * interp.c: Fix GCC warnings.
1919 (sim_get_quit_code): Delete.
1920
1921 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1922 * Makefile.in: Ditto.
1923 * configure: Re-generate.
1924
1925 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1926
1927Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1928
1929 * interp.c (mips_option_handler): New function parse argumes using
1930 sim-options.
1931 (myname): Replace with STATE_MY_NAME.
1932 (sim_open): Delete check for host endianness - performed by
1933 sim_config.
1934 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1935 (sim_open): Move much of the initialization from here.
1936 (sim_load): To here. After the image has been loaded and
1937 endianness set.
1938 (sim_open): Move ColdReset from here.
1939 (sim_create_inferior): To here.
1940 (sim_open): Make FP check less dependant on host endianness.
1941
1942 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1943 run.
1944 * interp.c (sim_set_callbacks): Delete.
1945
1946 * interp.c (membank, membank_base, membank_size): Replace with
1947 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1948 (sim_open): Remove call to callback->init. gdb/run do this.
1949
1950 * interp.c: Update
1951
1952 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1953
1954 * interp.c (big_endian_p): Delete, replaced by
1955 current_target_byte_order.
1956
1957Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1958
1959 * interp.c (host_read_long, host_read_word, host_swap_word,
1960 host_swap_long): Delete. Using common sim-endian.
1961 (sim_fetch_register, sim_store_register): Use H2T.
1962 (pipeline_ticks): Delete. Handled by sim-events.
1963 (sim_info): Update.
1964 (sim_engine_run): Update.
1965
1966Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1967
1968 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1969 reason from here.
1970 (SignalException): To here. Signal using sim_engine_halt.
1971 (sim_stop_reason): Delete, moved to common.
1972
1973Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1974
1975 * interp.c (sim_open): Add callback argument.
1976 (sim_set_callbacks): Delete SIM_DESC argument.
1977 (sim_size): Ditto.
1978
1979Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1980
1981 * Makefile.in (SIM_OBJS): Add common modules.
1982
1983 * interp.c (sim_set_callbacks): Also set SD callback.
1984 (set_endianness, xfer_*, swap_*): Delete.
1985 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1986 Change to functions using sim-endian macros.
1987 (control_c, sim_stop): Delete, use common version.
1988 (simulate): Convert into.
1989 (sim_engine_run): This function.
1990 (sim_resume): Delete.
1991
1992 * interp.c (simulation): New variable - the simulator object.
1993 (sim_kind): Delete global - merged into simulation.
1994 (sim_load): Cleanup. Move PC assignment from here.
1995 (sim_create_inferior): To here.
1996
1997 * sim-main.h: New file.
1998 * interp.c (sim-main.h): Include.
1999
2000Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2001
2002 * configure: Regenerated to track ../common/aclocal.m4 changes.
2003
2004Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2005
2006 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2007
2008Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2009
2010 * gencode.c (build_instruction): DIV instructions: check
2011 for division by zero and integer overflow before using
2012 host's division operation.
2013
2014Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2015
2016 * Makefile.in (SIM_OBJS): Add sim-load.o.
2017 * interp.c: #include bfd.h.
2018 (target_byte_order): Delete.
2019 (sim_kind, myname, big_endian_p): New static locals.
2020 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2021 after argument parsing. Recognize -E arg, set endianness accordingly.
2022 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2023 load file into simulator. Set PC from bfd.
2024 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2025 (set_endianness): Use big_endian_p instead of target_byte_order.
2026
2027Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2028
2029 * interp.c (sim_size): Delete prototype - conflicts with
2030 definition in remote-sim.h. Correct definition.
2031
2032Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2033
2034 * configure: Regenerated to track ../common/aclocal.m4 changes.
2035 * config.in: Ditto.
2036
2037Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2038
2039 * interp.c (sim_open): New arg `kind'.
2040
2041 * configure: Regenerated to track ../common/aclocal.m4 changes.
2042
2043Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2044
2045 * configure: Regenerated to track ../common/aclocal.m4 changes.
2046
2047Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2048
2049 * interp.c (sim_open): Set optind to 0 before calling getopt.
2050
2051Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2052
2053 * configure: Regenerated to track ../common/aclocal.m4 changes.
2054
2055Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2056
2057 * interp.c : Replace uses of pr_addr with pr_uword64
2058 where the bit length is always 64 independent of SIM_ADDR.
2059 (pr_uword64) : added.
2060
2061Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2062
2063 * configure: Re-generate.
2064
2065Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2066
2067 * configure: Regenerate to track ../common/aclocal.m4 changes.
2068
2069Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2070
2071 * interp.c (sim_open): New SIM_DESC result. Argument is now
2072 in argv form.
2073 (other sim_*): New SIM_DESC argument.
2074
2075Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2076
2077 * interp.c: Fix printing of addresses for non-64-bit targets.
2078 (pr_addr): Add function to print address based on size.
2079
2080Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2081
2082 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2083
2084Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2085
2086 * gencode.c (build_mips16_operands): Correct computation of base
2087 address for extended PC relative instruction.
2088
2089Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2090
2091 * interp.c (mips16_entry): Add support for floating point cases.
2092 (SignalException): Pass floating point cases to mips16_entry.
2093 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2094 registers.
2095 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2096 or fmt_word.
2097 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2098 and then set the state to fmt_uninterpreted.
2099 (COP_SW): Temporarily set the state to fmt_word while calling
2100 ValueFPR.
2101
2102Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2103
2104 * gencode.c (build_instruction): The high order may be set in the
2105 comparison flags at any ISA level, not just ISA 4.
2106
2107Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2108
2109 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2110 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2111 * configure.in: sinclude ../common/aclocal.m4.
2112 * configure: Regenerated.
2113
2114Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2115
2116 * configure: Rebuild after change to aclocal.m4.
2117
2118Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2119
2120 * configure configure.in Makefile.in: Update to new configure
2121 scheme which is more compatible with WinGDB builds.
2122 * configure.in: Improve comment on how to run autoconf.
2123 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2124 * Makefile.in: Use autoconf substitution to install common
2125 makefile fragment.
2126
2127Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2128
2129 * gencode.c (build_instruction): Use BigEndianCPU instead of
2130 ByteSwapMem.
2131
2132Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2133
2134 * interp.c (sim_monitor): Make output to stdout visible in
2135 wingdb's I/O log window.
2136
2137Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2138
2139 * support.h: Undo previous change to SIGTRAP
2140 and SIGQUIT values.
2141
2142Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2143
2144 * interp.c (store_word, load_word): New static functions.
2145 (mips16_entry): New static function.
2146 (SignalException): Look for mips16 entry and exit instructions.
2147 (simulate): Use the correct index when setting fpr_state after
2148 doing a pending move.
2149
2150Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2151
2152 * interp.c: Fix byte-swapping code throughout to work on
2153 both little- and big-endian hosts.
2154
2155Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2156
2157 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2158 with gdb/config/i386/xm-windows.h.
2159
2160Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2161
2162 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2163 that messes up arithmetic shifts.
2164
2165Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2166
2167 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2168 SIGTRAP and SIGQUIT for _WIN32.
2169
2170Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2171
2172 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2173 force a 64 bit multiplication.
2174 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2175 destination register is 0, since that is the default mips16 nop
2176 instruction.
2177
2178Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2179
2180 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2181 (build_endian_shift): Don't check proc64.
2182 (build_instruction): Always set memval to uword64. Cast op2 to
2183 uword64 when shifting it left in memory instructions. Always use
2184 the same code for stores--don't special case proc64.
2185
2186 * gencode.c (build_mips16_operands): Fix base PC value for PC
2187 relative operands.
2188 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2189 jal instruction.
2190 * interp.c (simJALDELAYSLOT): Define.
2191 (JALDELAYSLOT): Define.
2192 (INDELAYSLOT, INJALDELAYSLOT): Define.
2193 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2194
2195Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2196
2197 * interp.c (sim_open): add flush_cache as a PMON routine
2198 (sim_monitor): handle flush_cache by ignoring it
2199
2200Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2201
2202 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2203 BigEndianMem.
2204 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2205 (BigEndianMem): Rename to ByteSwapMem and change sense.
2206 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2207 BigEndianMem references to !ByteSwapMem.
2208 (set_endianness): New function, with prototype.
2209 (sim_open): Call set_endianness.
2210 (sim_info): Use simBE instead of BigEndianMem.
2211 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2212 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2213 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2214 ifdefs, keeping the prototype declaration.
2215 (swap_word): Rewrite correctly.
2216 (ColdReset): Delete references to CONFIG. Delete endianness related
2217 code; moved to set_endianness.
2218
2219Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2220
2221 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2222 * interp.c (CHECKHILO): Define away.
2223 (simSIGINT): New macro.
2224 (membank_size): Increase from 1MB to 2MB.
2225 (control_c): New function.
2226 (sim_resume): Rename parameter signal to signal_number. Add local
2227 variable prev. Call signal before and after simulate.
2228 (sim_stop_reason): Add simSIGINT support.
2229 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2230 functions always.
2231 (sim_warning): Delete call to SignalException. Do call printf_filtered
2232 if logfh is NULL.
2233 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2234 a call to sim_warning.
2235
2236Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2237
2238 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2239 16 bit instructions.
2240
2241Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2242
2243 Add support for mips16 (16 bit MIPS implementation):
2244 * gencode.c (inst_type): Add mips16 instruction encoding types.
2245 (GETDATASIZEINSN): Define.
2246 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2247 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2248 mtlo.
2249 (MIPS16_DECODE): New table, for mips16 instructions.
2250 (bitmap_val): New static function.
2251 (struct mips16_op): Define.
2252 (mips16_op_table): New table, for mips16 operands.
2253 (build_mips16_operands): New static function.
2254 (process_instructions): If PC is odd, decode a mips16
2255 instruction. Break out instruction handling into new
2256 build_instruction function.
2257 (build_instruction): New static function, broken out of
2258 process_instructions. Check modifiers rather than flags for SHIFT
2259 bit count and m[ft]{hi,lo} direction.
2260 (usage): Pass program name to fprintf.
2261 (main): Remove unused variable this_option_optind. Change
2262 ``*loptarg++'' to ``loptarg++''.
2263 (my_strtoul): Parenthesize && within ||.
2264 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2265 (simulate): If PC is odd, fetch a 16 bit instruction, and
2266 increment PC by 2 rather than 4.
2267 * configure.in: Add case for mips16*-*-*.
2268 * configure: Rebuild.
2269
2270Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2271
2272 * interp.c: Allow -t to enable tracing in standalone simulator.
2273 Fix garbage output in trace file and error messages.
2274
2275Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2276
2277 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2278 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2279 * configure.in: Simplify using macros in ../common/aclocal.m4.
2280 * configure: Regenerated.
2281 * tconfig.in: New file.
2282
2283Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2284
2285 * interp.c: Fix bugs in 64-bit port.
2286 Use ansi function declarations for msvc compiler.
2287 Initialize and test file pointer in trace code.
2288 Prevent duplicate definition of LAST_EMED_REGNUM.
2289
2290Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2291
2292 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2293
2294Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2295
2296 * interp.c (SignalException): Check for explicit terminating
2297 breakpoint value.
2298 * gencode.c: Pass instruction value through SignalException()
2299 calls for Trap, Breakpoint and Syscall.
2300
2301Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2302
2303 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2304 only used on those hosts that provide it.
2305 * configure.in: Add sqrt() to list of functions to be checked for.
2306 * config.in: Re-generated.
2307 * configure: Re-generated.
2308
2309Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2310
2311 * gencode.c (process_instructions): Call build_endian_shift when
2312 expanding STORE RIGHT, to fix swr.
2313 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2314 clear the high bits.
2315 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2316 Fix float to int conversions to produce signed values.
2317
2318Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2319
2320 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2321 (process_instructions): Correct handling of nor instruction.
2322 Correct shift count for 32 bit shift instructions. Correct sign
2323 extension for arithmetic shifts to not shift the number of bits in
2324 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2325 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2326 Fix madd.
2327 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2328 It's OK to have a mult follow a mult. What's not OK is to have a
2329 mult follow an mfhi.
2330 (Convert): Comment out incorrect rounding code.
2331
2332Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2333
2334 * interp.c (sim_monitor): Improved monitor printf
2335 simulation. Tidied up simulator warnings, and added "--log" option
2336 for directing warning message output.
2337 * gencode.c: Use sim_warning() rather than WARNING macro.
2338
2339Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2340
2341 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2342 getopt1.o, rather than on gencode.c. Link objects together.
2343 Don't link against -liberty.
2344 (gencode.o, getopt.o, getopt1.o): New targets.
2345 * gencode.c: Include <ctype.h> and "ansidecl.h".
2346 (AND): Undefine after including "ansidecl.h".
2347 (ULONG_MAX): Define if not defined.
2348 (OP_*): Don't define macros; now defined in opcode/mips.h.
2349 (main): Call my_strtoul rather than strtoul.
2350 (my_strtoul): New static function.
2351
2352Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2353
2354 * gencode.c (process_instructions): Generate word64 and uword64
2355 instead of `long long' and `unsigned long long' data types.
2356 * interp.c: #include sysdep.h to get signals, and define default
2357 for SIGBUS.
2358 * (Convert): Work around for Visual-C++ compiler bug with type
2359 conversion.
2360 * support.h: Make things compile under Visual-C++ by using
2361 __int64 instead of `long long'. Change many refs to long long
2362 into word64/uword64 typedefs.
2363
2364Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2365
2366 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2367 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2368 (docdir): Removed.
2369 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2370 (AC_PROG_INSTALL): Added.
2371 (AC_PROG_CC): Moved to before configure.host call.
2372 * configure: Rebuilt.
2373
2374Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2375
2376 * configure.in: Define @SIMCONF@ depending on mips target.
2377 * configure: Rebuild.
2378 * Makefile.in (run): Add @SIMCONF@ to control simulator
2379 construction.
2380 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2381 * interp.c: Remove some debugging, provide more detailed error
2382 messages, update memory accesses to use LOADDRMASK.
2383
2384Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2385
2386 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2387 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2388 stamp-h.
2389 * configure: Rebuild.
2390 * config.in: New file, generated by autoheader.
2391 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2392 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2393 HAVE_ANINT and HAVE_AINT, as appropriate.
2394 * Makefile.in (run): Use @LIBS@ rather than -lm.
2395 (interp.o): Depend upon config.h.
2396 (Makefile): Just rebuild Makefile.
2397 (clean): Remove stamp-h.
2398 (mostlyclean): Make the same as clean, not as distclean.
2399 (config.h, stamp-h): New targets.
2400
2401Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2402
2403 * interp.c (ColdReset): Fix boolean test. Make all simulator
2404 globals static.
2405
2406Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2407
2408 * interp.c (xfer_direct_word, xfer_direct_long,
2409 swap_direct_word, swap_direct_long, xfer_big_word,
2410 xfer_big_long, xfer_little_word, xfer_little_long,
2411 swap_word,swap_long): Added.
2412 * interp.c (ColdReset): Provide function indirection to
2413 host<->simulated_target transfer routines.
2414 * interp.c (sim_store_register, sim_fetch_register): Updated to
2415 make use of indirected transfer routines.
2416
2417Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2418
2419 * gencode.c (process_instructions): Ensure FP ABS instruction
2420 recognised.
2421 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2422 system call support.
2423
2424Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2425
2426 * interp.c (sim_do_command): Complain if callback structure not
2427 initialised.
2428
2429Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2430
2431 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2432 support for Sun hosts.
2433 * Makefile.in (gencode): Ensure the host compiler and libraries
2434 used for cross-hosted build.
2435
2436Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2437
2438 * interp.c, gencode.c: Some more (TODO) tidying.
2439
2440Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2441
2442 * gencode.c, interp.c: Replaced explicit long long references with
2443 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2444 * support.h (SET64LO, SET64HI): Macros added.
2445
2446Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2447
2448 * configure: Regenerate with autoconf 2.7.
2449
2450Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2451
2452 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2453 * support.h: Remove superfluous "1" from #if.
2454 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2455
2456Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2457
2458 * interp.c (StoreFPR): Control UndefinedResult() call on
2459 WARN_RESULT manifest.
2460
2461Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2462
2463 * gencode.c: Tidied instruction decoding, and added FP instruction
2464 support.
2465
2466 * interp.c: Added dineroIII, and BSD profiling support. Also
2467 run-time FP handling.
2468
2469Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2470
2471 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2472 gencode.c, interp.c, support.h: created.
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