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sim: drop arch-specific config.h
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
52d37d2c
MF		 12021-06-16 Mike Frysinger <vapier@gentoo.org>
2
3 * configure: Regenerate.
4 * config.in: Removed.
5
bcaa61f7
MF		 62021-06-15 Mike Frysinger <vapier@gentoo.org>
7
8 * config.in, configure: Regenerate.
9
ba307cdd
MF		 102021-06-12 Mike Frysinger <vapier@gentoo.org>
11
12 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
13
dba333c1
MF		 142021-06-12 Mike Frysinger <vapier@gentoo.org>
15
16 * aclocal.m4, config.in, configure: Regenerate.
17
b15c5d7a
MF		 182021-06-12 Mike Frysinger <vapier@gentoo.org>
19
20 * configure.ac: Delete call to AC_CHECK_FUNCS.
21 * config.in, configure: Regenerate.
22
a55b92be
MF		 232021-06-08 Mike Frysinger <vapier@gentoo.org>
24
25 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
26 with $(IGEN).
27
8ea881d9
MF		 282021-05-29 Mike Frysinger <vapier@gentoo.org>
29
30 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
31
b312488f
FS		 322021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
33
168671c1
FS		 34 * interp.c (sim_open): Add shadow mappings from 32-bit
35 address space to 64-bit sign-extended address space.
36
372021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
38
b312488f
FS		 39 * interp.c (sim_create_inferior): Only truncate sign extension
40 bits for 32-bit target models.
41
f4fdd845
MF		 422021-05-17 Mike Frysinger <vapier@gentoo.org>
43
44 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
45
8ea7241c
MF		 462021-05-17 Mike Frysinger <vapier@gentoo.org>
47
48 * interp.c (sim_open): Switch to sim_state_alloc_extra.
49 * micromips.igen: Change SD to mips_sim_state.
50 * micromipsrun.c (sim_engine_run): Likewise.
51 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
52 (watch_options_install): Delete.
53 (struct swatch): Delete.
54 (struct sim_state): Delete.
55 (struct mips_sim_state): New struct.
56 (MIPS_SIM_STATE): Define.
57
6df01ab8
MF		 582021-05-16 Mike Frysinger <vapier@gentoo.org>
59
60 * interp.c: Replace config.h include with defs.h.
61 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
62 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
63 Include defs.h.
64
79633c12
MF		 652021-05-16 Mike Frysinger <vapier@gentoo.org>
66
67 * config.in, configure: Regenerate.
68
df68e12b
MF		 692021-05-14 Mike Frysinger <vapier@gentoo.org>
70
71 * interp.c: Update include path.
72
77c0fdb7
MF		 732021-05-04 Mike Frysinger <vapier@gentoo.org>
74
75 * dv-tx3904sio.c: Include stdlib.h.
76
9b1af85c
MF		 772021-05-04 Mike Frysinger <vapier@gentoo.org>
78
79 * configure.ac (hw_extra_devices): Inline contents into
80 SIM_AC_OPTION_HARDWARE and delete.
81 * configure: Regenerate.
82
d97ba9c6
MF		 832021-05-04 Mike Frysinger <vapier@gentoo.org>
84
85 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
86 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
87 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
88 * configure: Regenerate.
89
4df817de
MF		 902021-05-04 Mike Frysinger <vapier@gentoo.org>
91
92 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
93
aa0fca16
MF		 942021-05-04 Mike Frysinger <vapier@gentoo.org>
95
96 * configure: Regenerate.
97
adbaa7b8
MF		 982021-05-01 Mike Frysinger <vapier@gentoo.org>
99
100 * cp1.c (store_fcr): Mark static.
101
fe348617
MF		 1022021-05-01 Mike Frysinger <vapier@gentoo.org>
103
104 * config.in, configure: Regenerate.
105
9d903352
MF		 1062021-04-23 Mike Frysinger <vapier@gentoo.org>
107
108 * configure.ac (hw_enabled): Delete.
109 (SIM_AC_OPTION_HARDWARE): Delete first two args.
110 * configure: Regenerate.
111
19f6a43c
TT		 1122021-04-22 Tom Tromey <tom@tromey.com>
113
114 * configure, config.in: Rebuild.
115
e7d8f1da
TT		 1162021-04-22 Tom Tromey <tom@tromey.com>
117
118 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
119 Remove.
120 (SIM_EXTRA_DEPS): New variable.
121
efd82ac7
TT		 1222021-04-22 Tom Tromey <tom@tromey.com>
123
124 * configure: Rebuild.
125
2662c237
MF		 1262021-04-21 Mike Frysinger <vapier@gentoo.org>
127
128 * aclocal.m4: Regenerate.
129
1f195bc3
SM		 1302021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
131
132 * configure: Regenerate.
133
37e9f182
MF		 1342021-04-18 Mike Frysinger <vapier@gentoo.org>
135
136 * configure: Regenerate.
137
d5a71b11
MF		 1382021-04-12 Mike Frysinger <vapier@gentoo.org>
139
140 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
141
2b8d134b
SM		 1422021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
143
144 * Makefile.in: Set ASAN_OPTIONS when running igen.
145
5c6f091a
FS		 1462021-04-04 Steve Ellcey <sellcey@mips.com>
147 Faraz Shahbazker <fshahbazker@wavecomp.com>
148
149 * interp.c (sim_monitor): Add switch entries for unlink (13),
150 lseek (14), and stat (15).
151
b6b1c790
MF		 1522021-04-02 Mike Frysinger <vapier@gentoo.org>
153
154 * Makefile.in (../igen/igen): Delete rule.
155 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
156
c2783492
MF		 1572021-04-02 Mike Frysinger <vapier@gentoo.org>
158
159 * aclocal.m4, configure: Regenerate.
160
ebe9564b
MF		 1612021-02-28 Mike Frysinger <vapier@gentoo.org>
162
163 * configure: Regenerate.
164
f8069d55
MF		 1652021-02-27 Mike Frysinger <vapier@gentoo.org>
166
167 * Makefile.in (SIM_EXTRA_ALL): Delete.
168 (all): New target.
169
760b3e8b
MF		 1702021-02-21 Mike Frysinger <vapier@gentoo.org>
171
172 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
173 * aclocal.m4, configure: Regenerate.
174
136da8cd
MF		 1752021-02-13 Mike Frysinger <vapier@gentoo.org>
176
177 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
178 * aclocal.m4, configure: Regenerate.
179
4c0d76b9
MF		 1802021-02-06 Mike Frysinger <vapier@gentoo.org>
181
182 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
183
aa09469f
MF		 1842021-02-06 Mike Frysinger <vapier@gentoo.org>
185
186 * configure: Regenerate.
187
d4e3adda
MF		 1882021-01-30 Mike Frysinger <vapier@gentoo.org>
189
190 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
191
68ed2854
MF		 1922021-01-11 Mike Frysinger <vapier@gentoo.org>
193
194 * config.in, configure: Regenerate.
195 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
196 and strings.h include.
197
50df264d
MF		 1982021-01-09 Mike Frysinger <vapier@gentoo.org>
199
200 * configure: Regenerate.
201
bf470982
MF		 2022021-01-09 Mike Frysinger <vapier@gentoo.org>
203
204 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
205 * configure: Regenerate.
206
46f900c0
MF		 2072021-01-08 Mike Frysinger <vapier@gentoo.org>
208
209 * configure: Regenerate.
210
dfb856ba
MF		 2112021-01-04 Mike Frysinger <vapier@gentoo.org>
212
213 * configure: Regenerate.
214
382bc56b
PK		 2152020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
216
217 * sim-main.c: Include <stdlib.h>.
218
ad9675dd
PK		 2192020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
220
221 * cp1.c: Include <stdlib.h>.
222
f693213d
SM		 2232020-07-29 Simon Marchi <simon.marchi@efficios.com>
224
225 * configure: Re-generate.
226
5c887dd5
JB		 2272017-09-06 John Baldwin <jhb@FreeBSD.org>
228
229 * configure: Regenerate.
230
91588b3a
MF		 2312016-11-11 Mike Frysinger <vapier@gentoo.org>
232
6cb2202b 233 PR sim/20808
91588b3a
MF		 234 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
235 and SD to sd.
236
e04659e8
MF		 2372016-11-11 Mike Frysinger <vapier@gentoo.org>
238
6cb2202b 239 PR sim/20809
e04659e8
MF		 240 * mips.igen (check_u64): Enable for `r3900'.
241
1554f758
MF		 2422016-02-05 Mike Frysinger <vapier@gentoo.org>
243
244 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
245 STATE_PROG_BFD (sd).
246 * configure: Regenerate.
247
3d304f48
AB		 2482016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
249 Maciej W. Rozycki <macro@imgtec.com>
250
251 PR sim/19441
252 * micromips.igen (delayslot_micromips): Enable for `micromips32',
253 `micromips64' and `micromipsdsp' only.
254 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
255 (do_micromips_jalr, do_micromips_jal): Likewise.
256 (compute_movep_src_reg): Likewise.
257 (compute_andi16_imm): Likewise.
258 (convert_fmt_micromips): Likewise.
259 (convert_fmt_micromips_cvt_d): Likewise.
260 (convert_fmt_micromips_cvt_s): Likewise.
261 (FMT_MICROMIPS): Likewise.
262 (FMT_MICROMIPS_CVT_D): Likewise.
263 (FMT_MICROMIPS_CVT_S): Likewise.
264
b36d953b
MF		 2652016-01-12 Mike Frysinger <vapier@gentoo.org>
266
267 * interp.c: Include elf-bfd.h.
268 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
269 ELFCLASS32.
270
ce39bd38
MF		 2712016-01-10 Mike Frysinger <vapier@gentoo.org>
272
273 * config.in, configure: Regenerate.
274
99d8e879
MF		 2752016-01-10 Mike Frysinger <vapier@gentoo.org>
276
277 * configure: Regenerate.
278
35656e95
MF		 2792016-01-10 Mike Frysinger <vapier@gentoo.org>
280
281 * configure: Regenerate.
282
16f7876d
MF		 2832016-01-10 Mike Frysinger <vapier@gentoo.org>
284
285 * configure: Regenerate.
286
e19418e0
MF		 2872016-01-10 Mike Frysinger <vapier@gentoo.org>
288
289 * configure: Regenerate.
290
6d90347b
MF		 2912016-01-10 Mike Frysinger <vapier@gentoo.org>
292
293 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
294 * configure: Regenerate.
295
347fe5bb
MF		 2962016-01-10 Mike Frysinger <vapier@gentoo.org>
297
298 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
299 * configure: Regenerate.
300
22be3fbe
MF		 3012016-01-10 Mike Frysinger <vapier@gentoo.org>
302
303 * configure: Regenerate.
304
0dc73ef7
MF		 3052016-01-10 Mike Frysinger <vapier@gentoo.org>
306
307 * configure: Regenerate.
308
936df756
MF		 3092016-01-09 Mike Frysinger <vapier@gentoo.org>
310
311 * config.in, configure: Regenerate.
312
2e3d4f4d
MF		 3132016-01-06 Mike Frysinger <vapier@gentoo.org>
314
315 * interp.c (sim_open): Mark argv const.
316 (sim_create_inferior): Mark argv and env const.
317
9bbf6f91
MF		 3182016-01-04 Mike Frysinger <vapier@gentoo.org>
319
320 * configure: Regenerate.
321
77cf2ef5
MF		 3222016-01-03 Mike Frysinger <vapier@gentoo.org>
323
324 * interp.c (sim_open): Update sim_parse_args comment.
325
0cb8d851
MF		 3262016-01-03 Mike Frysinger <vapier@gentoo.org>
327
328 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
329 * configure: Regenerate.
330
1ac72f06
MF		 3312016-01-02 Mike Frysinger <vapier@gentoo.org>
332
333 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
334 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
335 * configure: Regenerate.
336 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
337
d47f5b30
MF		 3382016-01-02 Mike Frysinger <vapier@gentoo.org>
339
340 * dv-tx3904cpu.c (CPU, SD): Delete.
341
e1211e55
MF		 3422015-12-30 Mike Frysinger <vapier@gentoo.org>
343
344 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
345 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
346 (sim_store_register): Rename to ...
347 (mips_reg_store): ... this. Delete local cpu var.
348 Update sim_io_eprintf calls.
349 (sim_fetch_register): Rename to ...
350 (mips_reg_fetch): ... this. Delete local cpu var.
351 Update sim_io_eprintf calls.
352
5e744ef8
MF		 3532015-12-27 Mike Frysinger <vapier@gentoo.org>
354
355 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
356
1b393626
MF		 3572015-12-26 Mike Frysinger <vapier@gentoo.org>
358
359 * config.in, configure: Regenerate.
360
26f8bf63
MF		 3612015-12-26 Mike Frysinger <vapier@gentoo.org>
362
363 * interp.c (sim_write, sim_read): Delete.
364 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
365 (load_word): Likewise.
366 * micromips.igen (cache): Likewise.
367 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
368 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
369 do_store_left, do_store_right, do_load_double, do_store_double):
370 Likewise.
371 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
372 (do_prefx): Likewise.
373 * sim-main.c (address_translation, prefetch): Delete.
374 (ifetch32, ifetch16): Delete call to AddressTranslation and set
375 paddr=vaddr.
376 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
377 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
378 (LoadMemory, StoreMemory): Delete CCA arg.
379
ef04e371
MF		 3802015-12-24 Mike Frysinger <vapier@gentoo.org>
381
382 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
383 * configure: Regenerated.
384
cb379ede
MF		 3852015-12-24 Mike Frysinger <vapier@gentoo.org>
386
387 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
388 * tconfig.h: Delete.
389
26936211
MF		 3902015-12-24 Mike Frysinger <vapier@gentoo.org>
391
392 * tconfig.h (SIM_HANDLES_LMA): Delete.
393
84e8e361
MF		 3942015-12-24 Mike Frysinger <vapier@gentoo.org>
395
396 * sim-main.h (WITH_WATCHPOINTS): Delete.
397
3cabaf66
MF		 3982015-12-24 Mike Frysinger <vapier@gentoo.org>
399
400 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
401
8abe6c66
MF		 4022015-12-24 Mike Frysinger <vapier@gentoo.org>
403
404 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
405
1d19cae7
DV		 4062015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
407
408 * micromips.igen (process_isa_mode): Fix left shift of negative
409 value.
410
cdf850e9
MF		 4112015-11-17 Mike Frysinger <vapier@gentoo.org>
412
413 * sim-main.h (WITH_MODULO_MEMORY): Delete.
414
797eee42
MF		 4152015-11-15 Mike Frysinger <vapier@gentoo.org>
416
417 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
418
6e4f085c
MF		 4192015-11-14 Mike Frysinger <vapier@gentoo.org>
420
421 * interp.c (sim_close): Rename to ...
422 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
423 sim_io_shutdown.
424 * sim-main.h (mips_sim_close): Declare.
425 (SIM_CLOSE_HOOK): Define.
426
8e394ffc
AB		 4272015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
428 Ali Lown <ali.lown@imgtec.com>
429
430 * Makefile.in (tmp-micromips): New rule.
431 (tmp-mach-multi): Add support for micromips.
432 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
433 that works for both mips64 and micromips64.
434 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
435 micromips32.
436 Add build support for micromips.
437 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
438 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
439 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
440 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
441 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
442 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
443 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
444 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
445 Refactored instruction code to use these functions.
446 * dsp2.igen: Refactored instruction code to use the new functions.
447 * interp.c (decode_coproc): Refactored to work with any instruction
448 encoding.
449 (isa_mode): New variable
450 (RSVD_INSTRUCTION): Changed to 0x00000039.
451 * m16.igen (BREAK16): Refactored instruction to use do_break16.
452 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
453 * micromips.dc: New file.
454 * micromips.igen: New file.
455 * micromips16.dc: New file.
456 * micromipsdsp.igen: New file.
457 * micromipsrun.c: New file.
458 * mips.igen (do_swc1): Changed to work with any instruction encoding.
459 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
460 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
461 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
462 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
463 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
464 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
465 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
466 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
467 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
468 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
469 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
470 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
471 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
472 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
473 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
474 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
475 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
476 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
477 instructions.
478 Refactored instruction code to use these functions.
479 (RSVD): Changed to use new reserved instruction.
480 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
481 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
482 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
483 do_store_double): Added micromips32 and micromips64 models.
484 Added include for micromips.igen and micromipsdsp.igen
485 Add micromips32 and micromips64 models.
486 (DecodeCoproc): Updated to use new macro definition.
487 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
488 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
489 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
490 Refactored instruction code to use these functions.
491 * sim-main.h (CP0_operation): New enum.
492 (DecodeCoproc): Updated macro.
493 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
494 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
495 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
496 ISA_MODE_MICROMIPS): New defines.
497 (sim_state): Add isa_mode field.
498
8d0978fb
MF		 4992015-06-23 Mike Frysinger <vapier@gentoo.org>
500
501 * configure: Regenerate.
502
306f4178
MF		 5032015-06-12 Mike Frysinger <vapier@gentoo.org>
504
505 * configure.ac: Change configure.in to configure.ac.
506 * configure: Regenerate.
507
a3487082
MF		 5082015-06-12 Mike Frysinger <vapier@gentoo.org>
509
510 * configure: Regenerate.
511
29bc024d
MF		 5122015-06-12 Mike Frysinger <vapier@gentoo.org>
513
514 * interp.c [TRACE]: Delete.
515 (TRACE): Change to WITH_TRACE_ANY_P.
516 [!WITH_TRACE_ANY_P] (open_trace): Define.
517 (mips_option_handler, open_trace, sim_close, dotrace):
518 Change defined(TRACE) to WITH_TRACE_ANY_P.
519 (sim_open): Delete TRACE ifdef check.
520 * sim-main.c (load_memory): Delete TRACE ifdef check.
521 (store_memory): Likewise.
522 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
523 [!WITH_TRACE_ANY_P] (dotrace): Define.
524
3ebe2863
MF		 5252015-04-18 Mike Frysinger <vapier@gentoo.org>
526
527 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
528 comments.
529
20bca71d
MF		 5302015-04-18 Mike Frysinger <vapier@gentoo.org>
531
532 * sim-main.h (SIM_CPU): Delete.
533
7e83aa92
MF		 5342015-04-18 Mike Frysinger <vapier@gentoo.org>
535
536 * sim-main.h (sim_cia): Delete.
537
034685f9
MF		 5382015-04-17 Mike Frysinger <vapier@gentoo.org>
539
540 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
541 PU_PC_GET.
542 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
543 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
544 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
545 CIA_SET to CPU_PC_SET.
546 * sim-main.h (CIA_GET, CIA_SET): Delete.
547
78e9aa70
MF		 5482015-04-15 Mike Frysinger <vapier@gentoo.org>
549
550 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
551 * sim-main.h (STATE_CPU): Delete.
552
bf12d44e
MF		 5532015-04-13 Mike Frysinger <vapier@gentoo.org>
554
555 * configure: Regenerate.
556
7bebb329
MF		 5572015-04-13 Mike Frysinger <vapier@gentoo.org>
558
559 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
560 * interp.c (mips_pc_get, mips_pc_set): New functions.
561 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
562 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
563 (sim_pc_get): Delete.
564 * sim-main.h (SIM_CPU): Define.
565 (struct sim_state): Change cpu to an array of pointers.
566 (STATE_CPU): Drop &.
567
8ac57fbd
MF		 5682015-04-13 Mike Frysinger <vapier@gentoo.org>
569
570 * interp.c (mips_option_handler, open_trace, sim_close,
571 sim_write, sim_read, sim_store_register, sim_fetch_register,
572 sim_create_inferior, pr_addr, pr_uword64): Convert old style
573 prototypes.
574 (sim_open): Convert old style prototype. Change casts with
575 sim_write to unsigned char *.
576 (fetch_str): Change null to unsigned char, and change cast to
577 unsigned char *.
578 (sim_monitor): Change c & ch to unsigned char. Change cast to
579 unsigned char *.
580
e787f858
MF		 5812015-04-12 Mike Frysinger <vapier@gentoo.org>
582
583 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
584
122bbfb5
MF		 5852015-04-06 Mike Frysinger <vapier@gentoo.org>
586
587 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
588
0fe84f3f
MF		 5892015-04-01 Mike Frysinger <vapier@gentoo.org>
590
591 * tconfig.h (SIM_HAVE_PROFILE): Delete.
592
aadc9410
MF		 5932015-03-31 Mike Frysinger <vapier@gentoo.org>
594
595 * config.in, configure: Regenerate.
596
05f53ed6
MF		 5972015-03-24 Mike Frysinger <vapier@gentoo.org>
598
599 * interp.c (sim_pc_get): New function.
600
c0931f26
MF		 6012015-03-24 Mike Frysinger <vapier@gentoo.org>
602
603 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
604 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
605
30452bbe
MF		 6062015-03-24 Mike Frysinger <vapier@gentoo.org>
607
608 * configure: Regenerate.
609
64dd13df
MF		 6102015-03-23 Mike Frysinger <vapier@gentoo.org>
611
612 * configure: Regenerate.
613
49cd1634
MF		 6142015-03-23 Mike Frysinger <vapier@gentoo.org>
615
616 * configure: Regenerate.
617 * configure.ac (mips_extra_objs): Delete.
618 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
619 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
620
3649cb06
MF		 6212015-03-23 Mike Frysinger <vapier@gentoo.org>
622
623 * configure: Regenerate.
624 * configure.ac: Delete sim_hw checks for dv-sockser.
625
ae7d0cac
MF		 6262015-03-16 Mike Frysinger <vapier@gentoo.org>
627
628 * config.in, configure: Regenerate.
629 * tconfig.in: Rename file ...
630 * tconfig.h: ... here.
631
8406bb59
MF		 6322015-03-15 Mike Frysinger <vapier@gentoo.org>
633
634 * tconfig.in: Delete includes.
635 [HAVE_DV_SOCKSER]: Delete.
636
465fb143
MF		 6372015-03-14 Mike Frysinger <vapier@gentoo.org>
638
639 * Makefile.in (SIM_RUN_OBJS): Delete.
640
5cddc23a
MF		 6412015-03-14 Mike Frysinger <vapier@gentoo.org>
642
643 * configure.ac (AC_CHECK_HEADERS): Delete.
644 * aclocal.m4, configure: Regenerate.
645
2974be62
AM		 6462014-08-19 Alan Modra <amodra@gmail.com>
647
648 * configure: Regenerate.
649
faa743bb
RM		 6502014-08-15 Roland McGrath <mcgrathr@google.com>
651
652 * configure: Regenerate.
653 * config.in: Regenerate.
654
1a8a700e
MF		 6552014-03-04 Mike Frysinger <vapier@gentoo.org>
656
657 * configure: Regenerate.
658
bf3d9781
AM		 6592013-09-23 Alan Modra <amodra@gmail.com>
660
661 * configure: Regenerate.
662
31e6ad7d
MF		 6632013-06-03 Mike Frysinger <vapier@gentoo.org>
664
665 * aclocal.m4, configure: Regenerate.
666
d3685d60
TT		 6672013-05-10 Freddie Chopin <freddie_chopin@op.pl>
668
669 * configure: Rebuild.
670
1517bd27
MF		 6712013-03-26 Mike Frysinger <vapier@gentoo.org>
672
673 * configure: Regenerate.
674
3be31516
JS		 6752013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
676
677 * configure.ac: Address use of dv-sockser.o.
678 * tconfig.in: Conditionalize use of dv_sockser_install.
679 * configure: Regenerated.
680 * config.in: Regenerated.
681
37cb8f8e
SE		 6822012-10-04 Chao-ying Fu <fu@mips.com>
683 Steve Ellcey <sellcey@mips.com>
684
685 * mips/mips3264r2.igen (rdhwr): New.
686
87c8644f
JS		 6872012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
688
689 * configure.ac: Always link against dv-sockser.o.
690 * configure: Regenerate.
691
5f3ef9d0
JB		 6922012-06-15 Joel Brobecker <brobecker@adacore.com>
693
694 * config.in, configure: Regenerate.
695
a6ff997c
NC		 6962012-05-18 Nick Clifton <nickc@redhat.com>
697
698 PR 14072
699 * interp.c: Include config.h before system header files.
700
2232061b
MF		 7012012-03-24 Mike Frysinger <vapier@gentoo.org>
702
703 * aclocal.m4, config.in, configure: Regenerate.
704
db2e4d67
MF		 7052011-12-03 Mike Frysinger <vapier@gentoo.org>
706
707 * aclocal.m4: New file.
708 * configure: Regenerate.
709
4399a56b
MF		 7102011-10-19 Mike Frysinger <vapier@gentoo.org>
711
712 * configure: Regenerate after common/acinclude.m4 update.
713
9c082ca8
MF		 7142011-10-17 Mike Frysinger <vapier@gentoo.org>
715
716 * configure.ac: Change include to common/acinclude.m4.
717
6ffe910a
MF		 7182011-10-17 Mike Frysinger <vapier@gentoo.org>
719
720 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
721 call. Replace common.m4 include with SIM_AC_COMMON.
722 * configure: Regenerate.
723
31b28250
HPN		 7242011-07-08 Hans-Peter Nilsson <hp@axis.com>
725
3faa01e3
HPN		 726 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
727 $(SIM_EXTRA_DEPS).
728 (tmp-mach-multi): Exit early when igen fails.
31b28250 729
2419798b
MF		 7302011-07-05 Mike Frysinger <vapier@gentoo.org>
731
732 * interp.c (sim_do_command): Delete.
733
d79fe0d6
MF		 7342011-02-14 Mike Frysinger <vapier@gentoo.org>
735
736 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
737 (tx3904sio_fifo_reset): Likewise.
738 * interp.c (sim_monitor): Likewise.
739
5558e7e6
MF		 7402010-04-14 Mike Frysinger <vapier@gentoo.org>
741
742 * interp.c (sim_write): Add const to buffer arg.
743
35aafff4
JB		 7442010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
745
746 * interp.c: Don't include sysdep.h
747
3725885a
RW		 7482010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
749
750 * configure: Regenerate.
751
d6416cdc
RW		 7522009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
753
81ecdfbb
RW		 754 * config.in: Regenerate.
755 * configure: Likewise.
756
d6416cdc
RW		 757 * configure: Regenerate.
758
b5bd9624
HPN		 7592008-07-11 Hans-Peter Nilsson <hp@axis.com>
760
761 * configure: Regenerate to track ../common/common.m4 changes.
762 * config.in: Ditto.
763
6efef468 7642008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 765 Daniel Jacobowitz <dan@codesourcery.com>
766 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 767
768 * configure: Regenerate.
769
60dc88db
RS		 7702007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
771
772 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
773 that unconditionally allows fmt_ps.
774 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
775 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
776 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
777 filter from 64,f to 32,f.
778 (PREFX): Change filter from 64 to 32.
779 (LDXC1, LUXC1): Provide separate mips32r2 implementations
780 that use do_load_double instead of do_load. Make both LUXC1
781 versions unpredictable if SizeFGR () != 64.
782 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
783 instead of do_store. Remove unused variable. Make both SUXC1
784 versions unpredictable if SizeFGR () != 64.
785
599ca73e
RS		 7862007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
787
788 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
789 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
790 shifts for that case.
791
2525df03
NC		 7922007-09-04 Nick Clifton <nickc@redhat.com>
793
794 * interp.c (options enum): Add OPTION_INFO_MEMORY.
795 (display_mem_info): New static variable.
796 (mips_option_handler): Handle OPTION_INFO_MEMORY.
797 (mips_options): Add info-memory and memory-info.
798 (sim_open): After processing the command line and board
799 specification, check display_mem_info. If it is set then
800 call the real handler for the --memory-info command line
801 switch.
802
35ee6e1e
JB		 8032007-08-24 Joel Brobecker <brobecker@adacore.com>
804
805 * configure.ac: Change license of multi-run.c to GPL version 3.
806 * configure: Regenerate.
807
d5fb0879
RS		 8082007-06-28 Richard Sandiford <richard@codesourcery.com>
809
810 * configure.ac, configure: Revert last patch.
811
2a2ce21b
RS		 8122007-06-26 Richard Sandiford <richard@codesourcery.com>
813
814 * configure.ac (sim_mipsisa3264_configs): New variable.
815 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
816 every configuration support all four targets, using the triplet to
817 determine the default.
818 * configure: Regenerate.
819
efdcccc9
RS		 8202007-06-25 Richard Sandiford <richard@codesourcery.com>
821
0a7692b2 822 * Makefile.in (m16run.o): New rule.
efdcccc9 823
f532a356
TS		 8242007-05-15 Thiemo Seufer <ths@mips.com>
825
826 * mips3264r2.igen (DSHD): Fix compile warning.
827
bfe9c90b
TS		 8282007-05-14 Thiemo Seufer <ths@mips.com>
829
830 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
831 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
832 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
833 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
834 for mips32r2.
835
53f4826b
TS		 8362007-03-01 Thiemo Seufer <ths@mips.com>
837
838 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
839 and mips64.
840
8bf3ddc8
TS		 8412007-02-20 Thiemo Seufer <ths@mips.com>
842
843 * dsp.igen: Update copyright notice.
844 * dsp2.igen: Fix copyright notice.
845
8b082fb1 8462007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 847 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 848
849 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
850 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
851 Add dsp2 to sim_igen_machine.
852 * configure: Regenerate.
853 * dsp.igen (do_ph_op): Add MUL support when op = 2.
854 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
855 (mulq_rs.ph): Use do_ph_mulq.
856 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
857 * mips.igen: Add dsp2 model and include dsp2.igen.
858 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
859 for *mips32r2, *mips64r2, *dsp.
860 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
861 for *mips32r2, *mips64r2, *dsp2.
862 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
863
b1004875 8642007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 865 Nigel Stephens <nigel@mips.com>
b1004875
TS		 866
867 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
868 jumps with hazard barrier.
869
f8df4c77 8702007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 871 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 872
873 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
874 after each call to sim_io_write.
875
b1004875 8762007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 877 Nigel Stephens <nigel@mips.com>
b1004875
TS		 878
879 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
880 supported by this simulator.
07802d98
TS		 881 (decode_coproc): Recognise additional CP0 Config registers
882 correctly.
883
14fb6c5a 8842007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 885 Nigel Stephens <nigel@mips.com>
886 David Ung <davidu@mips.com>
14fb6c5a
TS		 887
888 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
889 uninterpreted formats. If fmt is one of the uninterpreted types
890 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
891 fmt_word, and fmt_uninterpreted_64 like fmt_long.
892 (store_fpr): When writing an invalid odd register, set the
893 matching even register to fmt_unknown, not the following register.
894 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
895 the the memory window at offset 0 set by --memory-size command
896 line option.
897 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
898 point register.
899 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
900 register.
901 (sim_monitor): When returning the memory size to the MIPS
902 application, use the value in STATE_MEM_SIZE, not an arbitrary
903 hardcoded value.
904 (cop_lw): Don' mess around with FPR_STATE, just pass
905 fmt_uninterpreted_32 to StoreFPR.
906 (cop_sw): Similarly.
907 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
908 (cop_sd): Similarly.
909 * mips.igen (not_word_value): Single version for mips32, mips64
910 and mips16.
911
c8847145 9122007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 913 Nigel Stephens <nigel@mips.com>
c8847145
TS		 914
915 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
916 MBytes.
917
4b5d35ee
TS		 9182007-02-17 Thiemo Seufer <ths@mips.com>
919
920 * configure.ac (mips*-sde-elf*): Move in front of generic machine
921 configuration.
922 * configure: Regenerate.
923
3669427c
TS		 9242007-02-17 Thiemo Seufer <ths@mips.com>
925
926 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
927 Add mdmx to sim_igen_machine.
928 (mipsisa64*-*-*): Likewise. Remove dsp.
929 (mipsisa32*-*-*): Remove dsp.
930 * configure: Regenerate.
931
109ad085
TS		 9322007-02-13 Thiemo Seufer <ths@mips.com>
933
934 * configure.ac: Add mips*-sde-elf* target.
935 * configure: Regenerate.
936
921d7ad3
HPN		 9372006-12-21 Hans-Peter Nilsson <hp@axis.com>
938
939 * acconfig.h: Remove.
940 * config.in, configure: Regenerate.
941
02f97da7
TS		 9422006-11-07 Thiemo Seufer <ths@mips.com>
943
944 * dsp.igen (do_w_op): Fix compiler warning.
945
2d2733fc 9462006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 947 David Ung <davidu@mips.com>
2d2733fc
TS		 948
949 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
950 sim_igen_machine.
951 * configure: Regenerate.
952 * mips.igen (model): Add smartmips.
953 (MADDU): Increment ACX if carry.
954 (do_mult): Clear ACX.
955 (ROR,RORV): Add smartmips.
72f4393d 956 (include): Include smartmips.igen.
2d2733fc
TS		 957 * sim-main.h (ACX): Set to REGISTERS[89].
958 * smartmips.igen: New file.
959
d85c3a10 9602006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 961 David Ung <davidu@mips.com>
d85c3a10
TS		 962
963 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
964 mips3264r2.igen. Add missing dependency rules.
965 * m16e.igen: Support for mips16e save/restore instructions.
966
e85e3205
RE		 9672006-06-13 Richard Earnshaw <rearnsha@arm.com>
968
969 * configure: Regenerated.
970
2f0122dc
DJ		 9712006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
972
973 * configure: Regenerated.
974
20e95c23
DJ		 9752006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
976
977 * configure: Regenerated.
978
69088b17
CF		 9792006-05-15 Chao-ying Fu <fu@mips.com>
980
981 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
982
0275de4e
NC		 9832006-04-18 Nick Clifton <nickc@redhat.com>
984
985 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
986 statement.
987
b3a3ffef
HPN		 9882006-03-29 Hans-Peter Nilsson <hp@axis.com>
989
990 * configure: Regenerate.
991
40a5538e
CF		 9922005-12-14 Chao-ying Fu <fu@mips.com>
993
994 * Makefile.in (SIM_OBJS): Add dsp.o.
995 (dsp.o): New dependency.
996 (IGEN_INCLUDE): Add dsp.igen.
997 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
998 mipsisa64*-*-*): Add dsp to sim_igen_machine.
999 * configure: Regenerate.
1000 * mips.igen: Add dsp model and include dsp.igen.
1001 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
1002 because these instructions are extended in DSP ASE.
1003 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
1004 adding 6 DSP accumulator registers and 1 DSP control register.
1005 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
1006 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
1007 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
1008 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
1009 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
1010 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
1011 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
1012 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
1013 DSPCR_CCOND_SMASK): New define.
1014 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
1015 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
1016
21d14896
ILT		 10172005-07-08 Ian Lance Taylor <ian@airs.com>
1018
1019 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
1020
b16d63da 10212005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1022 Nigel Stephens <nigel@mips.com>
1023
1024 * mips.igen: New mips16e model and include m16e.igen.
1025 (check_u64): Add mips16e tag.
1026 * m16e.igen: New file for MIPS16e instructions.
1027 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1028 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1029 models.
1030 * configure: Regenerate.
b16d63da 1031
e70cb6cd 10322005-05-26 David Ung <davidu@mips.com>
72f4393d 1033
e70cb6cd
CD		 1034 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1035 tags to all instructions which are applicable to the new ISAs.
1036 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1037 vr.igen.
1038 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1039 instructions.
e70cb6cd
CD		 1040 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1041 to mips.igen.
1042 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1043 * configure: Regenerate.
72f4393d 1044
2b193c4a
MK		 10452005-03-23 Mark Kettenis <kettenis@gnu.org>
1046
1047 * configure: Regenerate.
1048
35695fd6
AC		 10492005-01-14 Andrew Cagney <cagney@gnu.org>
1050
1051 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1052 explicit call to AC_CONFIG_HEADER.
1053 * configure: Regenerate.
1054
f0569246
AC		 10552005-01-12 Andrew Cagney <cagney@gnu.org>
1056
1057 * configure.ac: Update to use ../common/common.m4.
1058 * configure: Re-generate.
1059
38f48d72
AC		 10602005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1061
1062 * configure: Regenerated to track ../common/aclocal.m4 changes.
1063
b7026657
AC		 10642005-01-07 Andrew Cagney <cagney@gnu.org>
1065
1066 * configure.ac: Rename configure.in, require autoconf 2.59.
1067 * configure: Re-generate.
1068
379832de
HPN		 10692004-12-08 Hans-Peter Nilsson <hp@axis.com>
1070
1071 * configure: Regenerate for ../common/aclocal.m4 update.
1072
cd62154c 10732004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1074
cd62154c
AC		 1075 Committed by Andrew Cagney.
1076 * m16.igen (CMP, CMPI): Fix assembler.
1077
e5da76ec
CD		 10782004-08-18 Chris Demetriou <cgd@broadcom.com>
1079
1080 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1081 * configure: Regenerate.
1082
139181c8
CD		 10832004-06-25 Chris Demetriou <cgd@broadcom.com>
1084
1085 * configure.in (sim_m16_machine): Include mipsIII.
1086 * configure: Regenerate.
1087
1a27f959
CD		 10882004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1089
72f4393d 1090 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1091 from COP0_BADVADDR.
1092 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1093
5dbb7b5a
CD		 10942004-04-10 Chris Demetriou <cgd@broadcom.com>
1095
1096 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1097
14234056
CD		 10982004-04-09 Chris Demetriou <cgd@broadcom.com>
1099
1100 * mips.igen (check_fmt): Remove.
1101 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1102 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1103 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1104 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1105 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1106 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1107 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1108 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1109 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1110 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1111
c6f9085c
CD		 11122004-04-09 Chris Demetriou <cgd@broadcom.com>
1113
1114 * sb1.igen (check_sbx): New function.
1115 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1116
11d66e66 11172004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1118 Richard Sandiford <rsandifo@redhat.com>
1119
1120 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1121 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1122 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1123 separate implementations for mipsIV and mipsV. Use new macros to
1124 determine whether the restrictions apply.
1125
b3208fb8
CD		 11262004-01-19 Chris Demetriou <cgd@broadcom.com>
1127
1128 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1129 (check_mult_hilo): Improve comments.
1130 (check_div_hilo): Likewise. Also, fork off a new version
1131 to handle mips32/mips64 (since there are no hazards to check
1132 in MIPS32/MIPS64).
1133
9a1d84fb
CD		 11342003-06-17 Richard Sandiford <rsandifo@redhat.com>
1135
1136 * mips.igen (do_dmultx): Fix check for negative operands.
1137
ae451ac6
ILT		 11382003-05-16 Ian Lance Taylor <ian@airs.com>
1139
1140 * Makefile.in (SHELL): Make sure this is defined.
1141 (various): Use $(SHELL) whenever we invoke move-if-change.
1142
dd69d292
CD		 11432003-05-03 Chris Demetriou <cgd@broadcom.com>
1144
1145 * cp1.c: Tweak attribution slightly.
1146 * cp1.h: Likewise.
1147 * mdmx.c: Likewise.
1148 * mdmx.igen: Likewise.
1149 * mips3d.igen: Likewise.
1150 * sb1.igen: Likewise.
1151
bcd0068e
CD		 11522003-04-15 Richard Sandiford <rsandifo@redhat.com>
1153
1154 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1155 unsigned operands.
1156
6b4a8935
AC		 11572003-02-27 Andrew Cagney <cagney@redhat.com>
1158
601da316
AC		 1159 * interp.c (sim_open): Rename _bfd to bfd.
1160 (sim_create_inferior): Ditto.
6b4a8935 1161
d29e330f
CD		 11622003-01-14 Chris Demetriou <cgd@broadcom.com>
1163
1164 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1165
a2353a08
CD		 11662003-01-14 Chris Demetriou <cgd@broadcom.com>
1167
1168 * mips.igen (EI, DI): Remove.
1169
80551777
CD		 11702003-01-05 Richard Sandiford <rsandifo@redhat.com>
1171
1172 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1173
4c54fc26
CD		 11742003-01-04 Richard Sandiford <rsandifo@redhat.com>
1175 Andrew Cagney <ac131313@redhat.com>
1176 Gavin Romig-Koch <gavin@redhat.com>
1177 Graydon Hoare <graydon@redhat.com>
1178 Aldy Hernandez <aldyh@redhat.com>
1179 Dave Brolley <brolley@redhat.com>
1180 Chris Demetriou <cgd@broadcom.com>
1181
1182 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1183 (sim_mach_default): New variable.
1184 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1185 Add a new simulator generator, MULTI.
1186 * configure: Regenerate.
1187 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1188 (multi-run.o): New dependency.
1189 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1190 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1191 (tmp-multi): Combine them.
1192 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1193 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1194 (distclean-extra): New rule.
1195 * sim-main.h: Include bfd.h.
1196 (MIPS_MACH): New macro.
1197 * mips.igen (vr4120, vr5400, vr5500): New models.
1198 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1199 * vr.igen: Replace with new version.
1200
e6c674b8
CD		 12012003-01-04 Chris Demetriou <cgd@broadcom.com>
1202
1203 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1204 * configure: Regenerate.
1205
28f50ac8
CD		 12062002-12-31 Chris Demetriou <cgd@broadcom.com>
1207
1208 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1209 * mips.igen: Remove all invocations of check_branch_bug and
1210 mark_branch_bug.
1211
5071ffe6
CD		 12122002-12-16 Chris Demetriou <cgd@broadcom.com>
1213
72f4393d 1214 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1215
06e7837e
CD		 12162002-07-30 Chris Demetriou <cgd@broadcom.com>
1217
1218 * mips.igen (do_load_double, do_store_double): New functions.
1219 (LDC1, SDC1): Rename to...
1220 (LDC1b, SDC1b): respectively.
1221 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1222
2265c243
MS		 12232002-07-29 Michael Snyder <msnyder@redhat.com>
1224
1225 * cp1.c (fp_recip2): Modify initialization expression so that
1226 GCC will recognize it as constant.
1227
a2f8b4f3
CD		 12282002-06-18 Chris Demetriou <cgd@broadcom.com>
1229
1230 * mdmx.c (SD_): Delete.
1231 (Unpredictable): Re-define, for now, to directly invoke
1232 unpredictable_action().
1233 (mdmx_acc_op): Fix error in .ob immediate handling.
1234
b4b6c939
AC		 12352002-06-18 Andrew Cagney <cagney@redhat.com>
1236
1237 * interp.c (sim_firmware_command): Initialize `address'.
1238
c8cca39f
AC		 12392002-06-16 Andrew Cagney <ac131313@redhat.com>
1240
1241 * configure: Regenerated to track ../common/aclocal.m4 changes.
1242
e7e81181 12432002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1244 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1245
1246 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1247 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1248 * mips.igen: Include mips3d.igen.
1249 (mips3d): New model name for MIPS-3D ASE instructions.
1250 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1251 instructions.
e7e81181
CD		 1252 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1253 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1254 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1255 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1256 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1257 (RSquareRoot1, RSquareRoot2): New macros.
1258 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1259 (fp_rsqrt2): New functions.
1260 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1261 * configure: Regenerate.
1262
3a2b820e 12632002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1264 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1265
1266 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1267 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1268 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1269 (convert): Note that this function is not used for paired-single
1270 format conversions.
1271 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1272 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1273 (check_fmt_p): Enable paired-single support.
1274 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1275 (PUU.PS): New instructions.
1276 (CVT.S.fmt): Don't use this instruction for paired-single format
1277 destinations.
1278 * sim-main.h (FP_formats): New value 'fmt_ps.'
1279 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1280 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1281
d18ea9c2
CD		 12822002-06-12 Chris Demetriou <cgd@broadcom.com>
1283
1284 * mips.igen: Fix formatting of function calls in
1285 many FP operations.
1286
95fd5cee
CD		 12872002-06-12 Chris Demetriou <cgd@broadcom.com>
1288
1289 * mips.igen (MOVN, MOVZ): Trace result.
1290 (TNEI): Print "tnei" as the opcode name in traces.
1291 (CEIL.W): Add disassembly string for traces.
1292 (RSQRT.fmt): Make location of disassembly string consistent
1293 with other instructions.
1294
4f0d55ae
CD		 12952002-06-12 Chris Demetriou <cgd@broadcom.com>
1296
1297 * mips.igen (X): Delete unused function.
1298
3c25f8c7
AC		 12992002-06-08 Andrew Cagney <cagney@redhat.com>
1300
1301 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1302
f3c08b7e 13032002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1304 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1305
1306 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1307 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1308 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1309 (fp_nmsub): New prototypes.
1310 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1311 (NegMultiplySub): New defines.
1312 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1313 (MADD.D, MADD.S): Replace with...
1314 (MADD.fmt): New instruction.
1315 (MSUB.D, MSUB.S): Replace with...
1316 (MSUB.fmt): New instruction.
1317 (NMADD.D, NMADD.S): Replace with...
1318 (NMADD.fmt): New instruction.
1319 (NMSUB.D, MSUB.S): Replace with...
1320 (NMSUB.fmt): New instruction.
1321
52714ff9 13222002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1323 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1324
1325 * cp1.c: Fix more comment spelling and formatting.
1326 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1327 (denorm_mode): New function.
1328 (fpu_unary, fpu_binary): Round results after operation, collect
1329 status from rounding operations, and update the FCSR.
1330 (convert): Collect status from integer conversions and rounding
1331 operations, and update the FCSR. Adjust NaN values that result
1332 from conversions. Convert to use sim_io_eprintf rather than
1333 fprintf, and remove some debugging code.
1334 * cp1.h (fenr_FS): New define.
1335
577d8c4b
CD		 13362002-06-07 Chris Demetriou <cgd@broadcom.com>
1337
1338 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1339 rounding mode to sim FP rounding mode flag conversion code into...
1340 (rounding_mode): New function.
1341
196496ed
CD		 13422002-06-07 Chris Demetriou <cgd@broadcom.com>
1343
1344 * cp1.c: Clean up formatting of a few comments.
1345 (value_fpr): Reformat switch statement.
1346
cfe9ea23 13472002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1348 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1349
1350 * cp1.h: New file.
1351 * sim-main.h: Include cp1.h.
1352 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1353 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1354 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1355 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1356 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1357 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1358 * cp1.c: Don't include sim-fpu.h; already included by
1359 sim-main.h. Clean up formatting of some comments.
1360 (NaN, Equal, Less): Remove.
1361 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1362 (fp_cmp): New functions.
1363 * mips.igen (do_c_cond_fmt): Remove.
1364 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1365 Compare. Add result tracing.
1366 (CxC1): Remove, replace with...
1367 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1368 (DMxC1): Remove, replace with...
1369 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1370 (MxC1): Remove, replace with...
1371 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1372
ee7254b0
CD		 13732002-06-04 Chris Demetriou <cgd@broadcom.com>
1374
1375 * sim-main.h (FGRIDX): Remove, replace all uses with...
1376 (FGR_BASE): New macro.
1377 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1378 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1379 (NR_FGR, FGR): Likewise.
1380 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1381 * mips.igen: Likewise.
1382
d3eb724f
CD		 13832002-06-04 Chris Demetriou <cgd@broadcom.com>
1384
1385 * cp1.c: Add an FSF Copyright notice to this file.
1386
ba46ddd0 13872002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1388 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1389
1390 * cp1.c (Infinity): Remove.
1391 * sim-main.h (Infinity): Likewise.
1392
1393 * cp1.c (fp_unary, fp_binary): New functions.
1394 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1395 (fp_sqrt): New functions, implemented in terms of the above.
1396 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1397 (Recip, SquareRoot): Remove (replaced by functions above).
1398 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1399 (fp_recip, fp_sqrt): New prototypes.
1400 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1401 (Recip, SquareRoot): Replace prototypes with #defines which
1402 invoke the functions above.
72f4393d 1403
18d8a52d
CD		 14042002-06-03 Chris Demetriou <cgd@broadcom.com>
1405
1406 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1407 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1408 file, remove PARAMS from prototypes.
1409 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1410 simulator state arguments.
1411 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1412 pass simulator state arguments.
1413 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1414 (store_fpr, convert): Remove 'sd' argument.
1415 (value_fpr): Likewise. Convert to use 'SD' instead.
1416
0f154cbd
CD		 14172002-06-03 Chris Demetriou <cgd@broadcom.com>
1418
1419 * cp1.c (Min, Max): Remove #if 0'd functions.
1420 * sim-main.h (Min, Max): Remove.
1421
e80fc152
CD		 14222002-06-03 Chris Demetriou <cgd@broadcom.com>
1423
1424 * cp1.c: fix formatting of switch case and default labels.
1425 * interp.c: Likewise.
1426 * sim-main.c: Likewise.
1427
bad673a9
CD		 14282002-06-03 Chris Demetriou <cgd@broadcom.com>
1429
1430 * cp1.c: Clean up comments which describe FP formats.
1431 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1432
7cbea089 14332002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1434 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1435
1436 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1437 Broadcom SiByte SB-1 processor configurations.
1438 * configure: Regenerate.
1439 * sb1.igen: New file.
1440 * mips.igen: Include sb1.igen.
1441 (sb1): New model.
1442 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1443 * mdmx.igen: Add "sb1" model to all appropriate functions and
1444 instructions.
1445 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1446 (ob_func, ob_acc): Reference the above.
1447 (qh_acc): Adjust to keep the same size as ob_acc.
1448 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1449 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1450
909daa82
CD		 14512002-06-03 Chris Demetriou <cgd@broadcom.com>
1452
1453 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1454
f4f1b9f1 14552002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1456 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1457
1458 * mips.igen (mdmx): New (pseudo-)model.
1459 * mdmx.c, mdmx.igen: New files.
1460 * Makefile.in (SIM_OBJS): Add mdmx.o.
1461 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1462 New typedefs.
1463 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1464 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1465 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1466 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1467 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1468 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1469 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1470 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1471 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1472 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1473 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1474 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1475 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1476 (qh_fmtsel): New macros.
1477 (_sim_cpu): New member "acc".
1478 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1479 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1480
5accf1ff
CD		 14812002-05-01 Chris Demetriou <cgd@broadcom.com>
1482
1483 * interp.c: Use 'deprecated' rather than 'depreciated.'
1484 * sim-main.h: Likewise.
1485
402586aa
CD		 14862002-05-01 Chris Demetriou <cgd@broadcom.com>
1487
1488 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1489 which wouldn't compile anyway.
1490 * sim-main.h (unpredictable_action): New function prototype.
1491 (Unpredictable): Define to call igen function unpredictable().
1492 (NotWordValue): New macro to call igen function not_word_value().
1493 (UndefinedResult): Remove.
1494 * interp.c (undefined_result): Remove.
1495 (unpredictable_action): New function.
1496 * mips.igen (not_word_value, unpredictable): New functions.
1497 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1498 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1499 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1500 NotWordValue() to check for unpredictable inputs, then
1501 Unpredictable() to handle them.
1502
c9b9995a
CD		 15032002-02-24 Chris Demetriou <cgd@broadcom.com>
1504
1505 * mips.igen: Fix formatting of calls to Unpredictable().
1506
e1015982
AC		 15072002-04-20 Andrew Cagney <ac131313@redhat.com>
1508
1509 * interp.c (sim_open): Revert previous change.
1510
b882a66b
AO		 15112002-04-18 Alexandre Oliva <aoliva@redhat.com>
1512
1513 * interp.c (sim_open): Disable chunk of code that wrote code in
1514 vector table entries.
1515
c429b7dd
CD		 15162002-03-19 Chris Demetriou <cgd@broadcom.com>
1517
1518 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1519 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1520 unused definitions.
1521
37d146fa
CD		 15222002-03-19 Chris Demetriou <cgd@broadcom.com>
1523
1524 * cp1.c: Fix many formatting issues.
1525
07892c0b
CD		 15262002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1527
1528 * cp1.c (fpu_format_name): New function to replace...
1529 (DOFMT): This. Delete, and update all callers.
1530 (fpu_rounding_mode_name): New function to replace...
1531 (RMMODE): This. Delete, and update all callers.
1532
487f79b7
CD		 15332002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1534
1535 * interp.c: Move FPU support routines from here to...
1536 * cp1.c: Here. New file.
1537 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1538 (cp1.o): New target.
1539
1e799e28
CD		 15402002-03-12 Chris Demetriou <cgd@broadcom.com>
1541
1542 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1543 * mips.igen (mips32, mips64): New models, add to all instructions
1544 and functions as appropriate.
1545 (loadstore_ea, check_u64): New variant for model mips64.
1546 (check_fmt_p): New variant for models mipsV and mips64, remove
1547 mipsV model marking fro other variant.
1548 (SLL) Rename to...
1549 (SLLa) this.
1550 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1551 for mips32 and mips64.
1552 (DCLO, DCLZ): New instructions for mips64.
1553
82f728db
CD		 15542002-03-07 Chris Demetriou <cgd@broadcom.com>
1555
1556 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1557 immediate or code as a hex value with the "%#lx" format.
1558 (ANDI): Likewise, and fix printed instruction name.
1559
b96e7ef1
CD		 15602002-03-05 Chris Demetriou <cgd@broadcom.com>
1561
1562 * sim-main.h (UndefinedResult, Unpredictable): New macros
1563 which currently do nothing.
1564
d35d4f70
CD		 15652002-03-05 Chris Demetriou <cgd@broadcom.com>
1566
1567 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1568 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1569 (status_CU3): New definitions.
1570
1571 * sim-main.h (ExceptionCause): Add new values for MIPS32
1572 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1573 for DebugBreakPoint and NMIReset to note their status in
1574 MIPS32 and MIPS64.
1575 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1576 (SignalExceptionCacheErr): New exception macros.
1577
3ad6f714
CD		 15782002-03-05 Chris Demetriou <cgd@broadcom.com>
1579
1580 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1581 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1582 is always enabled.
1583 (SignalExceptionCoProcessorUnusable): Take as argument the
1584 unusable coprocessor number.
1585
86b77b47
CD		 15862002-03-05 Chris Demetriou <cgd@broadcom.com>
1587
1588 * mips.igen: Fix formatting of all SignalException calls.
1589
97a88e93 15902002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1591
1592 * sim-main.h (SIGNEXTEND): Remove.
1593
97a88e93 15942002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1595
1596 * mips.igen: Remove gencode comment from top of file, fix
1597 spelling in another comment.
1598
97a88e93 15992002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1600
1601 * mips.igen (check_fmt, check_fmt_p): New functions to check
1602 whether specific floating point formats are usable.
1603 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1604 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1605 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1606 Use the new functions.
1607 (do_c_cond_fmt): Remove format checks...
1608 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1609
97a88e93 16102002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1611
1612 * mips.igen: Fix formatting of check_fpu calls.
1613
41774c9d
CD		 16142002-03-03 Chris Demetriou <cgd@broadcom.com>
1615
1616 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1617
4a0bd876
CD		 16182002-03-03 Chris Demetriou <cgd@broadcom.com>
1619
1620 * mips.igen: Remove whitespace at end of lines.
1621
09297648
CD		 16222002-03-02 Chris Demetriou <cgd@broadcom.com>
1623
1624 * mips.igen (loadstore_ea): New function to do effective
1625 address calculations.
1626 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1627 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1628 CACHE): Use loadstore_ea to do effective address computations.
1629
043b7057
CD		 16302002-03-02 Chris Demetriou <cgd@broadcom.com>
1631
1632 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1633 * mips.igen (LL, CxC1, MxC1): Likewise.
1634
c1e8ada4
CD		 16352002-03-02 Chris Demetriou <cgd@broadcom.com>
1636
1637 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1638 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1639 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1640 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1641 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1642 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1643 Don't split opcode fields by hand, use the opcode field values
1644 provided by igen.
1645
3e1dca16
CD		 16462002-03-01 Chris Demetriou <cgd@broadcom.com>
1647
1648 * mips.igen (do_divu): Fix spacing.
1649
1650 * mips.igen (do_dsllv): Move to be right before DSLLV,
1651 to match the rest of the do_<shift> functions.
1652
fff8d27d
CD		 16532002-03-01 Chris Demetriou <cgd@broadcom.com>
1654
1655 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1656 DSRL32, do_dsrlv): Trace inputs and results.
1657
0d3e762b
CD		 16582002-03-01 Chris Demetriou <cgd@broadcom.com>
1659
1660 * mips.igen (CACHE): Provide instruction-printing string.
1661
1662 * interp.c (signal_exception): Comment tokens after #endif.
1663
eb5fcf93
CD		 16642002-02-28 Chris Demetriou <cgd@broadcom.com>
1665
1666 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1667 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1668 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1669 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1670 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1671 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1672 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1673 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1674
bb22bd7d
CD		 16752002-02-28 Chris Demetriou <cgd@broadcom.com>
1676
1677 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1678 instruction-printing string.
1679 (LWU): Use '64' as the filter flag.
1680
91a177cf
CD		 16812002-02-28 Chris Demetriou <cgd@broadcom.com>
1682
1683 * mips.igen (SDXC1): Fix instruction-printing string.
1684
387f484a
CD		 16852002-02-28 Chris Demetriou <cgd@broadcom.com>
1686
1687 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1688 filter flags "32,f".
1689
3d81f391
CD		 16902002-02-27 Chris Demetriou <cgd@broadcom.com>
1691
1692 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1693 as the filter flag.
1694
af5107af
CD		 16952002-02-27 Chris Demetriou <cgd@broadcom.com>
1696
1697 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1698 add a comma) so that it more closely match the MIPS ISA
1699 documentation opcode partitioning.
1700 (PREF): Put useful names on opcode fields, and include
1701 instruction-printing string.
1702
ca971540
CD		 17032002-02-27 Chris Demetriou <cgd@broadcom.com>
1704
1705 * mips.igen (check_u64): New function which in the future will
1706 check whether 64-bit instructions are usable and signal an
1707 exception if not. Currently a no-op.
1708 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1709 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1710 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1711 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1712
1713 * mips.igen (check_fpu): New function which in the future will
1714 check whether FPU instructions are usable and signal an exception
1715 if not. Currently a no-op.
1716 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1717 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1718 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1719 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1720 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1721 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1722 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1723 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1724
1c47a468
CD		 17252002-02-27 Chris Demetriou <cgd@broadcom.com>
1726
1727 * mips.igen (do_load_left, do_load_right): Move to be immediately
1728 following do_load.
1729 (do_store_left, do_store_right): Move to be immediately following
1730 do_store.
1731
603a98e7
CD		 17322002-02-27 Chris Demetriou <cgd@broadcom.com>
1733
1734 * mips.igen (mipsV): New model name. Also, add it to
1735 all instructions and functions where it is appropriate.
1736
c5d00cc7
CD		 17372002-02-18 Chris Demetriou <cgd@broadcom.com>
1738
1739 * mips.igen: For all functions and instructions, list model
1740 names that support that instruction one per line.
1741
074e9cb8
CD		 17422002-02-11 Chris Demetriou <cgd@broadcom.com>
1743
1744 * mips.igen: Add some additional comments about supported
1745 models, and about which instructions go where.
1746 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1747 order as is used in the rest of the file.
1748
9805e229
CD		 17492002-02-11 Chris Demetriou <cgd@broadcom.com>
1750
1751 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1752 indicating that ALU32_END or ALU64_END are there to check
1753 for overflow.
1754 (DADD): Likewise, but also remove previous comment about
1755 overflow checking.
1756
f701dad2
CD		 17572002-02-10 Chris Demetriou <cgd@broadcom.com>
1758
1759 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1760 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1761 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1762 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1763 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1764 fields (i.e., add and move commas) so that they more closely
1765 match the MIPS ISA documentation opcode partitioning.
1766
17672002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1768
72f4393d
L		 1769 * mips.igen (ADDI): Print immediate value.
1770 (BREAK): Print code.
1771 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1772 (SLL): Print "nop" specially, and don't run the code
1773 that does the shift for the "nop" case.
20ae0098 1774
9e52972e
FF		 17752001-11-17 Fred Fish <fnf@redhat.com>
1776
1777 * sim-main.h (float_operation): Move enum declaration outside
1778 of _sim_cpu struct declaration.
1779
c0efbca4
JB		 17802001-04-12 Jim Blandy <jimb@redhat.com>
1781
1782 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1783 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1784 set of the FCSR.
1785 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1786 PENDING_FILL, and you can get the intended effect gracefully by
1787 calling PENDING_SCHED directly.
1788
fb891446
BE		 17892001-02-23 Ben Elliston <bje@redhat.com>
1790
1791 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1792 already defined elsewhere.
1793
8030f857
BE		 17942001-02-19 Ben Elliston <bje@redhat.com>
1795
1796 * sim-main.h (sim_monitor): Return an int.
1797 * interp.c (sim_monitor): Add return values.
1798 (signal_exception): Handle error conditions from sim_monitor.
1799
56b48a7a
CD		 18002001-02-08 Ben Elliston <bje@redhat.com>
1801
1802 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1803 (store_memory): Likewise, pass cia to sim_core_write*.
1804
d3ee60d9
FCE		 18052000-10-19 Frank Ch. Eigler <fche@redhat.com>
1806
1807 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1808 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1809
071da002
AC		 1810Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1811
1812 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1813 * Makefile.in: Don't delete *.igen when cleaning directory.
1814
a28c02cd
AC		 1815Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1816
1817 * m16.igen (break): Call SignalException not sim_engine_halt.
1818
80ee11fa
AC		 1819Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1820
1821 From Jason Eckhardt:
1822 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1823
673388c0
AC		 1824Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1825
1826 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1827
4c0deff4
NC		 18282000-05-24 Michael Hayes <mhayes@cygnus.com>
1829
1830 * mips.igen (do_dmultx): Fix typo.
1831
eb2d80b4
AC		 1832Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1833
1834 * configure: Regenerated to track ../common/aclocal.m4 changes.
1835
dd37a34b
AC		 1836Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1837
1838 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1839
4c0deff4
NC		 18402000-04-12 Frank Ch. Eigler <fche@redhat.com>
1841
1842 * sim-main.h (GPR_CLEAR): Define macro.
1843
e30db738
AC		 1844Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1845
1846 * interp.c (decode_coproc): Output long using %lx and not %s.
1847
cb7450ea
FCE		 18482000-03-21 Frank Ch. Eigler <fche@redhat.com>
1849
1850 * interp.c (sim_open): Sort & extend dummy memory regions for
1851 --board=jmr3904 for eCos.
1852
a3027dd7
FCE		 18532000-03-02 Frank Ch. Eigler <fche@redhat.com>
1854
1855 * configure: Regenerated.
1856
1857Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1858
1859 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1860 calls, conditional on the simulator being in verbose mode.
1861
dfcd3bfb
JM		 1862Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1863
1864 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1865 cache don't get ReservedInstruction traps.
1866
c2d11a7d
JM		 18671999-11-29 Mark Salter <msalter@cygnus.com>
1868
1869 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1870 to clear status bits in sdisr register. This is how the hardware works.
1871
1872 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1873 being used by cygmon.
1874
4ce44c66
JM		 18751999-11-11 Andrew Haley <aph@cygnus.com>
1876
1877 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1878 instructions.
1879
cff3e48b
JM		 1880Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1881
1882 * mips.igen (MULT): Correct previous mis-applied patch.
1883
d4f3574e
SS		 1884Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1885
1886 * mips.igen (delayslot32): Handle sequence like
1887 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1888 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1889 (MULT): Actually pass the third register...
1890
18911999-09-03 Mark Salter <msalter@cygnus.com>
1892
1893 * interp.c (sim_open): Added more memory aliases for additional
1894 hardware being touched by cygmon on jmr3904 board.
1895
1896Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1897
1898 * configure: Regenerated to track ../common/aclocal.m4 changes.
1899
a0b3c4fd
JM		 1900Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1901
1902 * interp.c (sim_store_register): Handle case where client - GDB -
1903 specifies that a 4 byte register is 8 bytes in size.
1904 (sim_fetch_register): Ditto.
72f4393d 1905
adf40b2e
JM		 19061999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1907
1908 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1909 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1910 (idt_monitor_base): Base address for IDT monitor traps.
1911 (pmon_monitor_base): Ditto for PMON.
1912 (lsipmon_monitor_base): Ditto for LSI PMON.
1913 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1914 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1915 (sim_firmware_command): New function.
1916 (mips_option_handler): Call it for OPTION_FIRMWARE.
1917 (sim_open): Allocate memory for idt_monitor region. If "--board"
1918 option was given, add no monitor by default. Add BREAK hooks only if
1919 monitors are also there.
72f4393d 1920
43e526b9
JM		 1921Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1922
1923 * interp.c (sim_monitor): Flush output before reading input.
1924
1925Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1926
1927 * tconfig.in (SIM_HANDLES_LMA): Always define.
1928
1929Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1930
1931 From Mark Salter <msalter@cygnus.com>:
1932 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1933 (sim_open): Add setup for BSP board.
1934
9846de1b
JM		 1935Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1936
1937 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1938 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1939 them as unimplemented.
1940
cd0fc7c3
SS		 19411999-05-08 Felix Lee <flee@cygnus.com>
1942
1943 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1944
7a292a7a
SS		 19451999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1946
1947 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1948
1949Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1950
1951 * configure.in: Any mips64vr5*-*-* target should have
1952 -DTARGET_ENABLE_FR=1.
1953 (default_endian): Any mips64vr*el-*-* target should default to
1954 LITTLE_ENDIAN.
1955 * configure: Re-generate.
1956
19571999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1958
1959 * mips.igen (ldl): Extend from _16_, not 32.
1960
1961Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1962
1963 * interp.c (sim_store_register): Force registers written to by GDB
1964 into an un-interpreted state.
1965
c906108c
SS		 19661999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1967
1968 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1969 CPU, start periodic background I/O polls.
72f4393d 1970 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1971
19721998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1973
1974 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1975
c906108c
SS		 1976Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1977
1978 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1979 case statement.
1980
19811998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1982
1983 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1984 (load_word): Call SIM_CORE_SIGNAL hook on error.
1985 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1986 starting. For exception dispatching, pass PC instead of NULL_CIA.
1987 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1988 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1989 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1990 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1991 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1992 * mips.igen (*): Replace memory-related SignalException* calls
1993 with references to SIM_CORE_SIGNAL hook.
72f4393d 1994
c906108c
SS		 1995 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1996 fix.
1997 * sim-main.c (*): Minor warning cleanups.
72f4393d 1998
c906108c
SS		 19991998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
2000
2001 * m16.igen (DADDIU5): Correct type-o.
2002
2003Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
2004
2005 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
2006 variables.
2007
2008Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
2009
2010 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
2011 to include path.
2012 (interp.o): Add dependency on itable.h
2013 (oengine.c, gencode): Delete remaining references.
2014 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 2015
c906108c 20161998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 2017
c906108c
SS		 2018 * vr4run.c: New.
2019 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
2020 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
2021 tmp-run-hack) : New.
2022 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2023 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2024 Drop the "64" qualifier to get the HACK generator working.
2025 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2026 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2027 qualifier to get the hack generator working.
2028 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2029 (DSLL): Use do_dsll.
2030 (DSLLV): Use do_dsllv.
2031 (DSRA): Use do_dsra.
2032 (DSRL): Use do_dsrl.
2033 (DSRLV): Use do_dsrlv.
2034 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2035 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2036 get the HACK generator working.
2037 (MACC) Rename to get the HACK generator working.
2038 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2039
c906108c
SS		 20401998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2041
2042 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2043 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2044
c906108c
SS		 20451998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2046
2047 * mips/interp.c (DEBUG): Cleanups.
2048
20491998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2050
2051 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2052 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2053
c906108c
SS		 20541998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2055
2056 * interp.c (sim_close): Uninstall modules.
2057
2058Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2059
2060 * sim-main.h, interp.c (sim_monitor): Change to global
2061 function.
2062
2063Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2064
2065 * configure.in (vr4100): Only include vr4100 instructions in
2066 simulator.
2067 * configure: Re-generate.
2068 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2069
2070Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2071
2072 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2073 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2074 true alternative.
2075
2076 * configure.in (sim_default_gen, sim_use_gen): Replace with
2077 sim_gen.
2078 (--enable-sim-igen): Delete config option. Always using IGEN.
2079 * configure: Re-generate.
72f4393d 2080
c906108c
SS		 2081 * Makefile.in (gencode): Kill, kill, kill.
2082 * gencode.c: Ditto.
72f4393d 2083
c906108c
SS		 2084Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2085
2086 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2087 bit mips16 igen simulator.
2088 * configure: Re-generate.
2089
2090 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2091 as part of vr4100 ISA.
2092 * vr.igen: Mark all instructions as 64 bit only.
2093
2094Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2095
2096 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2097 Pacify GCC.
2098
2099Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2100
2101 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2102 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2103 * configure: Re-generate.
2104
2105 * m16.igen (BREAK): Define breakpoint instruction.
2106 (JALX32): Mark instruction as mips16 and not r3900.
2107 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2108
2109 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2110
2111Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2112
2113 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2114 insn as a debug breakpoint.
2115
2116 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2117 pending.slot_size.
2118 (PENDING_SCHED): Clean up trace statement.
2119 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2120 (PENDING_FILL): Delay write by only one cycle.
2121 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2122
2123 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2124 of pending writes.
2125 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2126 32 & 64.
2127 (pending_tick): Move incrementing of index to FOR statement.
2128 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2129
c906108c
SS		 2130 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2131 build simulator.
2132 * configure: Re-generate.
72f4393d 2133
c906108c
SS		 2134 * interp.c (sim_engine_run OLD): Delete explicit call to
2135 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2136
c906108c
SS		 2137Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2138
2139 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2140 interrupt level number to match changed SignalExceptionInterrupt
2141 macro.
2142
2143Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2144
2145 * interp.c: #include "itable.h" if WITH_IGEN.
2146 (get_insn_name): New function.
2147 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2148 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2149
2150Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2151
2152 * configure: Rebuilt to inhale new common/aclocal.m4.
2153
2154Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2155
2156 * dv-tx3904sio.c: Include sim-assert.h.
2157
2158Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2159
2160 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2161 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2162 Reorganize target-specific sim-hardware checks.
2163 * configure: rebuilt.
2164 * interp.c (sim_open): For tx39 target boards, set
2165 OPERATING_ENVIRONMENT, add tx3904sio devices.
2166 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2167 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2168
c906108c
SS		 2169 * dv-tx3904irc.c: Compiler warning clean-up.
2170 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2171 frequent hw-trace messages.
2172
2173Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2174
2175 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2176
2177Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2178
2179 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2180
2181 * vr.igen: New file.
2182 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2183 * mips.igen: Define vr4100 model. Include vr.igen.
2184Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2185
2186 * mips.igen (check_mf_hilo): Correct check.
2187
2188Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2189
2190 * sim-main.h (interrupt_event): Add prototype.
2191
2192 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2193 register_ptr, register_value.
2194 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2195
2196 * sim-main.h (tracefh): Make extern.
2197
2198Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2199
2200 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2201 Reduce unnecessarily high timer event frequency.
c906108c 2202 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2203
c906108c
SS		 2204Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2205
2206 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2207 to allay warnings.
2208 (interrupt_event): Made non-static.
72f4393d 2209
c906108c
SS		 2210 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2211 interchange of configuration values for external vs. internal
2212 clock dividers.
72f4393d 2213
c906108c
SS		 2214Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2215
72f4393d 2216 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2217 simulator-reserved break instructions.
2218 * gencode.c (build_instruction): Ditto.
2219 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2220 reserved instructions now use exception vector, rather
c906108c
SS		 2221 than halting sim.
2222 * sim-main.h: Moved magic constants to here.
2223
2224Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2225
2226 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2227 register upon non-zero interrupt event level, clear upon zero
2228 event value.
2229 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2230 by passing zero event value.
2231 (*_io_{read,write}_buffer): Endianness fixes.
2232 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2233 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2234
2235 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2236 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2237
c906108c
SS		 2238Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2239
72f4393d 2240 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2241 and BigEndianCPU.
2242
2243Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2244
2245 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2246 parts.
2247 * configure: Update.
2248
2249Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2250
2251 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2252 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2253 * configure.in: Include tx3904tmr in hw_device list.
2254 * configure: Rebuilt.
2255 * interp.c (sim_open): Instantiate three timer instances.
2256 Fix address typo of tx3904irc instance.
2257
2258Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2259
2260 * interp.c (signal_exception): SystemCall exception now uses
2261 the exception vector.
2262
2263Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2264
2265 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2266 to allay warnings.
2267
2268Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2269
2270 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2271
2272Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2273
2274 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2275
2276 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2277 sim-main.h. Declare a struct hw_descriptor instead of struct
2278 hw_device_descriptor.
2279
2280Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2283 right bits and then re-align left hand bytes to correct byte
2284 lanes. Fix incorrect computation in do_store_left when loading
2285 bytes from second word.
2286
2287Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2288
2289 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2290 * interp.c (sim_open): Only create a device tree when HW is
2291 enabled.
2292
2293 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2294 * interp.c (signal_exception): Ditto.
2295
2296Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2297
2298 * gencode.c: Mark BEGEZALL as LIKELY.
2299
2300Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2301
2302 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2303 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2304
c906108c
SS		 2305Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2306
2307 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2308 modules. Recognize TX39 target with "mips*tx39" pattern.
2309 * configure: Rebuilt.
2310 * sim-main.h (*): Added many macros defining bits in
2311 TX39 control registers.
2312 (SignalInterrupt): Send actual PC instead of NULL.
2313 (SignalNMIReset): New exception type.
2314 * interp.c (board): New variable for future use to identify
2315 a particular board being simulated.
2316 (mips_option_handler,mips_options): Added "--board" option.
2317 (interrupt_event): Send actual PC.
2318 (sim_open): Make memory layout conditional on board setting.
2319 (signal_exception): Initial implementation of hardware interrupt
2320 handling. Accept another break instruction variant for simulator
2321 exit.
2322 (decode_coproc): Implement RFE instruction for TX39.
2323 (mips.igen): Decode RFE instruction as such.
2324 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2325 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2326 bbegin to implement memory map.
2327 * dv-tx3904cpu.c: New file.
2328 * dv-tx3904irc.c: New file.
2329
2330Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2331
2332 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2333
2334Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2335
2336 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2337 with calls to check_div_hilo.
2338
2339Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2340
2341 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2342 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2343 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2344 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2345 with calls to check_mult_hilo.
2346 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2347 with calls to check_div_hilo.
2348
2349Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2350
2351 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2352 Document a replacement.
2353
2354Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2355
2356 * interp.c (sim_monitor): Make mon_printf work.
2357
2358Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2359
2360 * sim-main.h (INSN_NAME): New arg `cpu'.
2361
2362Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2363
72f4393d 2364 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2365
2366Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2367
2368 * configure: Regenerated to track ../common/aclocal.m4 changes.
2369 * config.in: Ditto.
2370
2371Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2372
2373 * acconfig.h: New file.
2374 * configure.in: Reverted change of Apr 24; use sinclude again.
2375
2376Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2377
2378 * configure: Regenerated to track ../common/aclocal.m4 changes.
2379 * config.in: Ditto.
2380
2381Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2382
2383 * configure.in: Don't call sinclude.
2384
2385Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2386
2387 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2388
2389Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2390
2391 * mips.igen (ERET): Implement.
2392
2393 * interp.c (decode_coproc): Return sign-extended EPC.
2394
2395 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2396
2397 * interp.c (signal_exception): Do not ignore Trap.
2398 (signal_exception): On TRAP, restart at exception address.
2399 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2400 (signal_exception): Update.
2401 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2402 so that TRAP instructions are caught.
2403
2404Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2405
2406 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2407 contains HI/LO access history.
2408 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2409 (HIACCESS, LOACCESS): Delete, replace with
2410 (HIHISTORY, LOHISTORY): New macros.
2411 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2412
c906108c
SS		 2413 * gencode.c (build_instruction): Do not generate checks for
2414 correct HI/LO register usage.
2415
2416 * interp.c (old_engine_run): Delete checks for correct HI/LO
2417 register usage.
2418
2419 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2420 check_mf_cycles): New functions.
2421 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2422 do_divu, domultx, do_mult, do_multu): Use.
2423
2424 * tx.igen ("madd", "maddu"): Use.
72f4393d 2425
c906108c
SS		 2426Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2427
2428 * mips.igen (DSRAV): Use function do_dsrav.
2429 (SRAV): Use new function do_srav.
2430
2431 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2432 (B): Sign extend 11 bit immediate.
2433 (EXT-B*): Shift 16 bit immediate left by 1.
2434 (ADDIU*): Don't sign extend immediate value.
2435
2436Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2437
2438 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2439
2440 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2441 functions.
2442
2443 * mips.igen (delayslot32, nullify_next_insn): New functions.
2444 (m16.igen): Always include.
2445 (do_*): Add more tracing.
2446
2447 * m16.igen (delayslot16): Add NIA argument, could be called by a
2448 32 bit MIPS16 instruction.
72f4393d 2449
c906108c
SS		 2450 * interp.c (ifetch16): Move function from here.
2451 * sim-main.c (ifetch16): To here.
72f4393d 2452
c906108c
SS		 2453 * sim-main.c (ifetch16, ifetch32): Update to match current
2454 implementations of LH, LW.
2455 (signal_exception): Don't print out incorrect hex value of illegal
2456 instruction.
2457
2458Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2459
2460 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2461 instruction.
2462
2463 * m16.igen: Implement MIPS16 instructions.
72f4393d 2464
c906108c
SS		 2465 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2466 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2467 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2468 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2469 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2470 bodies of corresponding code from 32 bit insn to these. Also used
2471 by MIPS16 versions of functions.
72f4393d 2472
c906108c
SS		 2473 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2474 (IMEM16): Drop NR argument from macro.
2475
2476Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2477
2478 * Makefile.in (SIM_OBJS): Add sim-main.o.
2479
2480 * sim-main.h (address_translation, load_memory, store_memory,
2481 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2482 as INLINE_SIM_MAIN.
2483 (pr_addr, pr_uword64): Declare.
2484 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2485
c906108c
SS		 2486 * interp.c (address_translation, load_memory, store_memory,
2487 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2488 from here.
2489 * sim-main.c: To here. Fix compilation problems.
72f4393d 2490
c906108c
SS		 2491 * configure.in: Enable inlining.
2492 * configure: Re-config.
2493
2494Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2495
2496 * configure: Regenerated to track ../common/aclocal.m4 changes.
2497
2498Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2499
2500 * mips.igen: Include tx.igen.
2501 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2502 * tx.igen: New file, contains MADD and MADDU.
2503
2504 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2505 the hardwired constant `7'.
2506 (store_memory): Ditto.
2507 (LOADDRMASK): Move definition to sim-main.h.
2508
2509 mips.igen (MTC0): Enable for r3900.
2510 (ADDU): Add trace.
2511
2512 mips.igen (do_load_byte): Delete.
2513 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2514 do_store_right): New functions.
2515 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2516
2517 configure.in: Let the tx39 use igen again.
2518 configure: Update.
72f4393d 2519
c906108c
SS		 2520Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2521
2522 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2523 not an address sized quantity. Return zero for cache sizes.
2524
2525Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2526
2527 * mips.igen (r3900): r3900 does not support 64 bit integer
2528 operations.
2529
2530Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2531
2532 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2533 than igen one.
2534 * configure : Rebuild.
72f4393d 2535
c906108c
SS		 2536Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2537
2538 * configure: Regenerated to track ../common/aclocal.m4 changes.
2539
2540Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2541
2542 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2543
2544Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2545
2546 * configure: Regenerated to track ../common/aclocal.m4 changes.
2547 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2548
2549Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2550
2551 * configure: Regenerated to track ../common/aclocal.m4 changes.
2552
2553Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2554
2555 * interp.c (Max, Min): Comment out functions. Not yet used.
2556
2557Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2558
2559 * configure: Regenerated to track ../common/aclocal.m4 changes.
2560
2561Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2562
2563 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2564 configurable settings for stand-alone simulator.
72f4393d 2565
c906108c 2566 * configure.in: Added X11 search, just in case.
72f4393d 2567
c906108c
SS		 2568 * configure: Regenerated.
2569
2570Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2571
2572 * interp.c (sim_write, sim_read, load_memory, store_memory):
2573 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2574
2575Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2576
2577 * sim-main.h (GETFCC): Return an unsigned value.
2578
2579Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2580
2581 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2582 (DADD): Result destination is RD not RT.
2583
2584Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2585
2586 * sim-main.h (HIACCESS, LOACCESS): Always define.
2587
2588 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2589
2590 * interp.c (sim_info): Delete.
2591
2592Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2593
2594 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2595 (mips_option_handler): New argument `cpu'.
2596 (sim_open): Update call to sim_add_option_table.
2597
2598Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2599
2600 * mips.igen (CxC1): Add tracing.
2601
2602Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2603
2604 * sim-main.h (Max, Min): Declare.
2605
2606 * interp.c (Max, Min): New functions.
2607
2608 * mips.igen (BC1): Add tracing.
72f4393d 2609
c906108c 2610Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2611
c906108c 2612 * interp.c Added memory map for stack in vr4100
72f4393d 2613
c906108c
SS		 2614Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2615
2616 * interp.c (load_memory): Add missing "break"'s.
2617
2618Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2619
2620 * interp.c (sim_store_register, sim_fetch_register): Pass in
2621 length parameter. Return -1.
2622
2623Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2624
2625 * interp.c: Added hardware init hook, fixed warnings.
2626
2627Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2628
2629 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2630
2631Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2632
2633 * interp.c (ifetch16): New function.
2634
2635 * sim-main.h (IMEM32): Rename IMEM.
2636 (IMEM16_IMMED): Define.
2637 (IMEM16): Define.
2638 (DELAY_SLOT): Update.
72f4393d 2639
c906108c 2640 * m16run.c (sim_engine_run): New file.
72f4393d 2641
c906108c
SS		 2642 * m16.igen: All instructions except LB.
2643 (LB): Call do_load_byte.
2644 * mips.igen (do_load_byte): New function.
2645 (LB): Call do_load_byte.
2646
2647 * mips.igen: Move spec for insn bit size and high bit from here.
2648 * Makefile.in (tmp-igen, tmp-m16): To here.
2649
2650 * m16.dc: New file, decode mips16 instructions.
2651
2652 * Makefile.in (SIM_NO_ALL): Define.
2653 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2654
2655Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2656
2657 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2658 point unit to 32 bit registers.
2659 * configure: Re-generate.
2660
2661Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2662
2663 * configure.in (sim_use_gen): Make IGEN the default simulator
2664 generator for generic 32 and 64 bit mips targets.
2665 * configure: Re-generate.
2666
2667Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2668
2669 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2670 bitsize.
2671
2672 * interp.c (sim_fetch_register, sim_store_register): Read/write
2673 FGR from correct location.
2674 (sim_open): Set size of FGR's according to
2675 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2676
c906108c
SS		 2677 * sim-main.h (FGR): Store floating point registers in a separate
2678 array.
2679
2680Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2681
2682 * configure: Regenerated to track ../common/aclocal.m4 changes.
2683
2684Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2685
2686 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2687
2688 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2689
2690 * interp.c (pending_tick): New function. Deliver pending writes.
2691
2692 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2693 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2694 it can handle mixed sized quantites and single bits.
72f4393d 2695
c906108c
SS		 2696Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2697
2698 * interp.c (oengine.h): Do not include when building with IGEN.
2699 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2700 (sim_info): Ditto for PROCESSOR_64BIT.
2701 (sim_monitor): Replace ut_reg with unsigned_word.
2702 (*): Ditto for t_reg.
2703 (LOADDRMASK): Define.
2704 (sim_open): Remove defunct check that host FP is IEEE compliant,
2705 using software to emulate floating point.
2706 (value_fpr, ...): Always compile, was conditional on HASFPU.
2707
2708Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2709
2710 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2711 size.
2712
2713 * interp.c (SD, CPU): Define.
2714 (mips_option_handler): Set flags in each CPU.
2715 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2716 (sim_close): Do not clear STATE, deleted anyway.
2717 (sim_write, sim_read): Assume CPU zero's vm should be used for
2718 data transfers.
2719 (sim_create_inferior): Set the PC for all processors.
2720 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2721 argument.
2722 (mips16_entry): Pass correct nr of args to store_word, load_word.
2723 (ColdReset): Cold reset all cpu's.
2724 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2725 (sim_monitor, load_memory, store_memory, signal_exception): Use
2726 `CPU' instead of STATE_CPU.
2727
2728
2729 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2730 SD or CPU_.
72f4393d 2731
c906108c
SS		 2732 * sim-main.h (signal_exception): Add sim_cpu arg.
2733 (SignalException*): Pass both SD and CPU to signal_exception.
2734 * interp.c (signal_exception): Update.
72f4393d 2735
c906108c
SS		 2736 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2737 Ditto
2738 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2739 address_translation): Ditto
2740 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2741
c906108c
SS		 2742Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2743
2744 * configure: Regenerated to track ../common/aclocal.m4 changes.
2745
2746Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2747
2748 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2749
72f4393d 2750 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2751
2752 * sim-main.h (CPU_CIA): Delete.
2753 (SET_CIA, GET_CIA): Define
2754
2755Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2756
2757 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2758 regiser.
2759
2760 * configure.in (default_endian): Configure a big-endian simulator
2761 by default.
2762 * configure: Re-generate.
72f4393d 2763
c906108c
SS		 2764Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2765
2766 * configure: Regenerated to track ../common/aclocal.m4 changes.
2767
2768Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2769
2770 * interp.c (sim_monitor): Handle Densan monitor outbyte
2771 and inbyte functions.
2772
27731997-12-29 Felix Lee <flee@cygnus.com>
2774
2775 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2776
2777Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2778
2779 * Makefile.in (tmp-igen): Arrange for $zero to always be
2780 reset to zero after every instruction.
2781
2782Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2783
2784 * configure: Regenerated to track ../common/aclocal.m4 changes.
2785 * config.in: Ditto.
2786
2787Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2788
2789 * mips.igen (MSUB): Fix to work like MADD.
2790 * gencode.c (MSUB): Similarly.
2791
2792Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2793
2794 * configure: Regenerated to track ../common/aclocal.m4 changes.
2795
2796Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2797
2798 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2799
2800Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2801
2802 * sim-main.h (sim-fpu.h): Include.
2803
2804 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2805 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2806 using host independant sim_fpu module.
2807
2808Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2809
2810 * interp.c (signal_exception): Report internal errors with SIGABRT
2811 not SIGQUIT.
2812
2813 * sim-main.h (C0_CONFIG): New register.
2814 (signal.h): No longer include.
2815
2816 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2817
2818Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2819
2820 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2821
2822Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2823
2824 * mips.igen: Tag vr5000 instructions.
2825 (ANDI): Was missing mipsIV model, fix assembler syntax.
2826 (do_c_cond_fmt): New function.
2827 (C.cond.fmt): Handle mips I-III which do not support CC field
2828 separatly.
2829 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2830 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2831 in IV3.2 spec.
2832 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2833 vr5000 which saves LO in a GPR separatly.
72f4393d 2834
c906108c
SS		 2835 * configure.in (enable-sim-igen): For vr5000, select vr5000
2836 specific instructions.
2837 * configure: Re-generate.
72f4393d 2838
c906108c
SS		 2839Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2840
2841 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2842
2843 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2844 fmt_uninterpreted_64 bit cases to switch. Convert to
2845 fmt_formatted,
2846
2847 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2848
2849 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2850 as specified in IV3.2 spec.
2851 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2852
2853Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2854
2855 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2856 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2857 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2858 PENDING_FILL versions of instructions. Simplify.
2859 (X): New function.
2860 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2861 instructions.
2862 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2863 a signed value.
2864 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2865
c906108c
SS		 2866 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2867 global.
2868 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2869
2870Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2871
2872 * gencode.c (build_mips16_operands): Replace IPC with cia.
2873
2874 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2875 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2876 IPC to `cia'.
2877 (UndefinedResult): Replace function with macro/function
2878 combination.
2879 (sim_engine_run): Don't save PC in IPC.
2880
2881 * sim-main.h (IPC): Delete.
2882
2883
2884 * interp.c (signal_exception, store_word, load_word,
2885 address_translation, load_memory, store_memory, cache_op,
2886 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2887 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2888 current instruction address - cia - argument.
2889 (sim_read, sim_write): Call address_translation directly.
2890 (sim_engine_run): Rename variable vaddr to cia.
2891 (signal_exception): Pass cia to sim_monitor
72f4393d 2892
c906108c
SS		 2893 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2894 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2895 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2896
2897 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2898 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2899 SIM_ASSERT.
72f4393d 2900
c906108c
SS		 2901 * interp.c (signal_exception): Pass restart address to
2902 sim_engine_restart.
2903
2904 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2905 idecode.o): Add dependency.
2906
2907 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2908 Delete definitions
2909 (DELAY_SLOT): Update NIA not PC with branch address.
2910 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2911
2912 * mips.igen: Use CIA not PC in branch calculations.
2913 (illegal): Call SignalException.
2914 (BEQ, ADDIU): Fix assembler.
2915
2916Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2917
2918 * m16.igen (JALX): Was missing.
2919
2920 * configure.in (enable-sim-igen): New configuration option.
2921 * configure: Re-generate.
72f4393d 2922
c906108c
SS		 2923 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2924
2925 * interp.c (load_memory, store_memory): Delete parameter RAW.
2926 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2927 bypassing {load,store}_memory.
2928
2929 * sim-main.h (ByteSwapMem): Delete definition.
2930
2931 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2932
2933 * interp.c (sim_do_command, sim_commands): Delete mips specific
2934 commands. Handled by module sim-options.
72f4393d 2935
c906108c
SS		 2936 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2937 (WITH_MODULO_MEMORY): Define.
2938
2939 * interp.c (sim_info): Delete code printing memory size.
2940
2941 * interp.c (mips_size): Nee sim_size, delete function.
2942 (power2): Delete.
2943 (monitor, monitor_base, monitor_size): Delete global variables.
2944 (sim_open, sim_close): Delete code creating monitor and other
2945 memory regions. Use sim-memopts module, via sim_do_commandf, to
2946 manage memory regions.
2947 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2948
c906108c
SS		 2949 * interp.c (address_translation): Delete all memory map code
2950 except line forcing 32 bit addresses.
2951
2952Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2953
2954 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2955 trace options.
2956
2957 * interp.c (logfh, logfile): Delete globals.
2958 (sim_open, sim_close): Delete code opening & closing log file.
2959 (mips_option_handler): Delete -l and -n options.
2960 (OPTION mips_options): Ditto.
2961
2962 * interp.c (OPTION mips_options): Rename option trace to dinero.
2963 (mips_option_handler): Update.
2964
2965Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2966
2967 * interp.c (fetch_str): New function.
2968 (sim_monitor): Rewrite using sim_read & sim_write.
2969 (sim_open): Check magic number.
2970 (sim_open): Write monitor vectors into memory using sim_write.
2971 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2972 (sim_read, sim_write): Simplify - transfer data one byte at a
2973 time.
2974 (load_memory, store_memory): Clarify meaning of parameter RAW.
2975
2976 * sim-main.h (isHOST): Defete definition.
2977 (isTARGET): Mark as depreciated.
2978 (address_translation): Delete parameter HOST.
2979
2980 * interp.c (address_translation): Delete parameter HOST.
2981
2982Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2983
72f4393d 2984 * mips.igen:
c906108c
SS		 2985
2986 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2987 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2988
2989Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2990
2991 * mips.igen: Add model filter field to records.
2992
2993Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2994
2995 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2996
c906108c
SS		 2997 interp.c (sim_engine_run): Do not compile function sim_engine_run
2998 when WITH_IGEN == 1.
2999
3000 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
3001 target architecture.
3002
3003 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
3004 igen. Replace with configuration variables sim_igen_flags /
3005 sim_m16_flags.
3006
3007 * m16.igen: New file. Copy mips16 insns here.
3008 * mips.igen: From here.
3009
3010Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3011
3012 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
3013 to top.
3014 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
3015
3016Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
3017
3018 * gencode.c (build_instruction): Follow sim_write's lead in using
3019 BigEndianMem instead of !ByteSwapMem.
3020
3021Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3022
3023 * configure.in (sim_gen): Dependent on target, select type of
3024 generator. Always select old style generator.
3025
3026 configure: Re-generate.
3027
3028 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3029 targets.
3030 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3031 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3032 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3033 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3034 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3035
c906108c
SS		 3036Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3037
3038 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3039
3040 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3041 CURRENT_FLOATING_POINT instead.
3042
3043 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3044 (address_translation): Raise exception InstructionFetch when
3045 translation fails and isINSTRUCTION.
72f4393d 3046
c906108c
SS		 3047 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3048 sim_engine_run): Change type of of vaddr and paddr to
3049 address_word.
3050 (address_translation, prefetch, load_memory, store_memory,
3051 cache_op): Change type of vAddr and pAddr to address_word.
3052
3053 * gencode.c (build_instruction): Change type of vaddr and paddr to
3054 address_word.
3055
3056Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3057
3058 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3059 macro to obtain result of ALU op.
3060
3061Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3062
3063 * interp.c (sim_info): Call profile_print.
3064
3065Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3066
3067 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3068
3069 * sim-main.h (WITH_PROFILE): Do not define, defined in
3070 common/sim-config.h. Use sim-profile module.
3071 (simPROFILE): Delete defintion.
3072
3073 * interp.c (PROFILE): Delete definition.
3074 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3075 (sim_close): Delete code writing profile histogram.
3076 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3077 Delete.
3078 (sim_engine_run): Delete code profiling the PC.
3079
3080Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3081
3082 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3083
3084 * interp.c (sim_monitor): Make register pointers of type
3085 unsigned_word*.
3086
3087 * sim-main.h: Make registers of type unsigned_word not
3088 signed_word.
3089
3090Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3091
3092 * interp.c (sync_operation): Rename from SyncOperation, make
3093 global, add SD argument.
3094 (prefetch): Rename from Prefetch, make global, add SD argument.
3095 (decode_coproc): Make global.
3096
3097 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3098
3099 * gencode.c (build_instruction): Generate DecodeCoproc not
3100 decode_coproc calls.
3101
3102 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3103 (SizeFGR): Move to sim-main.h
3104 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3105 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3106 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3107 sim-main.h.
3108 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3109 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3110 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3111 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3112 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3113 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3114
c906108c
SS		 3115 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3116 exception.
3117 (sim-alu.h): Include.
3118 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3119 (sim_cia): Typedef to instruction_address.
72f4393d 3120
c906108c
SS		 3121Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3122
3123 * Makefile.in (interp.o): Rename generated file engine.c to
3124 oengine.c.
72f4393d 3125
c906108c 3126 * interp.c: Update.
72f4393d 3127
c906108c
SS		 3128Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3129
3130 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3131
c906108c
SS		 3132Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3133
3134 * gencode.c (build_instruction): For "FPSQRT", output correct
3135 number of arguments to Recip.
72f4393d 3136
c906108c
SS		 3137Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3138
3139 * Makefile.in (interp.o): Depends on sim-main.h
3140
3141 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3142
3143 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3144 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3145 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3146 STATE, DSSTATE): Define
3147 (GPR, FGRIDX, ..): Define.
3148
3149 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3150 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3151 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3152
c906108c 3153 * interp.c: Update names to match defines from sim-main.h
72f4393d 3154
c906108c
SS		 3155Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3156
3157 * interp.c (sim_monitor): Add SD argument.
3158 (sim_warning): Delete. Replace calls with calls to
3159 sim_io_eprintf.
3160 (sim_error): Delete. Replace calls with sim_io_error.
3161 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3162 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3163 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3164 argument.
3165 (mips_size): Rename from sim_size. Add SD argument.
3166
3167 * interp.c (simulator): Delete global variable.
3168 (callback): Delete global variable.
3169 (mips_option_handler, sim_open, sim_write, sim_read,
3170 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3171 sim_size,sim_monitor): Use sim_io_* not callback->*.
3172 (sim_open): ZALLOC simulator struct.
3173 (PROFILE): Do not define.
3174
3175Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3176
3177 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3178 support.h with corresponding code.
3179
3180 * sim-main.h (word64, uword64), support.h: Move definition to
3181 sim-main.h.
3182 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3183
3184 * support.h: Delete
3185 * Makefile.in: Update dependencies
3186 * interp.c: Do not include.
72f4393d 3187
c906108c
SS		 3188Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3189
3190 * interp.c (address_translation, load_memory, store_memory,
3191 cache_op): Rename to from AddressTranslation et.al., make global,
3192 add SD argument
72f4393d 3193
c906108c
SS		 3194 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3195 CacheOp): Define.
72f4393d 3196
c906108c
SS		 3197 * interp.c (SignalException): Rename to signal_exception, make
3198 global.
3199
3200 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3201
c906108c
SS		 3202 * sim-main.h (SignalException, SignalExceptionInterrupt,
3203 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3204 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3205 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3206 Define.
72f4393d 3207
c906108c 3208 * interp.c, support.h: Use.
72f4393d 3209
c906108c
SS		 3210Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3211
3212 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3213 to value_fpr / store_fpr. Add SD argument.
3214 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3215 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3216
3217 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3218
c906108c
SS		 3219Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3220
3221 * interp.c (sim_engine_run): Check consistency between configure
3222 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3223 and HASFPU.
3224
3225 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3226 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3227 (mips_endian): Configure WITH_TARGET_ENDIAN.
3228 * configure: Update.
3229
3230Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3231
3232 * configure: Regenerated to track ../common/aclocal.m4 changes.
3233
3234Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3235
3236 * configure: Regenerated.
3237
3238Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3239
3240 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3241
3242Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3243
3244 * gencode.c (print_igen_insn_models): Assume certain architectures
3245 include all mips* instructions.
3246 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3247 instruction.
3248
3249 * Makefile.in (tmp.igen): Add target. Generate igen input from
3250 gencode file.
3251
3252 * gencode.c (FEATURE_IGEN): Define.
3253 (main): Add --igen option. Generate output in igen format.
3254 (process_instructions): Format output according to igen option.
3255 (print_igen_insn_format): New function.
3256 (print_igen_insn_models): New function.
3257 (process_instructions): Only issue warnings and ignore
3258 instructions when no FEATURE_IGEN.
3259
3260Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3261
3262 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3263 MIPS targets.
3264
3265Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3266
3267 * configure: Regenerated to track ../common/aclocal.m4 changes.
3268
3269Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3270
3271 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3272 SIM_RESERVED_BITS): Delete, moved to common.
3273 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3274
c906108c
SS		 3275Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3276
3277 * configure.in: Configure non-strict memory alignment.
3278 * configure: Regenerated to track ../common/aclocal.m4 changes.
3279
3280Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3281
3282 * configure: Regenerated to track ../common/aclocal.m4 changes.
3283
3284Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3285
3286 * gencode.c (SDBBP,DERET): Added (3900) insns.
3287 (RFE): Turn on for 3900.
3288 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3289 (dsstate): Made global.
3290 (SUBTARGET_R3900): Added.
3291 (CANCELDELAYSLOT): New.
3292 (SignalException): Ignore SystemCall rather than ignore and
3293 terminate. Add DebugBreakPoint handling.
3294 (decode_coproc): New insns RFE, DERET; and new registers Debug
3295 and DEPC protected by SUBTARGET_R3900.
3296 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3297 bits explicitly.
3298 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3299 * configure: Update.
c906108c
SS		 3300
3301Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3302
3303 * gencode.c: Add r3900 (tx39).
72f4393d 3304
c906108c
SS		 3305
3306Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3307
3308 * gencode.c (build_instruction): Don't need to subtract 4 for
3309 JALR, just 2.
3310
3311Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3312
3313 * interp.c: Correct some HASFPU problems.
3314
3315Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3316
3317 * configure: Regenerated to track ../common/aclocal.m4 changes.
3318
3319Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3320
3321 * interp.c (mips_options): Fix samples option short form, should
3322 be `x'.
3323
3324Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3325
3326 * interp.c (sim_info): Enable info code. Was just returning.
3327
3328Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3329
3330 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3331 MFC0.
3332
3333Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3334
3335 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3336 constants.
3337 (build_instruction): Ditto for LL.
3338
3339Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3340
3341 * configure: Regenerated to track ../common/aclocal.m4 changes.
3342
3343Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3344
3345 * configure: Regenerated to track ../common/aclocal.m4 changes.
3346 * config.in: Ditto.
3347
3348Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3349
3350 * interp.c (sim_open): Add call to sim_analyze_program, update
3351 call to sim_config.
3352
3353Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3354
3355 * interp.c (sim_kill): Delete.
3356 (sim_create_inferior): Add ABFD argument. Set PC from same.
3357 (sim_load): Move code initializing trap handlers from here.
3358 (sim_open): To here.
3359 (sim_load): Delete, use sim-hload.c.
3360
3361 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3362
3363Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3364
3365 * configure: Regenerated to track ../common/aclocal.m4 changes.
3366 * config.in: Ditto.
3367
3368Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3369
3370 * interp.c (sim_open): Add ABFD argument.
3371 (sim_load): Move call to sim_config from here.
3372 (sim_open): To here. Check return status.
3373
3374Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3375
c906108c
SS		 3376 * gencode.c (build_instruction): Two arg MADD should
3377 not assign result to $0.
72f4393d 3378
c906108c
SS		 3379Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3380
3381 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3382 * sim/mips/configure.in: Regenerate.
3383
3384Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3385
3386 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3387 signed8, unsigned8 et.al. types.
3388
3389 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3390 hosts when selecting subreg.
3391
3392Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3393
3394 * interp.c (sim_engine_run): Reset the ZERO register to zero
3395 regardless of FEATURE_WARN_ZERO.
3396 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3397
3398Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3399
3400 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3401 (SignalException): For BreakPoints ignore any mode bits and just
3402 save the PC.
3403 (SignalException): Always set the CAUSE register.
3404
3405Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3406
3407 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3408 exception has been taken.
3409
3410 * interp.c: Implement the ERET and mt/f sr instructions.
3411
3412Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3413
3414 * interp.c (SignalException): Don't bother restarting an
3415 interrupt.
3416
3417Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3418
3419 * interp.c (SignalException): Really take an interrupt.
3420 (interrupt_event): Only deliver interrupts when enabled.
3421
3422Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3423
3424 * interp.c (sim_info): Only print info when verbose.
3425 (sim_info) Use sim_io_printf for output.
72f4393d 3426
c906108c
SS		 3427Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3428
3429 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3430 mips architectures.
3431
3432Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3433
3434 * interp.c (sim_do_command): Check for common commands if a
3435 simulator specific command fails.
3436
3437Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3438
3439 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3440 and simBE when DEBUG is defined.
3441
3442Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3443
3444 * interp.c (interrupt_event): New function. Pass exception event
3445 onto exception handler.
3446
3447 * configure.in: Check for stdlib.h.
3448 * configure: Regenerate.
3449
3450 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3451 variable declaration.
3452 (build_instruction): Initialize memval1.
3453 (build_instruction): Add UNUSED attribute to byte, bigend,
3454 reverse.
3455 (build_operands): Ditto.
3456
3457 * interp.c: Fix GCC warnings.
3458 (sim_get_quit_code): Delete.
3459
3460 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3461 * Makefile.in: Ditto.
3462 * configure: Re-generate.
72f4393d 3463
c906108c
SS		 3464 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3465
3466Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3467
3468 * interp.c (mips_option_handler): New function parse argumes using
3469 sim-options.
3470 (myname): Replace with STATE_MY_NAME.
3471 (sim_open): Delete check for host endianness - performed by
3472 sim_config.
3473 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3474 (sim_open): Move much of the initialization from here.
3475 (sim_load): To here. After the image has been loaded and
3476 endianness set.
3477 (sim_open): Move ColdReset from here.
3478 (sim_create_inferior): To here.
3479 (sim_open): Make FP check less dependant on host endianness.
3480
3481 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3482 run.
3483 * interp.c (sim_set_callbacks): Delete.
3484
3485 * interp.c (membank, membank_base, membank_size): Replace with
3486 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3487 (sim_open): Remove call to callback->init. gdb/run do this.
3488
3489 * interp.c: Update
3490
3491 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3492
3493 * interp.c (big_endian_p): Delete, replaced by
3494 current_target_byte_order.
3495
3496Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3497
3498 * interp.c (host_read_long, host_read_word, host_swap_word,
3499 host_swap_long): Delete. Using common sim-endian.
3500 (sim_fetch_register, sim_store_register): Use H2T.
3501 (pipeline_ticks): Delete. Handled by sim-events.
3502 (sim_info): Update.
3503 (sim_engine_run): Update.
3504
3505Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3506
3507 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3508 reason from here.
3509 (SignalException): To here. Signal using sim_engine_halt.
3510 (sim_stop_reason): Delete, moved to common.
72f4393d 3511
c906108c
SS		 3512Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3513
3514 * interp.c (sim_open): Add callback argument.
3515 (sim_set_callbacks): Delete SIM_DESC argument.
3516 (sim_size): Ditto.
3517
3518Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3519
3520 * Makefile.in (SIM_OBJS): Add common modules.
3521
3522 * interp.c (sim_set_callbacks): Also set SD callback.
3523 (set_endianness, xfer_*, swap_*): Delete.
3524 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3525 Change to functions using sim-endian macros.
3526 (control_c, sim_stop): Delete, use common version.
3527 (simulate): Convert into.
3528 (sim_engine_run): This function.
3529 (sim_resume): Delete.
72f4393d 3530
c906108c
SS		 3531 * interp.c (simulation): New variable - the simulator object.
3532 (sim_kind): Delete global - merged into simulation.
3533 (sim_load): Cleanup. Move PC assignment from here.
3534 (sim_create_inferior): To here.
3535
3536 * sim-main.h: New file.
3537 * interp.c (sim-main.h): Include.
72f4393d 3538
c906108c
SS		 3539Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3540
3541 * configure: Regenerated to track ../common/aclocal.m4 changes.
3542
3543Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3544
3545 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3546
3547Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3548
72f4393d
L		 3549 * gencode.c (build_instruction): DIV instructions: check
3550 for division by zero and integer overflow before using
c906108c
SS		 3551 host's division operation.
3552
3553Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3554
3555 * Makefile.in (SIM_OBJS): Add sim-load.o.
3556 * interp.c: #include bfd.h.
3557 (target_byte_order): Delete.
3558 (sim_kind, myname, big_endian_p): New static locals.
3559 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3560 after argument parsing. Recognize -E arg, set endianness accordingly.
3561 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3562 load file into simulator. Set PC from bfd.
3563 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3564 (set_endianness): Use big_endian_p instead of target_byte_order.
3565
3566Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3567
3568 * interp.c (sim_size): Delete prototype - conflicts with
3569 definition in remote-sim.h. Correct definition.
3570
3571Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3572
3573 * configure: Regenerated to track ../common/aclocal.m4 changes.
3574 * config.in: Ditto.
3575
3576Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3577
3578 * interp.c (sim_open): New arg `kind'.
3579
3580 * configure: Regenerated to track ../common/aclocal.m4 changes.
3581
3582Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3583
3584 * configure: Regenerated to track ../common/aclocal.m4 changes.
3585
3586Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3587
3588 * interp.c (sim_open): Set optind to 0 before calling getopt.
3589
3590Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3591
3592 * configure: Regenerated to track ../common/aclocal.m4 changes.
3593
3594Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3595
3596 * interp.c : Replace uses of pr_addr with pr_uword64
3597 where the bit length is always 64 independent of SIM_ADDR.
3598 (pr_uword64) : added.
3599
3600Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3601
3602 * configure: Re-generate.
3603
3604Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3605
3606 * configure: Regenerate to track ../common/aclocal.m4 changes.
3607
3608Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3609
3610 * interp.c (sim_open): New SIM_DESC result. Argument is now
3611 in argv form.
3612 (other sim_*): New SIM_DESC argument.
3613
3614Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3615
3616 * interp.c: Fix printing of addresses for non-64-bit targets.
3617 (pr_addr): Add function to print address based on size.
3618
3619Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3620
3621 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3622
3623Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3624
3625 * gencode.c (build_mips16_operands): Correct computation of base
3626 address for extended PC relative instruction.
3627
3628Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3629
3630 * interp.c (mips16_entry): Add support for floating point cases.
3631 (SignalException): Pass floating point cases to mips16_entry.
3632 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3633 registers.
3634 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3635 or fmt_word.
3636 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3637 and then set the state to fmt_uninterpreted.
3638 (COP_SW): Temporarily set the state to fmt_word while calling
3639 ValueFPR.
3640
3641Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3642
3643 * gencode.c (build_instruction): The high order may be set in the
3644 comparison flags at any ISA level, not just ISA 4.
3645
3646Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3647
3648 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3649 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3650 * configure.in: sinclude ../common/aclocal.m4.
3651 * configure: Regenerated.
3652
3653Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3654
3655 * configure: Rebuild after change to aclocal.m4.
3656
3657Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3658
3659 * configure configure.in Makefile.in: Update to new configure
3660 scheme which is more compatible with WinGDB builds.
3661 * configure.in: Improve comment on how to run autoconf.
3662 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3663 * Makefile.in: Use autoconf substitution to install common
3664 makefile fragment.
3665
3666Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3667
3668 * gencode.c (build_instruction): Use BigEndianCPU instead of
3669 ByteSwapMem.
3670
3671Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3672
3673 * interp.c (sim_monitor): Make output to stdout visible in
3674 wingdb's I/O log window.
3675
3676Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3677
3678 * support.h: Undo previous change to SIGTRAP
3679 and SIGQUIT values.
3680
3681Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3682
3683 * interp.c (store_word, load_word): New static functions.
3684 (mips16_entry): New static function.
3685 (SignalException): Look for mips16 entry and exit instructions.
3686 (simulate): Use the correct index when setting fpr_state after
3687 doing a pending move.
3688
3689Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3690
3691 * interp.c: Fix byte-swapping code throughout to work on
3692 both little- and big-endian hosts.
3693
3694Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3695
3696 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3697 with gdb/config/i386/xm-windows.h.
3698
3699Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3700
3701 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3702 that messes up arithmetic shifts.
3703
3704Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3705
3706 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3707 SIGTRAP and SIGQUIT for _WIN32.
3708
3709Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3710
3711 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3712 force a 64 bit multiplication.
3713 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3714 destination register is 0, since that is the default mips16 nop
3715 instruction.
3716
3717Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3718
3719 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3720 (build_endian_shift): Don't check proc64.
3721 (build_instruction): Always set memval to uword64. Cast op2 to
3722 uword64 when shifting it left in memory instructions. Always use
3723 the same code for stores--don't special case proc64.
3724
3725 * gencode.c (build_mips16_operands): Fix base PC value for PC
3726 relative operands.
3727 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3728 jal instruction.
3729 * interp.c (simJALDELAYSLOT): Define.
3730 (JALDELAYSLOT): Define.
3731 (INDELAYSLOT, INJALDELAYSLOT): Define.
3732 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3733
3734Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3735
3736 * interp.c (sim_open): add flush_cache as a PMON routine
3737 (sim_monitor): handle flush_cache by ignoring it
3738
3739Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3740
3741 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3742 BigEndianMem.
3743 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3744 (BigEndianMem): Rename to ByteSwapMem and change sense.
3745 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3746 BigEndianMem references to !ByteSwapMem.
3747 (set_endianness): New function, with prototype.
3748 (sim_open): Call set_endianness.
3749 (sim_info): Use simBE instead of BigEndianMem.
3750 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3751 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3752 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3753 ifdefs, keeping the prototype declaration.
3754 (swap_word): Rewrite correctly.
3755 (ColdReset): Delete references to CONFIG. Delete endianness related
3756 code; moved to set_endianness.
72f4393d 3757
c906108c
SS		 3758Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3759
3760 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3761 * interp.c (CHECKHILO): Define away.
3762 (simSIGINT): New macro.
3763 (membank_size): Increase from 1MB to 2MB.
3764 (control_c): New function.
3765 (sim_resume): Rename parameter signal to signal_number. Add local
3766 variable prev. Call signal before and after simulate.
3767 (sim_stop_reason): Add simSIGINT support.
3768 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3769 functions always.
3770 (sim_warning): Delete call to SignalException. Do call printf_filtered
3771 if logfh is NULL.
3772 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3773 a call to sim_warning.
3774
3775Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3776
3777 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3778 16 bit instructions.
3779
3780Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3781
3782 Add support for mips16 (16 bit MIPS implementation):
3783 * gencode.c (inst_type): Add mips16 instruction encoding types.
3784 (GETDATASIZEINSN): Define.
3785 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3786 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3787 mtlo.
3788 (MIPS16_DECODE): New table, for mips16 instructions.
3789 (bitmap_val): New static function.
3790 (struct mips16_op): Define.
3791 (mips16_op_table): New table, for mips16 operands.
3792 (build_mips16_operands): New static function.
3793 (process_instructions): If PC is odd, decode a mips16
3794 instruction. Break out instruction handling into new
3795 build_instruction function.
3796 (build_instruction): New static function, broken out of
3797 process_instructions. Check modifiers rather than flags for SHIFT
3798 bit count and m[ft]{hi,lo} direction.
3799 (usage): Pass program name to fprintf.
3800 (main): Remove unused variable this_option_optind. Change
3801 ``*loptarg++'' to ``loptarg++''.
3802 (my_strtoul): Parenthesize && within ||.
3803 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3804 (simulate): If PC is odd, fetch a 16 bit instruction, and
3805 increment PC by 2 rather than 4.
3806 * configure.in: Add case for mips16*-*-*.
3807 * configure: Rebuild.
3808
3809Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3810
3811 * interp.c: Allow -t to enable tracing in standalone simulator.
3812 Fix garbage output in trace file and error messages.
3813
3814Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3815
3816 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3817 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3818 * configure.in: Simplify using macros in ../common/aclocal.m4.
3819 * configure: Regenerated.
3820 * tconfig.in: New file.
3821
3822Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3823
3824 * interp.c: Fix bugs in 64-bit port.
3825 Use ansi function declarations for msvc compiler.
3826 Initialize and test file pointer in trace code.
3827 Prevent duplicate definition of LAST_EMED_REGNUM.
3828
3829Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3830
3831 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3832
3833Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3834
3835 * interp.c (SignalException): Check for explicit terminating
3836 breakpoint value.
3837 * gencode.c: Pass instruction value through SignalException()
3838 calls for Trap, Breakpoint and Syscall.
3839
3840Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3841
3842 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3843 only used on those hosts that provide it.
3844 * configure.in: Add sqrt() to list of functions to be checked for.
3845 * config.in: Re-generated.
3846 * configure: Re-generated.
3847
3848Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3849
3850 * gencode.c (process_instructions): Call build_endian_shift when
3851 expanding STORE RIGHT, to fix swr.
3852 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3853 clear the high bits.
3854 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3855 Fix float to int conversions to produce signed values.
3856
3857Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3858
3859 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3860 (process_instructions): Correct handling of nor instruction.
3861 Correct shift count for 32 bit shift instructions. Correct sign
3862 extension for arithmetic shifts to not shift the number of bits in
3863 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3864 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3865 Fix madd.
3866 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3867 It's OK to have a mult follow a mult. What's not OK is to have a
3868 mult follow an mfhi.
3869 (Convert): Comment out incorrect rounding code.
3870
3871Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3872
3873 * interp.c (sim_monitor): Improved monitor printf
3874 simulation. Tidied up simulator warnings, and added "--log" option
3875 for directing warning message output.
3876 * gencode.c: Use sim_warning() rather than WARNING macro.
3877
3878Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3879
3880 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3881 getopt1.o, rather than on gencode.c. Link objects together.
3882 Don't link against -liberty.
3883 (gencode.o, getopt.o, getopt1.o): New targets.
3884 * gencode.c: Include <ctype.h> and "ansidecl.h".
3885 (AND): Undefine after including "ansidecl.h".
3886 (ULONG_MAX): Define if not defined.
3887 (OP_*): Don't define macros; now defined in opcode/mips.h.
3888 (main): Call my_strtoul rather than strtoul.
3889 (my_strtoul): New static function.
3890
3891Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3892
3893 * gencode.c (process_instructions): Generate word64 and uword64
3894 instead of `long long' and `unsigned long long' data types.
3895 * interp.c: #include sysdep.h to get signals, and define default
3896 for SIGBUS.
3897 * (Convert): Work around for Visual-C++ compiler bug with type
3898 conversion.
3899 * support.h: Make things compile under Visual-C++ by using
3900 __int64 instead of `long long'. Change many refs to long long
3901 into word64/uword64 typedefs.
3902
3903Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3904
72f4393d
L		 3905 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3906 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3907 (docdir): Removed.
3908 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3909 (AC_PROG_INSTALL): Added.
c906108c 3910 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3911 * configure: Rebuilt.
3912
c906108c
SS		 3913Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3914
3915 * configure.in: Define @SIMCONF@ depending on mips target.
3916 * configure: Rebuild.
3917 * Makefile.in (run): Add @SIMCONF@ to control simulator
3918 construction.
3919 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3920 * interp.c: Remove some debugging, provide more detailed error
3921 messages, update memory accesses to use LOADDRMASK.
72f4393d 3922
c906108c
SS		 3923Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3924
3925 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3926 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3927 stamp-h.
3928 * configure: Rebuild.
3929 * config.in: New file, generated by autoheader.
3930 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3931 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3932 HAVE_ANINT and HAVE_AINT, as appropriate.
3933 * Makefile.in (run): Use @LIBS@ rather than -lm.
3934 (interp.o): Depend upon config.h.
3935 (Makefile): Just rebuild Makefile.
3936 (clean): Remove stamp-h.
3937 (mostlyclean): Make the same as clean, not as distclean.
3938 (config.h, stamp-h): New targets.
3939
3940Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3941
3942 * interp.c (ColdReset): Fix boolean test. Make all simulator
3943 globals static.
3944
3945Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3946
3947 * interp.c (xfer_direct_word, xfer_direct_long,
3948 swap_direct_word, swap_direct_long, xfer_big_word,
3949 xfer_big_long, xfer_little_word, xfer_little_long,
3950 swap_word,swap_long): Added.
3951 * interp.c (ColdReset): Provide function indirection to
3952 host<->simulated_target transfer routines.
3953 * interp.c (sim_store_register, sim_fetch_register): Updated to
3954 make use of indirected transfer routines.
3955
3956Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3957
3958 * gencode.c (process_instructions): Ensure FP ABS instruction
3959 recognised.
3960 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3961 system call support.
3962
3963Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3964
3965 * interp.c (sim_do_command): Complain if callback structure not
3966 initialised.
3967
3968Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3969
3970 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3971 support for Sun hosts.
3972 * Makefile.in (gencode): Ensure the host compiler and libraries
3973 used for cross-hosted build.
3974
3975Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3976
3977 * interp.c, gencode.c: Some more (TODO) tidying.
3978
3979Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3980
3981 * gencode.c, interp.c: Replaced explicit long long references with
3982 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3983 * support.h (SET64LO, SET64HI): Macros added.
3984
3985Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3986
3987 * configure: Regenerate with autoconf 2.7.
3988
3989Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3990
3991 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3992 * support.h: Remove superfluous "1" from #if.
3993 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3994
3995Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3996
3997 * interp.c (StoreFPR): Control UndefinedResult() call on
3998 WARN_RESULT manifest.
3999
4000Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
4001
4002 * gencode.c: Tidied instruction decoding, and added FP instruction
4003 support.
4004
4005 * interp.c: Added dineroIII, and BSD profiling support. Also
4006 run-time FP handling.
4007
4008Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
4009
4010 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
4011 gencode.c, interp.c, support.h: created.
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