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2002-03-07 Chris Demetriou <cgd@broadcom.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
b96e7ef1
CD		 12002-03-05 Chris Demetriou <cgd@broadcom.com>
2
3 * sim-main.h (UndefinedResult, Unpredictable): New macros
4 which currently do nothing.
5
d35d4f70
CD		 62002-03-05 Chris Demetriou <cgd@broadcom.com>
7
8 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
9 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
10 (status_CU3): New definitions.
11
12 * sim-main.h (ExceptionCause): Add new values for MIPS32
13 and MIPS64: MDMX, MCheck, CacheErr. Update comments
14 for DebugBreakPoint and NMIReset to note their status in
15 MIPS32 and MIPS64.
16 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
17 (SignalExceptionCacheErr): New exception macros.
18
3ad6f714
CD		 192002-03-05 Chris Demetriou <cgd@broadcom.com>
20
21 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
22 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
23 is always enabled.
24 (SignalExceptionCoProcessorUnusable): Take as argument the
25 unusable coprocessor number.
26
86b77b47
CD		 272002-03-05 Chris Demetriou <cgd@broadcom.com>
28
29 * mips.igen: Fix formatting of all SignalException calls.
30
97a88e93 312002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 32
33 * sim-main.h (SIGNEXTEND): Remove.
34
97a88e93 352002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 36
37 * mips.igen: Remove gencode comment from top of file, fix
38 spelling in another comment.
39
97a88e93 402002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 41
42 * mips.igen (check_fmt, check_fmt_p): New functions to check
43 whether specific floating point formats are usable.
44 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
45 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
46 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
47 Use the new functions.
48 (do_c_cond_fmt): Remove format checks...
49 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
50
97a88e93 512002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 52
53 * mips.igen: Fix formatting of check_fpu calls.
54
41774c9d
CD		 552002-03-03 Chris Demetriou <cgd@broadcom.com>
56
57 * mips.igen (FLOOR.L.fmt): Store correct destination register.
58
4a0bd876
CD		 592002-03-03 Chris Demetriou <cgd@broadcom.com>
60
61 * mips.igen: Remove whitespace at end of lines.
62
09297648
CD		 632002-03-02 Chris Demetriou <cgd@broadcom.com>
64
65 * mips.igen (loadstore_ea): New function to do effective
66 address calculations.
67 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
68 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
69 CACHE): Use loadstore_ea to do effective address computations.
70
043b7057
CD		 712002-03-02 Chris Demetriou <cgd@broadcom.com>
72
73 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
74 * mips.igen (LL, CxC1, MxC1): Likewise.
75
c1e8ada4
CD		 762002-03-02 Chris Demetriou <cgd@broadcom.com>
77
78 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
79 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
80 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
81 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
82 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
83 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
84 Don't split opcode fields by hand, use the opcode field values
85 provided by igen.
86
3e1dca16
CD		 872002-03-01 Chris Demetriou <cgd@broadcom.com>
88
89 * mips.igen (do_divu): Fix spacing.
90
91 * mips.igen (do_dsllv): Move to be right before DSLLV,
92 to match the rest of the do_<shift> functions.
93
fff8d27d
CD		 942002-03-01 Chris Demetriou <cgd@broadcom.com>
95
96 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
97 DSRL32, do_dsrlv): Trace inputs and results.
98
0d3e762b
CD		 992002-03-01 Chris Demetriou <cgd@broadcom.com>
100
101 * mips.igen (CACHE): Provide instruction-printing string.
102
103 * interp.c (signal_exception): Comment tokens after #endif.
104
eb5fcf93
CD		 1052002-02-28 Chris Demetriou <cgd@broadcom.com>
106
107 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
108 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
109 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
110 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
111 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
112 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
113 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
114 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
115
bb22bd7d
CD		 1162002-02-28 Chris Demetriou <cgd@broadcom.com>
117
118 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
119 instruction-printing string.
120 (LWU): Use '64' as the filter flag.
121
91a177cf
CD		 1222002-02-28 Chris Demetriou <cgd@broadcom.com>
123
124 * mips.igen (SDXC1): Fix instruction-printing string.
125
387f484a
CD		 1262002-02-28 Chris Demetriou <cgd@broadcom.com>
127
128 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
129 filter flags "32,f".
130
3d81f391
CD		 1312002-02-27 Chris Demetriou <cgd@broadcom.com>
132
133 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
134 as the filter flag.
135
af5107af
CD		 1362002-02-27 Chris Demetriou <cgd@broadcom.com>
137
138 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
139 add a comma) so that it more closely match the MIPS ISA
140 documentation opcode partitioning.
141 (PREF): Put useful names on opcode fields, and include
142 instruction-printing string.
143
ca971540
CD		 1442002-02-27 Chris Demetriou <cgd@broadcom.com>
145
146 * mips.igen (check_u64): New function which in the future will
147 check whether 64-bit instructions are usable and signal an
148 exception if not. Currently a no-op.
149 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
150 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
151 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
152 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
153
154 * mips.igen (check_fpu): New function which in the future will
155 check whether FPU instructions are usable and signal an exception
156 if not. Currently a no-op.
157 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
158 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
159 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
160 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
161 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
162 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
163 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
164 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
165
1c47a468
CD		 1662002-02-27 Chris Demetriou <cgd@broadcom.com>
167
168 * mips.igen (do_load_left, do_load_right): Move to be immediately
169 following do_load.
170 (do_store_left, do_store_right): Move to be immediately following
171 do_store.
172
603a98e7
CD		 1732002-02-27 Chris Demetriou <cgd@broadcom.com>
174
175 * mips.igen (mipsV): New model name. Also, add it to
176 all instructions and functions where it is appropriate.
177
c5d00cc7
CD		 1782002-02-18 Chris Demetriou <cgd@broadcom.com>
179
180 * mips.igen: For all functions and instructions, list model
181 names that support that instruction one per line.
182
074e9cb8
CD		 1832002-02-11 Chris Demetriou <cgd@broadcom.com>
184
185 * mips.igen: Add some additional comments about supported
186 models, and about which instructions go where.
187 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
188 order as is used in the rest of the file.
189
9805e229
CD		 1902002-02-11 Chris Demetriou <cgd@broadcom.com>
191
192 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
193 indicating that ALU32_END or ALU64_END are there to check
194 for overflow.
195 (DADD): Likewise, but also remove previous comment about
196 overflow checking.
197
f701dad2
CD		 1982002-02-10 Chris Demetriou <cgd@broadcom.com>
199
200 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
201 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
202 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
203 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
204 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
205 fields (i.e., add and move commas) so that they more closely
206 match the MIPS ISA documentation opcode partitioning.
207
2082002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 209
210 * mips.igen (ADDI): Print immediate value.
211 (BREAK): Print code.
212 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
213 (SLL): Print "nop" specially, and don't run the code
214 that does the shift for the "nop" case.
215
9e52972e
FF		 2162001-11-17 Fred Fish <fnf@redhat.com>
217
218 * sim-main.h (float_operation): Move enum declaration outside
219 of _sim_cpu struct declaration.
220
c0efbca4
JB		 2212001-04-12 Jim Blandy <jimb@redhat.com>
222
223 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
224 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
225 set of the FCSR.
226 * sim-main.h (COCIDX): Remove definition; this isn't supported by
227 PENDING_FILL, and you can get the intended effect gracefully by
228 calling PENDING_SCHED directly.
229
fb891446
BE		 2302001-02-23 Ben Elliston <bje@redhat.com>
231
232 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
233 already defined elsewhere.
234
8030f857
BE		 2352001-02-19 Ben Elliston <bje@redhat.com>
236
237 * sim-main.h (sim_monitor): Return an int.
238 * interp.c (sim_monitor): Add return values.
239 (signal_exception): Handle error conditions from sim_monitor.
240
56b48a7a
CD		 2412001-02-08 Ben Elliston <bje@redhat.com>
242
243 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
244 (store_memory): Likewise, pass cia to sim_core_write*.
245
d3ee60d9
FCE		 2462000-10-19 Frank Ch. Eigler <fche@redhat.com>
247
248 On advice from Chris G. Demetriou <cgd@sibyte.com>:
249 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
250
071da002
AC		 251Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
252
253 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
254 * Makefile.in: Don't delete *.igen when cleaning directory.
255
a28c02cd
AC		 256Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
257
258 * m16.igen (break): Call SignalException not sim_engine_halt.
259
80ee11fa
AC		 260Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
261
262 From Jason Eckhardt:
263 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
264
673388c0
AC		 265Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
266
267 * mips.igen (MxC1, DMxC1): Fix printf formatting.
268
4c0deff4
NC		 2692000-05-24 Michael Hayes <mhayes@cygnus.com>
270
271 * mips.igen (do_dmultx): Fix typo.
272
eb2d80b4
AC		 273Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
274
275 * configure: Regenerated to track ../common/aclocal.m4 changes.
276
dd37a34b
AC		 277Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
278
279 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
280
4c0deff4
NC		 2812000-04-12 Frank Ch. Eigler <fche@redhat.com>
282
283 * sim-main.h (GPR_CLEAR): Define macro.
284
e30db738
AC		 285Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
286
287 * interp.c (decode_coproc): Output long using %lx and not %s.
288
cb7450ea
FCE		 2892000-03-21 Frank Ch. Eigler <fche@redhat.com>
290
291 * interp.c (sim_open): Sort & extend dummy memory regions for
292 --board=jmr3904 for eCos.
293
a3027dd7
FCE		 2942000-03-02 Frank Ch. Eigler <fche@redhat.com>
295
296 * configure: Regenerated.
297
298Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
299
300 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
301 calls, conditional on the simulator being in verbose mode.
302
dfcd3bfb
JM		 303Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
304
305 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
306 cache don't get ReservedInstruction traps.
307
c2d11a7d
JM		 3081999-11-29 Mark Salter <msalter@cygnus.com>
309
310 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
311 to clear status bits in sdisr register. This is how the hardware works.
312
313 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
314 being used by cygmon.
315
4ce44c66
JM		 3161999-11-11 Andrew Haley <aph@cygnus.com>
317
318 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
319 instructions.
320
cff3e48b
JM		 321Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
322
323 * mips.igen (MULT): Correct previous mis-applied patch.
324
d4f3574e
SS		 325Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
326
327 * mips.igen (delayslot32): Handle sequence like
328 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
329 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
330 (MULT): Actually pass the third register...
331
3321999-09-03 Mark Salter <msalter@cygnus.com>
333
334 * interp.c (sim_open): Added more memory aliases for additional
335 hardware being touched by cygmon on jmr3904 board.
336
337Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
338
339 * configure: Regenerated to track ../common/aclocal.m4 changes.
340
a0b3c4fd
JM		 341Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
342
343 * interp.c (sim_store_register): Handle case where client - GDB -
344 specifies that a 4 byte register is 8 bytes in size.
345 (sim_fetch_register): Ditto.
346
adf40b2e
JM		 3471999-07-14 Frank Ch. Eigler <fche@cygnus.com>
348
349 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
350 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
351 (idt_monitor_base): Base address for IDT monitor traps.
352 (pmon_monitor_base): Ditto for PMON.
353 (lsipmon_monitor_base): Ditto for LSI PMON.
354 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
355 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
356 (sim_firmware_command): New function.
357 (mips_option_handler): Call it for OPTION_FIRMWARE.
358 (sim_open): Allocate memory for idt_monitor region. If "--board"
359 option was given, add no monitor by default. Add BREAK hooks only if
360 monitors are also there.
361
43e526b9
JM		 362Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
363
364 * interp.c (sim_monitor): Flush output before reading input.
365
366Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
367
368 * tconfig.in (SIM_HANDLES_LMA): Always define.
369
370Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
371
372 From Mark Salter <msalter@cygnus.com>:
373 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
374 (sim_open): Add setup for BSP board.
375
9846de1b
JM		 376Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
377
378 * mips.igen (MULT, MULTU): Add syntax for two operand version.
379 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
380 them as unimplemented.
381
cd0fc7c3
SS		 3821999-05-08 Felix Lee <flee@cygnus.com>
383
384 * configure: Regenerated to track ../common/aclocal.m4 changes.
385
7a292a7a
SS		 3861999-04-21 Frank Ch. Eigler <fche@cygnus.com>
387
388 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
389
390Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
391
392 * configure.in: Any mips64vr5*-*-* target should have
393 -DTARGET_ENABLE_FR=1.
394 (default_endian): Any mips64vr*el-*-* target should default to
395 LITTLE_ENDIAN.
396 * configure: Re-generate.
397
3981999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
399
400 * mips.igen (ldl): Extend from _16_, not 32.
401
402Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
403
404 * interp.c (sim_store_register): Force registers written to by GDB
405 into an un-interpreted state.
406
c906108c
SS		 4071999-02-05 Frank Ch. Eigler <fche@cygnus.com>
408
409 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
410 CPU, start periodic background I/O polls.
411 (tx3904sio_poll): New function: periodic I/O poller.
412
4131998-12-30 Frank Ch. Eigler <fche@cygnus.com>
414
415 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
416
417Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
418
419 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
420 case statement.
421
4221998-12-29 Frank Ch. Eigler <fche@cygnus.com>
423
424 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
425 (load_word): Call SIM_CORE_SIGNAL hook on error.
426 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
427 starting. For exception dispatching, pass PC instead of NULL_CIA.
428 (decode_coproc): Use COP0_BADVADDR to store faulting address.
429 * sim-main.h (COP0_BADVADDR): Define.
430 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
431 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
432 (_sim_cpu): Add exc_* fields to store register value snapshots.
433 * mips.igen (*): Replace memory-related SignalException* calls
434 with references to SIM_CORE_SIGNAL hook.
435
436 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
437 fix.
438 * sim-main.c (*): Minor warning cleanups.
439
4401998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
441
442 * m16.igen (DADDIU5): Correct type-o.
443
444Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
445
446 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
447 variables.
448
449Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
450
451 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
452 to include path.
453 (interp.o): Add dependency on itable.h
454 (oengine.c, gencode): Delete remaining references.
455 (BUILT_SRC_FROM_GEN): Clean up.
456
4571998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
458
459 * vr4run.c: New.
460 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
461 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
462 tmp-run-hack) : New.
463 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
464 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
465 Drop the "64" qualifier to get the HACK generator working.
466 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
467 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
468 qualifier to get the hack generator working.
469 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
470 (DSLL): Use do_dsll.
471 (DSLLV): Use do_dsllv.
472 (DSRA): Use do_dsra.
473 (DSRL): Use do_dsrl.
474 (DSRLV): Use do_dsrlv.
475 (BC1): Move *vr4100 to get the HACK generator working.
476 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
477 get the HACK generator working.
478 (MACC) Rename to get the HACK generator working.
479 (DMACC,MACCS,DMACCS): Add the 64.
480
4811998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
482
483 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
484 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
485
4861998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
487
488 * mips/interp.c (DEBUG): Cleanups.
489
4901998-12-10 Frank Ch. Eigler <fche@cygnus.com>
491
492 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
493 (tx3904sio_tickle): fflush after a stdout character output.
494
4951998-12-03 Frank Ch. Eigler <fche@cygnus.com>
496
497 * interp.c (sim_close): Uninstall modules.
498
499Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
500
501 * sim-main.h, interp.c (sim_monitor): Change to global
502 function.
503
504Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
505
506 * configure.in (vr4100): Only include vr4100 instructions in
507 simulator.
508 * configure: Re-generate.
509 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
510
511Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
512
513 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
514 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
515 true alternative.
516
517 * configure.in (sim_default_gen, sim_use_gen): Replace with
518 sim_gen.
519 (--enable-sim-igen): Delete config option. Always using IGEN.
520 * configure: Re-generate.
521
522 * Makefile.in (gencode): Kill, kill, kill.
523 * gencode.c: Ditto.
524
525Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
526
527 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
528 bit mips16 igen simulator.
529 * configure: Re-generate.
530
531 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
532 as part of vr4100 ISA.
533 * vr.igen: Mark all instructions as 64 bit only.
534
535Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
536
537 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
538 Pacify GCC.
539
540Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
541
542 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
543 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
544 * configure: Re-generate.
545
546 * m16.igen (BREAK): Define breakpoint instruction.
547 (JALX32): Mark instruction as mips16 and not r3900.
548 * mips.igen (C.cond.fmt): Fix typo in instruction format.
549
550 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
551
552Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
553
554 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
555 insn as a debug breakpoint.
556
557 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
558 pending.slot_size.
559 (PENDING_SCHED): Clean up trace statement.
560 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
561 (PENDING_FILL): Delay write by only one cycle.
562 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
563
564 * sim-main.c (pending_tick): Clean up trace statements. Add trace
565 of pending writes.
566 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
567 32 & 64.
568 (pending_tick): Move incrementing of index to FOR statement.
569 (pending_tick): Only update PENDING_OUT after a write has occured.
570
571 * configure.in: Add explicit mips-lsi-* target. Use gencode to
572 build simulator.
573 * configure: Re-generate.
574
575 * interp.c (sim_engine_run OLD): Delete explicit call to
576 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
577
578Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
579
580 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
581 interrupt level number to match changed SignalExceptionInterrupt
582 macro.
583
584Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
585
586 * interp.c: #include "itable.h" if WITH_IGEN.
587 (get_insn_name): New function.
588 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
589 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
590
591Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
592
593 * configure: Rebuilt to inhale new common/aclocal.m4.
594
595Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
596
597 * dv-tx3904sio.c: Include sim-assert.h.
598
599Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
600
601 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
602 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
603 Reorganize target-specific sim-hardware checks.
604 * configure: rebuilt.
605 * interp.c (sim_open): For tx39 target boards, set
606 OPERATING_ENVIRONMENT, add tx3904sio devices.
607 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
608 ROM executables. Install dv-sockser into sim-modules list.
609
610 * dv-tx3904irc.c: Compiler warning clean-up.
611 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
612 frequent hw-trace messages.
613
614Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
615
616 * vr.igen (MulAcc): Identify as a vr4100 specific function.
617
618Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
619
620 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
621
622 * vr.igen: New file.
623 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
624 * mips.igen: Define vr4100 model. Include vr.igen.
625Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
626
627 * mips.igen (check_mf_hilo): Correct check.
628
629Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
630
631 * sim-main.h (interrupt_event): Add prototype.
632
633 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
634 register_ptr, register_value.
635 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
636
637 * sim-main.h (tracefh): Make extern.
638
639Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
640
641 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
642 Reduce unnecessarily high timer event frequency.
643 * dv-tx3904cpu.c: Ditto for interrupt event.
644
645Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
646
647 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
648 to allay warnings.
649 (interrupt_event): Made non-static.
650
651 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
652 interchange of configuration values for external vs. internal
653 clock dividers.
654
655Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
656
657 * mips.igen (BREAK): Moved code to here for
658 simulator-reserved break instructions.
659 * gencode.c (build_instruction): Ditto.
660 * interp.c (signal_exception): Code moved from here. Non-
661 reserved instructions now use exception vector, rather
662 than halting sim.
663 * sim-main.h: Moved magic constants to here.
664
665Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
666
667 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
668 register upon non-zero interrupt event level, clear upon zero
669 event value.
670 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
671 by passing zero event value.
672 (*_io_{read,write}_buffer): Endianness fixes.
673 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
674 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
675
676 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
677 serial I/O and timer module at base address 0xFFFF0000.
678
679Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
680
681 * mips.igen (SWC1) : Correct the handling of ReverseEndian
682 and BigEndianCPU.
683
684Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
685
686 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
687 parts.
688 * configure: Update.
689
690Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
691
692 * dv-tx3904tmr.c: New file - implements tx3904 timer.
693 * dv-tx3904{irc,cpu}.c: Mild reformatting.
694 * configure.in: Include tx3904tmr in hw_device list.
695 * configure: Rebuilt.
696 * interp.c (sim_open): Instantiate three timer instances.
697 Fix address typo of tx3904irc instance.
698
699Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
700
701 * interp.c (signal_exception): SystemCall exception now uses
702 the exception vector.
703
704Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
705
706 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
707 to allay warnings.
708
709Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
710
711 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
712
713Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
714
715 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
716
717 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
718 sim-main.h. Declare a struct hw_descriptor instead of struct
719 hw_device_descriptor.
720
721Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
722
723 * mips.igen (do_store_left, do_load_left): Compute nr of left and
724 right bits and then re-align left hand bytes to correct byte
725 lanes. Fix incorrect computation in do_store_left when loading
726 bytes from second word.
727
728Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
729
730 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
731 * interp.c (sim_open): Only create a device tree when HW is
732 enabled.
733
734 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
735 * interp.c (signal_exception): Ditto.
736
737Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
738
739 * gencode.c: Mark BEGEZALL as LIKELY.
740
741Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
742
743 * sim-main.h (ALU32_END): Sign extend 32 bit results.
744 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
745
746Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
747
748 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
749 modules. Recognize TX39 target with "mips*tx39" pattern.
750 * configure: Rebuilt.
751 * sim-main.h (*): Added many macros defining bits in
752 TX39 control registers.
753 (SignalInterrupt): Send actual PC instead of NULL.
754 (SignalNMIReset): New exception type.
755 * interp.c (board): New variable for future use to identify
756 a particular board being simulated.
757 (mips_option_handler,mips_options): Added "--board" option.
758 (interrupt_event): Send actual PC.
759 (sim_open): Make memory layout conditional on board setting.
760 (signal_exception): Initial implementation of hardware interrupt
761 handling. Accept another break instruction variant for simulator
762 exit.
763 (decode_coproc): Implement RFE instruction for TX39.
764 (mips.igen): Decode RFE instruction as such.
765 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
766 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
767 bbegin to implement memory map.
768 * dv-tx3904cpu.c: New file.
769 * dv-tx3904irc.c: New file.
770
771Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
772
773 * mips.igen (check_mt_hilo): Create a separate r3900 version.
774
775Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
776
777 * tx.igen (madd,maddu): Replace calls to check_op_hilo
778 with calls to check_div_hilo.
779
780Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
781
782 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
783 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
784 Add special r3900 version of do_mult_hilo.
785 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
786 with calls to check_mult_hilo.
787 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
788 with calls to check_div_hilo.
789
790Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
791
792 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
793 Document a replacement.
794
795Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
796
797 * interp.c (sim_monitor): Make mon_printf work.
798
799Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
800
801 * sim-main.h (INSN_NAME): New arg `cpu'.
802
803Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
804
805 * configure: Regenerated to track ../common/aclocal.m4 changes.
806
807Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
808
809 * configure: Regenerated to track ../common/aclocal.m4 changes.
810 * config.in: Ditto.
811
812Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
813
814 * acconfig.h: New file.
815 * configure.in: Reverted change of Apr 24; use sinclude again.
816
817Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
818
819 * configure: Regenerated to track ../common/aclocal.m4 changes.
820 * config.in: Ditto.
821
822Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
823
824 * configure.in: Don't call sinclude.
825
826Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
827
828 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
829
830Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
831
832 * mips.igen (ERET): Implement.
833
834 * interp.c (decode_coproc): Return sign-extended EPC.
835
836 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
837
838 * interp.c (signal_exception): Do not ignore Trap.
839 (signal_exception): On TRAP, restart at exception address.
840 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
841 (signal_exception): Update.
842 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
843 so that TRAP instructions are caught.
844
845Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
846
847 * sim-main.h (struct hilo_access, struct hilo_history): Define,
848 contains HI/LO access history.
849 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
850 (HIACCESS, LOACCESS): Delete, replace with
851 (HIHISTORY, LOHISTORY): New macros.
852 (CHECKHILO): Delete all, moved to mips.igen
853
854 * gencode.c (build_instruction): Do not generate checks for
855 correct HI/LO register usage.
856
857 * interp.c (old_engine_run): Delete checks for correct HI/LO
858 register usage.
859
860 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
861 check_mf_cycles): New functions.
862 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
863 do_divu, domultx, do_mult, do_multu): Use.
864
865 * tx.igen ("madd", "maddu"): Use.
866
867Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
868
869 * mips.igen (DSRAV): Use function do_dsrav.
870 (SRAV): Use new function do_srav.
871
872 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
873 (B): Sign extend 11 bit immediate.
874 (EXT-B*): Shift 16 bit immediate left by 1.
875 (ADDIU*): Don't sign extend immediate value.
876
877Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
878
879 * m16run.c (sim_engine_run): Restore CIA after handling an event.
880
881 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
882 functions.
883
884 * mips.igen (delayslot32, nullify_next_insn): New functions.
885 (m16.igen): Always include.
886 (do_*): Add more tracing.
887
888 * m16.igen (delayslot16): Add NIA argument, could be called by a
889 32 bit MIPS16 instruction.
890
891 * interp.c (ifetch16): Move function from here.
892 * sim-main.c (ifetch16): To here.
893
894 * sim-main.c (ifetch16, ifetch32): Update to match current
895 implementations of LH, LW.
896 (signal_exception): Don't print out incorrect hex value of illegal
897 instruction.
898
899Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
900
901 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
902 instruction.
903
904 * m16.igen: Implement MIPS16 instructions.
905
906 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
907 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
908 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
909 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
910 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
911 bodies of corresponding code from 32 bit insn to these. Also used
912 by MIPS16 versions of functions.
913
914 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
915 (IMEM16): Drop NR argument from macro.
916
917Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
918
919 * Makefile.in (SIM_OBJS): Add sim-main.o.
920
921 * sim-main.h (address_translation, load_memory, store_memory,
922 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
923 as INLINE_SIM_MAIN.
924 (pr_addr, pr_uword64): Declare.
925 (sim-main.c): Include when H_REVEALS_MODULE_P.
926
927 * interp.c (address_translation, load_memory, store_memory,
928 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
929 from here.
930 * sim-main.c: To here. Fix compilation problems.
931
932 * configure.in: Enable inlining.
933 * configure: Re-config.
934
935Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
936
937 * configure: Regenerated to track ../common/aclocal.m4 changes.
938
939Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
940
941 * mips.igen: Include tx.igen.
942 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
943 * tx.igen: New file, contains MADD and MADDU.
944
945 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
946 the hardwired constant `7'.
947 (store_memory): Ditto.
948 (LOADDRMASK): Move definition to sim-main.h.
949
950 mips.igen (MTC0): Enable for r3900.
951 (ADDU): Add trace.
952
953 mips.igen (do_load_byte): Delete.
954 (do_load, do_store, do_load_left, do_load_write, do_store_left,
955 do_store_right): New functions.
956 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
957
958 configure.in: Let the tx39 use igen again.
959 configure: Update.
960
961Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
962
963 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
964 not an address sized quantity. Return zero for cache sizes.
965
966Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
967
968 * mips.igen (r3900): r3900 does not support 64 bit integer
969 operations.
970
971Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
972
973 * configure.in (mipstx39*-*-*): Use gencode simulator rather
974 than igen one.
975 * configure : Rebuild.
976
977Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
978
979 * configure: Regenerated to track ../common/aclocal.m4 changes.
980
981Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
982
983 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
984
985Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
986
987 * configure: Regenerated to track ../common/aclocal.m4 changes.
988 * config.in: Regenerated to track ../common/aclocal.m4 changes.
989
990Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
991
992 * configure: Regenerated to track ../common/aclocal.m4 changes.
993
994Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
995
996 * interp.c (Max, Min): Comment out functions. Not yet used.
997
998Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
999
1000 * configure: Regenerated to track ../common/aclocal.m4 changes.
1001
1002Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1003
1004 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1005 configurable settings for stand-alone simulator.
1006
1007 * configure.in: Added X11 search, just in case.
1008
1009 * configure: Regenerated.
1010
1011Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1012
1013 * interp.c (sim_write, sim_read, load_memory, store_memory):
1014 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1015
1016Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1017
1018 * sim-main.h (GETFCC): Return an unsigned value.
1019
1020Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1021
1022 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1023 (DADD): Result destination is RD not RT.
1024
1025Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1026
1027 * sim-main.h (HIACCESS, LOACCESS): Always define.
1028
1029 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1030
1031 * interp.c (sim_info): Delete.
1032
1033Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1034
1035 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1036 (mips_option_handler): New argument `cpu'.
1037 (sim_open): Update call to sim_add_option_table.
1038
1039Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1040
1041 * mips.igen (CxC1): Add tracing.
1042
1043Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1044
1045 * sim-main.h (Max, Min): Declare.
1046
1047 * interp.c (Max, Min): New functions.
1048
1049 * mips.igen (BC1): Add tracing.
1050
1051Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1052
1053 * interp.c Added memory map for stack in vr4100
1054
1055Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1056
1057 * interp.c (load_memory): Add missing "break"'s.
1058
1059Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1060
1061 * interp.c (sim_store_register, sim_fetch_register): Pass in
1062 length parameter. Return -1.
1063
1064Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1065
1066 * interp.c: Added hardware init hook, fixed warnings.
1067
1068Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1069
1070 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1071
1072Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1073
1074 * interp.c (ifetch16): New function.
1075
1076 * sim-main.h (IMEM32): Rename IMEM.
1077 (IMEM16_IMMED): Define.
1078 (IMEM16): Define.
1079 (DELAY_SLOT): Update.
1080
1081 * m16run.c (sim_engine_run): New file.
1082
1083 * m16.igen: All instructions except LB.
1084 (LB): Call do_load_byte.
1085 * mips.igen (do_load_byte): New function.
1086 (LB): Call do_load_byte.
1087
1088 * mips.igen: Move spec for insn bit size and high bit from here.
1089 * Makefile.in (tmp-igen, tmp-m16): To here.
1090
1091 * m16.dc: New file, decode mips16 instructions.
1092
1093 * Makefile.in (SIM_NO_ALL): Define.
1094 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1095
1096Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1097
1098 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1099 point unit to 32 bit registers.
1100 * configure: Re-generate.
1101
1102Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1103
1104 * configure.in (sim_use_gen): Make IGEN the default simulator
1105 generator for generic 32 and 64 bit mips targets.
1106 * configure: Re-generate.
1107
1108Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1109
1110 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1111 bitsize.
1112
1113 * interp.c (sim_fetch_register, sim_store_register): Read/write
1114 FGR from correct location.
1115 (sim_open): Set size of FGR's according to
1116 WITH_TARGET_FLOATING_POINT_BITSIZE.
1117
1118 * sim-main.h (FGR): Store floating point registers in a separate
1119 array.
1120
1121Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1122
1123 * configure: Regenerated to track ../common/aclocal.m4 changes.
1124
1125Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1126
1127 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1128
1129 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1130
1131 * interp.c (pending_tick): New function. Deliver pending writes.
1132
1133 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1134 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1135 it can handle mixed sized quantites and single bits.
1136
1137Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1138
1139 * interp.c (oengine.h): Do not include when building with IGEN.
1140 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1141 (sim_info): Ditto for PROCESSOR_64BIT.
1142 (sim_monitor): Replace ut_reg with unsigned_word.
1143 (*): Ditto for t_reg.
1144 (LOADDRMASK): Define.
1145 (sim_open): Remove defunct check that host FP is IEEE compliant,
1146 using software to emulate floating point.
1147 (value_fpr, ...): Always compile, was conditional on HASFPU.
1148
1149Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1150
1151 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1152 size.
1153
1154 * interp.c (SD, CPU): Define.
1155 (mips_option_handler): Set flags in each CPU.
1156 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1157 (sim_close): Do not clear STATE, deleted anyway.
1158 (sim_write, sim_read): Assume CPU zero's vm should be used for
1159 data transfers.
1160 (sim_create_inferior): Set the PC for all processors.
1161 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1162 argument.
1163 (mips16_entry): Pass correct nr of args to store_word, load_word.
1164 (ColdReset): Cold reset all cpu's.
1165 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1166 (sim_monitor, load_memory, store_memory, signal_exception): Use
1167 `CPU' instead of STATE_CPU.
1168
1169
1170 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1171 SD or CPU_.
1172
1173 * sim-main.h (signal_exception): Add sim_cpu arg.
1174 (SignalException*): Pass both SD and CPU to signal_exception.
1175 * interp.c (signal_exception): Update.
1176
1177 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1178 Ditto
1179 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1180 address_translation): Ditto
1181 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1182
1183Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1184
1185 * configure: Regenerated to track ../common/aclocal.m4 changes.
1186
1187Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1188
1189 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1190
1191 * mips.igen (model): Map processor names onto BFD name.
1192
1193 * sim-main.h (CPU_CIA): Delete.
1194 (SET_CIA, GET_CIA): Define
1195
1196Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1197
1198 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1199 regiser.
1200
1201 * configure.in (default_endian): Configure a big-endian simulator
1202 by default.
1203 * configure: Re-generate.
1204
1205Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1206
1207 * configure: Regenerated to track ../common/aclocal.m4 changes.
1208
1209Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1210
1211 * interp.c (sim_monitor): Handle Densan monitor outbyte
1212 and inbyte functions.
1213
12141997-12-29 Felix Lee <flee@cygnus.com>
1215
1216 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1217
1218Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1219
1220 * Makefile.in (tmp-igen): Arrange for $zero to always be
1221 reset to zero after every instruction.
1222
1223Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1224
1225 * configure: Regenerated to track ../common/aclocal.m4 changes.
1226 * config.in: Ditto.
1227
1228Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1229
1230 * mips.igen (MSUB): Fix to work like MADD.
1231 * gencode.c (MSUB): Similarly.
1232
1233Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1234
1235 * configure: Regenerated to track ../common/aclocal.m4 changes.
1236
1237Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1238
1239 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1240
1241Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1242
1243 * sim-main.h (sim-fpu.h): Include.
1244
1245 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1246 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1247 using host independant sim_fpu module.
1248
1249Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1250
1251 * interp.c (signal_exception): Report internal errors with SIGABRT
1252 not SIGQUIT.
1253
1254 * sim-main.h (C0_CONFIG): New register.
1255 (signal.h): No longer include.
1256
1257 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1258
1259Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1260
1261 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1262
1263Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1264
1265 * mips.igen: Tag vr5000 instructions.
1266 (ANDI): Was missing mipsIV model, fix assembler syntax.
1267 (do_c_cond_fmt): New function.
1268 (C.cond.fmt): Handle mips I-III which do not support CC field
1269 separatly.
1270 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1271 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1272 in IV3.2 spec.
1273 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1274 vr5000 which saves LO in a GPR separatly.
1275
1276 * configure.in (enable-sim-igen): For vr5000, select vr5000
1277 specific instructions.
1278 * configure: Re-generate.
1279
1280Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1281
1282 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1283
1284 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1285 fmt_uninterpreted_64 bit cases to switch. Convert to
1286 fmt_formatted,
1287
1288 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1289
1290 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1291 as specified in IV3.2 spec.
1292 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1293
1294Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1295
1296 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1297 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1298 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1299 PENDING_FILL versions of instructions. Simplify.
1300 (X): New function.
1301 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1302 instructions.
1303 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1304 a signed value.
1305 (MTHI, MFHI): Disable code checking HI-LO.
1306
1307 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1308 global.
1309 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1310
1311Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1312
1313 * gencode.c (build_mips16_operands): Replace IPC with cia.
1314
1315 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1316 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1317 IPC to `cia'.
1318 (UndefinedResult): Replace function with macro/function
1319 combination.
1320 (sim_engine_run): Don't save PC in IPC.
1321
1322 * sim-main.h (IPC): Delete.
1323
1324
1325 * interp.c (signal_exception, store_word, load_word,
1326 address_translation, load_memory, store_memory, cache_op,
1327 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1328 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1329 current instruction address - cia - argument.
1330 (sim_read, sim_write): Call address_translation directly.
1331 (sim_engine_run): Rename variable vaddr to cia.
1332 (signal_exception): Pass cia to sim_monitor
1333
1334 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1335 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1336 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1337
1338 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1339 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1340 SIM_ASSERT.
1341
1342 * interp.c (signal_exception): Pass restart address to
1343 sim_engine_restart.
1344
1345 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1346 idecode.o): Add dependency.
1347
1348 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1349 Delete definitions
1350 (DELAY_SLOT): Update NIA not PC with branch address.
1351 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1352
1353 * mips.igen: Use CIA not PC in branch calculations.
1354 (illegal): Call SignalException.
1355 (BEQ, ADDIU): Fix assembler.
1356
1357Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1358
1359 * m16.igen (JALX): Was missing.
1360
1361 * configure.in (enable-sim-igen): New configuration option.
1362 * configure: Re-generate.
1363
1364 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1365
1366 * interp.c (load_memory, store_memory): Delete parameter RAW.
1367 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1368 bypassing {load,store}_memory.
1369
1370 * sim-main.h (ByteSwapMem): Delete definition.
1371
1372 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1373
1374 * interp.c (sim_do_command, sim_commands): Delete mips specific
1375 commands. Handled by module sim-options.
1376
1377 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1378 (WITH_MODULO_MEMORY): Define.
1379
1380 * interp.c (sim_info): Delete code printing memory size.
1381
1382 * interp.c (mips_size): Nee sim_size, delete function.
1383 (power2): Delete.
1384 (monitor, monitor_base, monitor_size): Delete global variables.
1385 (sim_open, sim_close): Delete code creating monitor and other
1386 memory regions. Use sim-memopts module, via sim_do_commandf, to
1387 manage memory regions.
1388 (load_memory, store_memory): Use sim-core for memory model.
1389
1390 * interp.c (address_translation): Delete all memory map code
1391 except line forcing 32 bit addresses.
1392
1393Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1394
1395 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1396 trace options.
1397
1398 * interp.c (logfh, logfile): Delete globals.
1399 (sim_open, sim_close): Delete code opening & closing log file.
1400 (mips_option_handler): Delete -l and -n options.
1401 (OPTION mips_options): Ditto.
1402
1403 * interp.c (OPTION mips_options): Rename option trace to dinero.
1404 (mips_option_handler): Update.
1405
1406Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1407
1408 * interp.c (fetch_str): New function.
1409 (sim_monitor): Rewrite using sim_read & sim_write.
1410 (sim_open): Check magic number.
1411 (sim_open): Write monitor vectors into memory using sim_write.
1412 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1413 (sim_read, sim_write): Simplify - transfer data one byte at a
1414 time.
1415 (load_memory, store_memory): Clarify meaning of parameter RAW.
1416
1417 * sim-main.h (isHOST): Defete definition.
1418 (isTARGET): Mark as depreciated.
1419 (address_translation): Delete parameter HOST.
1420
1421 * interp.c (address_translation): Delete parameter HOST.
1422
1423Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1424
1425 * mips.igen:
1426
1427 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1428 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1429
1430Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1431
1432 * mips.igen: Add model filter field to records.
1433
1434Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1435
1436 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1437
1438 interp.c (sim_engine_run): Do not compile function sim_engine_run
1439 when WITH_IGEN == 1.
1440
1441 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1442 target architecture.
1443
1444 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1445 igen. Replace with configuration variables sim_igen_flags /
1446 sim_m16_flags.
1447
1448 * m16.igen: New file. Copy mips16 insns here.
1449 * mips.igen: From here.
1450
1451Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1452
1453 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1454 to top.
1455 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1456
1457Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1458
1459 * gencode.c (build_instruction): Follow sim_write's lead in using
1460 BigEndianMem instead of !ByteSwapMem.
1461
1462Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * configure.in (sim_gen): Dependent on target, select type of
1465 generator. Always select old style generator.
1466
1467 configure: Re-generate.
1468
1469 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1470 targets.
1471 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1472 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1473 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1474 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1475 SIM_@sim_gen@_*, set by autoconf.
1476
1477Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1478
1479 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1480
1481 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1482 CURRENT_FLOATING_POINT instead.
1483
1484 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1485 (address_translation): Raise exception InstructionFetch when
1486 translation fails and isINSTRUCTION.
1487
1488 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1489 sim_engine_run): Change type of of vaddr and paddr to
1490 address_word.
1491 (address_translation, prefetch, load_memory, store_memory,
1492 cache_op): Change type of vAddr and pAddr to address_word.
1493
1494 * gencode.c (build_instruction): Change type of vaddr and paddr to
1495 address_word.
1496
1497Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1498
1499 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1500 macro to obtain result of ALU op.
1501
1502Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1503
1504 * interp.c (sim_info): Call profile_print.
1505
1506Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1507
1508 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1509
1510 * sim-main.h (WITH_PROFILE): Do not define, defined in
1511 common/sim-config.h. Use sim-profile module.
1512 (simPROFILE): Delete defintion.
1513
1514 * interp.c (PROFILE): Delete definition.
1515 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1516 (sim_close): Delete code writing profile histogram.
1517 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1518 Delete.
1519 (sim_engine_run): Delete code profiling the PC.
1520
1521Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1522
1523 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1524
1525 * interp.c (sim_monitor): Make register pointers of type
1526 unsigned_word*.
1527
1528 * sim-main.h: Make registers of type unsigned_word not
1529 signed_word.
1530
1531Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1532
1533 * interp.c (sync_operation): Rename from SyncOperation, make
1534 global, add SD argument.
1535 (prefetch): Rename from Prefetch, make global, add SD argument.
1536 (decode_coproc): Make global.
1537
1538 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1539
1540 * gencode.c (build_instruction): Generate DecodeCoproc not
1541 decode_coproc calls.
1542
1543 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1544 (SizeFGR): Move to sim-main.h
1545 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1546 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1547 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1548 sim-main.h.
1549 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1550 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1551 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1552 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1553 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1554 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1555
1556 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1557 exception.
1558 (sim-alu.h): Include.
1559 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1560 (sim_cia): Typedef to instruction_address.
1561
1562Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1563
1564 * Makefile.in (interp.o): Rename generated file engine.c to
1565 oengine.c.
1566
1567 * interp.c: Update.
1568
1569Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1570
1571 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1572
1573Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1574
1575 * gencode.c (build_instruction): For "FPSQRT", output correct
1576 number of arguments to Recip.
1577
1578Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1579
1580 * Makefile.in (interp.o): Depends on sim-main.h
1581
1582 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1583
1584 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1585 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1586 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1587 STATE, DSSTATE): Define
1588 (GPR, FGRIDX, ..): Define.
1589
1590 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1591 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1592 (GPR, FGRIDX, ...): Delete macros.
1593
1594 * interp.c: Update names to match defines from sim-main.h
1595
1596Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1597
1598 * interp.c (sim_monitor): Add SD argument.
1599 (sim_warning): Delete. Replace calls with calls to
1600 sim_io_eprintf.
1601 (sim_error): Delete. Replace calls with sim_io_error.
1602 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1603 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1604 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1605 argument.
1606 (mips_size): Rename from sim_size. Add SD argument.
1607
1608 * interp.c (simulator): Delete global variable.
1609 (callback): Delete global variable.
1610 (mips_option_handler, sim_open, sim_write, sim_read,
1611 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1612 sim_size,sim_monitor): Use sim_io_* not callback->*.
1613 (sim_open): ZALLOC simulator struct.
1614 (PROFILE): Do not define.
1615
1616Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1617
1618 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1619 support.h with corresponding code.
1620
1621 * sim-main.h (word64, uword64), support.h: Move definition to
1622 sim-main.h.
1623 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1624
1625 * support.h: Delete
1626 * Makefile.in: Update dependencies
1627 * interp.c: Do not include.
1628
1629Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1630
1631 * interp.c (address_translation, load_memory, store_memory,
1632 cache_op): Rename to from AddressTranslation et.al., make global,
1633 add SD argument
1634
1635 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1636 CacheOp): Define.
1637
1638 * interp.c (SignalException): Rename to signal_exception, make
1639 global.
1640
1641 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1642
1643 * sim-main.h (SignalException, SignalExceptionInterrupt,
1644 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1645 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1646 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1647 Define.
1648
1649 * interp.c, support.h: Use.
1650
1651Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1652
1653 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1654 to value_fpr / store_fpr. Add SD argument.
1655 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1656 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1657
1658 * sim-main.h (ValueFPR, StoreFPR): Define.
1659
1660Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1661
1662 * interp.c (sim_engine_run): Check consistency between configure
1663 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1664 and HASFPU.
1665
1666 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1667 (mips_fpu): Configure WITH_FLOATING_POINT.
1668 (mips_endian): Configure WITH_TARGET_ENDIAN.
1669 * configure: Update.
1670
1671Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1672
1673 * configure: Regenerated to track ../common/aclocal.m4 changes.
1674
1675Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1676
1677 * configure: Regenerated.
1678
1679Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1680
1681 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1682
1683Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1684
1685 * gencode.c (print_igen_insn_models): Assume certain architectures
1686 include all mips* instructions.
1687 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1688 instruction.
1689
1690 * Makefile.in (tmp.igen): Add target. Generate igen input from
1691 gencode file.
1692
1693 * gencode.c (FEATURE_IGEN): Define.
1694 (main): Add --igen option. Generate output in igen format.
1695 (process_instructions): Format output according to igen option.
1696 (print_igen_insn_format): New function.
1697 (print_igen_insn_models): New function.
1698 (process_instructions): Only issue warnings and ignore
1699 instructions when no FEATURE_IGEN.
1700
1701Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1702
1703 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1704 MIPS targets.
1705
1706Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1707
1708 * configure: Regenerated to track ../common/aclocal.m4 changes.
1709
1710Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1711
1712 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1713 SIM_RESERVED_BITS): Delete, moved to common.
1714 (SIM_EXTRA_CFLAGS): Update.
1715
1716Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1717
1718 * configure.in: Configure non-strict memory alignment.
1719 * configure: Regenerated to track ../common/aclocal.m4 changes.
1720
1721Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1722
1723 * configure: Regenerated to track ../common/aclocal.m4 changes.
1724
1725Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1726
1727 * gencode.c (SDBBP,DERET): Added (3900) insns.
1728 (RFE): Turn on for 3900.
1729 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1730 (dsstate): Made global.
1731 (SUBTARGET_R3900): Added.
1732 (CANCELDELAYSLOT): New.
1733 (SignalException): Ignore SystemCall rather than ignore and
1734 terminate. Add DebugBreakPoint handling.
1735 (decode_coproc): New insns RFE, DERET; and new registers Debug
1736 and DEPC protected by SUBTARGET_R3900.
1737 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1738 bits explicitly.
1739 * Makefile.in,configure.in: Add mips subtarget option.
1740 * configure: Update.
1741
1742Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1743
1744 * gencode.c: Add r3900 (tx39).
1745
1746
1747Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1748
1749 * gencode.c (build_instruction): Don't need to subtract 4 for
1750 JALR, just 2.
1751
1752Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1753
1754 * interp.c: Correct some HASFPU problems.
1755
1756Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1757
1758 * configure: Regenerated to track ../common/aclocal.m4 changes.
1759
1760Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761
1762 * interp.c (mips_options): Fix samples option short form, should
1763 be `x'.
1764
1765Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1766
1767 * interp.c (sim_info): Enable info code. Was just returning.
1768
1769Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1770
1771 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1772 MFC0.
1773
1774Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1775
1776 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1777 constants.
1778 (build_instruction): Ditto for LL.
1779
1780Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1781
1782 * configure: Regenerated to track ../common/aclocal.m4 changes.
1783
1784Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1785
1786 * configure: Regenerated to track ../common/aclocal.m4 changes.
1787 * config.in: Ditto.
1788
1789Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1790
1791 * interp.c (sim_open): Add call to sim_analyze_program, update
1792 call to sim_config.
1793
1794Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1795
1796 * interp.c (sim_kill): Delete.
1797 (sim_create_inferior): Add ABFD argument. Set PC from same.
1798 (sim_load): Move code initializing trap handlers from here.
1799 (sim_open): To here.
1800 (sim_load): Delete, use sim-hload.c.
1801
1802 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1803
1804Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1805
1806 * configure: Regenerated to track ../common/aclocal.m4 changes.
1807 * config.in: Ditto.
1808
1809Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1810
1811 * interp.c (sim_open): Add ABFD argument.
1812 (sim_load): Move call to sim_config from here.
1813 (sim_open): To here. Check return status.
1814
1815Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1816
1817 * gencode.c (build_instruction): Two arg MADD should
1818 not assign result to $0.
1819
1820Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1821
1822 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1823 * sim/mips/configure.in: Regenerate.
1824
1825Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1826
1827 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1828 signed8, unsigned8 et.al. types.
1829
1830 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1831 hosts when selecting subreg.
1832
1833Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1834
1835 * interp.c (sim_engine_run): Reset the ZERO register to zero
1836 regardless of FEATURE_WARN_ZERO.
1837 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1838
1839Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1840
1841 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1842 (SignalException): For BreakPoints ignore any mode bits and just
1843 save the PC.
1844 (SignalException): Always set the CAUSE register.
1845
1846Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1847
1848 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1849 exception has been taken.
1850
1851 * interp.c: Implement the ERET and mt/f sr instructions.
1852
1853Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * interp.c (SignalException): Don't bother restarting an
1856 interrupt.
1857
1858Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1859
1860 * interp.c (SignalException): Really take an interrupt.
1861 (interrupt_event): Only deliver interrupts when enabled.
1862
1863Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1864
1865 * interp.c (sim_info): Only print info when verbose.
1866 (sim_info) Use sim_io_printf for output.
1867
1868Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1869
1870 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1871 mips architectures.
1872
1873Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1874
1875 * interp.c (sim_do_command): Check for common commands if a
1876 simulator specific command fails.
1877
1878Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1879
1880 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1881 and simBE when DEBUG is defined.
1882
1883Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1884
1885 * interp.c (interrupt_event): New function. Pass exception event
1886 onto exception handler.
1887
1888 * configure.in: Check for stdlib.h.
1889 * configure: Regenerate.
1890
1891 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1892 variable declaration.
1893 (build_instruction): Initialize memval1.
1894 (build_instruction): Add UNUSED attribute to byte, bigend,
1895 reverse.
1896 (build_operands): Ditto.
1897
1898 * interp.c: Fix GCC warnings.
1899 (sim_get_quit_code): Delete.
1900
1901 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1902 * Makefile.in: Ditto.
1903 * configure: Re-generate.
1904
1905 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1906
1907Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1908
1909 * interp.c (mips_option_handler): New function parse argumes using
1910 sim-options.
1911 (myname): Replace with STATE_MY_NAME.
1912 (sim_open): Delete check for host endianness - performed by
1913 sim_config.
1914 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1915 (sim_open): Move much of the initialization from here.
1916 (sim_load): To here. After the image has been loaded and
1917 endianness set.
1918 (sim_open): Move ColdReset from here.
1919 (sim_create_inferior): To here.
1920 (sim_open): Make FP check less dependant on host endianness.
1921
1922 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1923 run.
1924 * interp.c (sim_set_callbacks): Delete.
1925
1926 * interp.c (membank, membank_base, membank_size): Replace with
1927 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1928 (sim_open): Remove call to callback->init. gdb/run do this.
1929
1930 * interp.c: Update
1931
1932 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1933
1934 * interp.c (big_endian_p): Delete, replaced by
1935 current_target_byte_order.
1936
1937Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1938
1939 * interp.c (host_read_long, host_read_word, host_swap_word,
1940 host_swap_long): Delete. Using common sim-endian.
1941 (sim_fetch_register, sim_store_register): Use H2T.
1942 (pipeline_ticks): Delete. Handled by sim-events.
1943 (sim_info): Update.
1944 (sim_engine_run): Update.
1945
1946Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1947
1948 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1949 reason from here.
1950 (SignalException): To here. Signal using sim_engine_halt.
1951 (sim_stop_reason): Delete, moved to common.
1952
1953Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1954
1955 * interp.c (sim_open): Add callback argument.
1956 (sim_set_callbacks): Delete SIM_DESC argument.
1957 (sim_size): Ditto.
1958
1959Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1960
1961 * Makefile.in (SIM_OBJS): Add common modules.
1962
1963 * interp.c (sim_set_callbacks): Also set SD callback.
1964 (set_endianness, xfer_*, swap_*): Delete.
1965 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1966 Change to functions using sim-endian macros.
1967 (control_c, sim_stop): Delete, use common version.
1968 (simulate): Convert into.
1969 (sim_engine_run): This function.
1970 (sim_resume): Delete.
1971
1972 * interp.c (simulation): New variable - the simulator object.
1973 (sim_kind): Delete global - merged into simulation.
1974 (sim_load): Cleanup. Move PC assignment from here.
1975 (sim_create_inferior): To here.
1976
1977 * sim-main.h: New file.
1978 * interp.c (sim-main.h): Include.
1979
1980Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1981
1982 * configure: Regenerated to track ../common/aclocal.m4 changes.
1983
1984Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1985
1986 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1987
1988Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1989
1990 * gencode.c (build_instruction): DIV instructions: check
1991 for division by zero and integer overflow before using
1992 host's division operation.
1993
1994Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1995
1996 * Makefile.in (SIM_OBJS): Add sim-load.o.
1997 * interp.c: #include bfd.h.
1998 (target_byte_order): Delete.
1999 (sim_kind, myname, big_endian_p): New static locals.
2000 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2001 after argument parsing. Recognize -E arg, set endianness accordingly.
2002 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2003 load file into simulator. Set PC from bfd.
2004 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2005 (set_endianness): Use big_endian_p instead of target_byte_order.
2006
2007Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2008
2009 * interp.c (sim_size): Delete prototype - conflicts with
2010 definition in remote-sim.h. Correct definition.
2011
2012Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2013
2014 * configure: Regenerated to track ../common/aclocal.m4 changes.
2015 * config.in: Ditto.
2016
2017Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2018
2019 * interp.c (sim_open): New arg `kind'.
2020
2021 * configure: Regenerated to track ../common/aclocal.m4 changes.
2022
2023Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2024
2025 * configure: Regenerated to track ../common/aclocal.m4 changes.
2026
2027Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2028
2029 * interp.c (sim_open): Set optind to 0 before calling getopt.
2030
2031Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2032
2033 * configure: Regenerated to track ../common/aclocal.m4 changes.
2034
2035Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2036
2037 * interp.c : Replace uses of pr_addr with pr_uword64
2038 where the bit length is always 64 independent of SIM_ADDR.
2039 (pr_uword64) : added.
2040
2041Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2042
2043 * configure: Re-generate.
2044
2045Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2046
2047 * configure: Regenerate to track ../common/aclocal.m4 changes.
2048
2049Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2050
2051 * interp.c (sim_open): New SIM_DESC result. Argument is now
2052 in argv form.
2053 (other sim_*): New SIM_DESC argument.
2054
2055Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2056
2057 * interp.c: Fix printing of addresses for non-64-bit targets.
2058 (pr_addr): Add function to print address based on size.
2059
2060Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2061
2062 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2063
2064Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2065
2066 * gencode.c (build_mips16_operands): Correct computation of base
2067 address for extended PC relative instruction.
2068
2069Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2070
2071 * interp.c (mips16_entry): Add support for floating point cases.
2072 (SignalException): Pass floating point cases to mips16_entry.
2073 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2074 registers.
2075 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2076 or fmt_word.
2077 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2078 and then set the state to fmt_uninterpreted.
2079 (COP_SW): Temporarily set the state to fmt_word while calling
2080 ValueFPR.
2081
2082Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2083
2084 * gencode.c (build_instruction): The high order may be set in the
2085 comparison flags at any ISA level, not just ISA 4.
2086
2087Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2088
2089 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2090 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2091 * configure.in: sinclude ../common/aclocal.m4.
2092 * configure: Regenerated.
2093
2094Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2095
2096 * configure: Rebuild after change to aclocal.m4.
2097
2098Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2099
2100 * configure configure.in Makefile.in: Update to new configure
2101 scheme which is more compatible with WinGDB builds.
2102 * configure.in: Improve comment on how to run autoconf.
2103 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2104 * Makefile.in: Use autoconf substitution to install common
2105 makefile fragment.
2106
2107Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2108
2109 * gencode.c (build_instruction): Use BigEndianCPU instead of
2110 ByteSwapMem.
2111
2112Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2113
2114 * interp.c (sim_monitor): Make output to stdout visible in
2115 wingdb's I/O log window.
2116
2117Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2118
2119 * support.h: Undo previous change to SIGTRAP
2120 and SIGQUIT values.
2121
2122Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2123
2124 * interp.c (store_word, load_word): New static functions.
2125 (mips16_entry): New static function.
2126 (SignalException): Look for mips16 entry and exit instructions.
2127 (simulate): Use the correct index when setting fpr_state after
2128 doing a pending move.
2129
2130Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2131
2132 * interp.c: Fix byte-swapping code throughout to work on
2133 both little- and big-endian hosts.
2134
2135Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2136
2137 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2138 with gdb/config/i386/xm-windows.h.
2139
2140Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2141
2142 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2143 that messes up arithmetic shifts.
2144
2145Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2146
2147 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2148 SIGTRAP and SIGQUIT for _WIN32.
2149
2150Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2151
2152 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2153 force a 64 bit multiplication.
2154 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2155 destination register is 0, since that is the default mips16 nop
2156 instruction.
2157
2158Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2159
2160 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2161 (build_endian_shift): Don't check proc64.
2162 (build_instruction): Always set memval to uword64. Cast op2 to
2163 uword64 when shifting it left in memory instructions. Always use
2164 the same code for stores--don't special case proc64.
2165
2166 * gencode.c (build_mips16_operands): Fix base PC value for PC
2167 relative operands.
2168 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2169 jal instruction.
2170 * interp.c (simJALDELAYSLOT): Define.
2171 (JALDELAYSLOT): Define.
2172 (INDELAYSLOT, INJALDELAYSLOT): Define.
2173 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2174
2175Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2176
2177 * interp.c (sim_open): add flush_cache as a PMON routine
2178 (sim_monitor): handle flush_cache by ignoring it
2179
2180Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2181
2182 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2183 BigEndianMem.
2184 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2185 (BigEndianMem): Rename to ByteSwapMem and change sense.
2186 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2187 BigEndianMem references to !ByteSwapMem.
2188 (set_endianness): New function, with prototype.
2189 (sim_open): Call set_endianness.
2190 (sim_info): Use simBE instead of BigEndianMem.
2191 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2192 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2193 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2194 ifdefs, keeping the prototype declaration.
2195 (swap_word): Rewrite correctly.
2196 (ColdReset): Delete references to CONFIG. Delete endianness related
2197 code; moved to set_endianness.
2198
2199Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2200
2201 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2202 * interp.c (CHECKHILO): Define away.
2203 (simSIGINT): New macro.
2204 (membank_size): Increase from 1MB to 2MB.
2205 (control_c): New function.
2206 (sim_resume): Rename parameter signal to signal_number. Add local
2207 variable prev. Call signal before and after simulate.
2208 (sim_stop_reason): Add simSIGINT support.
2209 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2210 functions always.
2211 (sim_warning): Delete call to SignalException. Do call printf_filtered
2212 if logfh is NULL.
2213 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2214 a call to sim_warning.
2215
2216Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2217
2218 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2219 16 bit instructions.
2220
2221Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2222
2223 Add support for mips16 (16 bit MIPS implementation):
2224 * gencode.c (inst_type): Add mips16 instruction encoding types.
2225 (GETDATASIZEINSN): Define.
2226 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2227 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2228 mtlo.
2229 (MIPS16_DECODE): New table, for mips16 instructions.
2230 (bitmap_val): New static function.
2231 (struct mips16_op): Define.
2232 (mips16_op_table): New table, for mips16 operands.
2233 (build_mips16_operands): New static function.
2234 (process_instructions): If PC is odd, decode a mips16
2235 instruction. Break out instruction handling into new
2236 build_instruction function.
2237 (build_instruction): New static function, broken out of
2238 process_instructions. Check modifiers rather than flags for SHIFT
2239 bit count and m[ft]{hi,lo} direction.
2240 (usage): Pass program name to fprintf.
2241 (main): Remove unused variable this_option_optind. Change
2242 ``*loptarg++'' to ``loptarg++''.
2243 (my_strtoul): Parenthesize && within ||.
2244 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2245 (simulate): If PC is odd, fetch a 16 bit instruction, and
2246 increment PC by 2 rather than 4.
2247 * configure.in: Add case for mips16*-*-*.
2248 * configure: Rebuild.
2249
2250Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2251
2252 * interp.c: Allow -t to enable tracing in standalone simulator.
2253 Fix garbage output in trace file and error messages.
2254
2255Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2256
2257 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2258 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2259 * configure.in: Simplify using macros in ../common/aclocal.m4.
2260 * configure: Regenerated.
2261 * tconfig.in: New file.
2262
2263Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2264
2265 * interp.c: Fix bugs in 64-bit port.
2266 Use ansi function declarations for msvc compiler.
2267 Initialize and test file pointer in trace code.
2268 Prevent duplicate definition of LAST_EMED_REGNUM.
2269
2270Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2271
2272 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2273
2274Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2275
2276 * interp.c (SignalException): Check for explicit terminating
2277 breakpoint value.
2278 * gencode.c: Pass instruction value through SignalException()
2279 calls for Trap, Breakpoint and Syscall.
2280
2281Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2282
2283 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2284 only used on those hosts that provide it.
2285 * configure.in: Add sqrt() to list of functions to be checked for.
2286 * config.in: Re-generated.
2287 * configure: Re-generated.
2288
2289Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2290
2291 * gencode.c (process_instructions): Call build_endian_shift when
2292 expanding STORE RIGHT, to fix swr.
2293 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2294 clear the high bits.
2295 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2296 Fix float to int conversions to produce signed values.
2297
2298Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2299
2300 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2301 (process_instructions): Correct handling of nor instruction.
2302 Correct shift count for 32 bit shift instructions. Correct sign
2303 extension for arithmetic shifts to not shift the number of bits in
2304 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2305 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2306 Fix madd.
2307 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2308 It's OK to have a mult follow a mult. What's not OK is to have a
2309 mult follow an mfhi.
2310 (Convert): Comment out incorrect rounding code.
2311
2312Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2313
2314 * interp.c (sim_monitor): Improved monitor printf
2315 simulation. Tidied up simulator warnings, and added "--log" option
2316 for directing warning message output.
2317 * gencode.c: Use sim_warning() rather than WARNING macro.
2318
2319Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2320
2321 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2322 getopt1.o, rather than on gencode.c. Link objects together.
2323 Don't link against -liberty.
2324 (gencode.o, getopt.o, getopt1.o): New targets.
2325 * gencode.c: Include <ctype.h> and "ansidecl.h".
2326 (AND): Undefine after including "ansidecl.h".
2327 (ULONG_MAX): Define if not defined.
2328 (OP_*): Don't define macros; now defined in opcode/mips.h.
2329 (main): Call my_strtoul rather than strtoul.
2330 (my_strtoul): New static function.
2331
2332Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2333
2334 * gencode.c (process_instructions): Generate word64 and uword64
2335 instead of `long long' and `unsigned long long' data types.
2336 * interp.c: #include sysdep.h to get signals, and define default
2337 for SIGBUS.
2338 * (Convert): Work around for Visual-C++ compiler bug with type
2339 conversion.
2340 * support.h: Make things compile under Visual-C++ by using
2341 __int64 instead of `long long'. Change many refs to long long
2342 into word64/uword64 typedefs.
2343
2344Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2345
2346 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2347 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2348 (docdir): Removed.
2349 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2350 (AC_PROG_INSTALL): Added.
2351 (AC_PROG_CC): Moved to before configure.host call.
2352 * configure: Rebuilt.
2353
2354Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2355
2356 * configure.in: Define @SIMCONF@ depending on mips target.
2357 * configure: Rebuild.
2358 * Makefile.in (run): Add @SIMCONF@ to control simulator
2359 construction.
2360 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2361 * interp.c: Remove some debugging, provide more detailed error
2362 messages, update memory accesses to use LOADDRMASK.
2363
2364Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2365
2366 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2367 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2368 stamp-h.
2369 * configure: Rebuild.
2370 * config.in: New file, generated by autoheader.
2371 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2372 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2373 HAVE_ANINT and HAVE_AINT, as appropriate.
2374 * Makefile.in (run): Use @LIBS@ rather than -lm.
2375 (interp.o): Depend upon config.h.
2376 (Makefile): Just rebuild Makefile.
2377 (clean): Remove stamp-h.
2378 (mostlyclean): Make the same as clean, not as distclean.
2379 (config.h, stamp-h): New targets.
2380
2381Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2382
2383 * interp.c (ColdReset): Fix boolean test. Make all simulator
2384 globals static.
2385
2386Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2387
2388 * interp.c (xfer_direct_word, xfer_direct_long,
2389 swap_direct_word, swap_direct_long, xfer_big_word,
2390 xfer_big_long, xfer_little_word, xfer_little_long,
2391 swap_word,swap_long): Added.
2392 * interp.c (ColdReset): Provide function indirection to
2393 host<->simulated_target transfer routines.
2394 * interp.c (sim_store_register, sim_fetch_register): Updated to
2395 make use of indirected transfer routines.
2396
2397Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2398
2399 * gencode.c (process_instructions): Ensure FP ABS instruction
2400 recognised.
2401 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2402 system call support.
2403
2404Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2405
2406 * interp.c (sim_do_command): Complain if callback structure not
2407 initialised.
2408
2409Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2410
2411 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2412 support for Sun hosts.
2413 * Makefile.in (gencode): Ensure the host compiler and libraries
2414 used for cross-hosted build.
2415
2416Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2417
2418 * interp.c, gencode.c: Some more (TODO) tidying.
2419
2420Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2421
2422 * gencode.c, interp.c: Replaced explicit long long references with
2423 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2424 * support.h (SET64LO, SET64HI): Macros added.
2425
2426Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2427
2428 * configure: Regenerate with autoconf 2.7.
2429
2430Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2431
2432 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2433 * support.h: Remove superfluous "1" from #if.
2434 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2435
2436Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2437
2438 * interp.c (StoreFPR): Control UndefinedResult() call on
2439 WARN_RESULT manifest.
2440
2441Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2442
2443 * gencode.c: Tidied instruction decoding, and added FP instruction
2444 support.
2445
2446 * interp.c: Added dineroIII, and BSD profiling support. Also
2447 run-time FP handling.
2448
2449Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2450
2451 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2452 gencode.c, interp.c, support.h: created.
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