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sim: riscv: move __int128 check to configure
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
79633c12
MF		 12021-05-16 Mike Frysinger <vapier@gentoo.org>
2
3 * config.in, configure: Regenerate.
4
df68e12b
MF		 52021-05-14 Mike Frysinger <vapier@gentoo.org>
6
7 * interp.c: Update include path.
8
77c0fdb7
MF		 92021-05-04 Mike Frysinger <vapier@gentoo.org>
10
11 * dv-tx3904sio.c: Include stdlib.h.
12
9b1af85c
MF		 132021-05-04 Mike Frysinger <vapier@gentoo.org>
14
15 * configure.ac (hw_extra_devices): Inline contents into
16 SIM_AC_OPTION_HARDWARE and delete.
17 * configure: Regenerate.
18
d97ba9c6
MF		 192021-05-04 Mike Frysinger <vapier@gentoo.org>
20
21 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
22 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
23 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
24 * configure: Regenerate.
25
4df817de
MF		 262021-05-04 Mike Frysinger <vapier@gentoo.org>
27
28 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
29
aa0fca16
MF		 302021-05-04 Mike Frysinger <vapier@gentoo.org>
31
32 * configure: Regenerate.
33
adbaa7b8
MF		 342021-05-01 Mike Frysinger <vapier@gentoo.org>
35
36 * cp1.c (store_fcr): Mark static.
37
fe348617
MF		 382021-05-01 Mike Frysinger <vapier@gentoo.org>
39
40 * config.in, configure: Regenerate.
41
9d903352
MF		 422021-04-23 Mike Frysinger <vapier@gentoo.org>
43
44 * configure.ac (hw_enabled): Delete.
45 (SIM_AC_OPTION_HARDWARE): Delete first two args.
46 * configure: Regenerate.
47
19f6a43c
TT		 482021-04-22 Tom Tromey <tom@tromey.com>
49
50 * configure, config.in: Rebuild.
51
e7d8f1da
TT		 522021-04-22 Tom Tromey <tom@tromey.com>
53
54 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
55 Remove.
56 (SIM_EXTRA_DEPS): New variable.
57
efd82ac7
TT		 582021-04-22 Tom Tromey <tom@tromey.com>
59
60 * configure: Rebuild.
61
2662c237
MF		 622021-04-21 Mike Frysinger <vapier@gentoo.org>
63
64 * aclocal.m4: Regenerate.
65
1f195bc3
SM		 662021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
67
68 * configure: Regenerate.
69
37e9f182
MF		 702021-04-18 Mike Frysinger <vapier@gentoo.org>
71
72 * configure: Regenerate.
73
d5a71b11
MF		 742021-04-12 Mike Frysinger <vapier@gentoo.org>
75
76 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
77
2b8d134b
SM		 782021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
79
80 * Makefile.in: Set ASAN_OPTIONS when running igen.
81
5c6f091a
FS		 822021-04-04 Steve Ellcey <sellcey@mips.com>
83 Faraz Shahbazker <fshahbazker@wavecomp.com>
84
85 * interp.c (sim_monitor): Add switch entries for unlink (13),
86 lseek (14), and stat (15).
87
b6b1c790
MF		 882021-04-02 Mike Frysinger <vapier@gentoo.org>
89
90 * Makefile.in (../igen/igen): Delete rule.
91 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
92
c2783492
MF		 932021-04-02 Mike Frysinger <vapier@gentoo.org>
94
95 * aclocal.m4, configure: Regenerate.
96
ebe9564b
MF		 972021-02-28 Mike Frysinger <vapier@gentoo.org>
98
99 * configure: Regenerate.
100
f8069d55
MF		 1012021-02-27 Mike Frysinger <vapier@gentoo.org>
102
103 * Makefile.in (SIM_EXTRA_ALL): Delete.
104 (all): New target.
105
760b3e8b
MF		 1062021-02-21 Mike Frysinger <vapier@gentoo.org>
107
108 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
109 * aclocal.m4, configure: Regenerate.
110
136da8cd
MF		 1112021-02-13 Mike Frysinger <vapier@gentoo.org>
112
113 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
114 * aclocal.m4, configure: Regenerate.
115
4c0d76b9
MF		 1162021-02-06 Mike Frysinger <vapier@gentoo.org>
117
118 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
119
aa09469f
MF		 1202021-02-06 Mike Frysinger <vapier@gentoo.org>
121
122 * configure: Regenerate.
123
d4e3adda
MF		 1242021-01-30 Mike Frysinger <vapier@gentoo.org>
125
126 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
127
68ed2854
MF		 1282021-01-11 Mike Frysinger <vapier@gentoo.org>
129
130 * config.in, configure: Regenerate.
131 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
132 and strings.h include.
133
50df264d
MF		 1342021-01-09 Mike Frysinger <vapier@gentoo.org>
135
136 * configure: Regenerate.
137
bf470982
MF		 1382021-01-09 Mike Frysinger <vapier@gentoo.org>
139
140 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
141 * configure: Regenerate.
142
46f900c0
MF		 1432021-01-08 Mike Frysinger <vapier@gentoo.org>
144
145 * configure: Regenerate.
146
dfb856ba
MF		 1472021-01-04 Mike Frysinger <vapier@gentoo.org>
148
149 * configure: Regenerate.
150
382bc56b
PK		 1512020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
152
153 * sim-main.c: Include <stdlib.h>.
154
ad9675dd
PK		 1552020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
156
157 * cp1.c: Include <stdlib.h>.
158
f693213d
SM		 1592020-07-29 Simon Marchi <simon.marchi@efficios.com>
160
161 * configure: Re-generate.
162
5c887dd5
JB		 1632017-09-06 John Baldwin <jhb@FreeBSD.org>
164
165 * configure: Regenerate.
166
91588b3a
MF		 1672016-11-11 Mike Frysinger <vapier@gentoo.org>
168
6cb2202b 169 PR sim/20808
91588b3a
MF		 170 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
171 and SD to sd.
172
e04659e8
MF		 1732016-11-11 Mike Frysinger <vapier@gentoo.org>
174
6cb2202b 175 PR sim/20809
e04659e8
MF		 176 * mips.igen (check_u64): Enable for `r3900'.
177
1554f758
MF		 1782016-02-05 Mike Frysinger <vapier@gentoo.org>
179
180 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
181 STATE_PROG_BFD (sd).
182 * configure: Regenerate.
183
3d304f48
AB		 1842016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
185 Maciej W. Rozycki <macro@imgtec.com>
186
187 PR sim/19441
188 * micromips.igen (delayslot_micromips): Enable for `micromips32',
189 `micromips64' and `micromipsdsp' only.
190 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
191 (do_micromips_jalr, do_micromips_jal): Likewise.
192 (compute_movep_src_reg): Likewise.
193 (compute_andi16_imm): Likewise.
194 (convert_fmt_micromips): Likewise.
195 (convert_fmt_micromips_cvt_d): Likewise.
196 (convert_fmt_micromips_cvt_s): Likewise.
197 (FMT_MICROMIPS): Likewise.
198 (FMT_MICROMIPS_CVT_D): Likewise.
199 (FMT_MICROMIPS_CVT_S): Likewise.
200
b36d953b
MF		 2012016-01-12 Mike Frysinger <vapier@gentoo.org>
202
203 * interp.c: Include elf-bfd.h.
204 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
205 ELFCLASS32.
206
ce39bd38
MF		 2072016-01-10 Mike Frysinger <vapier@gentoo.org>
208
209 * config.in, configure: Regenerate.
210
99d8e879
MF		 2112016-01-10 Mike Frysinger <vapier@gentoo.org>
212
213 * configure: Regenerate.
214
35656e95
MF		 2152016-01-10 Mike Frysinger <vapier@gentoo.org>
216
217 * configure: Regenerate.
218
16f7876d
MF		 2192016-01-10 Mike Frysinger <vapier@gentoo.org>
220
221 * configure: Regenerate.
222
e19418e0
MF		 2232016-01-10 Mike Frysinger <vapier@gentoo.org>
224
225 * configure: Regenerate.
226
6d90347b
MF		 2272016-01-10 Mike Frysinger <vapier@gentoo.org>
228
229 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
230 * configure: Regenerate.
231
347fe5bb
MF		 2322016-01-10 Mike Frysinger <vapier@gentoo.org>
233
234 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
235 * configure: Regenerate.
236
22be3fbe
MF		 2372016-01-10 Mike Frysinger <vapier@gentoo.org>
238
239 * configure: Regenerate.
240
0dc73ef7
MF		 2412016-01-10 Mike Frysinger <vapier@gentoo.org>
242
243 * configure: Regenerate.
244
936df756
MF		 2452016-01-09 Mike Frysinger <vapier@gentoo.org>
246
247 * config.in, configure: Regenerate.
248
2e3d4f4d
MF		 2492016-01-06 Mike Frysinger <vapier@gentoo.org>
250
251 * interp.c (sim_open): Mark argv const.
252 (sim_create_inferior): Mark argv and env const.
253
9bbf6f91
MF		 2542016-01-04 Mike Frysinger <vapier@gentoo.org>
255
256 * configure: Regenerate.
257
77cf2ef5
MF		 2582016-01-03 Mike Frysinger <vapier@gentoo.org>
259
260 * interp.c (sim_open): Update sim_parse_args comment.
261
0cb8d851
MF		 2622016-01-03 Mike Frysinger <vapier@gentoo.org>
263
264 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
265 * configure: Regenerate.
266
1ac72f06
MF		 2672016-01-02 Mike Frysinger <vapier@gentoo.org>
268
269 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
270 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
271 * configure: Regenerate.
272 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
273
d47f5b30
MF		 2742016-01-02 Mike Frysinger <vapier@gentoo.org>
275
276 * dv-tx3904cpu.c (CPU, SD): Delete.
277
e1211e55
MF		 2782015-12-30 Mike Frysinger <vapier@gentoo.org>
279
280 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
281 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
282 (sim_store_register): Rename to ...
283 (mips_reg_store): ... this. Delete local cpu var.
284 Update sim_io_eprintf calls.
285 (sim_fetch_register): Rename to ...
286 (mips_reg_fetch): ... this. Delete local cpu var.
287 Update sim_io_eprintf calls.
288
5e744ef8
MF		 2892015-12-27 Mike Frysinger <vapier@gentoo.org>
290
291 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
292
1b393626
MF		 2932015-12-26 Mike Frysinger <vapier@gentoo.org>
294
295 * config.in, configure: Regenerate.
296
26f8bf63
MF		 2972015-12-26 Mike Frysinger <vapier@gentoo.org>
298
299 * interp.c (sim_write, sim_read): Delete.
300 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
301 (load_word): Likewise.
302 * micromips.igen (cache): Likewise.
303 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
304 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
305 do_store_left, do_store_right, do_load_double, do_store_double):
306 Likewise.
307 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
308 (do_prefx): Likewise.
309 * sim-main.c (address_translation, prefetch): Delete.
310 (ifetch32, ifetch16): Delete call to AddressTranslation and set
311 paddr=vaddr.
312 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
313 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
314 (LoadMemory, StoreMemory): Delete CCA arg.
315
ef04e371
MF		 3162015-12-24 Mike Frysinger <vapier@gentoo.org>
317
318 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
319 * configure: Regenerated.
320
cb379ede
MF		 3212015-12-24 Mike Frysinger <vapier@gentoo.org>
322
323 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
324 * tconfig.h: Delete.
325
26936211
MF		 3262015-12-24 Mike Frysinger <vapier@gentoo.org>
327
328 * tconfig.h (SIM_HANDLES_LMA): Delete.
329
84e8e361
MF		 3302015-12-24 Mike Frysinger <vapier@gentoo.org>
331
332 * sim-main.h (WITH_WATCHPOINTS): Delete.
333
3cabaf66
MF		 3342015-12-24 Mike Frysinger <vapier@gentoo.org>
335
336 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
337
8abe6c66
MF		 3382015-12-24 Mike Frysinger <vapier@gentoo.org>
339
340 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
341
1d19cae7
DV		 3422015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
343
344 * micromips.igen (process_isa_mode): Fix left shift of negative
345 value.
346
cdf850e9
MF		 3472015-11-17 Mike Frysinger <vapier@gentoo.org>
348
349 * sim-main.h (WITH_MODULO_MEMORY): Delete.
350
797eee42
MF		 3512015-11-15 Mike Frysinger <vapier@gentoo.org>
352
353 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
354
6e4f085c
MF		 3552015-11-14 Mike Frysinger <vapier@gentoo.org>
356
357 * interp.c (sim_close): Rename to ...
358 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
359 sim_io_shutdown.
360 * sim-main.h (mips_sim_close): Declare.
361 (SIM_CLOSE_HOOK): Define.
362
8e394ffc
AB		 3632015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
364 Ali Lown <ali.lown@imgtec.com>
365
366 * Makefile.in (tmp-micromips): New rule.
367 (tmp-mach-multi): Add support for micromips.
368 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
369 that works for both mips64 and micromips64.
370 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
371 micromips32.
372 Add build support for micromips.
373 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
374 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
375 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
376 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
377 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
378 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
379 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
380 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
381 Refactored instruction code to use these functions.
382 * dsp2.igen: Refactored instruction code to use the new functions.
383 * interp.c (decode_coproc): Refactored to work with any instruction
384 encoding.
385 (isa_mode): New variable
386 (RSVD_INSTRUCTION): Changed to 0x00000039.
387 * m16.igen (BREAK16): Refactored instruction to use do_break16.
388 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
389 * micromips.dc: New file.
390 * micromips.igen: New file.
391 * micromips16.dc: New file.
392 * micromipsdsp.igen: New file.
393 * micromipsrun.c: New file.
394 * mips.igen (do_swc1): Changed to work with any instruction encoding.
395 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
396 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
397 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
398 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
399 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
400 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
401 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
402 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
403 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
404 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
405 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
406 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
407 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
408 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
409 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
410 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
411 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
412 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
413 instructions.
414 Refactored instruction code to use these functions.
415 (RSVD): Changed to use new reserved instruction.
416 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
417 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
418 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
419 do_store_double): Added micromips32 and micromips64 models.
420 Added include for micromips.igen and micromipsdsp.igen
421 Add micromips32 and micromips64 models.
422 (DecodeCoproc): Updated to use new macro definition.
423 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
424 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
425 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
426 Refactored instruction code to use these functions.
427 * sim-main.h (CP0_operation): New enum.
428 (DecodeCoproc): Updated macro.
429 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
430 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
431 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
432 ISA_MODE_MICROMIPS): New defines.
433 (sim_state): Add isa_mode field.
434
8d0978fb
MF		 4352015-06-23 Mike Frysinger <vapier@gentoo.org>
436
437 * configure: Regenerate.
438
306f4178
MF		 4392015-06-12 Mike Frysinger <vapier@gentoo.org>
440
441 * configure.ac: Change configure.in to configure.ac.
442 * configure: Regenerate.
443
a3487082
MF		 4442015-06-12 Mike Frysinger <vapier@gentoo.org>
445
446 * configure: Regenerate.
447
29bc024d
MF		 4482015-06-12 Mike Frysinger <vapier@gentoo.org>
449
450 * interp.c [TRACE]: Delete.
451 (TRACE): Change to WITH_TRACE_ANY_P.
452 [!WITH_TRACE_ANY_P] (open_trace): Define.
453 (mips_option_handler, open_trace, sim_close, dotrace):
454 Change defined(TRACE) to WITH_TRACE_ANY_P.
455 (sim_open): Delete TRACE ifdef check.
456 * sim-main.c (load_memory): Delete TRACE ifdef check.
457 (store_memory): Likewise.
458 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
459 [!WITH_TRACE_ANY_P] (dotrace): Define.
460
3ebe2863
MF		 4612015-04-18 Mike Frysinger <vapier@gentoo.org>
462
463 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
464 comments.
465
20bca71d
MF		 4662015-04-18 Mike Frysinger <vapier@gentoo.org>
467
468 * sim-main.h (SIM_CPU): Delete.
469
7e83aa92
MF		 4702015-04-18 Mike Frysinger <vapier@gentoo.org>
471
472 * sim-main.h (sim_cia): Delete.
473
034685f9
MF		 4742015-04-17 Mike Frysinger <vapier@gentoo.org>
475
476 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
477 PU_PC_GET.
478 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
479 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
480 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
481 CIA_SET to CPU_PC_SET.
482 * sim-main.h (CIA_GET, CIA_SET): Delete.
483
78e9aa70
MF		 4842015-04-15 Mike Frysinger <vapier@gentoo.org>
485
486 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
487 * sim-main.h (STATE_CPU): Delete.
488
bf12d44e
MF		 4892015-04-13 Mike Frysinger <vapier@gentoo.org>
490
491 * configure: Regenerate.
492
7bebb329
MF		 4932015-04-13 Mike Frysinger <vapier@gentoo.org>
494
495 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
496 * interp.c (mips_pc_get, mips_pc_set): New functions.
497 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
498 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
499 (sim_pc_get): Delete.
500 * sim-main.h (SIM_CPU): Define.
501 (struct sim_state): Change cpu to an array of pointers.
502 (STATE_CPU): Drop &.
503
8ac57fbd
MF		 5042015-04-13 Mike Frysinger <vapier@gentoo.org>
505
506 * interp.c (mips_option_handler, open_trace, sim_close,
507 sim_write, sim_read, sim_store_register, sim_fetch_register,
508 sim_create_inferior, pr_addr, pr_uword64): Convert old style
509 prototypes.
510 (sim_open): Convert old style prototype. Change casts with
511 sim_write to unsigned char *.
512 (fetch_str): Change null to unsigned char, and change cast to
513 unsigned char *.
514 (sim_monitor): Change c & ch to unsigned char. Change cast to
515 unsigned char *.
516
e787f858
MF		 5172015-04-12 Mike Frysinger <vapier@gentoo.org>
518
519 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
520
122bbfb5
MF		 5212015-04-06 Mike Frysinger <vapier@gentoo.org>
522
523 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
524
0fe84f3f
MF		 5252015-04-01 Mike Frysinger <vapier@gentoo.org>
526
527 * tconfig.h (SIM_HAVE_PROFILE): Delete.
528
aadc9410
MF		 5292015-03-31 Mike Frysinger <vapier@gentoo.org>
530
531 * config.in, configure: Regenerate.
532
05f53ed6
MF		 5332015-03-24 Mike Frysinger <vapier@gentoo.org>
534
535 * interp.c (sim_pc_get): New function.
536
c0931f26
MF		 5372015-03-24 Mike Frysinger <vapier@gentoo.org>
538
539 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
540 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
541
30452bbe
MF		 5422015-03-24 Mike Frysinger <vapier@gentoo.org>
543
544 * configure: Regenerate.
545
64dd13df
MF		 5462015-03-23 Mike Frysinger <vapier@gentoo.org>
547
548 * configure: Regenerate.
549
49cd1634
MF		 5502015-03-23 Mike Frysinger <vapier@gentoo.org>
551
552 * configure: Regenerate.
553 * configure.ac (mips_extra_objs): Delete.
554 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
555 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
556
3649cb06
MF		 5572015-03-23 Mike Frysinger <vapier@gentoo.org>
558
559 * configure: Regenerate.
560 * configure.ac: Delete sim_hw checks for dv-sockser.
561
ae7d0cac
MF		 5622015-03-16 Mike Frysinger <vapier@gentoo.org>
563
564 * config.in, configure: Regenerate.
565 * tconfig.in: Rename file ...
566 * tconfig.h: ... here.
567
8406bb59
MF		 5682015-03-15 Mike Frysinger <vapier@gentoo.org>
569
570 * tconfig.in: Delete includes.
571 [HAVE_DV_SOCKSER]: Delete.
572
465fb143
MF		 5732015-03-14 Mike Frysinger <vapier@gentoo.org>
574
575 * Makefile.in (SIM_RUN_OBJS): Delete.
576
5cddc23a
MF		 5772015-03-14 Mike Frysinger <vapier@gentoo.org>
578
579 * configure.ac (AC_CHECK_HEADERS): Delete.
580 * aclocal.m4, configure: Regenerate.
581
2974be62
AM		 5822014-08-19 Alan Modra <amodra@gmail.com>
583
584 * configure: Regenerate.
585
faa743bb
RM		 5862014-08-15 Roland McGrath <mcgrathr@google.com>
587
588 * configure: Regenerate.
589 * config.in: Regenerate.
590
1a8a700e
MF		 5912014-03-04 Mike Frysinger <vapier@gentoo.org>
592
593 * configure: Regenerate.
594
bf3d9781
AM		 5952013-09-23 Alan Modra <amodra@gmail.com>
596
597 * configure: Regenerate.
598
31e6ad7d
MF		 5992013-06-03 Mike Frysinger <vapier@gentoo.org>
600
601 * aclocal.m4, configure: Regenerate.
602
d3685d60
TT		 6032013-05-10 Freddie Chopin <freddie_chopin@op.pl>
604
605 * configure: Rebuild.
606
1517bd27
MF		 6072013-03-26 Mike Frysinger <vapier@gentoo.org>
608
609 * configure: Regenerate.
610
3be31516
JS		 6112013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
612
613 * configure.ac: Address use of dv-sockser.o.
614 * tconfig.in: Conditionalize use of dv_sockser_install.
615 * configure: Regenerated.
616 * config.in: Regenerated.
617
37cb8f8e
SE		 6182012-10-04 Chao-ying Fu <fu@mips.com>
619 Steve Ellcey <sellcey@mips.com>
620
621 * mips/mips3264r2.igen (rdhwr): New.
622
87c8644f
JS		 6232012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
624
625 * configure.ac: Always link against dv-sockser.o.
626 * configure: Regenerate.
627
5f3ef9d0
JB		 6282012-06-15 Joel Brobecker <brobecker@adacore.com>
629
630 * config.in, configure: Regenerate.
631
a6ff997c
NC		 6322012-05-18 Nick Clifton <nickc@redhat.com>
633
634 PR 14072
635 * interp.c: Include config.h before system header files.
636
2232061b
MF		 6372012-03-24 Mike Frysinger <vapier@gentoo.org>
638
639 * aclocal.m4, config.in, configure: Regenerate.
640
db2e4d67
MF		 6412011-12-03 Mike Frysinger <vapier@gentoo.org>
642
643 * aclocal.m4: New file.
644 * configure: Regenerate.
645
4399a56b
MF		 6462011-10-19 Mike Frysinger <vapier@gentoo.org>
647
648 * configure: Regenerate after common/acinclude.m4 update.
649
9c082ca8
MF		 6502011-10-17 Mike Frysinger <vapier@gentoo.org>
651
652 * configure.ac: Change include to common/acinclude.m4.
653
6ffe910a
MF		 6542011-10-17 Mike Frysinger <vapier@gentoo.org>
655
656 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
657 call. Replace common.m4 include with SIM_AC_COMMON.
658 * configure: Regenerate.
659
31b28250
HPN		 6602011-07-08 Hans-Peter Nilsson <hp@axis.com>
661
3faa01e3
HPN		 662 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
663 $(SIM_EXTRA_DEPS).
664 (tmp-mach-multi): Exit early when igen fails.
31b28250 665
2419798b
MF		 6662011-07-05 Mike Frysinger <vapier@gentoo.org>
667
668 * interp.c (sim_do_command): Delete.
669
d79fe0d6
MF		 6702011-02-14 Mike Frysinger <vapier@gentoo.org>
671
672 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
673 (tx3904sio_fifo_reset): Likewise.
674 * interp.c (sim_monitor): Likewise.
675
5558e7e6
MF		 6762010-04-14 Mike Frysinger <vapier@gentoo.org>
677
678 * interp.c (sim_write): Add const to buffer arg.
679
35aafff4
JB		 6802010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
681
682 * interp.c: Don't include sysdep.h
683
3725885a
RW		 6842010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
685
686 * configure: Regenerate.
687
d6416cdc
RW		 6882009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
689
81ecdfbb
RW		 690 * config.in: Regenerate.
691 * configure: Likewise.
692
d6416cdc
RW		 693 * configure: Regenerate.
694
b5bd9624
HPN		 6952008-07-11 Hans-Peter Nilsson <hp@axis.com>
696
697 * configure: Regenerate to track ../common/common.m4 changes.
698 * config.in: Ditto.
699
6efef468 7002008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 701 Daniel Jacobowitz <dan@codesourcery.com>
702 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 703
704 * configure: Regenerate.
705
60dc88db
RS		 7062007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
707
708 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
709 that unconditionally allows fmt_ps.
710 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
711 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
712 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
713 filter from 64,f to 32,f.
714 (PREFX): Change filter from 64 to 32.
715 (LDXC1, LUXC1): Provide separate mips32r2 implementations
716 that use do_load_double instead of do_load. Make both LUXC1
717 versions unpredictable if SizeFGR () != 64.
718 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
719 instead of do_store. Remove unused variable. Make both SUXC1
720 versions unpredictable if SizeFGR () != 64.
721
599ca73e
RS		 7222007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
723
724 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
725 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
726 shifts for that case.
727
2525df03
NC		 7282007-09-04 Nick Clifton <nickc@redhat.com>
729
730 * interp.c (options enum): Add OPTION_INFO_MEMORY.
731 (display_mem_info): New static variable.
732 (mips_option_handler): Handle OPTION_INFO_MEMORY.
733 (mips_options): Add info-memory and memory-info.
734 (sim_open): After processing the command line and board
735 specification, check display_mem_info. If it is set then
736 call the real handler for the --memory-info command line
737 switch.
738
35ee6e1e
JB		 7392007-08-24 Joel Brobecker <brobecker@adacore.com>
740
741 * configure.ac: Change license of multi-run.c to GPL version 3.
742 * configure: Regenerate.
743
d5fb0879
RS		 7442007-06-28 Richard Sandiford <richard@codesourcery.com>
745
746 * configure.ac, configure: Revert last patch.
747
2a2ce21b
RS		 7482007-06-26 Richard Sandiford <richard@codesourcery.com>
749
750 * configure.ac (sim_mipsisa3264_configs): New variable.
751 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
752 every configuration support all four targets, using the triplet to
753 determine the default.
754 * configure: Regenerate.
755
efdcccc9
RS		 7562007-06-25 Richard Sandiford <richard@codesourcery.com>
757
0a7692b2 758 * Makefile.in (m16run.o): New rule.
efdcccc9 759
f532a356
TS		 7602007-05-15 Thiemo Seufer <ths@mips.com>
761
762 * mips3264r2.igen (DSHD): Fix compile warning.
763
bfe9c90b
TS		 7642007-05-14 Thiemo Seufer <ths@mips.com>
765
766 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
767 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
768 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
769 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
770 for mips32r2.
771
53f4826b
TS		 7722007-03-01 Thiemo Seufer <ths@mips.com>
773
774 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
775 and mips64.
776
8bf3ddc8
TS		 7772007-02-20 Thiemo Seufer <ths@mips.com>
778
779 * dsp.igen: Update copyright notice.
780 * dsp2.igen: Fix copyright notice.
781
8b082fb1 7822007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 783 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 784
785 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
786 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
787 Add dsp2 to sim_igen_machine.
788 * configure: Regenerate.
789 * dsp.igen (do_ph_op): Add MUL support when op = 2.
790 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
791 (mulq_rs.ph): Use do_ph_mulq.
792 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
793 * mips.igen: Add dsp2 model and include dsp2.igen.
794 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
795 for *mips32r2, *mips64r2, *dsp.
796 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
797 for *mips32r2, *mips64r2, *dsp2.
798 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
799
b1004875 8002007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 801 Nigel Stephens <nigel@mips.com>
b1004875
TS		 802
803 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
804 jumps with hazard barrier.
805
f8df4c77 8062007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 807 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 808
809 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
810 after each call to sim_io_write.
811
b1004875 8122007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 813 Nigel Stephens <nigel@mips.com>
b1004875
TS		 814
815 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
816 supported by this simulator.
07802d98
TS		 817 (decode_coproc): Recognise additional CP0 Config registers
818 correctly.
819
14fb6c5a 8202007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 821 Nigel Stephens <nigel@mips.com>
822 David Ung <davidu@mips.com>
14fb6c5a
TS		 823
824 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
825 uninterpreted formats. If fmt is one of the uninterpreted types
826 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
827 fmt_word, and fmt_uninterpreted_64 like fmt_long.
828 (store_fpr): When writing an invalid odd register, set the
829 matching even register to fmt_unknown, not the following register.
830 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
831 the the memory window at offset 0 set by --memory-size command
832 line option.
833 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
834 point register.
835 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
836 register.
837 (sim_monitor): When returning the memory size to the MIPS
838 application, use the value in STATE_MEM_SIZE, not an arbitrary
839 hardcoded value.
840 (cop_lw): Don' mess around with FPR_STATE, just pass
841 fmt_uninterpreted_32 to StoreFPR.
842 (cop_sw): Similarly.
843 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
844 (cop_sd): Similarly.
845 * mips.igen (not_word_value): Single version for mips32, mips64
846 and mips16.
847
c8847145 8482007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 849 Nigel Stephens <nigel@mips.com>
c8847145
TS		 850
851 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
852 MBytes.
853
4b5d35ee
TS		 8542007-02-17 Thiemo Seufer <ths@mips.com>
855
856 * configure.ac (mips*-sde-elf*): Move in front of generic machine
857 configuration.
858 * configure: Regenerate.
859
3669427c
TS		 8602007-02-17 Thiemo Seufer <ths@mips.com>
861
862 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
863 Add mdmx to sim_igen_machine.
864 (mipsisa64*-*-*): Likewise. Remove dsp.
865 (mipsisa32*-*-*): Remove dsp.
866 * configure: Regenerate.
867
109ad085
TS		 8682007-02-13 Thiemo Seufer <ths@mips.com>
869
870 * configure.ac: Add mips*-sde-elf* target.
871 * configure: Regenerate.
872
921d7ad3
HPN		 8732006-12-21 Hans-Peter Nilsson <hp@axis.com>
874
875 * acconfig.h: Remove.
876 * config.in, configure: Regenerate.
877
02f97da7
TS		 8782006-11-07 Thiemo Seufer <ths@mips.com>
879
880 * dsp.igen (do_w_op): Fix compiler warning.
881
2d2733fc 8822006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 883 David Ung <davidu@mips.com>
2d2733fc
TS		 884
885 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
886 sim_igen_machine.
887 * configure: Regenerate.
888 * mips.igen (model): Add smartmips.
889 (MADDU): Increment ACX if carry.
890 (do_mult): Clear ACX.
891 (ROR,RORV): Add smartmips.
72f4393d 892 (include): Include smartmips.igen.
2d2733fc
TS		 893 * sim-main.h (ACX): Set to REGISTERS[89].
894 * smartmips.igen: New file.
895
d85c3a10 8962006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 897 David Ung <davidu@mips.com>
d85c3a10
TS		 898
899 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
900 mips3264r2.igen. Add missing dependency rules.
901 * m16e.igen: Support for mips16e save/restore instructions.
902
e85e3205
RE		 9032006-06-13 Richard Earnshaw <rearnsha@arm.com>
904
905 * configure: Regenerated.
906
2f0122dc
DJ		 9072006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
908
909 * configure: Regenerated.
910
20e95c23
DJ		 9112006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
912
913 * configure: Regenerated.
914
69088b17
CF		 9152006-05-15 Chao-ying Fu <fu@mips.com>
916
917 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
918
0275de4e
NC		 9192006-04-18 Nick Clifton <nickc@redhat.com>
920
921 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
922 statement.
923
b3a3ffef
HPN		 9242006-03-29 Hans-Peter Nilsson <hp@axis.com>
925
926 * configure: Regenerate.
927
40a5538e
CF		 9282005-12-14 Chao-ying Fu <fu@mips.com>
929
930 * Makefile.in (SIM_OBJS): Add dsp.o.
931 (dsp.o): New dependency.
932 (IGEN_INCLUDE): Add dsp.igen.
933 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
934 mipsisa64*-*-*): Add dsp to sim_igen_machine.
935 * configure: Regenerate.
936 * mips.igen: Add dsp model and include dsp.igen.
937 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
938 because these instructions are extended in DSP ASE.
939 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
940 adding 6 DSP accumulator registers and 1 DSP control register.
941 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
942 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
943 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
944 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
945 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
946 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
947 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
948 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
949 DSPCR_CCOND_SMASK): New define.
950 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
951 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
952
21d14896
ILT		 9532005-07-08 Ian Lance Taylor <ian@airs.com>
954
955 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
956
b16d63da 9572005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 958 Nigel Stephens <nigel@mips.com>
959
960 * mips.igen: New mips16e model and include m16e.igen.
961 (check_u64): Add mips16e tag.
962 * m16e.igen: New file for MIPS16e instructions.
963 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
964 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
965 models.
966 * configure: Regenerate.
b16d63da 967
e70cb6cd 9682005-05-26 David Ung <davidu@mips.com>
72f4393d 969
e70cb6cd
CD		 970 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
971 tags to all instructions which are applicable to the new ISAs.
972 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
973 vr.igen.
974 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 975 instructions.
e70cb6cd
CD		 976 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
977 to mips.igen.
978 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
979 * configure: Regenerate.
72f4393d 980
2b193c4a
MK		 9812005-03-23 Mark Kettenis <kettenis@gnu.org>
982
983 * configure: Regenerate.
984
35695fd6
AC		 9852005-01-14 Andrew Cagney <cagney@gnu.org>
986
987 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
988 explicit call to AC_CONFIG_HEADER.
989 * configure: Regenerate.
990
f0569246
AC		 9912005-01-12 Andrew Cagney <cagney@gnu.org>
992
993 * configure.ac: Update to use ../common/common.m4.
994 * configure: Re-generate.
995
38f48d72
AC		 9962005-01-11 Andrew Cagney <cagney@localhost.localdomain>
997
998 * configure: Regenerated to track ../common/aclocal.m4 changes.
999
b7026657
AC		 10002005-01-07 Andrew Cagney <cagney@gnu.org>
1001
1002 * configure.ac: Rename configure.in, require autoconf 2.59.
1003 * configure: Re-generate.
1004
379832de
HPN		 10052004-12-08 Hans-Peter Nilsson <hp@axis.com>
1006
1007 * configure: Regenerate for ../common/aclocal.m4 update.
1008
cd62154c 10092004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1010
cd62154c
AC		 1011 Committed by Andrew Cagney.
1012 * m16.igen (CMP, CMPI): Fix assembler.
1013
e5da76ec
CD		 10142004-08-18 Chris Demetriou <cgd@broadcom.com>
1015
1016 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1017 * configure: Regenerate.
1018
139181c8
CD		 10192004-06-25 Chris Demetriou <cgd@broadcom.com>
1020
1021 * configure.in (sim_m16_machine): Include mipsIII.
1022 * configure: Regenerate.
1023
1a27f959
CD		 10242004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1025
72f4393d 1026 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1027 from COP0_BADVADDR.
1028 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1029
5dbb7b5a
CD		 10302004-04-10 Chris Demetriou <cgd@broadcom.com>
1031
1032 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1033
14234056
CD		 10342004-04-09 Chris Demetriou <cgd@broadcom.com>
1035
1036 * mips.igen (check_fmt): Remove.
1037 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1038 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1039 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1040 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1041 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1042 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1043 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1044 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1045 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1046 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1047
c6f9085c
CD		 10482004-04-09 Chris Demetriou <cgd@broadcom.com>
1049
1050 * sb1.igen (check_sbx): New function.
1051 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1052
11d66e66 10532004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1054 Richard Sandiford <rsandifo@redhat.com>
1055
1056 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1057 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1058 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1059 separate implementations for mipsIV and mipsV. Use new macros to
1060 determine whether the restrictions apply.
1061
b3208fb8
CD		 10622004-01-19 Chris Demetriou <cgd@broadcom.com>
1063
1064 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1065 (check_mult_hilo): Improve comments.
1066 (check_div_hilo): Likewise. Also, fork off a new version
1067 to handle mips32/mips64 (since there are no hazards to check
1068 in MIPS32/MIPS64).
1069
9a1d84fb
CD		 10702003-06-17 Richard Sandiford <rsandifo@redhat.com>
1071
1072 * mips.igen (do_dmultx): Fix check for negative operands.
1073
ae451ac6
ILT		 10742003-05-16 Ian Lance Taylor <ian@airs.com>
1075
1076 * Makefile.in (SHELL): Make sure this is defined.
1077 (various): Use $(SHELL) whenever we invoke move-if-change.
1078
dd69d292
CD		 10792003-05-03 Chris Demetriou <cgd@broadcom.com>
1080
1081 * cp1.c: Tweak attribution slightly.
1082 * cp1.h: Likewise.
1083 * mdmx.c: Likewise.
1084 * mdmx.igen: Likewise.
1085 * mips3d.igen: Likewise.
1086 * sb1.igen: Likewise.
1087
bcd0068e
CD		 10882003-04-15 Richard Sandiford <rsandifo@redhat.com>
1089
1090 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1091 unsigned operands.
1092
6b4a8935
AC		 10932003-02-27 Andrew Cagney <cagney@redhat.com>
1094
601da316
AC		 1095 * interp.c (sim_open): Rename _bfd to bfd.
1096 (sim_create_inferior): Ditto.
6b4a8935 1097
d29e330f
CD		 10982003-01-14 Chris Demetriou <cgd@broadcom.com>
1099
1100 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1101
a2353a08
CD		 11022003-01-14 Chris Demetriou <cgd@broadcom.com>
1103
1104 * mips.igen (EI, DI): Remove.
1105
80551777
CD		 11062003-01-05 Richard Sandiford <rsandifo@redhat.com>
1107
1108 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1109
4c54fc26
CD		 11102003-01-04 Richard Sandiford <rsandifo@redhat.com>
1111 Andrew Cagney <ac131313@redhat.com>
1112 Gavin Romig-Koch <gavin@redhat.com>
1113 Graydon Hoare <graydon@redhat.com>
1114 Aldy Hernandez <aldyh@redhat.com>
1115 Dave Brolley <brolley@redhat.com>
1116 Chris Demetriou <cgd@broadcom.com>
1117
1118 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1119 (sim_mach_default): New variable.
1120 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1121 Add a new simulator generator, MULTI.
1122 * configure: Regenerate.
1123 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1124 (multi-run.o): New dependency.
1125 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1126 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1127 (tmp-multi): Combine them.
1128 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1129 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1130 (distclean-extra): New rule.
1131 * sim-main.h: Include bfd.h.
1132 (MIPS_MACH): New macro.
1133 * mips.igen (vr4120, vr5400, vr5500): New models.
1134 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1135 * vr.igen: Replace with new version.
1136
e6c674b8
CD		 11372003-01-04 Chris Demetriou <cgd@broadcom.com>
1138
1139 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1140 * configure: Regenerate.
1141
28f50ac8
CD		 11422002-12-31 Chris Demetriou <cgd@broadcom.com>
1143
1144 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1145 * mips.igen: Remove all invocations of check_branch_bug and
1146 mark_branch_bug.
1147
5071ffe6
CD		 11482002-12-16 Chris Demetriou <cgd@broadcom.com>
1149
72f4393d 1150 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1151
06e7837e
CD		 11522002-07-30 Chris Demetriou <cgd@broadcom.com>
1153
1154 * mips.igen (do_load_double, do_store_double): New functions.
1155 (LDC1, SDC1): Rename to...
1156 (LDC1b, SDC1b): respectively.
1157 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1158
2265c243
MS		 11592002-07-29 Michael Snyder <msnyder@redhat.com>
1160
1161 * cp1.c (fp_recip2): Modify initialization expression so that
1162 GCC will recognize it as constant.
1163
a2f8b4f3
CD		 11642002-06-18 Chris Demetriou <cgd@broadcom.com>
1165
1166 * mdmx.c (SD_): Delete.
1167 (Unpredictable): Re-define, for now, to directly invoke
1168 unpredictable_action().
1169 (mdmx_acc_op): Fix error in .ob immediate handling.
1170
b4b6c939
AC		 11712002-06-18 Andrew Cagney <cagney@redhat.com>
1172
1173 * interp.c (sim_firmware_command): Initialize `address'.
1174
c8cca39f
AC		 11752002-06-16 Andrew Cagney <ac131313@redhat.com>
1176
1177 * configure: Regenerated to track ../common/aclocal.m4 changes.
1178
e7e81181 11792002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1180 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1181
1182 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1183 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1184 * mips.igen: Include mips3d.igen.
1185 (mips3d): New model name for MIPS-3D ASE instructions.
1186 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1187 instructions.
e7e81181
CD		 1188 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1189 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1190 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1191 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1192 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1193 (RSquareRoot1, RSquareRoot2): New macros.
1194 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1195 (fp_rsqrt2): New functions.
1196 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1197 * configure: Regenerate.
1198
3a2b820e 11992002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1200 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1201
1202 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1203 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1204 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1205 (convert): Note that this function is not used for paired-single
1206 format conversions.
1207 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1208 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1209 (check_fmt_p): Enable paired-single support.
1210 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1211 (PUU.PS): New instructions.
1212 (CVT.S.fmt): Don't use this instruction for paired-single format
1213 destinations.
1214 * sim-main.h (FP_formats): New value 'fmt_ps.'
1215 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1216 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1217
d18ea9c2
CD		 12182002-06-12 Chris Demetriou <cgd@broadcom.com>
1219
1220 * mips.igen: Fix formatting of function calls in
1221 many FP operations.
1222
95fd5cee
CD		 12232002-06-12 Chris Demetriou <cgd@broadcom.com>
1224
1225 * mips.igen (MOVN, MOVZ): Trace result.
1226 (TNEI): Print "tnei" as the opcode name in traces.
1227 (CEIL.W): Add disassembly string for traces.
1228 (RSQRT.fmt): Make location of disassembly string consistent
1229 with other instructions.
1230
4f0d55ae
CD		 12312002-06-12 Chris Demetriou <cgd@broadcom.com>
1232
1233 * mips.igen (X): Delete unused function.
1234
3c25f8c7
AC		 12352002-06-08 Andrew Cagney <cagney@redhat.com>
1236
1237 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1238
f3c08b7e 12392002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1240 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1241
1242 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1243 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1244 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1245 (fp_nmsub): New prototypes.
1246 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1247 (NegMultiplySub): New defines.
1248 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1249 (MADD.D, MADD.S): Replace with...
1250 (MADD.fmt): New instruction.
1251 (MSUB.D, MSUB.S): Replace with...
1252 (MSUB.fmt): New instruction.
1253 (NMADD.D, NMADD.S): Replace with...
1254 (NMADD.fmt): New instruction.
1255 (NMSUB.D, MSUB.S): Replace with...
1256 (NMSUB.fmt): New instruction.
1257
52714ff9 12582002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1259 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1260
1261 * cp1.c: Fix more comment spelling and formatting.
1262 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1263 (denorm_mode): New function.
1264 (fpu_unary, fpu_binary): Round results after operation, collect
1265 status from rounding operations, and update the FCSR.
1266 (convert): Collect status from integer conversions and rounding
1267 operations, and update the FCSR. Adjust NaN values that result
1268 from conversions. Convert to use sim_io_eprintf rather than
1269 fprintf, and remove some debugging code.
1270 * cp1.h (fenr_FS): New define.
1271
577d8c4b
CD		 12722002-06-07 Chris Demetriou <cgd@broadcom.com>
1273
1274 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1275 rounding mode to sim FP rounding mode flag conversion code into...
1276 (rounding_mode): New function.
1277
196496ed
CD		 12782002-06-07 Chris Demetriou <cgd@broadcom.com>
1279
1280 * cp1.c: Clean up formatting of a few comments.
1281 (value_fpr): Reformat switch statement.
1282
cfe9ea23 12832002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1284 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1285
1286 * cp1.h: New file.
1287 * sim-main.h: Include cp1.h.
1288 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1289 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1290 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1291 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1292 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1293 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1294 * cp1.c: Don't include sim-fpu.h; already included by
1295 sim-main.h. Clean up formatting of some comments.
1296 (NaN, Equal, Less): Remove.
1297 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1298 (fp_cmp): New functions.
1299 * mips.igen (do_c_cond_fmt): Remove.
1300 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1301 Compare. Add result tracing.
1302 (CxC1): Remove, replace with...
1303 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1304 (DMxC1): Remove, replace with...
1305 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1306 (MxC1): Remove, replace with...
1307 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1308
ee7254b0
CD		 13092002-06-04 Chris Demetriou <cgd@broadcom.com>
1310
1311 * sim-main.h (FGRIDX): Remove, replace all uses with...
1312 (FGR_BASE): New macro.
1313 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1314 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1315 (NR_FGR, FGR): Likewise.
1316 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1317 * mips.igen: Likewise.
1318
d3eb724f
CD		 13192002-06-04 Chris Demetriou <cgd@broadcom.com>
1320
1321 * cp1.c: Add an FSF Copyright notice to this file.
1322
ba46ddd0 13232002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1324 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1325
1326 * cp1.c (Infinity): Remove.
1327 * sim-main.h (Infinity): Likewise.
1328
1329 * cp1.c (fp_unary, fp_binary): New functions.
1330 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1331 (fp_sqrt): New functions, implemented in terms of the above.
1332 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1333 (Recip, SquareRoot): Remove (replaced by functions above).
1334 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1335 (fp_recip, fp_sqrt): New prototypes.
1336 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1337 (Recip, SquareRoot): Replace prototypes with #defines which
1338 invoke the functions above.
72f4393d 1339
18d8a52d
CD		 13402002-06-03 Chris Demetriou <cgd@broadcom.com>
1341
1342 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1343 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1344 file, remove PARAMS from prototypes.
1345 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1346 simulator state arguments.
1347 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1348 pass simulator state arguments.
1349 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1350 (store_fpr, convert): Remove 'sd' argument.
1351 (value_fpr): Likewise. Convert to use 'SD' instead.
1352
0f154cbd
CD		 13532002-06-03 Chris Demetriou <cgd@broadcom.com>
1354
1355 * cp1.c (Min, Max): Remove #if 0'd functions.
1356 * sim-main.h (Min, Max): Remove.
1357
e80fc152
CD		 13582002-06-03 Chris Demetriou <cgd@broadcom.com>
1359
1360 * cp1.c: fix formatting of switch case and default labels.
1361 * interp.c: Likewise.
1362 * sim-main.c: Likewise.
1363
bad673a9
CD		 13642002-06-03 Chris Demetriou <cgd@broadcom.com>
1365
1366 * cp1.c: Clean up comments which describe FP formats.
1367 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1368
7cbea089 13692002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1370 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1371
1372 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1373 Broadcom SiByte SB-1 processor configurations.
1374 * configure: Regenerate.
1375 * sb1.igen: New file.
1376 * mips.igen: Include sb1.igen.
1377 (sb1): New model.
1378 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1379 * mdmx.igen: Add "sb1" model to all appropriate functions and
1380 instructions.
1381 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1382 (ob_func, ob_acc): Reference the above.
1383 (qh_acc): Adjust to keep the same size as ob_acc.
1384 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1385 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1386
909daa82
CD		 13872002-06-03 Chris Demetriou <cgd@broadcom.com>
1388
1389 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1390
f4f1b9f1 13912002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1392 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1393
1394 * mips.igen (mdmx): New (pseudo-)model.
1395 * mdmx.c, mdmx.igen: New files.
1396 * Makefile.in (SIM_OBJS): Add mdmx.o.
1397 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1398 New typedefs.
1399 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1400 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1401 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1402 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1403 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1404 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1405 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1406 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1407 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1408 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1409 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1410 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1411 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1412 (qh_fmtsel): New macros.
1413 (_sim_cpu): New member "acc".
1414 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1415 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1416
5accf1ff
CD		 14172002-05-01 Chris Demetriou <cgd@broadcom.com>
1418
1419 * interp.c: Use 'deprecated' rather than 'depreciated.'
1420 * sim-main.h: Likewise.
1421
402586aa
CD		 14222002-05-01 Chris Demetriou <cgd@broadcom.com>
1423
1424 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1425 which wouldn't compile anyway.
1426 * sim-main.h (unpredictable_action): New function prototype.
1427 (Unpredictable): Define to call igen function unpredictable().
1428 (NotWordValue): New macro to call igen function not_word_value().
1429 (UndefinedResult): Remove.
1430 * interp.c (undefined_result): Remove.
1431 (unpredictable_action): New function.
1432 * mips.igen (not_word_value, unpredictable): New functions.
1433 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1434 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1435 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1436 NotWordValue() to check for unpredictable inputs, then
1437 Unpredictable() to handle them.
1438
c9b9995a
CD		 14392002-02-24 Chris Demetriou <cgd@broadcom.com>
1440
1441 * mips.igen: Fix formatting of calls to Unpredictable().
1442
e1015982
AC		 14432002-04-20 Andrew Cagney <ac131313@redhat.com>
1444
1445 * interp.c (sim_open): Revert previous change.
1446
b882a66b
AO		 14472002-04-18 Alexandre Oliva <aoliva@redhat.com>
1448
1449 * interp.c (sim_open): Disable chunk of code that wrote code in
1450 vector table entries.
1451
c429b7dd
CD		 14522002-03-19 Chris Demetriou <cgd@broadcom.com>
1453
1454 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1455 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1456 unused definitions.
1457
37d146fa
CD		 14582002-03-19 Chris Demetriou <cgd@broadcom.com>
1459
1460 * cp1.c: Fix many formatting issues.
1461
07892c0b
CD		 14622002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1463
1464 * cp1.c (fpu_format_name): New function to replace...
1465 (DOFMT): This. Delete, and update all callers.
1466 (fpu_rounding_mode_name): New function to replace...
1467 (RMMODE): This. Delete, and update all callers.
1468
487f79b7
CD		 14692002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1470
1471 * interp.c: Move FPU support routines from here to...
1472 * cp1.c: Here. New file.
1473 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1474 (cp1.o): New target.
1475
1e799e28
CD		 14762002-03-12 Chris Demetriou <cgd@broadcom.com>
1477
1478 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1479 * mips.igen (mips32, mips64): New models, add to all instructions
1480 and functions as appropriate.
1481 (loadstore_ea, check_u64): New variant for model mips64.
1482 (check_fmt_p): New variant for models mipsV and mips64, remove
1483 mipsV model marking fro other variant.
1484 (SLL) Rename to...
1485 (SLLa) this.
1486 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1487 for mips32 and mips64.
1488 (DCLO, DCLZ): New instructions for mips64.
1489
82f728db
CD		 14902002-03-07 Chris Demetriou <cgd@broadcom.com>
1491
1492 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1493 immediate or code as a hex value with the "%#lx" format.
1494 (ANDI): Likewise, and fix printed instruction name.
1495
b96e7ef1
CD		 14962002-03-05 Chris Demetriou <cgd@broadcom.com>
1497
1498 * sim-main.h (UndefinedResult, Unpredictable): New macros
1499 which currently do nothing.
1500
d35d4f70
CD		 15012002-03-05 Chris Demetriou <cgd@broadcom.com>
1502
1503 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1504 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1505 (status_CU3): New definitions.
1506
1507 * sim-main.h (ExceptionCause): Add new values for MIPS32
1508 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1509 for DebugBreakPoint and NMIReset to note their status in
1510 MIPS32 and MIPS64.
1511 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1512 (SignalExceptionCacheErr): New exception macros.
1513
3ad6f714
CD		 15142002-03-05 Chris Demetriou <cgd@broadcom.com>
1515
1516 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1517 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1518 is always enabled.
1519 (SignalExceptionCoProcessorUnusable): Take as argument the
1520 unusable coprocessor number.
1521
86b77b47
CD		 15222002-03-05 Chris Demetriou <cgd@broadcom.com>
1523
1524 * mips.igen: Fix formatting of all SignalException calls.
1525
97a88e93 15262002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1527
1528 * sim-main.h (SIGNEXTEND): Remove.
1529
97a88e93 15302002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1531
1532 * mips.igen: Remove gencode comment from top of file, fix
1533 spelling in another comment.
1534
97a88e93 15352002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1536
1537 * mips.igen (check_fmt, check_fmt_p): New functions to check
1538 whether specific floating point formats are usable.
1539 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1540 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1541 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1542 Use the new functions.
1543 (do_c_cond_fmt): Remove format checks...
1544 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1545
97a88e93 15462002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1547
1548 * mips.igen: Fix formatting of check_fpu calls.
1549
41774c9d
CD		 15502002-03-03 Chris Demetriou <cgd@broadcom.com>
1551
1552 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1553
4a0bd876
CD		 15542002-03-03 Chris Demetriou <cgd@broadcom.com>
1555
1556 * mips.igen: Remove whitespace at end of lines.
1557
09297648
CD		 15582002-03-02 Chris Demetriou <cgd@broadcom.com>
1559
1560 * mips.igen (loadstore_ea): New function to do effective
1561 address calculations.
1562 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1563 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1564 CACHE): Use loadstore_ea to do effective address computations.
1565
043b7057
CD		 15662002-03-02 Chris Demetriou <cgd@broadcom.com>
1567
1568 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1569 * mips.igen (LL, CxC1, MxC1): Likewise.
1570
c1e8ada4
CD		 15712002-03-02 Chris Demetriou <cgd@broadcom.com>
1572
1573 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1574 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1575 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1576 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1577 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1578 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1579 Don't split opcode fields by hand, use the opcode field values
1580 provided by igen.
1581
3e1dca16
CD		 15822002-03-01 Chris Demetriou <cgd@broadcom.com>
1583
1584 * mips.igen (do_divu): Fix spacing.
1585
1586 * mips.igen (do_dsllv): Move to be right before DSLLV,
1587 to match the rest of the do_<shift> functions.
1588
fff8d27d
CD		 15892002-03-01 Chris Demetriou <cgd@broadcom.com>
1590
1591 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1592 DSRL32, do_dsrlv): Trace inputs and results.
1593
0d3e762b
CD		 15942002-03-01 Chris Demetriou <cgd@broadcom.com>
1595
1596 * mips.igen (CACHE): Provide instruction-printing string.
1597
1598 * interp.c (signal_exception): Comment tokens after #endif.
1599
eb5fcf93
CD		 16002002-02-28 Chris Demetriou <cgd@broadcom.com>
1601
1602 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1603 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1604 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1605 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1606 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1607 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1608 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1609 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1610
bb22bd7d
CD		 16112002-02-28 Chris Demetriou <cgd@broadcom.com>
1612
1613 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1614 instruction-printing string.
1615 (LWU): Use '64' as the filter flag.
1616
91a177cf
CD		 16172002-02-28 Chris Demetriou <cgd@broadcom.com>
1618
1619 * mips.igen (SDXC1): Fix instruction-printing string.
1620
387f484a
CD		 16212002-02-28 Chris Demetriou <cgd@broadcom.com>
1622
1623 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1624 filter flags "32,f".
1625
3d81f391
CD		 16262002-02-27 Chris Demetriou <cgd@broadcom.com>
1627
1628 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1629 as the filter flag.
1630
af5107af
CD		 16312002-02-27 Chris Demetriou <cgd@broadcom.com>
1632
1633 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1634 add a comma) so that it more closely match the MIPS ISA
1635 documentation opcode partitioning.
1636 (PREF): Put useful names on opcode fields, and include
1637 instruction-printing string.
1638
ca971540
CD		 16392002-02-27 Chris Demetriou <cgd@broadcom.com>
1640
1641 * mips.igen (check_u64): New function which in the future will
1642 check whether 64-bit instructions are usable and signal an
1643 exception if not. Currently a no-op.
1644 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1645 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1646 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1647 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1648
1649 * mips.igen (check_fpu): New function which in the future will
1650 check whether FPU instructions are usable and signal an exception
1651 if not. Currently a no-op.
1652 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1653 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1654 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1655 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1656 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1657 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1658 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1659 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1660
1c47a468
CD		 16612002-02-27 Chris Demetriou <cgd@broadcom.com>
1662
1663 * mips.igen (do_load_left, do_load_right): Move to be immediately
1664 following do_load.
1665 (do_store_left, do_store_right): Move to be immediately following
1666 do_store.
1667
603a98e7
CD		 16682002-02-27 Chris Demetriou <cgd@broadcom.com>
1669
1670 * mips.igen (mipsV): New model name. Also, add it to
1671 all instructions and functions where it is appropriate.
1672
c5d00cc7
CD		 16732002-02-18 Chris Demetriou <cgd@broadcom.com>
1674
1675 * mips.igen: For all functions and instructions, list model
1676 names that support that instruction one per line.
1677
074e9cb8
CD		 16782002-02-11 Chris Demetriou <cgd@broadcom.com>
1679
1680 * mips.igen: Add some additional comments about supported
1681 models, and about which instructions go where.
1682 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1683 order as is used in the rest of the file.
1684
9805e229
CD		 16852002-02-11 Chris Demetriou <cgd@broadcom.com>
1686
1687 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1688 indicating that ALU32_END or ALU64_END are there to check
1689 for overflow.
1690 (DADD): Likewise, but also remove previous comment about
1691 overflow checking.
1692
f701dad2
CD		 16932002-02-10 Chris Demetriou <cgd@broadcom.com>
1694
1695 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1696 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1697 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1698 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1699 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1700 fields (i.e., add and move commas) so that they more closely
1701 match the MIPS ISA documentation opcode partitioning.
1702
17032002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1704
72f4393d
L		 1705 * mips.igen (ADDI): Print immediate value.
1706 (BREAK): Print code.
1707 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1708 (SLL): Print "nop" specially, and don't run the code
1709 that does the shift for the "nop" case.
20ae0098 1710
9e52972e
FF		 17112001-11-17 Fred Fish <fnf@redhat.com>
1712
1713 * sim-main.h (float_operation): Move enum declaration outside
1714 of _sim_cpu struct declaration.
1715
c0efbca4
JB		 17162001-04-12 Jim Blandy <jimb@redhat.com>
1717
1718 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1719 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1720 set of the FCSR.
1721 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1722 PENDING_FILL, and you can get the intended effect gracefully by
1723 calling PENDING_SCHED directly.
1724
fb891446
BE		 17252001-02-23 Ben Elliston <bje@redhat.com>
1726
1727 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1728 already defined elsewhere.
1729
8030f857
BE		 17302001-02-19 Ben Elliston <bje@redhat.com>
1731
1732 * sim-main.h (sim_monitor): Return an int.
1733 * interp.c (sim_monitor): Add return values.
1734 (signal_exception): Handle error conditions from sim_monitor.
1735
56b48a7a
CD		 17362001-02-08 Ben Elliston <bje@redhat.com>
1737
1738 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1739 (store_memory): Likewise, pass cia to sim_core_write*.
1740
d3ee60d9
FCE		 17412000-10-19 Frank Ch. Eigler <fche@redhat.com>
1742
1743 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1744 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1745
071da002
AC		 1746Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1747
1748 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1749 * Makefile.in: Don't delete *.igen when cleaning directory.
1750
a28c02cd
AC		 1751Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1752
1753 * m16.igen (break): Call SignalException not sim_engine_halt.
1754
80ee11fa
AC		 1755Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1756
1757 From Jason Eckhardt:
1758 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1759
673388c0
AC		 1760Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1761
1762 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1763
4c0deff4
NC		 17642000-05-24 Michael Hayes <mhayes@cygnus.com>
1765
1766 * mips.igen (do_dmultx): Fix typo.
1767
eb2d80b4
AC		 1768Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1769
1770 * configure: Regenerated to track ../common/aclocal.m4 changes.
1771
dd37a34b
AC		 1772Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1773
1774 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1775
4c0deff4
NC		 17762000-04-12 Frank Ch. Eigler <fche@redhat.com>
1777
1778 * sim-main.h (GPR_CLEAR): Define macro.
1779
e30db738
AC		 1780Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1781
1782 * interp.c (decode_coproc): Output long using %lx and not %s.
1783
cb7450ea
FCE		 17842000-03-21 Frank Ch. Eigler <fche@redhat.com>
1785
1786 * interp.c (sim_open): Sort & extend dummy memory regions for
1787 --board=jmr3904 for eCos.
1788
a3027dd7
FCE		 17892000-03-02 Frank Ch. Eigler <fche@redhat.com>
1790
1791 * configure: Regenerated.
1792
1793Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1794
1795 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1796 calls, conditional on the simulator being in verbose mode.
1797
dfcd3bfb
JM		 1798Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1799
1800 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1801 cache don't get ReservedInstruction traps.
1802
c2d11a7d
JM		 18031999-11-29 Mark Salter <msalter@cygnus.com>
1804
1805 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1806 to clear status bits in sdisr register. This is how the hardware works.
1807
1808 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1809 being used by cygmon.
1810
4ce44c66
JM		 18111999-11-11 Andrew Haley <aph@cygnus.com>
1812
1813 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1814 instructions.
1815
cff3e48b
JM		 1816Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1817
1818 * mips.igen (MULT): Correct previous mis-applied patch.
1819
d4f3574e
SS		 1820Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1821
1822 * mips.igen (delayslot32): Handle sequence like
1823 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1824 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1825 (MULT): Actually pass the third register...
1826
18271999-09-03 Mark Salter <msalter@cygnus.com>
1828
1829 * interp.c (sim_open): Added more memory aliases for additional
1830 hardware being touched by cygmon on jmr3904 board.
1831
1832Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1833
1834 * configure: Regenerated to track ../common/aclocal.m4 changes.
1835
a0b3c4fd
JM		 1836Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1837
1838 * interp.c (sim_store_register): Handle case where client - GDB -
1839 specifies that a 4 byte register is 8 bytes in size.
1840 (sim_fetch_register): Ditto.
72f4393d 1841
adf40b2e
JM		 18421999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1843
1844 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1845 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1846 (idt_monitor_base): Base address for IDT monitor traps.
1847 (pmon_monitor_base): Ditto for PMON.
1848 (lsipmon_monitor_base): Ditto for LSI PMON.
1849 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1850 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1851 (sim_firmware_command): New function.
1852 (mips_option_handler): Call it for OPTION_FIRMWARE.
1853 (sim_open): Allocate memory for idt_monitor region. If "--board"
1854 option was given, add no monitor by default. Add BREAK hooks only if
1855 monitors are also there.
72f4393d 1856
43e526b9
JM		 1857Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1858
1859 * interp.c (sim_monitor): Flush output before reading input.
1860
1861Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1862
1863 * tconfig.in (SIM_HANDLES_LMA): Always define.
1864
1865Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1866
1867 From Mark Salter <msalter@cygnus.com>:
1868 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1869 (sim_open): Add setup for BSP board.
1870
9846de1b
JM		 1871Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1872
1873 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1874 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1875 them as unimplemented.
1876
cd0fc7c3
SS		 18771999-05-08 Felix Lee <flee@cygnus.com>
1878
1879 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1880
7a292a7a
SS		 18811999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1882
1883 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1884
1885Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1886
1887 * configure.in: Any mips64vr5*-*-* target should have
1888 -DTARGET_ENABLE_FR=1.
1889 (default_endian): Any mips64vr*el-*-* target should default to
1890 LITTLE_ENDIAN.
1891 * configure: Re-generate.
1892
18931999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1894
1895 * mips.igen (ldl): Extend from _16_, not 32.
1896
1897Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1898
1899 * interp.c (sim_store_register): Force registers written to by GDB
1900 into an un-interpreted state.
1901
c906108c
SS		 19021999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1903
1904 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1905 CPU, start periodic background I/O polls.
72f4393d 1906 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1907
19081998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1909
1910 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1911
c906108c
SS		 1912Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1913
1914 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1915 case statement.
1916
19171998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1918
1919 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1920 (load_word): Call SIM_CORE_SIGNAL hook on error.
1921 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1922 starting. For exception dispatching, pass PC instead of NULL_CIA.
1923 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1924 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1925 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1926 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1927 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1928 * mips.igen (*): Replace memory-related SignalException* calls
1929 with references to SIM_CORE_SIGNAL hook.
72f4393d 1930
c906108c
SS		 1931 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1932 fix.
1933 * sim-main.c (*): Minor warning cleanups.
72f4393d 1934
c906108c
SS		 19351998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1936
1937 * m16.igen (DADDIU5): Correct type-o.
1938
1939Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1940
1941 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1942 variables.
1943
1944Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1945
1946 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1947 to include path.
1948 (interp.o): Add dependency on itable.h
1949 (oengine.c, gencode): Delete remaining references.
1950 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1951
c906108c 19521998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1953
c906108c
SS		 1954 * vr4run.c: New.
1955 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1956 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1957 tmp-run-hack) : New.
1958 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1959 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1960 Drop the "64" qualifier to get the HACK generator working.
1961 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1962 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1963 qualifier to get the hack generator working.
1964 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1965 (DSLL): Use do_dsll.
1966 (DSLLV): Use do_dsllv.
1967 (DSRA): Use do_dsra.
1968 (DSRL): Use do_dsrl.
1969 (DSRLV): Use do_dsrlv.
1970 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1971 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1972 get the HACK generator working.
1973 (MACC) Rename to get the HACK generator working.
1974 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1975
c906108c
SS		 19761998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1977
1978 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1979 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1980
c906108c
SS		 19811998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1982
1983 * mips/interp.c (DEBUG): Cleanups.
1984
19851998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1986
1987 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1988 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1989
c906108c
SS		 19901998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1991
1992 * interp.c (sim_close): Uninstall modules.
1993
1994Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1995
1996 * sim-main.h, interp.c (sim_monitor): Change to global
1997 function.
1998
1999Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2000
2001 * configure.in (vr4100): Only include vr4100 instructions in
2002 simulator.
2003 * configure: Re-generate.
2004 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2005
2006Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2007
2008 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2009 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2010 true alternative.
2011
2012 * configure.in (sim_default_gen, sim_use_gen): Replace with
2013 sim_gen.
2014 (--enable-sim-igen): Delete config option. Always using IGEN.
2015 * configure: Re-generate.
72f4393d 2016
c906108c
SS		 2017 * Makefile.in (gencode): Kill, kill, kill.
2018 * gencode.c: Ditto.
72f4393d 2019
c906108c
SS		 2020Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2021
2022 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2023 bit mips16 igen simulator.
2024 * configure: Re-generate.
2025
2026 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2027 as part of vr4100 ISA.
2028 * vr.igen: Mark all instructions as 64 bit only.
2029
2030Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2031
2032 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2033 Pacify GCC.
2034
2035Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2036
2037 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2038 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2039 * configure: Re-generate.
2040
2041 * m16.igen (BREAK): Define breakpoint instruction.
2042 (JALX32): Mark instruction as mips16 and not r3900.
2043 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2044
2045 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2046
2047Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2048
2049 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2050 insn as a debug breakpoint.
2051
2052 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2053 pending.slot_size.
2054 (PENDING_SCHED): Clean up trace statement.
2055 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2056 (PENDING_FILL): Delay write by only one cycle.
2057 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2058
2059 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2060 of pending writes.
2061 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2062 32 & 64.
2063 (pending_tick): Move incrementing of index to FOR statement.
2064 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2065
c906108c
SS		 2066 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2067 build simulator.
2068 * configure: Re-generate.
72f4393d 2069
c906108c
SS		 2070 * interp.c (sim_engine_run OLD): Delete explicit call to
2071 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2072
c906108c
SS		 2073Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2074
2075 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2076 interrupt level number to match changed SignalExceptionInterrupt
2077 macro.
2078
2079Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2080
2081 * interp.c: #include "itable.h" if WITH_IGEN.
2082 (get_insn_name): New function.
2083 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2084 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2085
2086Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2087
2088 * configure: Rebuilt to inhale new common/aclocal.m4.
2089
2090Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2091
2092 * dv-tx3904sio.c: Include sim-assert.h.
2093
2094Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2095
2096 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2097 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2098 Reorganize target-specific sim-hardware checks.
2099 * configure: rebuilt.
2100 * interp.c (sim_open): For tx39 target boards, set
2101 OPERATING_ENVIRONMENT, add tx3904sio devices.
2102 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2103 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2104
c906108c
SS		 2105 * dv-tx3904irc.c: Compiler warning clean-up.
2106 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2107 frequent hw-trace messages.
2108
2109Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2110
2111 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2112
2113Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2114
2115 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2116
2117 * vr.igen: New file.
2118 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2119 * mips.igen: Define vr4100 model. Include vr.igen.
2120Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2121
2122 * mips.igen (check_mf_hilo): Correct check.
2123
2124Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2125
2126 * sim-main.h (interrupt_event): Add prototype.
2127
2128 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2129 register_ptr, register_value.
2130 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2131
2132 * sim-main.h (tracefh): Make extern.
2133
2134Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2135
2136 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2137 Reduce unnecessarily high timer event frequency.
c906108c 2138 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2139
c906108c
SS		 2140Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2141
2142 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2143 to allay warnings.
2144 (interrupt_event): Made non-static.
72f4393d 2145
c906108c
SS		 2146 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2147 interchange of configuration values for external vs. internal
2148 clock dividers.
72f4393d 2149
c906108c
SS		 2150Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2151
72f4393d 2152 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2153 simulator-reserved break instructions.
2154 * gencode.c (build_instruction): Ditto.
2155 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2156 reserved instructions now use exception vector, rather
c906108c
SS		 2157 than halting sim.
2158 * sim-main.h: Moved magic constants to here.
2159
2160Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2161
2162 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2163 register upon non-zero interrupt event level, clear upon zero
2164 event value.
2165 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2166 by passing zero event value.
2167 (*_io_{read,write}_buffer): Endianness fixes.
2168 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2169 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2170
2171 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2172 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2173
c906108c
SS		 2174Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2175
72f4393d 2176 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2177 and BigEndianCPU.
2178
2179Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2180
2181 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2182 parts.
2183 * configure: Update.
2184
2185Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2186
2187 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2188 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2189 * configure.in: Include tx3904tmr in hw_device list.
2190 * configure: Rebuilt.
2191 * interp.c (sim_open): Instantiate three timer instances.
2192 Fix address typo of tx3904irc instance.
2193
2194Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2195
2196 * interp.c (signal_exception): SystemCall exception now uses
2197 the exception vector.
2198
2199Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2200
2201 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2202 to allay warnings.
2203
2204Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2205
2206 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2207
2208Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2209
2210 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2211
2212 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2213 sim-main.h. Declare a struct hw_descriptor instead of struct
2214 hw_device_descriptor.
2215
2216Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2217
2218 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2219 right bits and then re-align left hand bytes to correct byte
2220 lanes. Fix incorrect computation in do_store_left when loading
2221 bytes from second word.
2222
2223Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2224
2225 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2226 * interp.c (sim_open): Only create a device tree when HW is
2227 enabled.
2228
2229 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2230 * interp.c (signal_exception): Ditto.
2231
2232Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2233
2234 * gencode.c: Mark BEGEZALL as LIKELY.
2235
2236Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2237
2238 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2239 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2240
c906108c
SS		 2241Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2242
2243 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2244 modules. Recognize TX39 target with "mips*tx39" pattern.
2245 * configure: Rebuilt.
2246 * sim-main.h (*): Added many macros defining bits in
2247 TX39 control registers.
2248 (SignalInterrupt): Send actual PC instead of NULL.
2249 (SignalNMIReset): New exception type.
2250 * interp.c (board): New variable for future use to identify
2251 a particular board being simulated.
2252 (mips_option_handler,mips_options): Added "--board" option.
2253 (interrupt_event): Send actual PC.
2254 (sim_open): Make memory layout conditional on board setting.
2255 (signal_exception): Initial implementation of hardware interrupt
2256 handling. Accept another break instruction variant for simulator
2257 exit.
2258 (decode_coproc): Implement RFE instruction for TX39.
2259 (mips.igen): Decode RFE instruction as such.
2260 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2261 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2262 bbegin to implement memory map.
2263 * dv-tx3904cpu.c: New file.
2264 * dv-tx3904irc.c: New file.
2265
2266Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2267
2268 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2269
2270Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2271
2272 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2273 with calls to check_div_hilo.
2274
2275Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2276
2277 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2278 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2279 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2280 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2281 with calls to check_mult_hilo.
2282 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2283 with calls to check_div_hilo.
2284
2285Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2286
2287 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2288 Document a replacement.
2289
2290Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2291
2292 * interp.c (sim_monitor): Make mon_printf work.
2293
2294Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2295
2296 * sim-main.h (INSN_NAME): New arg `cpu'.
2297
2298Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2299
72f4393d 2300 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2301
2302Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2303
2304 * configure: Regenerated to track ../common/aclocal.m4 changes.
2305 * config.in: Ditto.
2306
2307Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2308
2309 * acconfig.h: New file.
2310 * configure.in: Reverted change of Apr 24; use sinclude again.
2311
2312Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2313
2314 * configure: Regenerated to track ../common/aclocal.m4 changes.
2315 * config.in: Ditto.
2316
2317Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2318
2319 * configure.in: Don't call sinclude.
2320
2321Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2322
2323 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2324
2325Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2326
2327 * mips.igen (ERET): Implement.
2328
2329 * interp.c (decode_coproc): Return sign-extended EPC.
2330
2331 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2332
2333 * interp.c (signal_exception): Do not ignore Trap.
2334 (signal_exception): On TRAP, restart at exception address.
2335 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2336 (signal_exception): Update.
2337 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2338 so that TRAP instructions are caught.
2339
2340Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2341
2342 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2343 contains HI/LO access history.
2344 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2345 (HIACCESS, LOACCESS): Delete, replace with
2346 (HIHISTORY, LOHISTORY): New macros.
2347 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2348
c906108c
SS		 2349 * gencode.c (build_instruction): Do not generate checks for
2350 correct HI/LO register usage.
2351
2352 * interp.c (old_engine_run): Delete checks for correct HI/LO
2353 register usage.
2354
2355 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2356 check_mf_cycles): New functions.
2357 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2358 do_divu, domultx, do_mult, do_multu): Use.
2359
2360 * tx.igen ("madd", "maddu"): Use.
72f4393d 2361
c906108c
SS		 2362Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2363
2364 * mips.igen (DSRAV): Use function do_dsrav.
2365 (SRAV): Use new function do_srav.
2366
2367 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2368 (B): Sign extend 11 bit immediate.
2369 (EXT-B*): Shift 16 bit immediate left by 1.
2370 (ADDIU*): Don't sign extend immediate value.
2371
2372Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2373
2374 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2375
2376 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2377 functions.
2378
2379 * mips.igen (delayslot32, nullify_next_insn): New functions.
2380 (m16.igen): Always include.
2381 (do_*): Add more tracing.
2382
2383 * m16.igen (delayslot16): Add NIA argument, could be called by a
2384 32 bit MIPS16 instruction.
72f4393d 2385
c906108c
SS		 2386 * interp.c (ifetch16): Move function from here.
2387 * sim-main.c (ifetch16): To here.
72f4393d 2388
c906108c
SS		 2389 * sim-main.c (ifetch16, ifetch32): Update to match current
2390 implementations of LH, LW.
2391 (signal_exception): Don't print out incorrect hex value of illegal
2392 instruction.
2393
2394Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2395
2396 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2397 instruction.
2398
2399 * m16.igen: Implement MIPS16 instructions.
72f4393d 2400
c906108c
SS		 2401 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2402 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2403 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2404 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2405 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2406 bodies of corresponding code from 32 bit insn to these. Also used
2407 by MIPS16 versions of functions.
72f4393d 2408
c906108c
SS		 2409 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2410 (IMEM16): Drop NR argument from macro.
2411
2412Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2413
2414 * Makefile.in (SIM_OBJS): Add sim-main.o.
2415
2416 * sim-main.h (address_translation, load_memory, store_memory,
2417 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2418 as INLINE_SIM_MAIN.
2419 (pr_addr, pr_uword64): Declare.
2420 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2421
c906108c
SS		 2422 * interp.c (address_translation, load_memory, store_memory,
2423 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2424 from here.
2425 * sim-main.c: To here. Fix compilation problems.
72f4393d 2426
c906108c
SS		 2427 * configure.in: Enable inlining.
2428 * configure: Re-config.
2429
2430Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2431
2432 * configure: Regenerated to track ../common/aclocal.m4 changes.
2433
2434Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2435
2436 * mips.igen: Include tx.igen.
2437 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2438 * tx.igen: New file, contains MADD and MADDU.
2439
2440 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2441 the hardwired constant `7'.
2442 (store_memory): Ditto.
2443 (LOADDRMASK): Move definition to sim-main.h.
2444
2445 mips.igen (MTC0): Enable for r3900.
2446 (ADDU): Add trace.
2447
2448 mips.igen (do_load_byte): Delete.
2449 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2450 do_store_right): New functions.
2451 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2452
2453 configure.in: Let the tx39 use igen again.
2454 configure: Update.
72f4393d 2455
c906108c
SS		 2456Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2457
2458 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2459 not an address sized quantity. Return zero for cache sizes.
2460
2461Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2462
2463 * mips.igen (r3900): r3900 does not support 64 bit integer
2464 operations.
2465
2466Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2467
2468 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2469 than igen one.
2470 * configure : Rebuild.
72f4393d 2471
c906108c
SS		 2472Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2473
2474 * configure: Regenerated to track ../common/aclocal.m4 changes.
2475
2476Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2477
2478 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2479
2480Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2481
2482 * configure: Regenerated to track ../common/aclocal.m4 changes.
2483 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2484
2485Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2486
2487 * configure: Regenerated to track ../common/aclocal.m4 changes.
2488
2489Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2490
2491 * interp.c (Max, Min): Comment out functions. Not yet used.
2492
2493Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2494
2495 * configure: Regenerated to track ../common/aclocal.m4 changes.
2496
2497Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2498
2499 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2500 configurable settings for stand-alone simulator.
72f4393d 2501
c906108c 2502 * configure.in: Added X11 search, just in case.
72f4393d 2503
c906108c
SS		 2504 * configure: Regenerated.
2505
2506Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2507
2508 * interp.c (sim_write, sim_read, load_memory, store_memory):
2509 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2510
2511Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2512
2513 * sim-main.h (GETFCC): Return an unsigned value.
2514
2515Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2516
2517 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2518 (DADD): Result destination is RD not RT.
2519
2520Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2521
2522 * sim-main.h (HIACCESS, LOACCESS): Always define.
2523
2524 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2525
2526 * interp.c (sim_info): Delete.
2527
2528Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2529
2530 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2531 (mips_option_handler): New argument `cpu'.
2532 (sim_open): Update call to sim_add_option_table.
2533
2534Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2535
2536 * mips.igen (CxC1): Add tracing.
2537
2538Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2539
2540 * sim-main.h (Max, Min): Declare.
2541
2542 * interp.c (Max, Min): New functions.
2543
2544 * mips.igen (BC1): Add tracing.
72f4393d 2545
c906108c 2546Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2547
c906108c 2548 * interp.c Added memory map for stack in vr4100
72f4393d 2549
c906108c
SS		 2550Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2551
2552 * interp.c (load_memory): Add missing "break"'s.
2553
2554Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2555
2556 * interp.c (sim_store_register, sim_fetch_register): Pass in
2557 length parameter. Return -1.
2558
2559Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2560
2561 * interp.c: Added hardware init hook, fixed warnings.
2562
2563Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2564
2565 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2566
2567Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2568
2569 * interp.c (ifetch16): New function.
2570
2571 * sim-main.h (IMEM32): Rename IMEM.
2572 (IMEM16_IMMED): Define.
2573 (IMEM16): Define.
2574 (DELAY_SLOT): Update.
72f4393d 2575
c906108c 2576 * m16run.c (sim_engine_run): New file.
72f4393d 2577
c906108c
SS		 2578 * m16.igen: All instructions except LB.
2579 (LB): Call do_load_byte.
2580 * mips.igen (do_load_byte): New function.
2581 (LB): Call do_load_byte.
2582
2583 * mips.igen: Move spec for insn bit size and high bit from here.
2584 * Makefile.in (tmp-igen, tmp-m16): To here.
2585
2586 * m16.dc: New file, decode mips16 instructions.
2587
2588 * Makefile.in (SIM_NO_ALL): Define.
2589 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2590
2591Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2592
2593 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2594 point unit to 32 bit registers.
2595 * configure: Re-generate.
2596
2597Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2598
2599 * configure.in (sim_use_gen): Make IGEN the default simulator
2600 generator for generic 32 and 64 bit mips targets.
2601 * configure: Re-generate.
2602
2603Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2604
2605 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2606 bitsize.
2607
2608 * interp.c (sim_fetch_register, sim_store_register): Read/write
2609 FGR from correct location.
2610 (sim_open): Set size of FGR's according to
2611 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2612
c906108c
SS		 2613 * sim-main.h (FGR): Store floating point registers in a separate
2614 array.
2615
2616Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2617
2618 * configure: Regenerated to track ../common/aclocal.m4 changes.
2619
2620Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2621
2622 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2623
2624 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2625
2626 * interp.c (pending_tick): New function. Deliver pending writes.
2627
2628 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2629 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2630 it can handle mixed sized quantites and single bits.
72f4393d 2631
c906108c
SS		 2632Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2633
2634 * interp.c (oengine.h): Do not include when building with IGEN.
2635 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2636 (sim_info): Ditto for PROCESSOR_64BIT.
2637 (sim_monitor): Replace ut_reg with unsigned_word.
2638 (*): Ditto for t_reg.
2639 (LOADDRMASK): Define.
2640 (sim_open): Remove defunct check that host FP is IEEE compliant,
2641 using software to emulate floating point.
2642 (value_fpr, ...): Always compile, was conditional on HASFPU.
2643
2644Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2645
2646 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2647 size.
2648
2649 * interp.c (SD, CPU): Define.
2650 (mips_option_handler): Set flags in each CPU.
2651 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2652 (sim_close): Do not clear STATE, deleted anyway.
2653 (sim_write, sim_read): Assume CPU zero's vm should be used for
2654 data transfers.
2655 (sim_create_inferior): Set the PC for all processors.
2656 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2657 argument.
2658 (mips16_entry): Pass correct nr of args to store_word, load_word.
2659 (ColdReset): Cold reset all cpu's.
2660 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2661 (sim_monitor, load_memory, store_memory, signal_exception): Use
2662 `CPU' instead of STATE_CPU.
2663
2664
2665 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2666 SD or CPU_.
72f4393d 2667
c906108c
SS		 2668 * sim-main.h (signal_exception): Add sim_cpu arg.
2669 (SignalException*): Pass both SD and CPU to signal_exception.
2670 * interp.c (signal_exception): Update.
72f4393d 2671
c906108c
SS		 2672 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2673 Ditto
2674 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2675 address_translation): Ditto
2676 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2677
c906108c
SS		 2678Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2679
2680 * configure: Regenerated to track ../common/aclocal.m4 changes.
2681
2682Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2683
2684 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2685
72f4393d 2686 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2687
2688 * sim-main.h (CPU_CIA): Delete.
2689 (SET_CIA, GET_CIA): Define
2690
2691Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2692
2693 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2694 regiser.
2695
2696 * configure.in (default_endian): Configure a big-endian simulator
2697 by default.
2698 * configure: Re-generate.
72f4393d 2699
c906108c
SS		 2700Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2701
2702 * configure: Regenerated to track ../common/aclocal.m4 changes.
2703
2704Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2705
2706 * interp.c (sim_monitor): Handle Densan monitor outbyte
2707 and inbyte functions.
2708
27091997-12-29 Felix Lee <flee@cygnus.com>
2710
2711 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2712
2713Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2714
2715 * Makefile.in (tmp-igen): Arrange for $zero to always be
2716 reset to zero after every instruction.
2717
2718Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2719
2720 * configure: Regenerated to track ../common/aclocal.m4 changes.
2721 * config.in: Ditto.
2722
2723Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2724
2725 * mips.igen (MSUB): Fix to work like MADD.
2726 * gencode.c (MSUB): Similarly.
2727
2728Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2729
2730 * configure: Regenerated to track ../common/aclocal.m4 changes.
2731
2732Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2733
2734 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2735
2736Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2737
2738 * sim-main.h (sim-fpu.h): Include.
2739
2740 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2741 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2742 using host independant sim_fpu module.
2743
2744Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2745
2746 * interp.c (signal_exception): Report internal errors with SIGABRT
2747 not SIGQUIT.
2748
2749 * sim-main.h (C0_CONFIG): New register.
2750 (signal.h): No longer include.
2751
2752 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2753
2754Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2755
2756 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2757
2758Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2759
2760 * mips.igen: Tag vr5000 instructions.
2761 (ANDI): Was missing mipsIV model, fix assembler syntax.
2762 (do_c_cond_fmt): New function.
2763 (C.cond.fmt): Handle mips I-III which do not support CC field
2764 separatly.
2765 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2766 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2767 in IV3.2 spec.
2768 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2769 vr5000 which saves LO in a GPR separatly.
72f4393d 2770
c906108c
SS		 2771 * configure.in (enable-sim-igen): For vr5000, select vr5000
2772 specific instructions.
2773 * configure: Re-generate.
72f4393d 2774
c906108c
SS		 2775Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2776
2777 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2778
2779 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2780 fmt_uninterpreted_64 bit cases to switch. Convert to
2781 fmt_formatted,
2782
2783 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2784
2785 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2786 as specified in IV3.2 spec.
2787 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2788
2789Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2790
2791 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2792 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2793 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2794 PENDING_FILL versions of instructions. Simplify.
2795 (X): New function.
2796 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2797 instructions.
2798 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2799 a signed value.
2800 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2801
c906108c
SS		 2802 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2803 global.
2804 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2805
2806Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2807
2808 * gencode.c (build_mips16_operands): Replace IPC with cia.
2809
2810 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2811 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2812 IPC to `cia'.
2813 (UndefinedResult): Replace function with macro/function
2814 combination.
2815 (sim_engine_run): Don't save PC in IPC.
2816
2817 * sim-main.h (IPC): Delete.
2818
2819
2820 * interp.c (signal_exception, store_word, load_word,
2821 address_translation, load_memory, store_memory, cache_op,
2822 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2823 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2824 current instruction address - cia - argument.
2825 (sim_read, sim_write): Call address_translation directly.
2826 (sim_engine_run): Rename variable vaddr to cia.
2827 (signal_exception): Pass cia to sim_monitor
72f4393d 2828
c906108c
SS		 2829 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2830 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2831 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2832
2833 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2834 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2835 SIM_ASSERT.
72f4393d 2836
c906108c
SS		 2837 * interp.c (signal_exception): Pass restart address to
2838 sim_engine_restart.
2839
2840 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2841 idecode.o): Add dependency.
2842
2843 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2844 Delete definitions
2845 (DELAY_SLOT): Update NIA not PC with branch address.
2846 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2847
2848 * mips.igen: Use CIA not PC in branch calculations.
2849 (illegal): Call SignalException.
2850 (BEQ, ADDIU): Fix assembler.
2851
2852Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2853
2854 * m16.igen (JALX): Was missing.
2855
2856 * configure.in (enable-sim-igen): New configuration option.
2857 * configure: Re-generate.
72f4393d 2858
c906108c
SS		 2859 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2860
2861 * interp.c (load_memory, store_memory): Delete parameter RAW.
2862 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2863 bypassing {load,store}_memory.
2864
2865 * sim-main.h (ByteSwapMem): Delete definition.
2866
2867 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2868
2869 * interp.c (sim_do_command, sim_commands): Delete mips specific
2870 commands. Handled by module sim-options.
72f4393d 2871
c906108c
SS		 2872 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2873 (WITH_MODULO_MEMORY): Define.
2874
2875 * interp.c (sim_info): Delete code printing memory size.
2876
2877 * interp.c (mips_size): Nee sim_size, delete function.
2878 (power2): Delete.
2879 (monitor, monitor_base, monitor_size): Delete global variables.
2880 (sim_open, sim_close): Delete code creating monitor and other
2881 memory regions. Use sim-memopts module, via sim_do_commandf, to
2882 manage memory regions.
2883 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2884
c906108c
SS		 2885 * interp.c (address_translation): Delete all memory map code
2886 except line forcing 32 bit addresses.
2887
2888Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2889
2890 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2891 trace options.
2892
2893 * interp.c (logfh, logfile): Delete globals.
2894 (sim_open, sim_close): Delete code opening & closing log file.
2895 (mips_option_handler): Delete -l and -n options.
2896 (OPTION mips_options): Ditto.
2897
2898 * interp.c (OPTION mips_options): Rename option trace to dinero.
2899 (mips_option_handler): Update.
2900
2901Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2902
2903 * interp.c (fetch_str): New function.
2904 (sim_monitor): Rewrite using sim_read & sim_write.
2905 (sim_open): Check magic number.
2906 (sim_open): Write monitor vectors into memory using sim_write.
2907 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2908 (sim_read, sim_write): Simplify - transfer data one byte at a
2909 time.
2910 (load_memory, store_memory): Clarify meaning of parameter RAW.
2911
2912 * sim-main.h (isHOST): Defete definition.
2913 (isTARGET): Mark as depreciated.
2914 (address_translation): Delete parameter HOST.
2915
2916 * interp.c (address_translation): Delete parameter HOST.
2917
2918Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2919
72f4393d 2920 * mips.igen:
c906108c
SS		 2921
2922 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2923 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2924
2925Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2926
2927 * mips.igen: Add model filter field to records.
2928
2929Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2930
2931 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2932
c906108c
SS		 2933 interp.c (sim_engine_run): Do not compile function sim_engine_run
2934 when WITH_IGEN == 1.
2935
2936 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2937 target architecture.
2938
2939 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2940 igen. Replace with configuration variables sim_igen_flags /
2941 sim_m16_flags.
2942
2943 * m16.igen: New file. Copy mips16 insns here.
2944 * mips.igen: From here.
2945
2946Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2947
2948 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2949 to top.
2950 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2951
2952Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2953
2954 * gencode.c (build_instruction): Follow sim_write's lead in using
2955 BigEndianMem instead of !ByteSwapMem.
2956
2957Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2958
2959 * configure.in (sim_gen): Dependent on target, select type of
2960 generator. Always select old style generator.
2961
2962 configure: Re-generate.
2963
2964 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2965 targets.
2966 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2967 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2968 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2969 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2970 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2971
c906108c
SS		 2972Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2973
2974 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2975
2976 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2977 CURRENT_FLOATING_POINT instead.
2978
2979 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2980 (address_translation): Raise exception InstructionFetch when
2981 translation fails and isINSTRUCTION.
72f4393d 2982
c906108c
SS		 2983 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2984 sim_engine_run): Change type of of vaddr and paddr to
2985 address_word.
2986 (address_translation, prefetch, load_memory, store_memory,
2987 cache_op): Change type of vAddr and pAddr to address_word.
2988
2989 * gencode.c (build_instruction): Change type of vaddr and paddr to
2990 address_word.
2991
2992Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2993
2994 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2995 macro to obtain result of ALU op.
2996
2997Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2998
2999 * interp.c (sim_info): Call profile_print.
3000
3001Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3002
3003 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3004
3005 * sim-main.h (WITH_PROFILE): Do not define, defined in
3006 common/sim-config.h. Use sim-profile module.
3007 (simPROFILE): Delete defintion.
3008
3009 * interp.c (PROFILE): Delete definition.
3010 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3011 (sim_close): Delete code writing profile histogram.
3012 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3013 Delete.
3014 (sim_engine_run): Delete code profiling the PC.
3015
3016Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3017
3018 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3019
3020 * interp.c (sim_monitor): Make register pointers of type
3021 unsigned_word*.
3022
3023 * sim-main.h: Make registers of type unsigned_word not
3024 signed_word.
3025
3026Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3027
3028 * interp.c (sync_operation): Rename from SyncOperation, make
3029 global, add SD argument.
3030 (prefetch): Rename from Prefetch, make global, add SD argument.
3031 (decode_coproc): Make global.
3032
3033 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3034
3035 * gencode.c (build_instruction): Generate DecodeCoproc not
3036 decode_coproc calls.
3037
3038 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3039 (SizeFGR): Move to sim-main.h
3040 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3041 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3042 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3043 sim-main.h.
3044 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3045 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3046 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3047 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3048 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3049 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3050
c906108c
SS		 3051 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3052 exception.
3053 (sim-alu.h): Include.
3054 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3055 (sim_cia): Typedef to instruction_address.
72f4393d 3056
c906108c
SS		 3057Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3058
3059 * Makefile.in (interp.o): Rename generated file engine.c to
3060 oengine.c.
72f4393d 3061
c906108c 3062 * interp.c: Update.
72f4393d 3063
c906108c
SS		 3064Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3065
3066 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3067
c906108c
SS		 3068Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3069
3070 * gencode.c (build_instruction): For "FPSQRT", output correct
3071 number of arguments to Recip.
72f4393d 3072
c906108c
SS		 3073Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3074
3075 * Makefile.in (interp.o): Depends on sim-main.h
3076
3077 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3078
3079 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3080 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3081 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3082 STATE, DSSTATE): Define
3083 (GPR, FGRIDX, ..): Define.
3084
3085 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3086 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3087 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3088
c906108c 3089 * interp.c: Update names to match defines from sim-main.h
72f4393d 3090
c906108c
SS		 3091Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3092
3093 * interp.c (sim_monitor): Add SD argument.
3094 (sim_warning): Delete. Replace calls with calls to
3095 sim_io_eprintf.
3096 (sim_error): Delete. Replace calls with sim_io_error.
3097 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3098 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3099 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3100 argument.
3101 (mips_size): Rename from sim_size. Add SD argument.
3102
3103 * interp.c (simulator): Delete global variable.
3104 (callback): Delete global variable.
3105 (mips_option_handler, sim_open, sim_write, sim_read,
3106 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3107 sim_size,sim_monitor): Use sim_io_* not callback->*.
3108 (sim_open): ZALLOC simulator struct.
3109 (PROFILE): Do not define.
3110
3111Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3112
3113 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3114 support.h with corresponding code.
3115
3116 * sim-main.h (word64, uword64), support.h: Move definition to
3117 sim-main.h.
3118 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3119
3120 * support.h: Delete
3121 * Makefile.in: Update dependencies
3122 * interp.c: Do not include.
72f4393d 3123
c906108c
SS		 3124Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3125
3126 * interp.c (address_translation, load_memory, store_memory,
3127 cache_op): Rename to from AddressTranslation et.al., make global,
3128 add SD argument
72f4393d 3129
c906108c
SS		 3130 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3131 CacheOp): Define.
72f4393d 3132
c906108c
SS		 3133 * interp.c (SignalException): Rename to signal_exception, make
3134 global.
3135
3136 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3137
c906108c
SS		 3138 * sim-main.h (SignalException, SignalExceptionInterrupt,
3139 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3140 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3141 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3142 Define.
72f4393d 3143
c906108c 3144 * interp.c, support.h: Use.
72f4393d 3145
c906108c
SS		 3146Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3147
3148 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3149 to value_fpr / store_fpr. Add SD argument.
3150 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3151 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3152
3153 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3154
c906108c
SS		 3155Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3156
3157 * interp.c (sim_engine_run): Check consistency between configure
3158 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3159 and HASFPU.
3160
3161 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3162 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3163 (mips_endian): Configure WITH_TARGET_ENDIAN.
3164 * configure: Update.
3165
3166Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3167
3168 * configure: Regenerated to track ../common/aclocal.m4 changes.
3169
3170Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3171
3172 * configure: Regenerated.
3173
3174Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3175
3176 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3177
3178Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3179
3180 * gencode.c (print_igen_insn_models): Assume certain architectures
3181 include all mips* instructions.
3182 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3183 instruction.
3184
3185 * Makefile.in (tmp.igen): Add target. Generate igen input from
3186 gencode file.
3187
3188 * gencode.c (FEATURE_IGEN): Define.
3189 (main): Add --igen option. Generate output in igen format.
3190 (process_instructions): Format output according to igen option.
3191 (print_igen_insn_format): New function.
3192 (print_igen_insn_models): New function.
3193 (process_instructions): Only issue warnings and ignore
3194 instructions when no FEATURE_IGEN.
3195
3196Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3197
3198 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3199 MIPS targets.
3200
3201Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3202
3203 * configure: Regenerated to track ../common/aclocal.m4 changes.
3204
3205Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3206
3207 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3208 SIM_RESERVED_BITS): Delete, moved to common.
3209 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3210
c906108c
SS		 3211Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3212
3213 * configure.in: Configure non-strict memory alignment.
3214 * configure: Regenerated to track ../common/aclocal.m4 changes.
3215
3216Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3217
3218 * configure: Regenerated to track ../common/aclocal.m4 changes.
3219
3220Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3221
3222 * gencode.c (SDBBP,DERET): Added (3900) insns.
3223 (RFE): Turn on for 3900.
3224 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3225 (dsstate): Made global.
3226 (SUBTARGET_R3900): Added.
3227 (CANCELDELAYSLOT): New.
3228 (SignalException): Ignore SystemCall rather than ignore and
3229 terminate. Add DebugBreakPoint handling.
3230 (decode_coproc): New insns RFE, DERET; and new registers Debug
3231 and DEPC protected by SUBTARGET_R3900.
3232 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3233 bits explicitly.
3234 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3235 * configure: Update.
c906108c
SS		 3236
3237Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3238
3239 * gencode.c: Add r3900 (tx39).
72f4393d 3240
c906108c
SS		 3241
3242Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3243
3244 * gencode.c (build_instruction): Don't need to subtract 4 for
3245 JALR, just 2.
3246
3247Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3248
3249 * interp.c: Correct some HASFPU problems.
3250
3251Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3252
3253 * configure: Regenerated to track ../common/aclocal.m4 changes.
3254
3255Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3256
3257 * interp.c (mips_options): Fix samples option short form, should
3258 be `x'.
3259
3260Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3261
3262 * interp.c (sim_info): Enable info code. Was just returning.
3263
3264Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3265
3266 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3267 MFC0.
3268
3269Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3270
3271 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3272 constants.
3273 (build_instruction): Ditto for LL.
3274
3275Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3276
3277 * configure: Regenerated to track ../common/aclocal.m4 changes.
3278
3279Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3280
3281 * configure: Regenerated to track ../common/aclocal.m4 changes.
3282 * config.in: Ditto.
3283
3284Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3285
3286 * interp.c (sim_open): Add call to sim_analyze_program, update
3287 call to sim_config.
3288
3289Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3290
3291 * interp.c (sim_kill): Delete.
3292 (sim_create_inferior): Add ABFD argument. Set PC from same.
3293 (sim_load): Move code initializing trap handlers from here.
3294 (sim_open): To here.
3295 (sim_load): Delete, use sim-hload.c.
3296
3297 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3298
3299Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3300
3301 * configure: Regenerated to track ../common/aclocal.m4 changes.
3302 * config.in: Ditto.
3303
3304Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3305
3306 * interp.c (sim_open): Add ABFD argument.
3307 (sim_load): Move call to sim_config from here.
3308 (sim_open): To here. Check return status.
3309
3310Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3311
c906108c
SS		 3312 * gencode.c (build_instruction): Two arg MADD should
3313 not assign result to $0.
72f4393d 3314
c906108c
SS		 3315Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3316
3317 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3318 * sim/mips/configure.in: Regenerate.
3319
3320Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3321
3322 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3323 signed8, unsigned8 et.al. types.
3324
3325 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3326 hosts when selecting subreg.
3327
3328Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3329
3330 * interp.c (sim_engine_run): Reset the ZERO register to zero
3331 regardless of FEATURE_WARN_ZERO.
3332 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3333
3334Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3335
3336 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3337 (SignalException): For BreakPoints ignore any mode bits and just
3338 save the PC.
3339 (SignalException): Always set the CAUSE register.
3340
3341Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3342
3343 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3344 exception has been taken.
3345
3346 * interp.c: Implement the ERET and mt/f sr instructions.
3347
3348Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3349
3350 * interp.c (SignalException): Don't bother restarting an
3351 interrupt.
3352
3353Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3354
3355 * interp.c (SignalException): Really take an interrupt.
3356 (interrupt_event): Only deliver interrupts when enabled.
3357
3358Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3359
3360 * interp.c (sim_info): Only print info when verbose.
3361 (sim_info) Use sim_io_printf for output.
72f4393d 3362
c906108c
SS		 3363Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3364
3365 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3366 mips architectures.
3367
3368Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3369
3370 * interp.c (sim_do_command): Check for common commands if a
3371 simulator specific command fails.
3372
3373Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3374
3375 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3376 and simBE when DEBUG is defined.
3377
3378Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3379
3380 * interp.c (interrupt_event): New function. Pass exception event
3381 onto exception handler.
3382
3383 * configure.in: Check for stdlib.h.
3384 * configure: Regenerate.
3385
3386 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3387 variable declaration.
3388 (build_instruction): Initialize memval1.
3389 (build_instruction): Add UNUSED attribute to byte, bigend,
3390 reverse.
3391 (build_operands): Ditto.
3392
3393 * interp.c: Fix GCC warnings.
3394 (sim_get_quit_code): Delete.
3395
3396 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3397 * Makefile.in: Ditto.
3398 * configure: Re-generate.
72f4393d 3399
c906108c
SS		 3400 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3401
3402Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3403
3404 * interp.c (mips_option_handler): New function parse argumes using
3405 sim-options.
3406 (myname): Replace with STATE_MY_NAME.
3407 (sim_open): Delete check for host endianness - performed by
3408 sim_config.
3409 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3410 (sim_open): Move much of the initialization from here.
3411 (sim_load): To here. After the image has been loaded and
3412 endianness set.
3413 (sim_open): Move ColdReset from here.
3414 (sim_create_inferior): To here.
3415 (sim_open): Make FP check less dependant on host endianness.
3416
3417 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3418 run.
3419 * interp.c (sim_set_callbacks): Delete.
3420
3421 * interp.c (membank, membank_base, membank_size): Replace with
3422 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3423 (sim_open): Remove call to callback->init. gdb/run do this.
3424
3425 * interp.c: Update
3426
3427 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3428
3429 * interp.c (big_endian_p): Delete, replaced by
3430 current_target_byte_order.
3431
3432Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3433
3434 * interp.c (host_read_long, host_read_word, host_swap_word,
3435 host_swap_long): Delete. Using common sim-endian.
3436 (sim_fetch_register, sim_store_register): Use H2T.
3437 (pipeline_ticks): Delete. Handled by sim-events.
3438 (sim_info): Update.
3439 (sim_engine_run): Update.
3440
3441Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3442
3443 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3444 reason from here.
3445 (SignalException): To here. Signal using sim_engine_halt.
3446 (sim_stop_reason): Delete, moved to common.
72f4393d 3447
c906108c
SS		 3448Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3449
3450 * interp.c (sim_open): Add callback argument.
3451 (sim_set_callbacks): Delete SIM_DESC argument.
3452 (sim_size): Ditto.
3453
3454Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3455
3456 * Makefile.in (SIM_OBJS): Add common modules.
3457
3458 * interp.c (sim_set_callbacks): Also set SD callback.
3459 (set_endianness, xfer_*, swap_*): Delete.
3460 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3461 Change to functions using sim-endian macros.
3462 (control_c, sim_stop): Delete, use common version.
3463 (simulate): Convert into.
3464 (sim_engine_run): This function.
3465 (sim_resume): Delete.
72f4393d 3466
c906108c
SS		 3467 * interp.c (simulation): New variable - the simulator object.
3468 (sim_kind): Delete global - merged into simulation.
3469 (sim_load): Cleanup. Move PC assignment from here.
3470 (sim_create_inferior): To here.
3471
3472 * sim-main.h: New file.
3473 * interp.c (sim-main.h): Include.
72f4393d 3474
c906108c
SS		 3475Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3476
3477 * configure: Regenerated to track ../common/aclocal.m4 changes.
3478
3479Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3480
3481 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3482
3483Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3484
72f4393d
L		 3485 * gencode.c (build_instruction): DIV instructions: check
3486 for division by zero and integer overflow before using
c906108c
SS		 3487 host's division operation.
3488
3489Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3490
3491 * Makefile.in (SIM_OBJS): Add sim-load.o.
3492 * interp.c: #include bfd.h.
3493 (target_byte_order): Delete.
3494 (sim_kind, myname, big_endian_p): New static locals.
3495 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3496 after argument parsing. Recognize -E arg, set endianness accordingly.
3497 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3498 load file into simulator. Set PC from bfd.
3499 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3500 (set_endianness): Use big_endian_p instead of target_byte_order.
3501
3502Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3503
3504 * interp.c (sim_size): Delete prototype - conflicts with
3505 definition in remote-sim.h. Correct definition.
3506
3507Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3508
3509 * configure: Regenerated to track ../common/aclocal.m4 changes.
3510 * config.in: Ditto.
3511
3512Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3513
3514 * interp.c (sim_open): New arg `kind'.
3515
3516 * configure: Regenerated to track ../common/aclocal.m4 changes.
3517
3518Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3519
3520 * configure: Regenerated to track ../common/aclocal.m4 changes.
3521
3522Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3523
3524 * interp.c (sim_open): Set optind to 0 before calling getopt.
3525
3526Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3527
3528 * configure: Regenerated to track ../common/aclocal.m4 changes.
3529
3530Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3531
3532 * interp.c : Replace uses of pr_addr with pr_uword64
3533 where the bit length is always 64 independent of SIM_ADDR.
3534 (pr_uword64) : added.
3535
3536Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3537
3538 * configure: Re-generate.
3539
3540Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3541
3542 * configure: Regenerate to track ../common/aclocal.m4 changes.
3543
3544Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3545
3546 * interp.c (sim_open): New SIM_DESC result. Argument is now
3547 in argv form.
3548 (other sim_*): New SIM_DESC argument.
3549
3550Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3551
3552 * interp.c: Fix printing of addresses for non-64-bit targets.
3553 (pr_addr): Add function to print address based on size.
3554
3555Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3556
3557 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3558
3559Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3560
3561 * gencode.c (build_mips16_operands): Correct computation of base
3562 address for extended PC relative instruction.
3563
3564Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3565
3566 * interp.c (mips16_entry): Add support for floating point cases.
3567 (SignalException): Pass floating point cases to mips16_entry.
3568 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3569 registers.
3570 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3571 or fmt_word.
3572 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3573 and then set the state to fmt_uninterpreted.
3574 (COP_SW): Temporarily set the state to fmt_word while calling
3575 ValueFPR.
3576
3577Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3578
3579 * gencode.c (build_instruction): The high order may be set in the
3580 comparison flags at any ISA level, not just ISA 4.
3581
3582Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3583
3584 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3585 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3586 * configure.in: sinclude ../common/aclocal.m4.
3587 * configure: Regenerated.
3588
3589Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3590
3591 * configure: Rebuild after change to aclocal.m4.
3592
3593Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3594
3595 * configure configure.in Makefile.in: Update to new configure
3596 scheme which is more compatible with WinGDB builds.
3597 * configure.in: Improve comment on how to run autoconf.
3598 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3599 * Makefile.in: Use autoconf substitution to install common
3600 makefile fragment.
3601
3602Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3603
3604 * gencode.c (build_instruction): Use BigEndianCPU instead of
3605 ByteSwapMem.
3606
3607Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3608
3609 * interp.c (sim_monitor): Make output to stdout visible in
3610 wingdb's I/O log window.
3611
3612Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3613
3614 * support.h: Undo previous change to SIGTRAP
3615 and SIGQUIT values.
3616
3617Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3618
3619 * interp.c (store_word, load_word): New static functions.
3620 (mips16_entry): New static function.
3621 (SignalException): Look for mips16 entry and exit instructions.
3622 (simulate): Use the correct index when setting fpr_state after
3623 doing a pending move.
3624
3625Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3626
3627 * interp.c: Fix byte-swapping code throughout to work on
3628 both little- and big-endian hosts.
3629
3630Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3631
3632 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3633 with gdb/config/i386/xm-windows.h.
3634
3635Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3636
3637 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3638 that messes up arithmetic shifts.
3639
3640Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3641
3642 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3643 SIGTRAP and SIGQUIT for _WIN32.
3644
3645Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3646
3647 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3648 force a 64 bit multiplication.
3649 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3650 destination register is 0, since that is the default mips16 nop
3651 instruction.
3652
3653Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3654
3655 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3656 (build_endian_shift): Don't check proc64.
3657 (build_instruction): Always set memval to uword64. Cast op2 to
3658 uword64 when shifting it left in memory instructions. Always use
3659 the same code for stores--don't special case proc64.
3660
3661 * gencode.c (build_mips16_operands): Fix base PC value for PC
3662 relative operands.
3663 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3664 jal instruction.
3665 * interp.c (simJALDELAYSLOT): Define.
3666 (JALDELAYSLOT): Define.
3667 (INDELAYSLOT, INJALDELAYSLOT): Define.
3668 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3669
3670Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3671
3672 * interp.c (sim_open): add flush_cache as a PMON routine
3673 (sim_monitor): handle flush_cache by ignoring it
3674
3675Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3676
3677 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3678 BigEndianMem.
3679 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3680 (BigEndianMem): Rename to ByteSwapMem and change sense.
3681 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3682 BigEndianMem references to !ByteSwapMem.
3683 (set_endianness): New function, with prototype.
3684 (sim_open): Call set_endianness.
3685 (sim_info): Use simBE instead of BigEndianMem.
3686 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3687 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3688 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3689 ifdefs, keeping the prototype declaration.
3690 (swap_word): Rewrite correctly.
3691 (ColdReset): Delete references to CONFIG. Delete endianness related
3692 code; moved to set_endianness.
72f4393d 3693
c906108c
SS		 3694Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3695
3696 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3697 * interp.c (CHECKHILO): Define away.
3698 (simSIGINT): New macro.
3699 (membank_size): Increase from 1MB to 2MB.
3700 (control_c): New function.
3701 (sim_resume): Rename parameter signal to signal_number. Add local
3702 variable prev. Call signal before and after simulate.
3703 (sim_stop_reason): Add simSIGINT support.
3704 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3705 functions always.
3706 (sim_warning): Delete call to SignalException. Do call printf_filtered
3707 if logfh is NULL.
3708 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3709 a call to sim_warning.
3710
3711Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3712
3713 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3714 16 bit instructions.
3715
3716Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3717
3718 Add support for mips16 (16 bit MIPS implementation):
3719 * gencode.c (inst_type): Add mips16 instruction encoding types.
3720 (GETDATASIZEINSN): Define.
3721 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3722 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3723 mtlo.
3724 (MIPS16_DECODE): New table, for mips16 instructions.
3725 (bitmap_val): New static function.
3726 (struct mips16_op): Define.
3727 (mips16_op_table): New table, for mips16 operands.
3728 (build_mips16_operands): New static function.
3729 (process_instructions): If PC is odd, decode a mips16
3730 instruction. Break out instruction handling into new
3731 build_instruction function.
3732 (build_instruction): New static function, broken out of
3733 process_instructions. Check modifiers rather than flags for SHIFT
3734 bit count and m[ft]{hi,lo} direction.
3735 (usage): Pass program name to fprintf.
3736 (main): Remove unused variable this_option_optind. Change
3737 ``*loptarg++'' to ``loptarg++''.
3738 (my_strtoul): Parenthesize && within ||.
3739 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3740 (simulate): If PC is odd, fetch a 16 bit instruction, and
3741 increment PC by 2 rather than 4.
3742 * configure.in: Add case for mips16*-*-*.
3743 * configure: Rebuild.
3744
3745Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3746
3747 * interp.c: Allow -t to enable tracing in standalone simulator.
3748 Fix garbage output in trace file and error messages.
3749
3750Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3751
3752 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3753 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3754 * configure.in: Simplify using macros in ../common/aclocal.m4.
3755 * configure: Regenerated.
3756 * tconfig.in: New file.
3757
3758Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3759
3760 * interp.c: Fix bugs in 64-bit port.
3761 Use ansi function declarations for msvc compiler.
3762 Initialize and test file pointer in trace code.
3763 Prevent duplicate definition of LAST_EMED_REGNUM.
3764
3765Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3766
3767 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3768
3769Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3770
3771 * interp.c (SignalException): Check for explicit terminating
3772 breakpoint value.
3773 * gencode.c: Pass instruction value through SignalException()
3774 calls for Trap, Breakpoint and Syscall.
3775
3776Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3777
3778 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3779 only used on those hosts that provide it.
3780 * configure.in: Add sqrt() to list of functions to be checked for.
3781 * config.in: Re-generated.
3782 * configure: Re-generated.
3783
3784Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3785
3786 * gencode.c (process_instructions): Call build_endian_shift when
3787 expanding STORE RIGHT, to fix swr.
3788 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3789 clear the high bits.
3790 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3791 Fix float to int conversions to produce signed values.
3792
3793Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3794
3795 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3796 (process_instructions): Correct handling of nor instruction.
3797 Correct shift count for 32 bit shift instructions. Correct sign
3798 extension for arithmetic shifts to not shift the number of bits in
3799 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3800 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3801 Fix madd.
3802 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3803 It's OK to have a mult follow a mult. What's not OK is to have a
3804 mult follow an mfhi.
3805 (Convert): Comment out incorrect rounding code.
3806
3807Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3808
3809 * interp.c (sim_monitor): Improved monitor printf
3810 simulation. Tidied up simulator warnings, and added "--log" option
3811 for directing warning message output.
3812 * gencode.c: Use sim_warning() rather than WARNING macro.
3813
3814Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3815
3816 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3817 getopt1.o, rather than on gencode.c. Link objects together.
3818 Don't link against -liberty.
3819 (gencode.o, getopt.o, getopt1.o): New targets.
3820 * gencode.c: Include <ctype.h> and "ansidecl.h".
3821 (AND): Undefine after including "ansidecl.h".
3822 (ULONG_MAX): Define if not defined.
3823 (OP_*): Don't define macros; now defined in opcode/mips.h.
3824 (main): Call my_strtoul rather than strtoul.
3825 (my_strtoul): New static function.
3826
3827Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3828
3829 * gencode.c (process_instructions): Generate word64 and uword64
3830 instead of `long long' and `unsigned long long' data types.
3831 * interp.c: #include sysdep.h to get signals, and define default
3832 for SIGBUS.
3833 * (Convert): Work around for Visual-C++ compiler bug with type
3834 conversion.
3835 * support.h: Make things compile under Visual-C++ by using
3836 __int64 instead of `long long'. Change many refs to long long
3837 into word64/uword64 typedefs.
3838
3839Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3840
72f4393d
L		 3841 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3842 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3843 (docdir): Removed.
3844 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3845 (AC_PROG_INSTALL): Added.
c906108c 3846 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3847 * configure: Rebuilt.
3848
c906108c
SS		 3849Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3850
3851 * configure.in: Define @SIMCONF@ depending on mips target.
3852 * configure: Rebuild.
3853 * Makefile.in (run): Add @SIMCONF@ to control simulator
3854 construction.
3855 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3856 * interp.c: Remove some debugging, provide more detailed error
3857 messages, update memory accesses to use LOADDRMASK.
72f4393d 3858
c906108c
SS		 3859Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3860
3861 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3862 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3863 stamp-h.
3864 * configure: Rebuild.
3865 * config.in: New file, generated by autoheader.
3866 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3867 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3868 HAVE_ANINT and HAVE_AINT, as appropriate.
3869 * Makefile.in (run): Use @LIBS@ rather than -lm.
3870 (interp.o): Depend upon config.h.
3871 (Makefile): Just rebuild Makefile.
3872 (clean): Remove stamp-h.
3873 (mostlyclean): Make the same as clean, not as distclean.
3874 (config.h, stamp-h): New targets.
3875
3876Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3877
3878 * interp.c (ColdReset): Fix boolean test. Make all simulator
3879 globals static.
3880
3881Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3882
3883 * interp.c (xfer_direct_word, xfer_direct_long,
3884 swap_direct_word, swap_direct_long, xfer_big_word,
3885 xfer_big_long, xfer_little_word, xfer_little_long,
3886 swap_word,swap_long): Added.
3887 * interp.c (ColdReset): Provide function indirection to
3888 host<->simulated_target transfer routines.
3889 * interp.c (sim_store_register, sim_fetch_register): Updated to
3890 make use of indirected transfer routines.
3891
3892Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3893
3894 * gencode.c (process_instructions): Ensure FP ABS instruction
3895 recognised.
3896 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3897 system call support.
3898
3899Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3900
3901 * interp.c (sim_do_command): Complain if callback structure not
3902 initialised.
3903
3904Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3905
3906 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3907 support for Sun hosts.
3908 * Makefile.in (gencode): Ensure the host compiler and libraries
3909 used for cross-hosted build.
3910
3911Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3912
3913 * interp.c, gencode.c: Some more (TODO) tidying.
3914
3915Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3916
3917 * gencode.c, interp.c: Replaced explicit long long references with
3918 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3919 * support.h (SET64LO, SET64HI): Macros added.
3920
3921Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3922
3923 * configure: Regenerate with autoconf 2.7.
3924
3925Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3926
3927 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3928 * support.h: Remove superfluous "1" from #if.
3929 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3930
3931Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3932
3933 * interp.c (StoreFPR): Control UndefinedResult() call on
3934 WARN_RESULT manifest.
3935
3936Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3937
3938 * gencode.c: Tidied instruction decoding, and added FP instruction
3939 support.
3940
3941 * interp.c: Added dineroIII, and BSD profiling support. Also
3942 run-time FP handling.
3943
3944Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3945
3946 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3947 gencode.c, interp.c, support.h: created.
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