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sim: bfin/msp430: drop run-sim.h include
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
ae7d0cac
MF		 12015-03-16 Mike Frysinger <vapier@gentoo.org>
2
3 * config.in, configure: Regenerate.
4 * tconfig.in: Rename file ...
5 * tconfig.h: ... here.
6
8406bb59
MF		 72015-03-15 Mike Frysinger <vapier@gentoo.org>
8
9 * tconfig.in: Delete includes.
10 [HAVE_DV_SOCKSER]: Delete.
11
465fb143
MF		 122015-03-14 Mike Frysinger <vapier@gentoo.org>
13
14 * Makefile.in (SIM_RUN_OBJS): Delete.
15
5cddc23a
MF		 162015-03-14 Mike Frysinger <vapier@gentoo.org>
17
18 * configure.ac (AC_CHECK_HEADERS): Delete.
19 * aclocal.m4, configure: Regenerate.
20
2974be62
AM		 212014-08-19 Alan Modra <amodra@gmail.com>
22
23 * configure: Regenerate.
24
faa743bb
RM		 252014-08-15 Roland McGrath <mcgrathr@google.com>
26
27 * configure: Regenerate.
28 * config.in: Regenerate.
29
1a8a700e
MF		 302014-03-04 Mike Frysinger <vapier@gentoo.org>
31
32 * configure: Regenerate.
33
bf3d9781
AM		 342013-09-23 Alan Modra <amodra@gmail.com>
35
36 * configure: Regenerate.
37
31e6ad7d
MF		 382013-06-03 Mike Frysinger <vapier@gentoo.org>
39
40 * aclocal.m4, configure: Regenerate.
41
d3685d60
TT		 422013-05-10 Freddie Chopin <freddie_chopin@op.pl>
43
44 * configure: Rebuild.
45
1517bd27
MF		 462013-03-26 Mike Frysinger <vapier@gentoo.org>
47
48 * configure: Regenerate.
49
3be31516
JS		 502013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
51
52 * configure.ac: Address use of dv-sockser.o.
53 * tconfig.in: Conditionalize use of dv_sockser_install.
54 * configure: Regenerated.
55 * config.in: Regenerated.
56
37cb8f8e
SE		 572012-10-04 Chao-ying Fu <fu@mips.com>
58 Steve Ellcey <sellcey@mips.com>
59
60 * mips/mips3264r2.igen (rdhwr): New.
61
87c8644f
JS		 622012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
63
64 * configure.ac: Always link against dv-sockser.o.
65 * configure: Regenerate.
66
5f3ef9d0
JB		 672012-06-15 Joel Brobecker <brobecker@adacore.com>
68
69 * config.in, configure: Regenerate.
70
a6ff997c
NC		 712012-05-18 Nick Clifton <nickc@redhat.com>
72
73 PR 14072
74 * interp.c: Include config.h before system header files.
75
2232061b
MF		 762012-03-24 Mike Frysinger <vapier@gentoo.org>
77
78 * aclocal.m4, config.in, configure: Regenerate.
79
db2e4d67
MF		 802011-12-03 Mike Frysinger <vapier@gentoo.org>
81
82 * aclocal.m4: New file.
83 * configure: Regenerate.
84
4399a56b
MF		 852011-10-19 Mike Frysinger <vapier@gentoo.org>
86
87 * configure: Regenerate after common/acinclude.m4 update.
88
9c082ca8
MF		 892011-10-17 Mike Frysinger <vapier@gentoo.org>
90
91 * configure.ac: Change include to common/acinclude.m4.
92
6ffe910a
MF		 932011-10-17 Mike Frysinger <vapier@gentoo.org>
94
95 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
96 call. Replace common.m4 include with SIM_AC_COMMON.
97 * configure: Regenerate.
98
31b28250
HPN		 992011-07-08 Hans-Peter Nilsson <hp@axis.com>
100
3faa01e3
HPN		 101 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
102 $(SIM_EXTRA_DEPS).
103 (tmp-mach-multi): Exit early when igen fails.
31b28250 104
2419798b
MF		 1052011-07-05 Mike Frysinger <vapier@gentoo.org>
106
107 * interp.c (sim_do_command): Delete.
108
d79fe0d6
MF		 1092011-02-14 Mike Frysinger <vapier@gentoo.org>
110
111 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
112 (tx3904sio_fifo_reset): Likewise.
113 * interp.c (sim_monitor): Likewise.
114
5558e7e6
MF		 1152010-04-14 Mike Frysinger <vapier@gentoo.org>
116
117 * interp.c (sim_write): Add const to buffer arg.
118
35aafff4
JB		 1192010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
120
121 * interp.c: Don't include sysdep.h
122
3725885a
RW		 1232010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
124
125 * configure: Regenerate.
126
d6416cdc
RW		 1272009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
128
81ecdfbb
RW		 129 * config.in: Regenerate.
130 * configure: Likewise.
131
d6416cdc
RW		 132 * configure: Regenerate.
133
b5bd9624
HPN		 1342008-07-11 Hans-Peter Nilsson <hp@axis.com>
135
136 * configure: Regenerate to track ../common/common.m4 changes.
137 * config.in: Ditto.
138
6efef468
JM		 1392008-06-06 Vladimir Prus <vladimir@codesourcery.com>
140 Daniel Jacobowitz <dan@codesourcery.com>
141 Joseph Myers <joseph@codesourcery.com>
142
143 * configure: Regenerate.
144
60dc88db
RS		 1452007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
146
147 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
148 that unconditionally allows fmt_ps.
149 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
150 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
151 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
152 filter from 64,f to 32,f.
153 (PREFX): Change filter from 64 to 32.
154 (LDXC1, LUXC1): Provide separate mips32r2 implementations
155 that use do_load_double instead of do_load. Make both LUXC1
156 versions unpredictable if SizeFGR () != 64.
157 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
158 instead of do_store. Remove unused variable. Make both SUXC1
159 versions unpredictable if SizeFGR () != 64.
160
599ca73e
RS		 1612007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
162
163 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
164 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
165 shifts for that case.
166
2525df03
NC		 1672007-09-04 Nick Clifton <nickc@redhat.com>
168
169 * interp.c (options enum): Add OPTION_INFO_MEMORY.
170 (display_mem_info): New static variable.
171 (mips_option_handler): Handle OPTION_INFO_MEMORY.
172 (mips_options): Add info-memory and memory-info.
173 (sim_open): After processing the command line and board
174 specification, check display_mem_info. If it is set then
175 call the real handler for the --memory-info command line
176 switch.
177
35ee6e1e
JB		 1782007-08-24 Joel Brobecker <brobecker@adacore.com>
179
180 * configure.ac: Change license of multi-run.c to GPL version 3.
181 * configure: Regenerate.
182
d5fb0879
RS		 1832007-06-28 Richard Sandiford <richard@codesourcery.com>
184
185 * configure.ac, configure: Revert last patch.
186
2a2ce21b
RS		 1872007-06-26 Richard Sandiford <richard@codesourcery.com>
188
189 * configure.ac (sim_mipsisa3264_configs): New variable.
190 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
191 every configuration support all four targets, using the triplet to
192 determine the default.
193 * configure: Regenerate.
194
efdcccc9
RS		 1952007-06-25 Richard Sandiford <richard@codesourcery.com>
196
0a7692b2 197 * Makefile.in (m16run.o): New rule.
efdcccc9 198
f532a356
TS		 1992007-05-15 Thiemo Seufer <ths@mips.com>
200
201 * mips3264r2.igen (DSHD): Fix compile warning.
202
bfe9c90b
TS		 2032007-05-14 Thiemo Seufer <ths@mips.com>
204
205 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
206 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
207 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
208 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
209 for mips32r2.
210
53f4826b
TS		 2112007-03-01 Thiemo Seufer <ths@mips.com>
212
213 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
214 and mips64.
215
8bf3ddc8
TS		 2162007-02-20 Thiemo Seufer <ths@mips.com>
217
218 * dsp.igen: Update copyright notice.
219 * dsp2.igen: Fix copyright notice.
220
8b082fb1
TS		 2212007-02-20 Thiemo Seufer <ths@mips.com>
222 Chao-Ying Fu <fu@mips.com>
223
224 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
225 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
226 Add dsp2 to sim_igen_machine.
227 * configure: Regenerate.
228 * dsp.igen (do_ph_op): Add MUL support when op = 2.
229 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
230 (mulq_rs.ph): Use do_ph_mulq.
231 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
232 * mips.igen: Add dsp2 model and include dsp2.igen.
233 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
234 for *mips32r2, *mips64r2, *dsp.
235 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
236 for *mips32r2, *mips64r2, *dsp2.
237 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
238
b1004875
TS		 2392007-02-19 Thiemo Seufer <ths@mips.com>
240 Nigel Stephens <nigel@mips.com>
241
242 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
243 jumps with hazard barrier.
244
f8df4c77
TS		 2452007-02-19 Thiemo Seufer <ths@mips.com>
246 Nigel Stephens <nigel@mips.com>
247
248 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
249 after each call to sim_io_write.
250
b1004875 2512007-02-19 Thiemo Seufer <ths@mips.com>
07802d98 252 Nigel Stephens <nigel@mips.com>
b1004875
TS		 253
254 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
255 supported by this simulator.
07802d98
TS		 256 (decode_coproc): Recognise additional CP0 Config registers
257 correctly.
258
14fb6c5a
TS		 2592007-02-19 Thiemo Seufer <ths@mips.com>
260 Nigel Stephens <nigel@mips.com>
261 David Ung <davidu@mips.com>
262
263 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
264 uninterpreted formats. If fmt is one of the uninterpreted types
265 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
266 fmt_word, and fmt_uninterpreted_64 like fmt_long.
267 (store_fpr): When writing an invalid odd register, set the
268 matching even register to fmt_unknown, not the following register.
269 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
270 the the memory window at offset 0 set by --memory-size command
271 line option.
272 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
273 point register.
274 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
275 register.
276 (sim_monitor): When returning the memory size to the MIPS
277 application, use the value in STATE_MEM_SIZE, not an arbitrary
278 hardcoded value.
279 (cop_lw): Don' mess around with FPR_STATE, just pass
280 fmt_uninterpreted_32 to StoreFPR.
281 (cop_sw): Similarly.
282 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
283 (cop_sd): Similarly.
284 * mips.igen (not_word_value): Single version for mips32, mips64
285 and mips16.
286
c8847145
TS		 2872007-02-19 Thiemo Seufer <ths@mips.com>
288 Nigel Stephens <nigel@mips.com>
289
290 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
291 MBytes.
292
4b5d35ee
TS		 2932007-02-17 Thiemo Seufer <ths@mips.com>
294
295 * configure.ac (mips*-sde-elf*): Move in front of generic machine
296 configuration.
297 * configure: Regenerate.
298
3669427c
TS		 2992007-02-17 Thiemo Seufer <ths@mips.com>
300
301 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
302 Add mdmx to sim_igen_machine.
303 (mipsisa64*-*-*): Likewise. Remove dsp.
304 (mipsisa32*-*-*): Remove dsp.
305 * configure: Regenerate.
306
109ad085
TS		 3072007-02-13 Thiemo Seufer <ths@mips.com>
308
309 * configure.ac: Add mips*-sde-elf* target.
310 * configure: Regenerate.
311
921d7ad3
HPN		 3122006-12-21 Hans-Peter Nilsson <hp@axis.com>
313
314 * acconfig.h: Remove.
315 * config.in, configure: Regenerate.
316
02f97da7
TS		 3172006-11-07 Thiemo Seufer <ths@mips.com>
318
319 * dsp.igen (do_w_op): Fix compiler warning.
320
2d2733fc
TS		 3212006-08-29 Thiemo Seufer <ths@mips.com>
322 David Ung <davidu@mips.com>
323
324 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
325 sim_igen_machine.
326 * configure: Regenerate.
327 * mips.igen (model): Add smartmips.
328 (MADDU): Increment ACX if carry.
329 (do_mult): Clear ACX.
330 (ROR,RORV): Add smartmips.
331 (include): Include smartmips.igen.
332 * sim-main.h (ACX): Set to REGISTERS[89].
333 * smartmips.igen: New file.
334
d85c3a10
TS		 3352006-08-29 Thiemo Seufer <ths@mips.com>
336 David Ung <davidu@mips.com>
337
338 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
339 mips3264r2.igen. Add missing dependency rules.
340 * m16e.igen: Support for mips16e save/restore instructions.
341
e85e3205
RE		 3422006-06-13 Richard Earnshaw <rearnsha@arm.com>
343
344 * configure: Regenerated.
345
2f0122dc
DJ		 3462006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
347
348 * configure: Regenerated.
349
20e95c23
DJ		 3502006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
351
352 * configure: Regenerated.
353
69088b17
CF		 3542006-05-15 Chao-ying Fu <fu@mips.com>
355
356 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
357
0275de4e
NC		 3582006-04-18 Nick Clifton <nickc@redhat.com>
359
360 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
361 statement.
362
b3a3ffef
HPN		 3632006-03-29 Hans-Peter Nilsson <hp@axis.com>
364
365 * configure: Regenerate.
366
40a5538e
CF		 3672005-12-14 Chao-ying Fu <fu@mips.com>
368
369 * Makefile.in (SIM_OBJS): Add dsp.o.
370 (dsp.o): New dependency.
371 (IGEN_INCLUDE): Add dsp.igen.
372 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
373 mipsisa64*-*-*): Add dsp to sim_igen_machine.
374 * configure: Regenerate.
375 * mips.igen: Add dsp model and include dsp.igen.
376 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
377 because these instructions are extended in DSP ASE.
378 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
379 adding 6 DSP accumulator registers and 1 DSP control register.
380 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
381 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
382 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
383 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
384 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
385 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
386 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
387 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
388 DSPCR_CCOND_SMASK): New define.
389 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
390 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
391
21d14896
ILT		 3922005-07-08 Ian Lance Taylor <ian@airs.com>
393
394 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
395
b16d63da
DU		 3962005-06-16 David Ung <davidu@mips.com>
397 Nigel Stephens <nigel@mips.com>
398
399 * mips.igen: New mips16e model and include m16e.igen.
400 (check_u64): Add mips16e tag.
401 * m16e.igen: New file for MIPS16e instructions.
402 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
403 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
404 models.
405 * configure: Regenerate.
406
e70cb6cd
CD		 4072005-05-26 David Ung <davidu@mips.com>
408
409 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
410 tags to all instructions which are applicable to the new ISAs.
411 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
412 vr.igen.
413 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
414 instructions.
415 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
416 to mips.igen.
417 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
418 * configure: Regenerate.
419
2b193c4a
MK		 4202005-03-23 Mark Kettenis <kettenis@gnu.org>
421
422 * configure: Regenerate.
423
35695fd6
AC		 4242005-01-14 Andrew Cagney <cagney@gnu.org>
425
426 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
427 explicit call to AC_CONFIG_HEADER.
428 * configure: Regenerate.
429
f0569246
AC		 4302005-01-12 Andrew Cagney <cagney@gnu.org>
431
432 * configure.ac: Update to use ../common/common.m4.
433 * configure: Re-generate.
434
38f48d72
AC		 4352005-01-11 Andrew Cagney <cagney@localhost.localdomain>
436
437 * configure: Regenerated to track ../common/aclocal.m4 changes.
438
b7026657
AC		 4392005-01-07 Andrew Cagney <cagney@gnu.org>
440
441 * configure.ac: Rename configure.in, require autoconf 2.59.
442 * configure: Re-generate.
443
379832de
HPN		 4442004-12-08 Hans-Peter Nilsson <hp@axis.com>
445
446 * configure: Regenerate for ../common/aclocal.m4 update.
447
cd62154c
AC		 4482004-09-24 Monika Chaddha <monika@acmet.com>
449
450 Committed by Andrew Cagney.
451 * m16.igen (CMP, CMPI): Fix assembler.
452
e5da76ec
CD		 4532004-08-18 Chris Demetriou <cgd@broadcom.com>
454
455 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
456 * configure: Regenerate.
457
139181c8
CD		 4582004-06-25 Chris Demetriou <cgd@broadcom.com>
459
460 * configure.in (sim_m16_machine): Include mipsIII.
461 * configure: Regenerate.
462
1a27f959
CD		 4632004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
464
465 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
466 from COP0_BADVADDR.
467 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
468
5dbb7b5a
CD		 4692004-04-10 Chris Demetriou <cgd@broadcom.com>
470
471 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
472
14234056
CD		 4732004-04-09 Chris Demetriou <cgd@broadcom.com>
474
475 * mips.igen (check_fmt): Remove.
476 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
477 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
478 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
479 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
480 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
481 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
482 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
483 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
484 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
485 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
486
c6f9085c
CD		 4872004-04-09 Chris Demetriou <cgd@broadcom.com>
488
489 * sb1.igen (check_sbx): New function.
490 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
491
11d66e66 4922004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 493 Richard Sandiford <rsandifo@redhat.com>
494
495 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
496 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
497 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
498 separate implementations for mipsIV and mipsV. Use new macros to
499 determine whether the restrictions apply.
500
b3208fb8
CD		 5012004-01-19 Chris Demetriou <cgd@broadcom.com>
502
503 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
504 (check_mult_hilo): Improve comments.
505 (check_div_hilo): Likewise. Also, fork off a new version
506 to handle mips32/mips64 (since there are no hazards to check
507 in MIPS32/MIPS64).
508
9a1d84fb
CD		 5092003-06-17 Richard Sandiford <rsandifo@redhat.com>
510
511 * mips.igen (do_dmultx): Fix check for negative operands.
512
ae451ac6
ILT		 5132003-05-16 Ian Lance Taylor <ian@airs.com>
514
515 * Makefile.in (SHELL): Make sure this is defined.
516 (various): Use $(SHELL) whenever we invoke move-if-change.
517
dd69d292
CD		 5182003-05-03 Chris Demetriou <cgd@broadcom.com>
519
520 * cp1.c: Tweak attribution slightly.
521 * cp1.h: Likewise.
522 * mdmx.c: Likewise.
523 * mdmx.igen: Likewise.
524 * mips3d.igen: Likewise.
525 * sb1.igen: Likewise.
526
bcd0068e
CD		 5272003-04-15 Richard Sandiford <rsandifo@redhat.com>
528
529 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
530 unsigned operands.
531
6b4a8935
AC		 5322003-02-27 Andrew Cagney <cagney@redhat.com>
533
601da316
AC		 534 * interp.c (sim_open): Rename _bfd to bfd.
535 (sim_create_inferior): Ditto.
6b4a8935 536
d29e330f
CD		 5372003-01-14 Chris Demetriou <cgd@broadcom.com>
538
539 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
540
a2353a08
CD		 5412003-01-14 Chris Demetriou <cgd@broadcom.com>
542
543 * mips.igen (EI, DI): Remove.
544
80551777
CD		 5452003-01-05 Richard Sandiford <rsandifo@redhat.com>
546
547 * Makefile.in (tmp-run-multi): Fix mips16 filter.
548
4c54fc26
CD		 5492003-01-04 Richard Sandiford <rsandifo@redhat.com>
550 Andrew Cagney <ac131313@redhat.com>
551 Gavin Romig-Koch <gavin@redhat.com>
552 Graydon Hoare <graydon@redhat.com>
553 Aldy Hernandez <aldyh@redhat.com>
554 Dave Brolley <brolley@redhat.com>
555 Chris Demetriou <cgd@broadcom.com>
556
557 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
558 (sim_mach_default): New variable.
559 (mips64vr-*-*, mips64vrel-*-*): New configurations.
560 Add a new simulator generator, MULTI.
561 * configure: Regenerate.
562 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
563 (multi-run.o): New dependency.
564 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
565 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
566 (tmp-multi): Combine them.
567 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
568 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
569 (distclean-extra): New rule.
570 * sim-main.h: Include bfd.h.
571 (MIPS_MACH): New macro.
572 * mips.igen (vr4120, vr5400, vr5500): New models.
573 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
574 * vr.igen: Replace with new version.
575
e6c674b8
CD		 5762003-01-04 Chris Demetriou <cgd@broadcom.com>
577
578 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
579 * configure: Regenerate.
580
28f50ac8
CD		 5812002-12-31 Chris Demetriou <cgd@broadcom.com>
582
583 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
584 * mips.igen: Remove all invocations of check_branch_bug and
585 mark_branch_bug.
586
5071ffe6
CD		 5872002-12-16 Chris Demetriou <cgd@broadcom.com>
588
589 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
590
06e7837e
CD		 5912002-07-30 Chris Demetriou <cgd@broadcom.com>
592
593 * mips.igen (do_load_double, do_store_double): New functions.
594 (LDC1, SDC1): Rename to...
595 (LDC1b, SDC1b): respectively.
596 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
597
2265c243
MS		 5982002-07-29 Michael Snyder <msnyder@redhat.com>
599
600 * cp1.c (fp_recip2): Modify initialization expression so that
601 GCC will recognize it as constant.
602
a2f8b4f3
CD		 6032002-06-18 Chris Demetriou <cgd@broadcom.com>
604
605 * mdmx.c (SD_): Delete.
606 (Unpredictable): Re-define, for now, to directly invoke
607 unpredictable_action().
608 (mdmx_acc_op): Fix error in .ob immediate handling.
609
b4b6c939
AC		 6102002-06-18 Andrew Cagney <cagney@redhat.com>
611
612 * interp.c (sim_firmware_command): Initialize `address'.
613
c8cca39f
AC		 6142002-06-16 Andrew Cagney <ac131313@redhat.com>
615
616 * configure: Regenerated to track ../common/aclocal.m4 changes.
617
e7e81181
CD		 6182002-06-14 Chris Demetriou <cgd@broadcom.com>
619 Ed Satterthwaite <ehs@broadcom.com>
620
621 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
622 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
623 * mips.igen: Include mips3d.igen.
624 (mips3d): New model name for MIPS-3D ASE instructions.
625 (CVT.W.fmt): Don't use this instruction for word (source) format
626 instructions.
627 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
628 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
629 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
630 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
631 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
632 (RSquareRoot1, RSquareRoot2): New macros.
633 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
634 (fp_rsqrt2): New functions.
635 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
636 * configure: Regenerate.
637
3a2b820e 6382002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 639 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 640
641 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
642 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
643 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
644 (convert): Note that this function is not used for paired-single
645 format conversions.
646 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
647 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
648 (check_fmt_p): Enable paired-single support.
649 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
650 (PUU.PS): New instructions.
651 (CVT.S.fmt): Don't use this instruction for paired-single format
652 destinations.
653 * sim-main.h (FP_formats): New value 'fmt_ps.'
654 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
655 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
656
d18ea9c2
CD		 6572002-06-12 Chris Demetriou <cgd@broadcom.com>
658
659 * mips.igen: Fix formatting of function calls in
660 many FP operations.
661
95fd5cee
CD		 6622002-06-12 Chris Demetriou <cgd@broadcom.com>
663
664 * mips.igen (MOVN, MOVZ): Trace result.
665 (TNEI): Print "tnei" as the opcode name in traces.
666 (CEIL.W): Add disassembly string for traces.
667 (RSQRT.fmt): Make location of disassembly string consistent
668 with other instructions.
669
4f0d55ae
CD		 6702002-06-12 Chris Demetriou <cgd@broadcom.com>
671
672 * mips.igen (X): Delete unused function.
673
3c25f8c7
AC		 6742002-06-08 Andrew Cagney <cagney@redhat.com>
675
676 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
677
f3c08b7e
CD		 6782002-06-07 Chris Demetriou <cgd@broadcom.com>
679 Ed Satterthwaite <ehs@broadcom.com>
680
681 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
682 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
683 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
684 (fp_nmsub): New prototypes.
685 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
686 (NegMultiplySub): New defines.
687 * mips.igen (RSQRT.fmt): Use RSquareRoot().
688 (MADD.D, MADD.S): Replace with...
689 (MADD.fmt): New instruction.
690 (MSUB.D, MSUB.S): Replace with...
691 (MSUB.fmt): New instruction.
692 (NMADD.D, NMADD.S): Replace with...
693 (NMADD.fmt): New instruction.
694 (NMSUB.D, MSUB.S): Replace with...
695 (NMSUB.fmt): New instruction.
696
52714ff9
CD		 6972002-06-07 Chris Demetriou <cgd@broadcom.com>
698 Ed Satterthwaite <ehs@broadcom.com>
699
700 * cp1.c: Fix more comment spelling and formatting.
701 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
702 (denorm_mode): New function.
703 (fpu_unary, fpu_binary): Round results after operation, collect
704 status from rounding operations, and update the FCSR.
705 (convert): Collect status from integer conversions and rounding
706 operations, and update the FCSR. Adjust NaN values that result
707 from conversions. Convert to use sim_io_eprintf rather than
708 fprintf, and remove some debugging code.
709 * cp1.h (fenr_FS): New define.
710
577d8c4b
CD		 7112002-06-07 Chris Demetriou <cgd@broadcom.com>
712
713 * cp1.c (convert): Remove unusable debugging code, and move MIPS
714 rounding mode to sim FP rounding mode flag conversion code into...
715 (rounding_mode): New function.
716
196496ed
CD		 7172002-06-07 Chris Demetriou <cgd@broadcom.com>
718
719 * cp1.c: Clean up formatting of a few comments.
720 (value_fpr): Reformat switch statement.
721
cfe9ea23
CD		 7222002-06-06 Chris Demetriou <cgd@broadcom.com>
723 Ed Satterthwaite <ehs@broadcom.com>
724
725 * cp1.h: New file.
726 * sim-main.h: Include cp1.h.
727 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
728 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
729 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
730 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
731 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
732 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
733 * cp1.c: Don't include sim-fpu.h; already included by
734 sim-main.h. Clean up formatting of some comments.
735 (NaN, Equal, Less): Remove.
736 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
737 (fp_cmp): New functions.
738 * mips.igen (do_c_cond_fmt): Remove.
739 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
740 Compare. Add result tracing.
741 (CxC1): Remove, replace with...
742 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
743 (DMxC1): Remove, replace with...
744 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
745 (MxC1): Remove, replace with...
746 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
747
ee7254b0
CD		 7482002-06-04 Chris Demetriou <cgd@broadcom.com>
749
750 * sim-main.h (FGRIDX): Remove, replace all uses with...
751 (FGR_BASE): New macro.
752 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
753 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
754 (NR_FGR, FGR): Likewise.
755 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
756 * mips.igen: Likewise.
757
d3eb724f
CD		 7582002-06-04 Chris Demetriou <cgd@broadcom.com>
759
760 * cp1.c: Add an FSF Copyright notice to this file.
761
ba46ddd0
CD		 7622002-06-04 Chris Demetriou <cgd@broadcom.com>
763 Ed Satterthwaite <ehs@broadcom.com>
764
765 * cp1.c (Infinity): Remove.
766 * sim-main.h (Infinity): Likewise.
767
768 * cp1.c (fp_unary, fp_binary): New functions.
769 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
770 (fp_sqrt): New functions, implemented in terms of the above.
771 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
772 (Recip, SquareRoot): Remove (replaced by functions above).
773 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
774 (fp_recip, fp_sqrt): New prototypes.
775 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
776 (Recip, SquareRoot): Replace prototypes with #defines which
777 invoke the functions above.
778
18d8a52d
CD		 7792002-06-03 Chris Demetriou <cgd@broadcom.com>
780
781 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
782 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
783 file, remove PARAMS from prototypes.
784 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
785 simulator state arguments.
786 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
787 pass simulator state arguments.
788 * cp1.c (SD): Redefine as CPU_STATE(cpu).
789 (store_fpr, convert): Remove 'sd' argument.
790 (value_fpr): Likewise. Convert to use 'SD' instead.
791
0f154cbd
CD		 7922002-06-03 Chris Demetriou <cgd@broadcom.com>
793
794 * cp1.c (Min, Max): Remove #if 0'd functions.
795 * sim-main.h (Min, Max): Remove.
796
e80fc152
CD		 7972002-06-03 Chris Demetriou <cgd@broadcom.com>
798
799 * cp1.c: fix formatting of switch case and default labels.
800 * interp.c: Likewise.
801 * sim-main.c: Likewise.
802
bad673a9
CD		 8032002-06-03 Chris Demetriou <cgd@broadcom.com>
804
805 * cp1.c: Clean up comments which describe FP formats.
806 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
807
7cbea089
CD		 8082002-06-03 Chris Demetriou <cgd@broadcom.com>
809 Ed Satterthwaite <ehs@broadcom.com>
810
811 * configure.in (mipsisa64sb1*-*-*): New target for supporting
812 Broadcom SiByte SB-1 processor configurations.
813 * configure: Regenerate.
814 * sb1.igen: New file.
815 * mips.igen: Include sb1.igen.
816 (sb1): New model.
817 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
818 * mdmx.igen: Add "sb1" model to all appropriate functions and
819 instructions.
820 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
821 (ob_func, ob_acc): Reference the above.
822 (qh_acc): Adjust to keep the same size as ob_acc.
823 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
824 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
825
909daa82
CD		 8262002-06-03 Chris Demetriou <cgd@broadcom.com>
827
828 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
829
f4f1b9f1
CD		 8302002-06-02 Chris Demetriou <cgd@broadcom.com>
831 Ed Satterthwaite <ehs@broadcom.com>
832
833 * mips.igen (mdmx): New (pseudo-)model.
834 * mdmx.c, mdmx.igen: New files.
835 * Makefile.in (SIM_OBJS): Add mdmx.o.
836 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
837 New typedefs.
838 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
839 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
840 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
841 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
842 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
843 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
844 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
845 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
846 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
847 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
848 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
849 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
850 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
851 (qh_fmtsel): New macros.
852 (_sim_cpu): New member "acc".
853 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
854 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
855
5accf1ff
CD		 8562002-05-01 Chris Demetriou <cgd@broadcom.com>
857
858 * interp.c: Use 'deprecated' rather than 'depreciated.'
859 * sim-main.h: Likewise.
860
402586aa
CD		 8612002-05-01 Chris Demetriou <cgd@broadcom.com>
862
863 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
864 which wouldn't compile anyway.
865 * sim-main.h (unpredictable_action): New function prototype.
866 (Unpredictable): Define to call igen function unpredictable().
867 (NotWordValue): New macro to call igen function not_word_value().
868 (UndefinedResult): Remove.
869 * interp.c (undefined_result): Remove.
870 (unpredictable_action): New function.
871 * mips.igen (not_word_value, unpredictable): New functions.
872 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
873 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
874 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
875 NotWordValue() to check for unpredictable inputs, then
876 Unpredictable() to handle them.
877
c9b9995a
CD		 8782002-02-24 Chris Demetriou <cgd@broadcom.com>
879
880 * mips.igen: Fix formatting of calls to Unpredictable().
881
e1015982
AC		 8822002-04-20 Andrew Cagney <ac131313@redhat.com>
883
884 * interp.c (sim_open): Revert previous change.
885
b882a66b
AO		 8862002-04-18 Alexandre Oliva <aoliva@redhat.com>
887
888 * interp.c (sim_open): Disable chunk of code that wrote code in
889 vector table entries.
890
c429b7dd
CD		 8912002-03-19 Chris Demetriou <cgd@broadcom.com>
892
893 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
894 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
895 unused definitions.
896
37d146fa
CD		 8972002-03-19 Chris Demetriou <cgd@broadcom.com>
898
899 * cp1.c: Fix many formatting issues.
900
07892c0b
CD		 9012002-03-19 Chris G. Demetriou <cgd@broadcom.com>
902
903 * cp1.c (fpu_format_name): New function to replace...
904 (DOFMT): This. Delete, and update all callers.
905 (fpu_rounding_mode_name): New function to replace...
906 (RMMODE): This. Delete, and update all callers.
907
487f79b7
CD		 9082002-03-19 Chris G. Demetriou <cgd@broadcom.com>
909
910 * interp.c: Move FPU support routines from here to...
911 * cp1.c: Here. New file.
912 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
913 (cp1.o): New target.
914
1e799e28
CD		 9152002-03-12 Chris Demetriou <cgd@broadcom.com>
916
917 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
918 * mips.igen (mips32, mips64): New models, add to all instructions
919 and functions as appropriate.
920 (loadstore_ea, check_u64): New variant for model mips64.
921 (check_fmt_p): New variant for models mipsV and mips64, remove
922 mipsV model marking fro other variant.
923 (SLL) Rename to...
924 (SLLa) this.
925 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
926 for mips32 and mips64.
927 (DCLO, DCLZ): New instructions for mips64.
928
82f728db
CD		 9292002-03-07 Chris Demetriou <cgd@broadcom.com>
930
931 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
932 immediate or code as a hex value with the "%#lx" format.
933 (ANDI): Likewise, and fix printed instruction name.
934
b96e7ef1
CD		 9352002-03-05 Chris Demetriou <cgd@broadcom.com>
936
937 * sim-main.h (UndefinedResult, Unpredictable): New macros
938 which currently do nothing.
939
d35d4f70
CD		 9402002-03-05 Chris Demetriou <cgd@broadcom.com>
941
942 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
943 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
944 (status_CU3): New definitions.
945
946 * sim-main.h (ExceptionCause): Add new values for MIPS32
947 and MIPS64: MDMX, MCheck, CacheErr. Update comments
948 for DebugBreakPoint and NMIReset to note their status in
949 MIPS32 and MIPS64.
950 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
951 (SignalExceptionCacheErr): New exception macros.
952
3ad6f714
CD		 9532002-03-05 Chris Demetriou <cgd@broadcom.com>
954
955 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
956 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
957 is always enabled.
958 (SignalExceptionCoProcessorUnusable): Take as argument the
959 unusable coprocessor number.
960
86b77b47
CD		 9612002-03-05 Chris Demetriou <cgd@broadcom.com>
962
963 * mips.igen: Fix formatting of all SignalException calls.
964
97a88e93 9652002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 966
967 * sim-main.h (SIGNEXTEND): Remove.
968
97a88e93 9692002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 970
971 * mips.igen: Remove gencode comment from top of file, fix
972 spelling in another comment.
973
97a88e93 9742002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 975
976 * mips.igen (check_fmt, check_fmt_p): New functions to check
977 whether specific floating point formats are usable.
978 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
979 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
980 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
981 Use the new functions.
982 (do_c_cond_fmt): Remove format checks...
983 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
984
97a88e93 9852002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 986
987 * mips.igen: Fix formatting of check_fpu calls.
988
41774c9d
CD		 9892002-03-03 Chris Demetriou <cgd@broadcom.com>
990
991 * mips.igen (FLOOR.L.fmt): Store correct destination register.
992
4a0bd876
CD		 9932002-03-03 Chris Demetriou <cgd@broadcom.com>
994
995 * mips.igen: Remove whitespace at end of lines.
996
09297648
CD		 9972002-03-02 Chris Demetriou <cgd@broadcom.com>
998
999 * mips.igen (loadstore_ea): New function to do effective
1000 address calculations.
1001 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1002 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1003 CACHE): Use loadstore_ea to do effective address computations.
1004
043b7057
CD		 10052002-03-02 Chris Demetriou <cgd@broadcom.com>
1006
1007 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1008 * mips.igen (LL, CxC1, MxC1): Likewise.
1009
c1e8ada4
CD		 10102002-03-02 Chris Demetriou <cgd@broadcom.com>
1011
1012 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1013 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1014 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1015 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1016 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1017 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1018 Don't split opcode fields by hand, use the opcode field values
1019 provided by igen.
1020
3e1dca16
CD		 10212002-03-01 Chris Demetriou <cgd@broadcom.com>
1022
1023 * mips.igen (do_divu): Fix spacing.
1024
1025 * mips.igen (do_dsllv): Move to be right before DSLLV,
1026 to match the rest of the do_<shift> functions.
1027
fff8d27d
CD		 10282002-03-01 Chris Demetriou <cgd@broadcom.com>
1029
1030 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1031 DSRL32, do_dsrlv): Trace inputs and results.
1032
0d3e762b
CD		 10332002-03-01 Chris Demetriou <cgd@broadcom.com>
1034
1035 * mips.igen (CACHE): Provide instruction-printing string.
1036
1037 * interp.c (signal_exception): Comment tokens after #endif.
1038
eb5fcf93
CD		 10392002-02-28 Chris Demetriou <cgd@broadcom.com>
1040
1041 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1042 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1043 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1044 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1045 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1046 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1047 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1048 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1049
bb22bd7d
CD		 10502002-02-28 Chris Demetriou <cgd@broadcom.com>
1051
1052 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1053 instruction-printing string.
1054 (LWU): Use '64' as the filter flag.
1055
91a177cf
CD		 10562002-02-28 Chris Demetriou <cgd@broadcom.com>
1057
1058 * mips.igen (SDXC1): Fix instruction-printing string.
1059
387f484a
CD		 10602002-02-28 Chris Demetriou <cgd@broadcom.com>
1061
1062 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1063 filter flags "32,f".
1064
3d81f391
CD		 10652002-02-27 Chris Demetriou <cgd@broadcom.com>
1066
1067 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1068 as the filter flag.
1069
af5107af
CD		 10702002-02-27 Chris Demetriou <cgd@broadcom.com>
1071
1072 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1073 add a comma) so that it more closely match the MIPS ISA
1074 documentation opcode partitioning.
1075 (PREF): Put useful names on opcode fields, and include
1076 instruction-printing string.
1077
ca971540
CD		 10782002-02-27 Chris Demetriou <cgd@broadcom.com>
1079
1080 * mips.igen (check_u64): New function which in the future will
1081 check whether 64-bit instructions are usable and signal an
1082 exception if not. Currently a no-op.
1083 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1084 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1085 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1086 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1087
1088 * mips.igen (check_fpu): New function which in the future will
1089 check whether FPU instructions are usable and signal an exception
1090 if not. Currently a no-op.
1091 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1092 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1093 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1094 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1095 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1096 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1097 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1098 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1099
1c47a468
CD		 11002002-02-27 Chris Demetriou <cgd@broadcom.com>
1101
1102 * mips.igen (do_load_left, do_load_right): Move to be immediately
1103 following do_load.
1104 (do_store_left, do_store_right): Move to be immediately following
1105 do_store.
1106
603a98e7
CD		 11072002-02-27 Chris Demetriou <cgd@broadcom.com>
1108
1109 * mips.igen (mipsV): New model name. Also, add it to
1110 all instructions and functions where it is appropriate.
1111
c5d00cc7
CD		 11122002-02-18 Chris Demetriou <cgd@broadcom.com>
1113
1114 * mips.igen: For all functions and instructions, list model
1115 names that support that instruction one per line.
1116
074e9cb8
CD		 11172002-02-11 Chris Demetriou <cgd@broadcom.com>
1118
1119 * mips.igen: Add some additional comments about supported
1120 models, and about which instructions go where.
1121 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1122 order as is used in the rest of the file.
1123
9805e229
CD		 11242002-02-11 Chris Demetriou <cgd@broadcom.com>
1125
1126 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1127 indicating that ALU32_END or ALU64_END are there to check
1128 for overflow.
1129 (DADD): Likewise, but also remove previous comment about
1130 overflow checking.
1131
f701dad2
CD		 11322002-02-10 Chris Demetriou <cgd@broadcom.com>
1133
1134 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1135 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1136 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1137 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1138 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1139 fields (i.e., add and move commas) so that they more closely
1140 match the MIPS ISA documentation opcode partitioning.
1141
11422002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 1143
1144 * mips.igen (ADDI): Print immediate value.
1145 (BREAK): Print code.
1146 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1147 (SLL): Print "nop" specially, and don't run the code
1148 that does the shift for the "nop" case.
1149
9e52972e
FF		 11502001-11-17 Fred Fish <fnf@redhat.com>
1151
1152 * sim-main.h (float_operation): Move enum declaration outside
1153 of _sim_cpu struct declaration.
1154
c0efbca4
JB		 11552001-04-12 Jim Blandy <jimb@redhat.com>
1156
1157 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1158 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1159 set of the FCSR.
1160 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1161 PENDING_FILL, and you can get the intended effect gracefully by
1162 calling PENDING_SCHED directly.
1163
fb891446
BE		 11642001-02-23 Ben Elliston <bje@redhat.com>
1165
1166 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1167 already defined elsewhere.
1168
8030f857
BE		 11692001-02-19 Ben Elliston <bje@redhat.com>
1170
1171 * sim-main.h (sim_monitor): Return an int.
1172 * interp.c (sim_monitor): Add return values.
1173 (signal_exception): Handle error conditions from sim_monitor.
1174
56b48a7a
CD		 11752001-02-08 Ben Elliston <bje@redhat.com>
1176
1177 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1178 (store_memory): Likewise, pass cia to sim_core_write*.
1179
d3ee60d9
FCE		 11802000-10-19 Frank Ch. Eigler <fche@redhat.com>
1181
1182 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1183 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1184
071da002
AC		 1185Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1186
1187 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1188 * Makefile.in: Don't delete *.igen when cleaning directory.
1189
a28c02cd
AC		 1190Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1191
1192 * m16.igen (break): Call SignalException not sim_engine_halt.
1193
80ee11fa
AC		 1194Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1195
1196 From Jason Eckhardt:
1197 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1198
673388c0
AC		 1199Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1200
1201 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1202
4c0deff4
NC		 12032000-05-24 Michael Hayes <mhayes@cygnus.com>
1204
1205 * mips.igen (do_dmultx): Fix typo.
1206
eb2d80b4
AC		 1207Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1208
1209 * configure: Regenerated to track ../common/aclocal.m4 changes.
1210
dd37a34b
AC		 1211Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1212
1213 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1214
4c0deff4
NC		 12152000-04-12 Frank Ch. Eigler <fche@redhat.com>
1216
1217 * sim-main.h (GPR_CLEAR): Define macro.
1218
e30db738
AC		 1219Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1220
1221 * interp.c (decode_coproc): Output long using %lx and not %s.
1222
cb7450ea
FCE		 12232000-03-21 Frank Ch. Eigler <fche@redhat.com>
1224
1225 * interp.c (sim_open): Sort & extend dummy memory regions for
1226 --board=jmr3904 for eCos.
1227
a3027dd7
FCE		 12282000-03-02 Frank Ch. Eigler <fche@redhat.com>
1229
1230 * configure: Regenerated.
1231
1232Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1233
1234 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1235 calls, conditional on the simulator being in verbose mode.
1236
dfcd3bfb
JM		 1237Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1238
1239 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1240 cache don't get ReservedInstruction traps.
1241
c2d11a7d
JM		 12421999-11-29 Mark Salter <msalter@cygnus.com>
1243
1244 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1245 to clear status bits in sdisr register. This is how the hardware works.
1246
1247 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1248 being used by cygmon.
1249
4ce44c66
JM		 12501999-11-11 Andrew Haley <aph@cygnus.com>
1251
1252 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1253 instructions.
1254
cff3e48b
JM		 1255Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1256
1257 * mips.igen (MULT): Correct previous mis-applied patch.
1258
d4f3574e
SS		 1259Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1260
1261 * mips.igen (delayslot32): Handle sequence like
1262 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1263 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1264 (MULT): Actually pass the third register...
1265
12661999-09-03 Mark Salter <msalter@cygnus.com>
1267
1268 * interp.c (sim_open): Added more memory aliases for additional
1269 hardware being touched by cygmon on jmr3904 board.
1270
1271Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1272
1273 * configure: Regenerated to track ../common/aclocal.m4 changes.
1274
a0b3c4fd
JM		 1275Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1276
1277 * interp.c (sim_store_register): Handle case where client - GDB -
1278 specifies that a 4 byte register is 8 bytes in size.
1279 (sim_fetch_register): Ditto.
1280
adf40b2e
JM		 12811999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1282
1283 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1284 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1285 (idt_monitor_base): Base address for IDT monitor traps.
1286 (pmon_monitor_base): Ditto for PMON.
1287 (lsipmon_monitor_base): Ditto for LSI PMON.
1288 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1289 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1290 (sim_firmware_command): New function.
1291 (mips_option_handler): Call it for OPTION_FIRMWARE.
1292 (sim_open): Allocate memory for idt_monitor region. If "--board"
1293 option was given, add no monitor by default. Add BREAK hooks only if
1294 monitors are also there.
1295
43e526b9
JM		 1296Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1297
1298 * interp.c (sim_monitor): Flush output before reading input.
1299
1300Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1301
1302 * tconfig.in (SIM_HANDLES_LMA): Always define.
1303
1304Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1305
1306 From Mark Salter <msalter@cygnus.com>:
1307 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1308 (sim_open): Add setup for BSP board.
1309
9846de1b
JM		 1310Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1311
1312 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1313 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1314 them as unimplemented.
1315
cd0fc7c3
SS		 13161999-05-08 Felix Lee <flee@cygnus.com>
1317
1318 * configure: Regenerated to track ../common/aclocal.m4 changes.
1319
7a292a7a
SS		 13201999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1321
1322 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1323
1324Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1325
1326 * configure.in: Any mips64vr5*-*-* target should have
1327 -DTARGET_ENABLE_FR=1.
1328 (default_endian): Any mips64vr*el-*-* target should default to
1329 LITTLE_ENDIAN.
1330 * configure: Re-generate.
1331
13321999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1333
1334 * mips.igen (ldl): Extend from _16_, not 32.
1335
1336Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1337
1338 * interp.c (sim_store_register): Force registers written to by GDB
1339 into an un-interpreted state.
1340
c906108c
SS		 13411999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1342
1343 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1344 CPU, start periodic background I/O polls.
1345 (tx3904sio_poll): New function: periodic I/O poller.
1346
13471998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1348
1349 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1350
1351Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1352
1353 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1354 case statement.
1355
13561998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1357
1358 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1359 (load_word): Call SIM_CORE_SIGNAL hook on error.
1360 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1361 starting. For exception dispatching, pass PC instead of NULL_CIA.
1362 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1363 * sim-main.h (COP0_BADVADDR): Define.
1364 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1365 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1366 (_sim_cpu): Add exc_* fields to store register value snapshots.
1367 * mips.igen (*): Replace memory-related SignalException* calls
1368 with references to SIM_CORE_SIGNAL hook.
1369
1370 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1371 fix.
1372 * sim-main.c (*): Minor warning cleanups.
1373
13741998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1375
1376 * m16.igen (DADDIU5): Correct type-o.
1377
1378Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1379
1380 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1381 variables.
1382
1383Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1384
1385 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1386 to include path.
1387 (interp.o): Add dependency on itable.h
1388 (oengine.c, gencode): Delete remaining references.
1389 (BUILT_SRC_FROM_GEN): Clean up.
1390
13911998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1392
1393 * vr4run.c: New.
1394 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1395 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1396 tmp-run-hack) : New.
1397 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1398 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1399 Drop the "64" qualifier to get the HACK generator working.
1400 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1401 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1402 qualifier to get the hack generator working.
1403 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1404 (DSLL): Use do_dsll.
1405 (DSLLV): Use do_dsllv.
1406 (DSRA): Use do_dsra.
1407 (DSRL): Use do_dsrl.
1408 (DSRLV): Use do_dsrlv.
1409 (BC1): Move *vr4100 to get the HACK generator working.
1410 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1411 get the HACK generator working.
1412 (MACC) Rename to get the HACK generator working.
1413 (DMACC,MACCS,DMACCS): Add the 64.
1414
14151998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1416
1417 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1418 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1419
14201998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1421
1422 * mips/interp.c (DEBUG): Cleanups.
1423
14241998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1425
1426 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1427 (tx3904sio_tickle): fflush after a stdout character output.
1428
14291998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1430
1431 * interp.c (sim_close): Uninstall modules.
1432
1433Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1434
1435 * sim-main.h, interp.c (sim_monitor): Change to global
1436 function.
1437
1438Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1439
1440 * configure.in (vr4100): Only include vr4100 instructions in
1441 simulator.
1442 * configure: Re-generate.
1443 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1444
1445Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1446
1447 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1448 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1449 true alternative.
1450
1451 * configure.in (sim_default_gen, sim_use_gen): Replace with
1452 sim_gen.
1453 (--enable-sim-igen): Delete config option. Always using IGEN.
1454 * configure: Re-generate.
1455
1456 * Makefile.in (gencode): Kill, kill, kill.
1457 * gencode.c: Ditto.
1458
1459Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1460
1461 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1462 bit mips16 igen simulator.
1463 * configure: Re-generate.
1464
1465 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1466 as part of vr4100 ISA.
1467 * vr.igen: Mark all instructions as 64 bit only.
1468
1469Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1470
1471 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1472 Pacify GCC.
1473
1474Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1475
1476 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1477 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1478 * configure: Re-generate.
1479
1480 * m16.igen (BREAK): Define breakpoint instruction.
1481 (JALX32): Mark instruction as mips16 and not r3900.
1482 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1483
1484 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1485
1486Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1487
1488 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1489 insn as a debug breakpoint.
1490
1491 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1492 pending.slot_size.
1493 (PENDING_SCHED): Clean up trace statement.
1494 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1495 (PENDING_FILL): Delay write by only one cycle.
1496 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1497
1498 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1499 of pending writes.
1500 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1501 32 & 64.
1502 (pending_tick): Move incrementing of index to FOR statement.
1503 (pending_tick): Only update PENDING_OUT after a write has occured.
1504
1505 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1506 build simulator.
1507 * configure: Re-generate.
1508
1509 * interp.c (sim_engine_run OLD): Delete explicit call to
1510 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1511
1512Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1513
1514 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1515 interrupt level number to match changed SignalExceptionInterrupt
1516 macro.
1517
1518Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1519
1520 * interp.c: #include "itable.h" if WITH_IGEN.
1521 (get_insn_name): New function.
1522 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1523 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1524
1525Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1526
1527 * configure: Rebuilt to inhale new common/aclocal.m4.
1528
1529Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1530
1531 * dv-tx3904sio.c: Include sim-assert.h.
1532
1533Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1534
1535 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1536 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1537 Reorganize target-specific sim-hardware checks.
1538 * configure: rebuilt.
1539 * interp.c (sim_open): For tx39 target boards, set
1540 OPERATING_ENVIRONMENT, add tx3904sio devices.
1541 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1542 ROM executables. Install dv-sockser into sim-modules list.
1543
1544 * dv-tx3904irc.c: Compiler warning clean-up.
1545 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1546 frequent hw-trace messages.
1547
1548Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1549
1550 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1551
1552Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1553
1554 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1555
1556 * vr.igen: New file.
1557 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1558 * mips.igen: Define vr4100 model. Include vr.igen.
1559Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1560
1561 * mips.igen (check_mf_hilo): Correct check.
1562
1563Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1564
1565 * sim-main.h (interrupt_event): Add prototype.
1566
1567 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1568 register_ptr, register_value.
1569 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1570
1571 * sim-main.h (tracefh): Make extern.
1572
1573Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1574
1575 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1576 Reduce unnecessarily high timer event frequency.
1577 * dv-tx3904cpu.c: Ditto for interrupt event.
1578
1579Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1580
1581 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1582 to allay warnings.
1583 (interrupt_event): Made non-static.
1584
1585 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1586 interchange of configuration values for external vs. internal
1587 clock dividers.
1588
1589Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1590
1591 * mips.igen (BREAK): Moved code to here for
1592 simulator-reserved break instructions.
1593 * gencode.c (build_instruction): Ditto.
1594 * interp.c (signal_exception): Code moved from here. Non-
1595 reserved instructions now use exception vector, rather
1596 than halting sim.
1597 * sim-main.h: Moved magic constants to here.
1598
1599Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1600
1601 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1602 register upon non-zero interrupt event level, clear upon zero
1603 event value.
1604 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1605 by passing zero event value.
1606 (*_io_{read,write}_buffer): Endianness fixes.
1607 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1608 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1609
1610 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1611 serial I/O and timer module at base address 0xFFFF0000.
1612
1613Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1614
1615 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1616 and BigEndianCPU.
1617
1618Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1619
1620 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1621 parts.
1622 * configure: Update.
1623
1624Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1625
1626 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1627 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1628 * configure.in: Include tx3904tmr in hw_device list.
1629 * configure: Rebuilt.
1630 * interp.c (sim_open): Instantiate three timer instances.
1631 Fix address typo of tx3904irc instance.
1632
1633Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1634
1635 * interp.c (signal_exception): SystemCall exception now uses
1636 the exception vector.
1637
1638Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1639
1640 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1641 to allay warnings.
1642
1643Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1644
1645 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1646
1647Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1648
1649 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1650
1651 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1652 sim-main.h. Declare a struct hw_descriptor instead of struct
1653 hw_device_descriptor.
1654
1655Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1656
1657 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1658 right bits and then re-align left hand bytes to correct byte
1659 lanes. Fix incorrect computation in do_store_left when loading
1660 bytes from second word.
1661
1662Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1663
1664 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1665 * interp.c (sim_open): Only create a device tree when HW is
1666 enabled.
1667
1668 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1669 * interp.c (signal_exception): Ditto.
1670
1671Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1672
1673 * gencode.c: Mark BEGEZALL as LIKELY.
1674
1675Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1676
1677 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1678 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1679
1680Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1681
1682 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1683 modules. Recognize TX39 target with "mips*tx39" pattern.
1684 * configure: Rebuilt.
1685 * sim-main.h (*): Added many macros defining bits in
1686 TX39 control registers.
1687 (SignalInterrupt): Send actual PC instead of NULL.
1688 (SignalNMIReset): New exception type.
1689 * interp.c (board): New variable for future use to identify
1690 a particular board being simulated.
1691 (mips_option_handler,mips_options): Added "--board" option.
1692 (interrupt_event): Send actual PC.
1693 (sim_open): Make memory layout conditional on board setting.
1694 (signal_exception): Initial implementation of hardware interrupt
1695 handling. Accept another break instruction variant for simulator
1696 exit.
1697 (decode_coproc): Implement RFE instruction for TX39.
1698 (mips.igen): Decode RFE instruction as such.
1699 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1700 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1701 bbegin to implement memory map.
1702 * dv-tx3904cpu.c: New file.
1703 * dv-tx3904irc.c: New file.
1704
1705Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1706
1707 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1708
1709Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1710
1711 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1712 with calls to check_div_hilo.
1713
1714Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1715
1716 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1717 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1718 Add special r3900 version of do_mult_hilo.
1719 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1720 with calls to check_mult_hilo.
1721 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1722 with calls to check_div_hilo.
1723
1724Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1725
1726 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1727 Document a replacement.
1728
1729Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1730
1731 * interp.c (sim_monitor): Make mon_printf work.
1732
1733Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1734
1735 * sim-main.h (INSN_NAME): New arg `cpu'.
1736
1737Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1738
1739 * configure: Regenerated to track ../common/aclocal.m4 changes.
1740
1741Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1742
1743 * configure: Regenerated to track ../common/aclocal.m4 changes.
1744 * config.in: Ditto.
1745
1746Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1747
1748 * acconfig.h: New file.
1749 * configure.in: Reverted change of Apr 24; use sinclude again.
1750
1751Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1752
1753 * configure: Regenerated to track ../common/aclocal.m4 changes.
1754 * config.in: Ditto.
1755
1756Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1757
1758 * configure.in: Don't call sinclude.
1759
1760Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1761
1762 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1763
1764Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1765
1766 * mips.igen (ERET): Implement.
1767
1768 * interp.c (decode_coproc): Return sign-extended EPC.
1769
1770 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1771
1772 * interp.c (signal_exception): Do not ignore Trap.
1773 (signal_exception): On TRAP, restart at exception address.
1774 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1775 (signal_exception): Update.
1776 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1777 so that TRAP instructions are caught.
1778
1779Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1780
1781 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1782 contains HI/LO access history.
1783 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1784 (HIACCESS, LOACCESS): Delete, replace with
1785 (HIHISTORY, LOHISTORY): New macros.
1786 (CHECKHILO): Delete all, moved to mips.igen
1787
1788 * gencode.c (build_instruction): Do not generate checks for
1789 correct HI/LO register usage.
1790
1791 * interp.c (old_engine_run): Delete checks for correct HI/LO
1792 register usage.
1793
1794 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1795 check_mf_cycles): New functions.
1796 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1797 do_divu, domultx, do_mult, do_multu): Use.
1798
1799 * tx.igen ("madd", "maddu"): Use.
1800
1801Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1802
1803 * mips.igen (DSRAV): Use function do_dsrav.
1804 (SRAV): Use new function do_srav.
1805
1806 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1807 (B): Sign extend 11 bit immediate.
1808 (EXT-B*): Shift 16 bit immediate left by 1.
1809 (ADDIU*): Don't sign extend immediate value.
1810
1811Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1812
1813 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1814
1815 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1816 functions.
1817
1818 * mips.igen (delayslot32, nullify_next_insn): New functions.
1819 (m16.igen): Always include.
1820 (do_*): Add more tracing.
1821
1822 * m16.igen (delayslot16): Add NIA argument, could be called by a
1823 32 bit MIPS16 instruction.
1824
1825 * interp.c (ifetch16): Move function from here.
1826 * sim-main.c (ifetch16): To here.
1827
1828 * sim-main.c (ifetch16, ifetch32): Update to match current
1829 implementations of LH, LW.
1830 (signal_exception): Don't print out incorrect hex value of illegal
1831 instruction.
1832
1833Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1834
1835 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1836 instruction.
1837
1838 * m16.igen: Implement MIPS16 instructions.
1839
1840 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1841 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1842 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1843 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1844 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1845 bodies of corresponding code from 32 bit insn to these. Also used
1846 by MIPS16 versions of functions.
1847
1848 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1849 (IMEM16): Drop NR argument from macro.
1850
1851Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1852
1853 * Makefile.in (SIM_OBJS): Add sim-main.o.
1854
1855 * sim-main.h (address_translation, load_memory, store_memory,
1856 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1857 as INLINE_SIM_MAIN.
1858 (pr_addr, pr_uword64): Declare.
1859 (sim-main.c): Include when H_REVEALS_MODULE_P.
1860
1861 * interp.c (address_translation, load_memory, store_memory,
1862 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1863 from here.
1864 * sim-main.c: To here. Fix compilation problems.
1865
1866 * configure.in: Enable inlining.
1867 * configure: Re-config.
1868
1869Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1870
1871 * configure: Regenerated to track ../common/aclocal.m4 changes.
1872
1873Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1874
1875 * mips.igen: Include tx.igen.
1876 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1877 * tx.igen: New file, contains MADD and MADDU.
1878
1879 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1880 the hardwired constant `7'.
1881 (store_memory): Ditto.
1882 (LOADDRMASK): Move definition to sim-main.h.
1883
1884 mips.igen (MTC0): Enable for r3900.
1885 (ADDU): Add trace.
1886
1887 mips.igen (do_load_byte): Delete.
1888 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1889 do_store_right): New functions.
1890 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1891
1892 configure.in: Let the tx39 use igen again.
1893 configure: Update.
1894
1895Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1896
1897 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1898 not an address sized quantity. Return zero for cache sizes.
1899
1900Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1901
1902 * mips.igen (r3900): r3900 does not support 64 bit integer
1903 operations.
1904
1905Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1906
1907 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1908 than igen one.
1909 * configure : Rebuild.
1910
1911Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1912
1913 * configure: Regenerated to track ../common/aclocal.m4 changes.
1914
1915Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1916
1917 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1918
1919Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1920
1921 * configure: Regenerated to track ../common/aclocal.m4 changes.
1922 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1923
1924Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1925
1926 * configure: Regenerated to track ../common/aclocal.m4 changes.
1927
1928Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1929
1930 * interp.c (Max, Min): Comment out functions. Not yet used.
1931
1932Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1933
1934 * configure: Regenerated to track ../common/aclocal.m4 changes.
1935
1936Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1937
1938 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1939 configurable settings for stand-alone simulator.
1940
1941 * configure.in: Added X11 search, just in case.
1942
1943 * configure: Regenerated.
1944
1945Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1946
1947 * interp.c (sim_write, sim_read, load_memory, store_memory):
1948 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1949
1950Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1951
1952 * sim-main.h (GETFCC): Return an unsigned value.
1953
1954Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1955
1956 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1957 (DADD): Result destination is RD not RT.
1958
1959Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1960
1961 * sim-main.h (HIACCESS, LOACCESS): Always define.
1962
1963 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1964
1965 * interp.c (sim_info): Delete.
1966
1967Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1968
1969 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1970 (mips_option_handler): New argument `cpu'.
1971 (sim_open): Update call to sim_add_option_table.
1972
1973Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1974
1975 * mips.igen (CxC1): Add tracing.
1976
1977Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1978
1979 * sim-main.h (Max, Min): Declare.
1980
1981 * interp.c (Max, Min): New functions.
1982
1983 * mips.igen (BC1): Add tracing.
1984
1985Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1986
1987 * interp.c Added memory map for stack in vr4100
1988
1989Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1990
1991 * interp.c (load_memory): Add missing "break"'s.
1992
1993Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1994
1995 * interp.c (sim_store_register, sim_fetch_register): Pass in
1996 length parameter. Return -1.
1997
1998Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1999
2000 * interp.c: Added hardware init hook, fixed warnings.
2001
2002Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2003
2004 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2005
2006Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2007
2008 * interp.c (ifetch16): New function.
2009
2010 * sim-main.h (IMEM32): Rename IMEM.
2011 (IMEM16_IMMED): Define.
2012 (IMEM16): Define.
2013 (DELAY_SLOT): Update.
2014
2015 * m16run.c (sim_engine_run): New file.
2016
2017 * m16.igen: All instructions except LB.
2018 (LB): Call do_load_byte.
2019 * mips.igen (do_load_byte): New function.
2020 (LB): Call do_load_byte.
2021
2022 * mips.igen: Move spec for insn bit size and high bit from here.
2023 * Makefile.in (tmp-igen, tmp-m16): To here.
2024
2025 * m16.dc: New file, decode mips16 instructions.
2026
2027 * Makefile.in (SIM_NO_ALL): Define.
2028 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2029
2030Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2031
2032 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2033 point unit to 32 bit registers.
2034 * configure: Re-generate.
2035
2036Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2037
2038 * configure.in (sim_use_gen): Make IGEN the default simulator
2039 generator for generic 32 and 64 bit mips targets.
2040 * configure: Re-generate.
2041
2042Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2043
2044 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2045 bitsize.
2046
2047 * interp.c (sim_fetch_register, sim_store_register): Read/write
2048 FGR from correct location.
2049 (sim_open): Set size of FGR's according to
2050 WITH_TARGET_FLOATING_POINT_BITSIZE.
2051
2052 * sim-main.h (FGR): Store floating point registers in a separate
2053 array.
2054
2055Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2056
2057 * configure: Regenerated to track ../common/aclocal.m4 changes.
2058
2059Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2060
2061 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2062
2063 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2064
2065 * interp.c (pending_tick): New function. Deliver pending writes.
2066
2067 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2068 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2069 it can handle mixed sized quantites and single bits.
2070
2071Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2072
2073 * interp.c (oengine.h): Do not include when building with IGEN.
2074 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2075 (sim_info): Ditto for PROCESSOR_64BIT.
2076 (sim_monitor): Replace ut_reg with unsigned_word.
2077 (*): Ditto for t_reg.
2078 (LOADDRMASK): Define.
2079 (sim_open): Remove defunct check that host FP is IEEE compliant,
2080 using software to emulate floating point.
2081 (value_fpr, ...): Always compile, was conditional on HASFPU.
2082
2083Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2084
2085 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2086 size.
2087
2088 * interp.c (SD, CPU): Define.
2089 (mips_option_handler): Set flags in each CPU.
2090 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2091 (sim_close): Do not clear STATE, deleted anyway.
2092 (sim_write, sim_read): Assume CPU zero's vm should be used for
2093 data transfers.
2094 (sim_create_inferior): Set the PC for all processors.
2095 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2096 argument.
2097 (mips16_entry): Pass correct nr of args to store_word, load_word.
2098 (ColdReset): Cold reset all cpu's.
2099 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2100 (sim_monitor, load_memory, store_memory, signal_exception): Use
2101 `CPU' instead of STATE_CPU.
2102
2103
2104 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2105 SD or CPU_.
2106
2107 * sim-main.h (signal_exception): Add sim_cpu arg.
2108 (SignalException*): Pass both SD and CPU to signal_exception.
2109 * interp.c (signal_exception): Update.
2110
2111 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2112 Ditto
2113 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2114 address_translation): Ditto
2115 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2116
2117Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2118
2119 * configure: Regenerated to track ../common/aclocal.m4 changes.
2120
2121Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2122
2123 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2124
2125 * mips.igen (model): Map processor names onto BFD name.
2126
2127 * sim-main.h (CPU_CIA): Delete.
2128 (SET_CIA, GET_CIA): Define
2129
2130Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2131
2132 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2133 regiser.
2134
2135 * configure.in (default_endian): Configure a big-endian simulator
2136 by default.
2137 * configure: Re-generate.
2138
2139Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2140
2141 * configure: Regenerated to track ../common/aclocal.m4 changes.
2142
2143Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2144
2145 * interp.c (sim_monitor): Handle Densan monitor outbyte
2146 and inbyte functions.
2147
21481997-12-29 Felix Lee <flee@cygnus.com>
2149
2150 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2151
2152Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2153
2154 * Makefile.in (tmp-igen): Arrange for $zero to always be
2155 reset to zero after every instruction.
2156
2157Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2158
2159 * configure: Regenerated to track ../common/aclocal.m4 changes.
2160 * config.in: Ditto.
2161
2162Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2163
2164 * mips.igen (MSUB): Fix to work like MADD.
2165 * gencode.c (MSUB): Similarly.
2166
2167Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2168
2169 * configure: Regenerated to track ../common/aclocal.m4 changes.
2170
2171Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2172
2173 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2174
2175Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2176
2177 * sim-main.h (sim-fpu.h): Include.
2178
2179 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2180 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2181 using host independant sim_fpu module.
2182
2183Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2184
2185 * interp.c (signal_exception): Report internal errors with SIGABRT
2186 not SIGQUIT.
2187
2188 * sim-main.h (C0_CONFIG): New register.
2189 (signal.h): No longer include.
2190
2191 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2192
2193Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2194
2195 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2196
2197Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2198
2199 * mips.igen: Tag vr5000 instructions.
2200 (ANDI): Was missing mipsIV model, fix assembler syntax.
2201 (do_c_cond_fmt): New function.
2202 (C.cond.fmt): Handle mips I-III which do not support CC field
2203 separatly.
2204 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2205 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2206 in IV3.2 spec.
2207 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2208 vr5000 which saves LO in a GPR separatly.
2209
2210 * configure.in (enable-sim-igen): For vr5000, select vr5000
2211 specific instructions.
2212 * configure: Re-generate.
2213
2214Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2215
2216 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2217
2218 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2219 fmt_uninterpreted_64 bit cases to switch. Convert to
2220 fmt_formatted,
2221
2222 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2223
2224 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2225 as specified in IV3.2 spec.
2226 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2227
2228Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2229
2230 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2231 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2232 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2233 PENDING_FILL versions of instructions. Simplify.
2234 (X): New function.
2235 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2236 instructions.
2237 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2238 a signed value.
2239 (MTHI, MFHI): Disable code checking HI-LO.
2240
2241 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2242 global.
2243 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2244
2245Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2246
2247 * gencode.c (build_mips16_operands): Replace IPC with cia.
2248
2249 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2250 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2251 IPC to `cia'.
2252 (UndefinedResult): Replace function with macro/function
2253 combination.
2254 (sim_engine_run): Don't save PC in IPC.
2255
2256 * sim-main.h (IPC): Delete.
2257
2258
2259 * interp.c (signal_exception, store_word, load_word,
2260 address_translation, load_memory, store_memory, cache_op,
2261 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2262 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2263 current instruction address - cia - argument.
2264 (sim_read, sim_write): Call address_translation directly.
2265 (sim_engine_run): Rename variable vaddr to cia.
2266 (signal_exception): Pass cia to sim_monitor
2267
2268 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2269 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2270 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2271
2272 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2273 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2274 SIM_ASSERT.
2275
2276 * interp.c (signal_exception): Pass restart address to
2277 sim_engine_restart.
2278
2279 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2280 idecode.o): Add dependency.
2281
2282 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2283 Delete definitions
2284 (DELAY_SLOT): Update NIA not PC with branch address.
2285 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2286
2287 * mips.igen: Use CIA not PC in branch calculations.
2288 (illegal): Call SignalException.
2289 (BEQ, ADDIU): Fix assembler.
2290
2291Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2292
2293 * m16.igen (JALX): Was missing.
2294
2295 * configure.in (enable-sim-igen): New configuration option.
2296 * configure: Re-generate.
2297
2298 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2299
2300 * interp.c (load_memory, store_memory): Delete parameter RAW.
2301 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2302 bypassing {load,store}_memory.
2303
2304 * sim-main.h (ByteSwapMem): Delete definition.
2305
2306 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2307
2308 * interp.c (sim_do_command, sim_commands): Delete mips specific
2309 commands. Handled by module sim-options.
2310
2311 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2312 (WITH_MODULO_MEMORY): Define.
2313
2314 * interp.c (sim_info): Delete code printing memory size.
2315
2316 * interp.c (mips_size): Nee sim_size, delete function.
2317 (power2): Delete.
2318 (monitor, monitor_base, monitor_size): Delete global variables.
2319 (sim_open, sim_close): Delete code creating monitor and other
2320 memory regions. Use sim-memopts module, via sim_do_commandf, to
2321 manage memory regions.
2322 (load_memory, store_memory): Use sim-core for memory model.
2323
2324 * interp.c (address_translation): Delete all memory map code
2325 except line forcing 32 bit addresses.
2326
2327Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2328
2329 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2330 trace options.
2331
2332 * interp.c (logfh, logfile): Delete globals.
2333 (sim_open, sim_close): Delete code opening & closing log file.
2334 (mips_option_handler): Delete -l and -n options.
2335 (OPTION mips_options): Ditto.
2336
2337 * interp.c (OPTION mips_options): Rename option trace to dinero.
2338 (mips_option_handler): Update.
2339
2340Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2341
2342 * interp.c (fetch_str): New function.
2343 (sim_monitor): Rewrite using sim_read & sim_write.
2344 (sim_open): Check magic number.
2345 (sim_open): Write monitor vectors into memory using sim_write.
2346 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2347 (sim_read, sim_write): Simplify - transfer data one byte at a
2348 time.
2349 (load_memory, store_memory): Clarify meaning of parameter RAW.
2350
2351 * sim-main.h (isHOST): Defete definition.
2352 (isTARGET): Mark as depreciated.
2353 (address_translation): Delete parameter HOST.
2354
2355 * interp.c (address_translation): Delete parameter HOST.
2356
2357Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2358
2359 * mips.igen:
2360
2361 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2362 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2363
2364Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2365
2366 * mips.igen: Add model filter field to records.
2367
2368Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2369
2370 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2371
2372 interp.c (sim_engine_run): Do not compile function sim_engine_run
2373 when WITH_IGEN == 1.
2374
2375 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2376 target architecture.
2377
2378 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2379 igen. Replace with configuration variables sim_igen_flags /
2380 sim_m16_flags.
2381
2382 * m16.igen: New file. Copy mips16 insns here.
2383 * mips.igen: From here.
2384
2385Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2386
2387 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2388 to top.
2389 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2390
2391Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2392
2393 * gencode.c (build_instruction): Follow sim_write's lead in using
2394 BigEndianMem instead of !ByteSwapMem.
2395
2396Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2397
2398 * configure.in (sim_gen): Dependent on target, select type of
2399 generator. Always select old style generator.
2400
2401 configure: Re-generate.
2402
2403 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2404 targets.
2405 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2406 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2407 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2408 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2409 SIM_@sim_gen@_*, set by autoconf.
2410
2411Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2412
2413 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2414
2415 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2416 CURRENT_FLOATING_POINT instead.
2417
2418 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2419 (address_translation): Raise exception InstructionFetch when
2420 translation fails and isINSTRUCTION.
2421
2422 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2423 sim_engine_run): Change type of of vaddr and paddr to
2424 address_word.
2425 (address_translation, prefetch, load_memory, store_memory,
2426 cache_op): Change type of vAddr and pAddr to address_word.
2427
2428 * gencode.c (build_instruction): Change type of vaddr and paddr to
2429 address_word.
2430
2431Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2432
2433 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2434 macro to obtain result of ALU op.
2435
2436Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2437
2438 * interp.c (sim_info): Call profile_print.
2439
2440Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2441
2442 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2443
2444 * sim-main.h (WITH_PROFILE): Do not define, defined in
2445 common/sim-config.h. Use sim-profile module.
2446 (simPROFILE): Delete defintion.
2447
2448 * interp.c (PROFILE): Delete definition.
2449 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2450 (sim_close): Delete code writing profile histogram.
2451 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2452 Delete.
2453 (sim_engine_run): Delete code profiling the PC.
2454
2455Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2456
2457 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2458
2459 * interp.c (sim_monitor): Make register pointers of type
2460 unsigned_word*.
2461
2462 * sim-main.h: Make registers of type unsigned_word not
2463 signed_word.
2464
2465Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2466
2467 * interp.c (sync_operation): Rename from SyncOperation, make
2468 global, add SD argument.
2469 (prefetch): Rename from Prefetch, make global, add SD argument.
2470 (decode_coproc): Make global.
2471
2472 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2473
2474 * gencode.c (build_instruction): Generate DecodeCoproc not
2475 decode_coproc calls.
2476
2477 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2478 (SizeFGR): Move to sim-main.h
2479 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2480 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2481 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2482 sim-main.h.
2483 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2484 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2485 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2486 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2487 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2488 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2489
2490 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2491 exception.
2492 (sim-alu.h): Include.
2493 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2494 (sim_cia): Typedef to instruction_address.
2495
2496Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2497
2498 * Makefile.in (interp.o): Rename generated file engine.c to
2499 oengine.c.
2500
2501 * interp.c: Update.
2502
2503Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2504
2505 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2506
2507Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2508
2509 * gencode.c (build_instruction): For "FPSQRT", output correct
2510 number of arguments to Recip.
2511
2512Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2513
2514 * Makefile.in (interp.o): Depends on sim-main.h
2515
2516 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2517
2518 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2519 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2520 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2521 STATE, DSSTATE): Define
2522 (GPR, FGRIDX, ..): Define.
2523
2524 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2525 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2526 (GPR, FGRIDX, ...): Delete macros.
2527
2528 * interp.c: Update names to match defines from sim-main.h
2529
2530Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2531
2532 * interp.c (sim_monitor): Add SD argument.
2533 (sim_warning): Delete. Replace calls with calls to
2534 sim_io_eprintf.
2535 (sim_error): Delete. Replace calls with sim_io_error.
2536 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2537 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2538 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2539 argument.
2540 (mips_size): Rename from sim_size. Add SD argument.
2541
2542 * interp.c (simulator): Delete global variable.
2543 (callback): Delete global variable.
2544 (mips_option_handler, sim_open, sim_write, sim_read,
2545 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2546 sim_size,sim_monitor): Use sim_io_* not callback->*.
2547 (sim_open): ZALLOC simulator struct.
2548 (PROFILE): Do not define.
2549
2550Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2551
2552 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2553 support.h with corresponding code.
2554
2555 * sim-main.h (word64, uword64), support.h: Move definition to
2556 sim-main.h.
2557 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2558
2559 * support.h: Delete
2560 * Makefile.in: Update dependencies
2561 * interp.c: Do not include.
2562
2563Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2564
2565 * interp.c (address_translation, load_memory, store_memory,
2566 cache_op): Rename to from AddressTranslation et.al., make global,
2567 add SD argument
2568
2569 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2570 CacheOp): Define.
2571
2572 * interp.c (SignalException): Rename to signal_exception, make
2573 global.
2574
2575 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2576
2577 * sim-main.h (SignalException, SignalExceptionInterrupt,
2578 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2579 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2580 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2581 Define.
2582
2583 * interp.c, support.h: Use.
2584
2585Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2586
2587 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2588 to value_fpr / store_fpr. Add SD argument.
2589 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2590 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2591
2592 * sim-main.h (ValueFPR, StoreFPR): Define.
2593
2594Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2595
2596 * interp.c (sim_engine_run): Check consistency between configure
2597 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2598 and HASFPU.
2599
2600 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2601 (mips_fpu): Configure WITH_FLOATING_POINT.
2602 (mips_endian): Configure WITH_TARGET_ENDIAN.
2603 * configure: Update.
2604
2605Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2606
2607 * configure: Regenerated to track ../common/aclocal.m4 changes.
2608
2609Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2610
2611 * configure: Regenerated.
2612
2613Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2614
2615 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2616
2617Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2618
2619 * gencode.c (print_igen_insn_models): Assume certain architectures
2620 include all mips* instructions.
2621 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2622 instruction.
2623
2624 * Makefile.in (tmp.igen): Add target. Generate igen input from
2625 gencode file.
2626
2627 * gencode.c (FEATURE_IGEN): Define.
2628 (main): Add --igen option. Generate output in igen format.
2629 (process_instructions): Format output according to igen option.
2630 (print_igen_insn_format): New function.
2631 (print_igen_insn_models): New function.
2632 (process_instructions): Only issue warnings and ignore
2633 instructions when no FEATURE_IGEN.
2634
2635Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2636
2637 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2638 MIPS targets.
2639
2640Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2641
2642 * configure: Regenerated to track ../common/aclocal.m4 changes.
2643
2644Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2645
2646 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2647 SIM_RESERVED_BITS): Delete, moved to common.
2648 (SIM_EXTRA_CFLAGS): Update.
2649
2650Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2651
2652 * configure.in: Configure non-strict memory alignment.
2653 * configure: Regenerated to track ../common/aclocal.m4 changes.
2654
2655Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2656
2657 * configure: Regenerated to track ../common/aclocal.m4 changes.
2658
2659Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2660
2661 * gencode.c (SDBBP,DERET): Added (3900) insns.
2662 (RFE): Turn on for 3900.
2663 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2664 (dsstate): Made global.
2665 (SUBTARGET_R3900): Added.
2666 (CANCELDELAYSLOT): New.
2667 (SignalException): Ignore SystemCall rather than ignore and
2668 terminate. Add DebugBreakPoint handling.
2669 (decode_coproc): New insns RFE, DERET; and new registers Debug
2670 and DEPC protected by SUBTARGET_R3900.
2671 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2672 bits explicitly.
2673 * Makefile.in,configure.in: Add mips subtarget option.
2674 * configure: Update.
2675
2676Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2677
2678 * gencode.c: Add r3900 (tx39).
2679
2680
2681Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2682
2683 * gencode.c (build_instruction): Don't need to subtract 4 for
2684 JALR, just 2.
2685
2686Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2687
2688 * interp.c: Correct some HASFPU problems.
2689
2690Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2691
2692 * configure: Regenerated to track ../common/aclocal.m4 changes.
2693
2694Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2695
2696 * interp.c (mips_options): Fix samples option short form, should
2697 be `x'.
2698
2699Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2700
2701 * interp.c (sim_info): Enable info code. Was just returning.
2702
2703Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2704
2705 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2706 MFC0.
2707
2708Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2709
2710 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2711 constants.
2712 (build_instruction): Ditto for LL.
2713
2714Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2715
2716 * configure: Regenerated to track ../common/aclocal.m4 changes.
2717
2718Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2719
2720 * configure: Regenerated to track ../common/aclocal.m4 changes.
2721 * config.in: Ditto.
2722
2723Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2724
2725 * interp.c (sim_open): Add call to sim_analyze_program, update
2726 call to sim_config.
2727
2728Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2729
2730 * interp.c (sim_kill): Delete.
2731 (sim_create_inferior): Add ABFD argument. Set PC from same.
2732 (sim_load): Move code initializing trap handlers from here.
2733 (sim_open): To here.
2734 (sim_load): Delete, use sim-hload.c.
2735
2736 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2737
2738Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2739
2740 * configure: Regenerated to track ../common/aclocal.m4 changes.
2741 * config.in: Ditto.
2742
2743Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2744
2745 * interp.c (sim_open): Add ABFD argument.
2746 (sim_load): Move call to sim_config from here.
2747 (sim_open): To here. Check return status.
2748
2749Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2750
2751 * gencode.c (build_instruction): Two arg MADD should
2752 not assign result to $0.
2753
2754Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2755
2756 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2757 * sim/mips/configure.in: Regenerate.
2758
2759Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2760
2761 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2762 signed8, unsigned8 et.al. types.
2763
2764 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2765 hosts when selecting subreg.
2766
2767Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2768
2769 * interp.c (sim_engine_run): Reset the ZERO register to zero
2770 regardless of FEATURE_WARN_ZERO.
2771 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2772
2773Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2774
2775 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2776 (SignalException): For BreakPoints ignore any mode bits and just
2777 save the PC.
2778 (SignalException): Always set the CAUSE register.
2779
2780Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2781
2782 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2783 exception has been taken.
2784
2785 * interp.c: Implement the ERET and mt/f sr instructions.
2786
2787Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2788
2789 * interp.c (SignalException): Don't bother restarting an
2790 interrupt.
2791
2792Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2793
2794 * interp.c (SignalException): Really take an interrupt.
2795 (interrupt_event): Only deliver interrupts when enabled.
2796
2797Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2798
2799 * interp.c (sim_info): Only print info when verbose.
2800 (sim_info) Use sim_io_printf for output.
2801
2802Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2803
2804 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2805 mips architectures.
2806
2807Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2808
2809 * interp.c (sim_do_command): Check for common commands if a
2810 simulator specific command fails.
2811
2812Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2813
2814 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2815 and simBE when DEBUG is defined.
2816
2817Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2818
2819 * interp.c (interrupt_event): New function. Pass exception event
2820 onto exception handler.
2821
2822 * configure.in: Check for stdlib.h.
2823 * configure: Regenerate.
2824
2825 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2826 variable declaration.
2827 (build_instruction): Initialize memval1.
2828 (build_instruction): Add UNUSED attribute to byte, bigend,
2829 reverse.
2830 (build_operands): Ditto.
2831
2832 * interp.c: Fix GCC warnings.
2833 (sim_get_quit_code): Delete.
2834
2835 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2836 * Makefile.in: Ditto.
2837 * configure: Re-generate.
2838
2839 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2840
2841Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2842
2843 * interp.c (mips_option_handler): New function parse argumes using
2844 sim-options.
2845 (myname): Replace with STATE_MY_NAME.
2846 (sim_open): Delete check for host endianness - performed by
2847 sim_config.
2848 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2849 (sim_open): Move much of the initialization from here.
2850 (sim_load): To here. After the image has been loaded and
2851 endianness set.
2852 (sim_open): Move ColdReset from here.
2853 (sim_create_inferior): To here.
2854 (sim_open): Make FP check less dependant on host endianness.
2855
2856 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2857 run.
2858 * interp.c (sim_set_callbacks): Delete.
2859
2860 * interp.c (membank, membank_base, membank_size): Replace with
2861 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2862 (sim_open): Remove call to callback->init. gdb/run do this.
2863
2864 * interp.c: Update
2865
2866 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2867
2868 * interp.c (big_endian_p): Delete, replaced by
2869 current_target_byte_order.
2870
2871Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2872
2873 * interp.c (host_read_long, host_read_word, host_swap_word,
2874 host_swap_long): Delete. Using common sim-endian.
2875 (sim_fetch_register, sim_store_register): Use H2T.
2876 (pipeline_ticks): Delete. Handled by sim-events.
2877 (sim_info): Update.
2878 (sim_engine_run): Update.
2879
2880Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2881
2882 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2883 reason from here.
2884 (SignalException): To here. Signal using sim_engine_halt.
2885 (sim_stop_reason): Delete, moved to common.
2886
2887Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2888
2889 * interp.c (sim_open): Add callback argument.
2890 (sim_set_callbacks): Delete SIM_DESC argument.
2891 (sim_size): Ditto.
2892
2893Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2894
2895 * Makefile.in (SIM_OBJS): Add common modules.
2896
2897 * interp.c (sim_set_callbacks): Also set SD callback.
2898 (set_endianness, xfer_*, swap_*): Delete.
2899 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2900 Change to functions using sim-endian macros.
2901 (control_c, sim_stop): Delete, use common version.
2902 (simulate): Convert into.
2903 (sim_engine_run): This function.
2904 (sim_resume): Delete.
2905
2906 * interp.c (simulation): New variable - the simulator object.
2907 (sim_kind): Delete global - merged into simulation.
2908 (sim_load): Cleanup. Move PC assignment from here.
2909 (sim_create_inferior): To here.
2910
2911 * sim-main.h: New file.
2912 * interp.c (sim-main.h): Include.
2913
2914Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2915
2916 * configure: Regenerated to track ../common/aclocal.m4 changes.
2917
2918Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2919
2920 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2921
2922Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2923
2924 * gencode.c (build_instruction): DIV instructions: check
2925 for division by zero and integer overflow before using
2926 host's division operation.
2927
2928Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2929
2930 * Makefile.in (SIM_OBJS): Add sim-load.o.
2931 * interp.c: #include bfd.h.
2932 (target_byte_order): Delete.
2933 (sim_kind, myname, big_endian_p): New static locals.
2934 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2935 after argument parsing. Recognize -E arg, set endianness accordingly.
2936 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2937 load file into simulator. Set PC from bfd.
2938 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2939 (set_endianness): Use big_endian_p instead of target_byte_order.
2940
2941Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2942
2943 * interp.c (sim_size): Delete prototype - conflicts with
2944 definition in remote-sim.h. Correct definition.
2945
2946Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2947
2948 * configure: Regenerated to track ../common/aclocal.m4 changes.
2949 * config.in: Ditto.
2950
2951Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2952
2953 * interp.c (sim_open): New arg `kind'.
2954
2955 * configure: Regenerated to track ../common/aclocal.m4 changes.
2956
2957Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2958
2959 * configure: Regenerated to track ../common/aclocal.m4 changes.
2960
2961Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2962
2963 * interp.c (sim_open): Set optind to 0 before calling getopt.
2964
2965Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2966
2967 * configure: Regenerated to track ../common/aclocal.m4 changes.
2968
2969Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2970
2971 * interp.c : Replace uses of pr_addr with pr_uword64
2972 where the bit length is always 64 independent of SIM_ADDR.
2973 (pr_uword64) : added.
2974
2975Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2976
2977 * configure: Re-generate.
2978
2979Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2980
2981 * configure: Regenerate to track ../common/aclocal.m4 changes.
2982
2983Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2984
2985 * interp.c (sim_open): New SIM_DESC result. Argument is now
2986 in argv form.
2987 (other sim_*): New SIM_DESC argument.
2988
2989Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2990
2991 * interp.c: Fix printing of addresses for non-64-bit targets.
2992 (pr_addr): Add function to print address based on size.
2993
2994Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2995
2996 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2997
2998Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2999
3000 * gencode.c (build_mips16_operands): Correct computation of base
3001 address for extended PC relative instruction.
3002
3003Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3004
3005 * interp.c (mips16_entry): Add support for floating point cases.
3006 (SignalException): Pass floating point cases to mips16_entry.
3007 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3008 registers.
3009 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3010 or fmt_word.
3011 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3012 and then set the state to fmt_uninterpreted.
3013 (COP_SW): Temporarily set the state to fmt_word while calling
3014 ValueFPR.
3015
3016Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3017
3018 * gencode.c (build_instruction): The high order may be set in the
3019 comparison flags at any ISA level, not just ISA 4.
3020
3021Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3022
3023 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3024 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3025 * configure.in: sinclude ../common/aclocal.m4.
3026 * configure: Regenerated.
3027
3028Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3029
3030 * configure: Rebuild after change to aclocal.m4.
3031
3032Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3033
3034 * configure configure.in Makefile.in: Update to new configure
3035 scheme which is more compatible with WinGDB builds.
3036 * configure.in: Improve comment on how to run autoconf.
3037 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3038 * Makefile.in: Use autoconf substitution to install common
3039 makefile fragment.
3040
3041Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3042
3043 * gencode.c (build_instruction): Use BigEndianCPU instead of
3044 ByteSwapMem.
3045
3046Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3047
3048 * interp.c (sim_monitor): Make output to stdout visible in
3049 wingdb's I/O log window.
3050
3051Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3052
3053 * support.h: Undo previous change to SIGTRAP
3054 and SIGQUIT values.
3055
3056Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3057
3058 * interp.c (store_word, load_word): New static functions.
3059 (mips16_entry): New static function.
3060 (SignalException): Look for mips16 entry and exit instructions.
3061 (simulate): Use the correct index when setting fpr_state after
3062 doing a pending move.
3063
3064Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3065
3066 * interp.c: Fix byte-swapping code throughout to work on
3067 both little- and big-endian hosts.
3068
3069Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3070
3071 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3072 with gdb/config/i386/xm-windows.h.
3073
3074Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3075
3076 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3077 that messes up arithmetic shifts.
3078
3079Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3080
3081 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3082 SIGTRAP and SIGQUIT for _WIN32.
3083
3084Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3085
3086 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3087 force a 64 bit multiplication.
3088 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3089 destination register is 0, since that is the default mips16 nop
3090 instruction.
3091
3092Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3093
3094 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3095 (build_endian_shift): Don't check proc64.
3096 (build_instruction): Always set memval to uword64. Cast op2 to
3097 uword64 when shifting it left in memory instructions. Always use
3098 the same code for stores--don't special case proc64.
3099
3100 * gencode.c (build_mips16_operands): Fix base PC value for PC
3101 relative operands.
3102 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3103 jal instruction.
3104 * interp.c (simJALDELAYSLOT): Define.
3105 (JALDELAYSLOT): Define.
3106 (INDELAYSLOT, INJALDELAYSLOT): Define.
3107 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3108
3109Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3110
3111 * interp.c (sim_open): add flush_cache as a PMON routine
3112 (sim_monitor): handle flush_cache by ignoring it
3113
3114Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3115
3116 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3117 BigEndianMem.
3118 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3119 (BigEndianMem): Rename to ByteSwapMem and change sense.
3120 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3121 BigEndianMem references to !ByteSwapMem.
3122 (set_endianness): New function, with prototype.
3123 (sim_open): Call set_endianness.
3124 (sim_info): Use simBE instead of BigEndianMem.
3125 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3126 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3127 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3128 ifdefs, keeping the prototype declaration.
3129 (swap_word): Rewrite correctly.
3130 (ColdReset): Delete references to CONFIG. Delete endianness related
3131 code; moved to set_endianness.
3132
3133Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3134
3135 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3136 * interp.c (CHECKHILO): Define away.
3137 (simSIGINT): New macro.
3138 (membank_size): Increase from 1MB to 2MB.
3139 (control_c): New function.
3140 (sim_resume): Rename parameter signal to signal_number. Add local
3141 variable prev. Call signal before and after simulate.
3142 (sim_stop_reason): Add simSIGINT support.
3143 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3144 functions always.
3145 (sim_warning): Delete call to SignalException. Do call printf_filtered
3146 if logfh is NULL.
3147 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3148 a call to sim_warning.
3149
3150Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3151
3152 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3153 16 bit instructions.
3154
3155Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3156
3157 Add support for mips16 (16 bit MIPS implementation):
3158 * gencode.c (inst_type): Add mips16 instruction encoding types.
3159 (GETDATASIZEINSN): Define.
3160 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3161 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3162 mtlo.
3163 (MIPS16_DECODE): New table, for mips16 instructions.
3164 (bitmap_val): New static function.
3165 (struct mips16_op): Define.
3166 (mips16_op_table): New table, for mips16 operands.
3167 (build_mips16_operands): New static function.
3168 (process_instructions): If PC is odd, decode a mips16
3169 instruction. Break out instruction handling into new
3170 build_instruction function.
3171 (build_instruction): New static function, broken out of
3172 process_instructions. Check modifiers rather than flags for SHIFT
3173 bit count and m[ft]{hi,lo} direction.
3174 (usage): Pass program name to fprintf.
3175 (main): Remove unused variable this_option_optind. Change
3176 ``*loptarg++'' to ``loptarg++''.
3177 (my_strtoul): Parenthesize && within ||.
3178 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3179 (simulate): If PC is odd, fetch a 16 bit instruction, and
3180 increment PC by 2 rather than 4.
3181 * configure.in: Add case for mips16*-*-*.
3182 * configure: Rebuild.
3183
3184Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3185
3186 * interp.c: Allow -t to enable tracing in standalone simulator.
3187 Fix garbage output in trace file and error messages.
3188
3189Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3190
3191 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3192 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3193 * configure.in: Simplify using macros in ../common/aclocal.m4.
3194 * configure: Regenerated.
3195 * tconfig.in: New file.
3196
3197Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3198
3199 * interp.c: Fix bugs in 64-bit port.
3200 Use ansi function declarations for msvc compiler.
3201 Initialize and test file pointer in trace code.
3202 Prevent duplicate definition of LAST_EMED_REGNUM.
3203
3204Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3205
3206 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3207
3208Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3209
3210 * interp.c (SignalException): Check for explicit terminating
3211 breakpoint value.
3212 * gencode.c: Pass instruction value through SignalException()
3213 calls for Trap, Breakpoint and Syscall.
3214
3215Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3216
3217 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3218 only used on those hosts that provide it.
3219 * configure.in: Add sqrt() to list of functions to be checked for.
3220 * config.in: Re-generated.
3221 * configure: Re-generated.
3222
3223Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3224
3225 * gencode.c (process_instructions): Call build_endian_shift when
3226 expanding STORE RIGHT, to fix swr.
3227 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3228 clear the high bits.
3229 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3230 Fix float to int conversions to produce signed values.
3231
3232Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3233
3234 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3235 (process_instructions): Correct handling of nor instruction.
3236 Correct shift count for 32 bit shift instructions. Correct sign
3237 extension for arithmetic shifts to not shift the number of bits in
3238 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3239 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3240 Fix madd.
3241 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3242 It's OK to have a mult follow a mult. What's not OK is to have a
3243 mult follow an mfhi.
3244 (Convert): Comment out incorrect rounding code.
3245
3246Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3247
3248 * interp.c (sim_monitor): Improved monitor printf
3249 simulation. Tidied up simulator warnings, and added "--log" option
3250 for directing warning message output.
3251 * gencode.c: Use sim_warning() rather than WARNING macro.
3252
3253Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3254
3255 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3256 getopt1.o, rather than on gencode.c. Link objects together.
3257 Don't link against -liberty.
3258 (gencode.o, getopt.o, getopt1.o): New targets.
3259 * gencode.c: Include <ctype.h> and "ansidecl.h".
3260 (AND): Undefine after including "ansidecl.h".
3261 (ULONG_MAX): Define if not defined.
3262 (OP_*): Don't define macros; now defined in opcode/mips.h.
3263 (main): Call my_strtoul rather than strtoul.
3264 (my_strtoul): New static function.
3265
3266Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3267
3268 * gencode.c (process_instructions): Generate word64 and uword64
3269 instead of `long long' and `unsigned long long' data types.
3270 * interp.c: #include sysdep.h to get signals, and define default
3271 for SIGBUS.
3272 * (Convert): Work around for Visual-C++ compiler bug with type
3273 conversion.
3274 * support.h: Make things compile under Visual-C++ by using
3275 __int64 instead of `long long'. Change many refs to long long
3276 into word64/uword64 typedefs.
3277
3278Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3279
3280 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3281 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3282 (docdir): Removed.
3283 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3284 (AC_PROG_INSTALL): Added.
3285 (AC_PROG_CC): Moved to before configure.host call.
3286 * configure: Rebuilt.
3287
3288Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3289
3290 * configure.in: Define @SIMCONF@ depending on mips target.
3291 * configure: Rebuild.
3292 * Makefile.in (run): Add @SIMCONF@ to control simulator
3293 construction.
3294 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3295 * interp.c: Remove some debugging, provide more detailed error
3296 messages, update memory accesses to use LOADDRMASK.
3297
3298Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3299
3300 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3301 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3302 stamp-h.
3303 * configure: Rebuild.
3304 * config.in: New file, generated by autoheader.
3305 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3306 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3307 HAVE_ANINT and HAVE_AINT, as appropriate.
3308 * Makefile.in (run): Use @LIBS@ rather than -lm.
3309 (interp.o): Depend upon config.h.
3310 (Makefile): Just rebuild Makefile.
3311 (clean): Remove stamp-h.
3312 (mostlyclean): Make the same as clean, not as distclean.
3313 (config.h, stamp-h): New targets.
3314
3315Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3316
3317 * interp.c (ColdReset): Fix boolean test. Make all simulator
3318 globals static.
3319
3320Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3321
3322 * interp.c (xfer_direct_word, xfer_direct_long,
3323 swap_direct_word, swap_direct_long, xfer_big_word,
3324 xfer_big_long, xfer_little_word, xfer_little_long,
3325 swap_word,swap_long): Added.
3326 * interp.c (ColdReset): Provide function indirection to
3327 host<->simulated_target transfer routines.
3328 * interp.c (sim_store_register, sim_fetch_register): Updated to
3329 make use of indirected transfer routines.
3330
3331Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3332
3333 * gencode.c (process_instructions): Ensure FP ABS instruction
3334 recognised.
3335 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3336 system call support.
3337
3338Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3339
3340 * interp.c (sim_do_command): Complain if callback structure not
3341 initialised.
3342
3343Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3344
3345 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3346 support for Sun hosts.
3347 * Makefile.in (gencode): Ensure the host compiler and libraries
3348 used for cross-hosted build.
3349
3350Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3351
3352 * interp.c, gencode.c: Some more (TODO) tidying.
3353
3354Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3355
3356 * gencode.c, interp.c: Replaced explicit long long references with
3357 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3358 * support.h (SET64LO, SET64HI): Macros added.
3359
3360Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3361
3362 * configure: Regenerate with autoconf 2.7.
3363
3364Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3365
3366 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3367 * support.h: Remove superfluous "1" from #if.
3368 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3369
3370Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3371
3372 * interp.c (StoreFPR): Control UndefinedResult() call on
3373 WARN_RESULT manifest.
3374
3375Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3376
3377 * gencode.c: Tidied instruction decoding, and added FP instruction
3378 support.
3379
3380 * interp.c: Added dineroIII, and BSD profiling support. Also
3381 run-time FP handling.
3382
3383Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3384
3385 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3386 gencode.c, interp.c, support.h: created.
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