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CommitLineData
d6416cdc
RW		 12009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
2
81ecdfbb
RW		 3 * config.in: Regenerate.
4 * configure: Likewise.
5
d6416cdc
RW		 6 * configure: Regenerate.
7
b5bd9624
HPN		 82008-07-11 Hans-Peter Nilsson <hp@axis.com>
9
10 * configure: Regenerate to track ../common/common.m4 changes.
11 * config.in: Ditto.
12
6efef468
JM		 132008-06-06 Vladimir Prus <vladimir@codesourcery.com>
14 Daniel Jacobowitz <dan@codesourcery.com>
15 Joseph Myers <joseph@codesourcery.com>
16
17 * configure: Regenerate.
18
60dc88db
RS		 192007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
20
21 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
22 that unconditionally allows fmt_ps.
23 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
24 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
25 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
26 filter from 64,f to 32,f.
27 (PREFX): Change filter from 64 to 32.
28 (LDXC1, LUXC1): Provide separate mips32r2 implementations
29 that use do_load_double instead of do_load. Make both LUXC1
30 versions unpredictable if SizeFGR () != 64.
31 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
32 instead of do_store. Remove unused variable. Make both SUXC1
33 versions unpredictable if SizeFGR () != 64.
34
599ca73e
RS		 352007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
36
37 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
38 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
39 shifts for that case.
40
2525df03
NC		 412007-09-04 Nick Clifton <nickc@redhat.com>
42
43 * interp.c (options enum): Add OPTION_INFO_MEMORY.
44 (display_mem_info): New static variable.
45 (mips_option_handler): Handle OPTION_INFO_MEMORY.
46 (mips_options): Add info-memory and memory-info.
47 (sim_open): After processing the command line and board
48 specification, check display_mem_info. If it is set then
49 call the real handler for the --memory-info command line
50 switch.
51
35ee6e1e
JB		 522007-08-24 Joel Brobecker <brobecker@adacore.com>
53
54 * configure.ac: Change license of multi-run.c to GPL version 3.
55 * configure: Regenerate.
56
d5fb0879
RS		 572007-06-28 Richard Sandiford <richard@codesourcery.com>
58
59 * configure.ac, configure: Revert last patch.
60
2a2ce21b
RS		 612007-06-26 Richard Sandiford <richard@codesourcery.com>
62
63 * configure.ac (sim_mipsisa3264_configs): New variable.
64 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
65 every configuration support all four targets, using the triplet to
66 determine the default.
67 * configure: Regenerate.
68
efdcccc9
RS		 692007-06-25 Richard Sandiford <richard@codesourcery.com>
70
0a7692b2 71 * Makefile.in (m16run.o): New rule.
efdcccc9 72
f532a356
TS		 732007-05-15 Thiemo Seufer <ths@mips.com>
74
75 * mips3264r2.igen (DSHD): Fix compile warning.
76
bfe9c90b
TS		 772007-05-14 Thiemo Seufer <ths@mips.com>
78
79 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
80 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
81 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
82 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
83 for mips32r2.
84
53f4826b
TS		 852007-03-01 Thiemo Seufer <ths@mips.com>
86
87 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
88 and mips64.
89
8bf3ddc8
TS		 902007-02-20 Thiemo Seufer <ths@mips.com>
91
92 * dsp.igen: Update copyright notice.
93 * dsp2.igen: Fix copyright notice.
94
8b082fb1
TS		 952007-02-20 Thiemo Seufer <ths@mips.com>
96 Chao-Ying Fu <fu@mips.com>
97
98 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
99 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
100 Add dsp2 to sim_igen_machine.
101 * configure: Regenerate.
102 * dsp.igen (do_ph_op): Add MUL support when op = 2.
103 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
104 (mulq_rs.ph): Use do_ph_mulq.
105 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
106 * mips.igen: Add dsp2 model and include dsp2.igen.
107 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
108 for *mips32r2, *mips64r2, *dsp.
109 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
110 for *mips32r2, *mips64r2, *dsp2.
111 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
112
b1004875
TS		 1132007-02-19 Thiemo Seufer <ths@mips.com>
114 Nigel Stephens <nigel@mips.com>
115
116 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
117 jumps with hazard barrier.
118
f8df4c77
TS		 1192007-02-19 Thiemo Seufer <ths@mips.com>
120 Nigel Stephens <nigel@mips.com>
121
122 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
123 after each call to sim_io_write.
124
b1004875 1252007-02-19 Thiemo Seufer <ths@mips.com>
07802d98 126 Nigel Stephens <nigel@mips.com>
b1004875
TS		 127
128 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
129 supported by this simulator.
07802d98
TS		 130 (decode_coproc): Recognise additional CP0 Config registers
131 correctly.
132
14fb6c5a
TS		 1332007-02-19 Thiemo Seufer <ths@mips.com>
134 Nigel Stephens <nigel@mips.com>
135 David Ung <davidu@mips.com>
136
137 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
138 uninterpreted formats. If fmt is one of the uninterpreted types
139 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
140 fmt_word, and fmt_uninterpreted_64 like fmt_long.
141 (store_fpr): When writing an invalid odd register, set the
142 matching even register to fmt_unknown, not the following register.
143 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
144 the the memory window at offset 0 set by --memory-size command
145 line option.
146 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
147 point register.
148 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
149 register.
150 (sim_monitor): When returning the memory size to the MIPS
151 application, use the value in STATE_MEM_SIZE, not an arbitrary
152 hardcoded value.
153 (cop_lw): Don' mess around with FPR_STATE, just pass
154 fmt_uninterpreted_32 to StoreFPR.
155 (cop_sw): Similarly.
156 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
157 (cop_sd): Similarly.
158 * mips.igen (not_word_value): Single version for mips32, mips64
159 and mips16.
160
c8847145
TS		 1612007-02-19 Thiemo Seufer <ths@mips.com>
162 Nigel Stephens <nigel@mips.com>
163
164 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
165 MBytes.
166
4b5d35ee
TS		 1672007-02-17 Thiemo Seufer <ths@mips.com>
168
169 * configure.ac (mips*-sde-elf*): Move in front of generic machine
170 configuration.
171 * configure: Regenerate.
172
3669427c
TS		 1732007-02-17 Thiemo Seufer <ths@mips.com>
174
175 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
176 Add mdmx to sim_igen_machine.
177 (mipsisa64*-*-*): Likewise. Remove dsp.
178 (mipsisa32*-*-*): Remove dsp.
179 * configure: Regenerate.
180
109ad085
TS		 1812007-02-13 Thiemo Seufer <ths@mips.com>
182
183 * configure.ac: Add mips*-sde-elf* target.
184 * configure: Regenerate.
185
921d7ad3
HPN		 1862006-12-21 Hans-Peter Nilsson <hp@axis.com>
187
188 * acconfig.h: Remove.
189 * config.in, configure: Regenerate.
190
02f97da7
TS		 1912006-11-07 Thiemo Seufer <ths@mips.com>
192
193 * dsp.igen (do_w_op): Fix compiler warning.
194
2d2733fc
TS		 1952006-08-29 Thiemo Seufer <ths@mips.com>
196 David Ung <davidu@mips.com>
197
198 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
199 sim_igen_machine.
200 * configure: Regenerate.
201 * mips.igen (model): Add smartmips.
202 (MADDU): Increment ACX if carry.
203 (do_mult): Clear ACX.
204 (ROR,RORV): Add smartmips.
205 (include): Include smartmips.igen.
206 * sim-main.h (ACX): Set to REGISTERS[89].
207 * smartmips.igen: New file.
208
d85c3a10
TS		 2092006-08-29 Thiemo Seufer <ths@mips.com>
210 David Ung <davidu@mips.com>
211
212 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
213 mips3264r2.igen. Add missing dependency rules.
214 * m16e.igen: Support for mips16e save/restore instructions.
215
e85e3205
RE		 2162006-06-13 Richard Earnshaw <rearnsha@arm.com>
217
218 * configure: Regenerated.
219
2f0122dc
DJ		 2202006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
221
222 * configure: Regenerated.
223
20e95c23
DJ		 2242006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
225
226 * configure: Regenerated.
227
69088b17
CF		 2282006-05-15 Chao-ying Fu <fu@mips.com>
229
230 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
231
0275de4e
NC		 2322006-04-18 Nick Clifton <nickc@redhat.com>
233
234 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
235 statement.
236
b3a3ffef
HPN		 2372006-03-29 Hans-Peter Nilsson <hp@axis.com>
238
239 * configure: Regenerate.
240
40a5538e
CF		 2412005-12-14 Chao-ying Fu <fu@mips.com>
242
243 * Makefile.in (SIM_OBJS): Add dsp.o.
244 (dsp.o): New dependency.
245 (IGEN_INCLUDE): Add dsp.igen.
246 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
247 mipsisa64*-*-*): Add dsp to sim_igen_machine.
248 * configure: Regenerate.
249 * mips.igen: Add dsp model and include dsp.igen.
250 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
251 because these instructions are extended in DSP ASE.
252 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
253 adding 6 DSP accumulator registers and 1 DSP control register.
254 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
255 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
256 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
257 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
258 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
259 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
260 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
261 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
262 DSPCR_CCOND_SMASK): New define.
263 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
264 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
265
21d14896
ILT		 2662005-07-08 Ian Lance Taylor <ian@airs.com>
267
268 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
269
b16d63da
DU		 2702005-06-16 David Ung <davidu@mips.com>
271 Nigel Stephens <nigel@mips.com>
272
273 * mips.igen: New mips16e model and include m16e.igen.
274 (check_u64): Add mips16e tag.
275 * m16e.igen: New file for MIPS16e instructions.
276 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
277 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
278 models.
279 * configure: Regenerate.
280
e70cb6cd
CD		 2812005-05-26 David Ung <davidu@mips.com>
282
283 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
284 tags to all instructions which are applicable to the new ISAs.
285 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
286 vr.igen.
287 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
288 instructions.
289 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
290 to mips.igen.
291 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
292 * configure: Regenerate.
293
2b193c4a
MK		 2942005-03-23 Mark Kettenis <kettenis@gnu.org>
295
296 * configure: Regenerate.
297
35695fd6
AC		 2982005-01-14 Andrew Cagney <cagney@gnu.org>
299
300 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
301 explicit call to AC_CONFIG_HEADER.
302 * configure: Regenerate.
303
f0569246
AC		 3042005-01-12 Andrew Cagney <cagney@gnu.org>
305
306 * configure.ac: Update to use ../common/common.m4.
307 * configure: Re-generate.
308
38f48d72
AC		 3092005-01-11 Andrew Cagney <cagney@localhost.localdomain>
310
311 * configure: Regenerated to track ../common/aclocal.m4 changes.
312
b7026657
AC		 3132005-01-07 Andrew Cagney <cagney@gnu.org>
314
315 * configure.ac: Rename configure.in, require autoconf 2.59.
316 * configure: Re-generate.
317
379832de
HPN		 3182004-12-08 Hans-Peter Nilsson <hp@axis.com>
319
320 * configure: Regenerate for ../common/aclocal.m4 update.
321
cd62154c
AC		 3222004-09-24 Monika Chaddha <monika@acmet.com>
323
324 Committed by Andrew Cagney.
325 * m16.igen (CMP, CMPI): Fix assembler.
326
e5da76ec
CD		 3272004-08-18 Chris Demetriou <cgd@broadcom.com>
328
329 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
330 * configure: Regenerate.
331
139181c8
CD		 3322004-06-25 Chris Demetriou <cgd@broadcom.com>
333
334 * configure.in (sim_m16_machine): Include mipsIII.
335 * configure: Regenerate.
336
1a27f959
CD		 3372004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
338
339 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
340 from COP0_BADVADDR.
341 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
342
5dbb7b5a
CD		 3432004-04-10 Chris Demetriou <cgd@broadcom.com>
344
345 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
346
14234056
CD		 3472004-04-09 Chris Demetriou <cgd@broadcom.com>
348
349 * mips.igen (check_fmt): Remove.
350 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
351 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
352 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
353 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
354 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
355 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
356 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
357 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
358 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
359 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
360
c6f9085c
CD		 3612004-04-09 Chris Demetriou <cgd@broadcom.com>
362
363 * sb1.igen (check_sbx): New function.
364 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
365
11d66e66 3662004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 367 Richard Sandiford <rsandifo@redhat.com>
368
369 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
370 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
371 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
372 separate implementations for mipsIV and mipsV. Use new macros to
373 determine whether the restrictions apply.
374
b3208fb8
CD		 3752004-01-19 Chris Demetriou <cgd@broadcom.com>
376
377 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
378 (check_mult_hilo): Improve comments.
379 (check_div_hilo): Likewise. Also, fork off a new version
380 to handle mips32/mips64 (since there are no hazards to check
381 in MIPS32/MIPS64).
382
9a1d84fb
CD		 3832003-06-17 Richard Sandiford <rsandifo@redhat.com>
384
385 * mips.igen (do_dmultx): Fix check for negative operands.
386
ae451ac6
ILT		 3872003-05-16 Ian Lance Taylor <ian@airs.com>
388
389 * Makefile.in (SHELL): Make sure this is defined.
390 (various): Use $(SHELL) whenever we invoke move-if-change.
391
dd69d292
CD		 3922003-05-03 Chris Demetriou <cgd@broadcom.com>
393
394 * cp1.c: Tweak attribution slightly.
395 * cp1.h: Likewise.
396 * mdmx.c: Likewise.
397 * mdmx.igen: Likewise.
398 * mips3d.igen: Likewise.
399 * sb1.igen: Likewise.
400
bcd0068e
CD		 4012003-04-15 Richard Sandiford <rsandifo@redhat.com>
402
403 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
404 unsigned operands.
405
6b4a8935
AC		 4062003-02-27 Andrew Cagney <cagney@redhat.com>
407
601da316
AC		 408 * interp.c (sim_open): Rename _bfd to bfd.
409 (sim_create_inferior): Ditto.
6b4a8935 410
d29e330f
CD		 4112003-01-14 Chris Demetriou <cgd@broadcom.com>
412
413 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
414
a2353a08
CD		 4152003-01-14 Chris Demetriou <cgd@broadcom.com>
416
417 * mips.igen (EI, DI): Remove.
418
80551777
CD		 4192003-01-05 Richard Sandiford <rsandifo@redhat.com>
420
421 * Makefile.in (tmp-run-multi): Fix mips16 filter.
422
4c54fc26
CD		 4232003-01-04 Richard Sandiford <rsandifo@redhat.com>
424 Andrew Cagney <ac131313@redhat.com>
425 Gavin Romig-Koch <gavin@redhat.com>
426 Graydon Hoare <graydon@redhat.com>
427 Aldy Hernandez <aldyh@redhat.com>
428 Dave Brolley <brolley@redhat.com>
429 Chris Demetriou <cgd@broadcom.com>
430
431 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
432 (sim_mach_default): New variable.
433 (mips64vr-*-*, mips64vrel-*-*): New configurations.
434 Add a new simulator generator, MULTI.
435 * configure: Regenerate.
436 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
437 (multi-run.o): New dependency.
438 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
439 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
440 (tmp-multi): Combine them.
441 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
442 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
443 (distclean-extra): New rule.
444 * sim-main.h: Include bfd.h.
445 (MIPS_MACH): New macro.
446 * mips.igen (vr4120, vr5400, vr5500): New models.
447 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
448 * vr.igen: Replace with new version.
449
e6c674b8
CD		 4502003-01-04 Chris Demetriou <cgd@broadcom.com>
451
452 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
453 * configure: Regenerate.
454
28f50ac8
CD		 4552002-12-31 Chris Demetriou <cgd@broadcom.com>
456
457 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
458 * mips.igen: Remove all invocations of check_branch_bug and
459 mark_branch_bug.
460
5071ffe6
CD		 4612002-12-16 Chris Demetriou <cgd@broadcom.com>
462
463 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
464
06e7837e
CD		 4652002-07-30 Chris Demetriou <cgd@broadcom.com>
466
467 * mips.igen (do_load_double, do_store_double): New functions.
468 (LDC1, SDC1): Rename to...
469 (LDC1b, SDC1b): respectively.
470 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
471
2265c243
MS		 4722002-07-29 Michael Snyder <msnyder@redhat.com>
473
474 * cp1.c (fp_recip2): Modify initialization expression so that
475 GCC will recognize it as constant.
476
a2f8b4f3
CD		 4772002-06-18 Chris Demetriou <cgd@broadcom.com>
478
479 * mdmx.c (SD_): Delete.
480 (Unpredictable): Re-define, for now, to directly invoke
481 unpredictable_action().
482 (mdmx_acc_op): Fix error in .ob immediate handling.
483
b4b6c939
AC		 4842002-06-18 Andrew Cagney <cagney@redhat.com>
485
486 * interp.c (sim_firmware_command): Initialize `address'.
487
c8cca39f
AC		 4882002-06-16 Andrew Cagney <ac131313@redhat.com>
489
490 * configure: Regenerated to track ../common/aclocal.m4 changes.
491
e7e81181
CD		 4922002-06-14 Chris Demetriou <cgd@broadcom.com>
493 Ed Satterthwaite <ehs@broadcom.com>
494
495 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
496 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
497 * mips.igen: Include mips3d.igen.
498 (mips3d): New model name for MIPS-3D ASE instructions.
499 (CVT.W.fmt): Don't use this instruction for word (source) format
500 instructions.
501 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
502 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
503 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
504 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
505 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
506 (RSquareRoot1, RSquareRoot2): New macros.
507 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
508 (fp_rsqrt2): New functions.
509 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
510 * configure: Regenerate.
511
3a2b820e 5122002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 513 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 514
515 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
516 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
517 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
518 (convert): Note that this function is not used for paired-single
519 format conversions.
520 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
521 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
522 (check_fmt_p): Enable paired-single support.
523 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
524 (PUU.PS): New instructions.
525 (CVT.S.fmt): Don't use this instruction for paired-single format
526 destinations.
527 * sim-main.h (FP_formats): New value 'fmt_ps.'
528 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
529 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
530
d18ea9c2
CD		 5312002-06-12 Chris Demetriou <cgd@broadcom.com>
532
533 * mips.igen: Fix formatting of function calls in
534 many FP operations.
535
95fd5cee
CD		 5362002-06-12 Chris Demetriou <cgd@broadcom.com>
537
538 * mips.igen (MOVN, MOVZ): Trace result.
539 (TNEI): Print "tnei" as the opcode name in traces.
540 (CEIL.W): Add disassembly string for traces.
541 (RSQRT.fmt): Make location of disassembly string consistent
542 with other instructions.
543
4f0d55ae
CD		 5442002-06-12 Chris Demetriou <cgd@broadcom.com>
545
546 * mips.igen (X): Delete unused function.
547
3c25f8c7
AC		 5482002-06-08 Andrew Cagney <cagney@redhat.com>
549
550 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
551
f3c08b7e
CD		 5522002-06-07 Chris Demetriou <cgd@broadcom.com>
553 Ed Satterthwaite <ehs@broadcom.com>
554
555 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
556 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
557 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
558 (fp_nmsub): New prototypes.
559 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
560 (NegMultiplySub): New defines.
561 * mips.igen (RSQRT.fmt): Use RSquareRoot().
562 (MADD.D, MADD.S): Replace with...
563 (MADD.fmt): New instruction.
564 (MSUB.D, MSUB.S): Replace with...
565 (MSUB.fmt): New instruction.
566 (NMADD.D, NMADD.S): Replace with...
567 (NMADD.fmt): New instruction.
568 (NMSUB.D, MSUB.S): Replace with...
569 (NMSUB.fmt): New instruction.
570
52714ff9
CD		 5712002-06-07 Chris Demetriou <cgd@broadcom.com>
572 Ed Satterthwaite <ehs@broadcom.com>
573
574 * cp1.c: Fix more comment spelling and formatting.
575 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
576 (denorm_mode): New function.
577 (fpu_unary, fpu_binary): Round results after operation, collect
578 status from rounding operations, and update the FCSR.
579 (convert): Collect status from integer conversions and rounding
580 operations, and update the FCSR. Adjust NaN values that result
581 from conversions. Convert to use sim_io_eprintf rather than
582 fprintf, and remove some debugging code.
583 * cp1.h (fenr_FS): New define.
584
577d8c4b
CD		 5852002-06-07 Chris Demetriou <cgd@broadcom.com>
586
587 * cp1.c (convert): Remove unusable debugging code, and move MIPS
588 rounding mode to sim FP rounding mode flag conversion code into...
589 (rounding_mode): New function.
590
196496ed
CD		 5912002-06-07 Chris Demetriou <cgd@broadcom.com>
592
593 * cp1.c: Clean up formatting of a few comments.
594 (value_fpr): Reformat switch statement.
595
cfe9ea23
CD		 5962002-06-06 Chris Demetriou <cgd@broadcom.com>
597 Ed Satterthwaite <ehs@broadcom.com>
598
599 * cp1.h: New file.
600 * sim-main.h: Include cp1.h.
601 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
602 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
603 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
604 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
605 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
606 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
607 * cp1.c: Don't include sim-fpu.h; already included by
608 sim-main.h. Clean up formatting of some comments.
609 (NaN, Equal, Less): Remove.
610 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
611 (fp_cmp): New functions.
612 * mips.igen (do_c_cond_fmt): Remove.
613 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
614 Compare. Add result tracing.
615 (CxC1): Remove, replace with...
616 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
617 (DMxC1): Remove, replace with...
618 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
619 (MxC1): Remove, replace with...
620 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
621
ee7254b0
CD		 6222002-06-04 Chris Demetriou <cgd@broadcom.com>
623
624 * sim-main.h (FGRIDX): Remove, replace all uses with...
625 (FGR_BASE): New macro.
626 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
627 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
628 (NR_FGR, FGR): Likewise.
629 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
630 * mips.igen: Likewise.
631
d3eb724f
CD		 6322002-06-04 Chris Demetriou <cgd@broadcom.com>
633
634 * cp1.c: Add an FSF Copyright notice to this file.
635
ba46ddd0
CD		 6362002-06-04 Chris Demetriou <cgd@broadcom.com>
637 Ed Satterthwaite <ehs@broadcom.com>
638
639 * cp1.c (Infinity): Remove.
640 * sim-main.h (Infinity): Likewise.
641
642 * cp1.c (fp_unary, fp_binary): New functions.
643 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
644 (fp_sqrt): New functions, implemented in terms of the above.
645 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
646 (Recip, SquareRoot): Remove (replaced by functions above).
647 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
648 (fp_recip, fp_sqrt): New prototypes.
649 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
650 (Recip, SquareRoot): Replace prototypes with #defines which
651 invoke the functions above.
652
18d8a52d
CD		 6532002-06-03 Chris Demetriou <cgd@broadcom.com>
654
655 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
656 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
657 file, remove PARAMS from prototypes.
658 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
659 simulator state arguments.
660 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
661 pass simulator state arguments.
662 * cp1.c (SD): Redefine as CPU_STATE(cpu).
663 (store_fpr, convert): Remove 'sd' argument.
664 (value_fpr): Likewise. Convert to use 'SD' instead.
665
0f154cbd
CD		 6662002-06-03 Chris Demetriou <cgd@broadcom.com>
667
668 * cp1.c (Min, Max): Remove #if 0'd functions.
669 * sim-main.h (Min, Max): Remove.
670
e80fc152
CD		 6712002-06-03 Chris Demetriou <cgd@broadcom.com>
672
673 * cp1.c: fix formatting of switch case and default labels.
674 * interp.c: Likewise.
675 * sim-main.c: Likewise.
676
bad673a9
CD		 6772002-06-03 Chris Demetriou <cgd@broadcom.com>
678
679 * cp1.c: Clean up comments which describe FP formats.
680 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
681
7cbea089
CD		 6822002-06-03 Chris Demetriou <cgd@broadcom.com>
683 Ed Satterthwaite <ehs@broadcom.com>
684
685 * configure.in (mipsisa64sb1*-*-*): New target for supporting
686 Broadcom SiByte SB-1 processor configurations.
687 * configure: Regenerate.
688 * sb1.igen: New file.
689 * mips.igen: Include sb1.igen.
690 (sb1): New model.
691 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
692 * mdmx.igen: Add "sb1" model to all appropriate functions and
693 instructions.
694 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
695 (ob_func, ob_acc): Reference the above.
696 (qh_acc): Adjust to keep the same size as ob_acc.
697 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
698 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
699
909daa82
CD		 7002002-06-03 Chris Demetriou <cgd@broadcom.com>
701
702 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
703
f4f1b9f1
CD		 7042002-06-02 Chris Demetriou <cgd@broadcom.com>
705 Ed Satterthwaite <ehs@broadcom.com>
706
707 * mips.igen (mdmx): New (pseudo-)model.
708 * mdmx.c, mdmx.igen: New files.
709 * Makefile.in (SIM_OBJS): Add mdmx.o.
710 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
711 New typedefs.
712 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
713 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
714 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
715 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
716 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
717 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
718 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
719 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
720 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
721 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
722 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
723 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
724 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
725 (qh_fmtsel): New macros.
726 (_sim_cpu): New member "acc".
727 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
728 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
729
5accf1ff
CD		 7302002-05-01 Chris Demetriou <cgd@broadcom.com>
731
732 * interp.c: Use 'deprecated' rather than 'depreciated.'
733 * sim-main.h: Likewise.
734
402586aa
CD		 7352002-05-01 Chris Demetriou <cgd@broadcom.com>
736
737 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
738 which wouldn't compile anyway.
739 * sim-main.h (unpredictable_action): New function prototype.
740 (Unpredictable): Define to call igen function unpredictable().
741 (NotWordValue): New macro to call igen function not_word_value().
742 (UndefinedResult): Remove.
743 * interp.c (undefined_result): Remove.
744 (unpredictable_action): New function.
745 * mips.igen (not_word_value, unpredictable): New functions.
746 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
747 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
748 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
749 NotWordValue() to check for unpredictable inputs, then
750 Unpredictable() to handle them.
751
c9b9995a
CD		 7522002-02-24 Chris Demetriou <cgd@broadcom.com>
753
754 * mips.igen: Fix formatting of calls to Unpredictable().
755
e1015982
AC		 7562002-04-20 Andrew Cagney <ac131313@redhat.com>
757
758 * interp.c (sim_open): Revert previous change.
759
b882a66b
AO		 7602002-04-18 Alexandre Oliva <aoliva@redhat.com>
761
762 * interp.c (sim_open): Disable chunk of code that wrote code in
763 vector table entries.
764
c429b7dd
CD		 7652002-03-19 Chris Demetriou <cgd@broadcom.com>
766
767 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
768 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
769 unused definitions.
770
37d146fa
CD		 7712002-03-19 Chris Demetriou <cgd@broadcom.com>
772
773 * cp1.c: Fix many formatting issues.
774
07892c0b
CD		 7752002-03-19 Chris G. Demetriou <cgd@broadcom.com>
776
777 * cp1.c (fpu_format_name): New function to replace...
778 (DOFMT): This. Delete, and update all callers.
779 (fpu_rounding_mode_name): New function to replace...
780 (RMMODE): This. Delete, and update all callers.
781
487f79b7
CD		 7822002-03-19 Chris G. Demetriou <cgd@broadcom.com>
783
784 * interp.c: Move FPU support routines from here to...
785 * cp1.c: Here. New file.
786 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
787 (cp1.o): New target.
788
1e799e28
CD		 7892002-03-12 Chris Demetriou <cgd@broadcom.com>
790
791 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
792 * mips.igen (mips32, mips64): New models, add to all instructions
793 and functions as appropriate.
794 (loadstore_ea, check_u64): New variant for model mips64.
795 (check_fmt_p): New variant for models mipsV and mips64, remove
796 mipsV model marking fro other variant.
797 (SLL) Rename to...
798 (SLLa) this.
799 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
800 for mips32 and mips64.
801 (DCLO, DCLZ): New instructions for mips64.
802
82f728db
CD		 8032002-03-07 Chris Demetriou <cgd@broadcom.com>
804
805 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
806 immediate or code as a hex value with the "%#lx" format.
807 (ANDI): Likewise, and fix printed instruction name.
808
b96e7ef1
CD		 8092002-03-05 Chris Demetriou <cgd@broadcom.com>
810
811 * sim-main.h (UndefinedResult, Unpredictable): New macros
812 which currently do nothing.
813
d35d4f70
CD		 8142002-03-05 Chris Demetriou <cgd@broadcom.com>
815
816 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
817 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
818 (status_CU3): New definitions.
819
820 * sim-main.h (ExceptionCause): Add new values for MIPS32
821 and MIPS64: MDMX, MCheck, CacheErr. Update comments
822 for DebugBreakPoint and NMIReset to note their status in
823 MIPS32 and MIPS64.
824 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
825 (SignalExceptionCacheErr): New exception macros.
826
3ad6f714
CD		 8272002-03-05 Chris Demetriou <cgd@broadcom.com>
828
829 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
830 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
831 is always enabled.
832 (SignalExceptionCoProcessorUnusable): Take as argument the
833 unusable coprocessor number.
834
86b77b47
CD		 8352002-03-05 Chris Demetriou <cgd@broadcom.com>
836
837 * mips.igen: Fix formatting of all SignalException calls.
838
97a88e93 8392002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 840
841 * sim-main.h (SIGNEXTEND): Remove.
842
97a88e93 8432002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 844
845 * mips.igen: Remove gencode comment from top of file, fix
846 spelling in another comment.
847
97a88e93 8482002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 849
850 * mips.igen (check_fmt, check_fmt_p): New functions to check
851 whether specific floating point formats are usable.
852 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
853 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
854 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
855 Use the new functions.
856 (do_c_cond_fmt): Remove format checks...
857 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
858
97a88e93 8592002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 860
861 * mips.igen: Fix formatting of check_fpu calls.
862
41774c9d
CD		 8632002-03-03 Chris Demetriou <cgd@broadcom.com>
864
865 * mips.igen (FLOOR.L.fmt): Store correct destination register.
866
4a0bd876
CD		 8672002-03-03 Chris Demetriou <cgd@broadcom.com>
868
869 * mips.igen: Remove whitespace at end of lines.
870
09297648
CD		 8712002-03-02 Chris Demetriou <cgd@broadcom.com>
872
873 * mips.igen (loadstore_ea): New function to do effective
874 address calculations.
875 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
876 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
877 CACHE): Use loadstore_ea to do effective address computations.
878
043b7057
CD		 8792002-03-02 Chris Demetriou <cgd@broadcom.com>
880
881 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
882 * mips.igen (LL, CxC1, MxC1): Likewise.
883
c1e8ada4
CD		 8842002-03-02 Chris Demetriou <cgd@broadcom.com>
885
886 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
887 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
888 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
889 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
890 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
891 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
892 Don't split opcode fields by hand, use the opcode field values
893 provided by igen.
894
3e1dca16
CD		 8952002-03-01 Chris Demetriou <cgd@broadcom.com>
896
897 * mips.igen (do_divu): Fix spacing.
898
899 * mips.igen (do_dsllv): Move to be right before DSLLV,
900 to match the rest of the do_<shift> functions.
901
fff8d27d
CD		 9022002-03-01 Chris Demetriou <cgd@broadcom.com>
903
904 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
905 DSRL32, do_dsrlv): Trace inputs and results.
906
0d3e762b
CD		 9072002-03-01 Chris Demetriou <cgd@broadcom.com>
908
909 * mips.igen (CACHE): Provide instruction-printing string.
910
911 * interp.c (signal_exception): Comment tokens after #endif.
912
eb5fcf93
CD		 9132002-02-28 Chris Demetriou <cgd@broadcom.com>
914
915 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
916 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
917 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
918 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
919 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
920 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
921 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
922 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
923
bb22bd7d
CD		 9242002-02-28 Chris Demetriou <cgd@broadcom.com>
925
926 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
927 instruction-printing string.
928 (LWU): Use '64' as the filter flag.
929
91a177cf
CD		 9302002-02-28 Chris Demetriou <cgd@broadcom.com>
931
932 * mips.igen (SDXC1): Fix instruction-printing string.
933
387f484a
CD		 9342002-02-28 Chris Demetriou <cgd@broadcom.com>
935
936 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
937 filter flags "32,f".
938
3d81f391
CD		 9392002-02-27 Chris Demetriou <cgd@broadcom.com>
940
941 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
942 as the filter flag.
943
af5107af
CD		 9442002-02-27 Chris Demetriou <cgd@broadcom.com>
945
946 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
947 add a comma) so that it more closely match the MIPS ISA
948 documentation opcode partitioning.
949 (PREF): Put useful names on opcode fields, and include
950 instruction-printing string.
951
ca971540
CD		 9522002-02-27 Chris Demetriou <cgd@broadcom.com>
953
954 * mips.igen (check_u64): New function which in the future will
955 check whether 64-bit instructions are usable and signal an
956 exception if not. Currently a no-op.
957 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
958 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
959 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
960 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
961
962 * mips.igen (check_fpu): New function which in the future will
963 check whether FPU instructions are usable and signal an exception
964 if not. Currently a no-op.
965 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
966 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
967 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
968 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
969 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
970 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
971 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
972 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
973
1c47a468
CD		 9742002-02-27 Chris Demetriou <cgd@broadcom.com>
975
976 * mips.igen (do_load_left, do_load_right): Move to be immediately
977 following do_load.
978 (do_store_left, do_store_right): Move to be immediately following
979 do_store.
980
603a98e7
CD		 9812002-02-27 Chris Demetriou <cgd@broadcom.com>
982
983 * mips.igen (mipsV): New model name. Also, add it to
984 all instructions and functions where it is appropriate.
985
c5d00cc7
CD		 9862002-02-18 Chris Demetriou <cgd@broadcom.com>
987
988 * mips.igen: For all functions and instructions, list model
989 names that support that instruction one per line.
990
074e9cb8
CD		 9912002-02-11 Chris Demetriou <cgd@broadcom.com>
992
993 * mips.igen: Add some additional comments about supported
994 models, and about which instructions go where.
995 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
996 order as is used in the rest of the file.
997
9805e229
CD		 9982002-02-11 Chris Demetriou <cgd@broadcom.com>
999
1000 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1001 indicating that ALU32_END or ALU64_END are there to check
1002 for overflow.
1003 (DADD): Likewise, but also remove previous comment about
1004 overflow checking.
1005
f701dad2
CD		 10062002-02-10 Chris Demetriou <cgd@broadcom.com>
1007
1008 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1009 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1010 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1011 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1012 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1013 fields (i.e., add and move commas) so that they more closely
1014 match the MIPS ISA documentation opcode partitioning.
1015
10162002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 1017
1018 * mips.igen (ADDI): Print immediate value.
1019 (BREAK): Print code.
1020 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1021 (SLL): Print "nop" specially, and don't run the code
1022 that does the shift for the "nop" case.
1023
9e52972e
FF		 10242001-11-17 Fred Fish <fnf@redhat.com>
1025
1026 * sim-main.h (float_operation): Move enum declaration outside
1027 of _sim_cpu struct declaration.
1028
c0efbca4
JB		 10292001-04-12 Jim Blandy <jimb@redhat.com>
1030
1031 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1032 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1033 set of the FCSR.
1034 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1035 PENDING_FILL, and you can get the intended effect gracefully by
1036 calling PENDING_SCHED directly.
1037
fb891446
BE		 10382001-02-23 Ben Elliston <bje@redhat.com>
1039
1040 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1041 already defined elsewhere.
1042
8030f857
BE		 10432001-02-19 Ben Elliston <bje@redhat.com>
1044
1045 * sim-main.h (sim_monitor): Return an int.
1046 * interp.c (sim_monitor): Add return values.
1047 (signal_exception): Handle error conditions from sim_monitor.
1048
56b48a7a
CD		 10492001-02-08 Ben Elliston <bje@redhat.com>
1050
1051 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1052 (store_memory): Likewise, pass cia to sim_core_write*.
1053
d3ee60d9
FCE		 10542000-10-19 Frank Ch. Eigler <fche@redhat.com>
1055
1056 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1057 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1058
071da002
AC		 1059Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1060
1061 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1062 * Makefile.in: Don't delete *.igen when cleaning directory.
1063
a28c02cd
AC		 1064Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1065
1066 * m16.igen (break): Call SignalException not sim_engine_halt.
1067
80ee11fa
AC		 1068Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1069
1070 From Jason Eckhardt:
1071 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1072
673388c0
AC		 1073Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1074
1075 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1076
4c0deff4
NC		 10772000-05-24 Michael Hayes <mhayes@cygnus.com>
1078
1079 * mips.igen (do_dmultx): Fix typo.
1080
eb2d80b4
AC		 1081Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1082
1083 * configure: Regenerated to track ../common/aclocal.m4 changes.
1084
dd37a34b
AC		 1085Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1086
1087 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1088
4c0deff4
NC		 10892000-04-12 Frank Ch. Eigler <fche@redhat.com>
1090
1091 * sim-main.h (GPR_CLEAR): Define macro.
1092
e30db738
AC		 1093Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1094
1095 * interp.c (decode_coproc): Output long using %lx and not %s.
1096
cb7450ea
FCE		 10972000-03-21 Frank Ch. Eigler <fche@redhat.com>
1098
1099 * interp.c (sim_open): Sort & extend dummy memory regions for
1100 --board=jmr3904 for eCos.
1101
a3027dd7
FCE		 11022000-03-02 Frank Ch. Eigler <fche@redhat.com>
1103
1104 * configure: Regenerated.
1105
1106Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1107
1108 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1109 calls, conditional on the simulator being in verbose mode.
1110
dfcd3bfb
JM		 1111Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1112
1113 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1114 cache don't get ReservedInstruction traps.
1115
c2d11a7d
JM		 11161999-11-29 Mark Salter <msalter@cygnus.com>
1117
1118 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1119 to clear status bits in sdisr register. This is how the hardware works.
1120
1121 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1122 being used by cygmon.
1123
4ce44c66
JM		 11241999-11-11 Andrew Haley <aph@cygnus.com>
1125
1126 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1127 instructions.
1128
cff3e48b
JM		 1129Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1130
1131 * mips.igen (MULT): Correct previous mis-applied patch.
1132
d4f3574e
SS		 1133Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1134
1135 * mips.igen (delayslot32): Handle sequence like
1136 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1137 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1138 (MULT): Actually pass the third register...
1139
11401999-09-03 Mark Salter <msalter@cygnus.com>
1141
1142 * interp.c (sim_open): Added more memory aliases for additional
1143 hardware being touched by cygmon on jmr3904 board.
1144
1145Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1146
1147 * configure: Regenerated to track ../common/aclocal.m4 changes.
1148
a0b3c4fd
JM		 1149Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1150
1151 * interp.c (sim_store_register): Handle case where client - GDB -
1152 specifies that a 4 byte register is 8 bytes in size.
1153 (sim_fetch_register): Ditto.
1154
adf40b2e
JM		 11551999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1156
1157 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1158 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1159 (idt_monitor_base): Base address for IDT monitor traps.
1160 (pmon_monitor_base): Ditto for PMON.
1161 (lsipmon_monitor_base): Ditto for LSI PMON.
1162 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1163 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1164 (sim_firmware_command): New function.
1165 (mips_option_handler): Call it for OPTION_FIRMWARE.
1166 (sim_open): Allocate memory for idt_monitor region. If "--board"
1167 option was given, add no monitor by default. Add BREAK hooks only if
1168 monitors are also there.
1169
43e526b9
JM		 1170Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1171
1172 * interp.c (sim_monitor): Flush output before reading input.
1173
1174Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1175
1176 * tconfig.in (SIM_HANDLES_LMA): Always define.
1177
1178Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1179
1180 From Mark Salter <msalter@cygnus.com>:
1181 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1182 (sim_open): Add setup for BSP board.
1183
9846de1b
JM		 1184Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1185
1186 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1187 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1188 them as unimplemented.
1189
cd0fc7c3
SS		 11901999-05-08 Felix Lee <flee@cygnus.com>
1191
1192 * configure: Regenerated to track ../common/aclocal.m4 changes.
1193
7a292a7a
SS		 11941999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1195
1196 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1197
1198Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1199
1200 * configure.in: Any mips64vr5*-*-* target should have
1201 -DTARGET_ENABLE_FR=1.
1202 (default_endian): Any mips64vr*el-*-* target should default to
1203 LITTLE_ENDIAN.
1204 * configure: Re-generate.
1205
12061999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1207
1208 * mips.igen (ldl): Extend from _16_, not 32.
1209
1210Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1211
1212 * interp.c (sim_store_register): Force registers written to by GDB
1213 into an un-interpreted state.
1214
c906108c
SS		 12151999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1216
1217 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1218 CPU, start periodic background I/O polls.
1219 (tx3904sio_poll): New function: periodic I/O poller.
1220
12211998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1222
1223 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1224
1225Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1226
1227 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1228 case statement.
1229
12301998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1231
1232 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1233 (load_word): Call SIM_CORE_SIGNAL hook on error.
1234 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1235 starting. For exception dispatching, pass PC instead of NULL_CIA.
1236 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1237 * sim-main.h (COP0_BADVADDR): Define.
1238 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1239 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1240 (_sim_cpu): Add exc_* fields to store register value snapshots.
1241 * mips.igen (*): Replace memory-related SignalException* calls
1242 with references to SIM_CORE_SIGNAL hook.
1243
1244 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1245 fix.
1246 * sim-main.c (*): Minor warning cleanups.
1247
12481998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1249
1250 * m16.igen (DADDIU5): Correct type-o.
1251
1252Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1253
1254 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1255 variables.
1256
1257Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1258
1259 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1260 to include path.
1261 (interp.o): Add dependency on itable.h
1262 (oengine.c, gencode): Delete remaining references.
1263 (BUILT_SRC_FROM_GEN): Clean up.
1264
12651998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1266
1267 * vr4run.c: New.
1268 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1269 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1270 tmp-run-hack) : New.
1271 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1272 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1273 Drop the "64" qualifier to get the HACK generator working.
1274 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1275 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1276 qualifier to get the hack generator working.
1277 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1278 (DSLL): Use do_dsll.
1279 (DSLLV): Use do_dsllv.
1280 (DSRA): Use do_dsra.
1281 (DSRL): Use do_dsrl.
1282 (DSRLV): Use do_dsrlv.
1283 (BC1): Move *vr4100 to get the HACK generator working.
1284 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1285 get the HACK generator working.
1286 (MACC) Rename to get the HACK generator working.
1287 (DMACC,MACCS,DMACCS): Add the 64.
1288
12891998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1290
1291 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1292 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1293
12941998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1295
1296 * mips/interp.c (DEBUG): Cleanups.
1297
12981998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1299
1300 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1301 (tx3904sio_tickle): fflush after a stdout character output.
1302
13031998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1304
1305 * interp.c (sim_close): Uninstall modules.
1306
1307Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1308
1309 * sim-main.h, interp.c (sim_monitor): Change to global
1310 function.
1311
1312Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1313
1314 * configure.in (vr4100): Only include vr4100 instructions in
1315 simulator.
1316 * configure: Re-generate.
1317 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1318
1319Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1320
1321 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1322 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1323 true alternative.
1324
1325 * configure.in (sim_default_gen, sim_use_gen): Replace with
1326 sim_gen.
1327 (--enable-sim-igen): Delete config option. Always using IGEN.
1328 * configure: Re-generate.
1329
1330 * Makefile.in (gencode): Kill, kill, kill.
1331 * gencode.c: Ditto.
1332
1333Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1334
1335 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1336 bit mips16 igen simulator.
1337 * configure: Re-generate.
1338
1339 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1340 as part of vr4100 ISA.
1341 * vr.igen: Mark all instructions as 64 bit only.
1342
1343Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1344
1345 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1346 Pacify GCC.
1347
1348Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1349
1350 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1351 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1352 * configure: Re-generate.
1353
1354 * m16.igen (BREAK): Define breakpoint instruction.
1355 (JALX32): Mark instruction as mips16 and not r3900.
1356 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1357
1358 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1359
1360Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1361
1362 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1363 insn as a debug breakpoint.
1364
1365 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1366 pending.slot_size.
1367 (PENDING_SCHED): Clean up trace statement.
1368 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1369 (PENDING_FILL): Delay write by only one cycle.
1370 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1371
1372 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1373 of pending writes.
1374 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1375 32 & 64.
1376 (pending_tick): Move incrementing of index to FOR statement.
1377 (pending_tick): Only update PENDING_OUT after a write has occured.
1378
1379 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1380 build simulator.
1381 * configure: Re-generate.
1382
1383 * interp.c (sim_engine_run OLD): Delete explicit call to
1384 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1385
1386Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1387
1388 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1389 interrupt level number to match changed SignalExceptionInterrupt
1390 macro.
1391
1392Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1393
1394 * interp.c: #include "itable.h" if WITH_IGEN.
1395 (get_insn_name): New function.
1396 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1397 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1398
1399Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1400
1401 * configure: Rebuilt to inhale new common/aclocal.m4.
1402
1403Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1404
1405 * dv-tx3904sio.c: Include sim-assert.h.
1406
1407Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1408
1409 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1410 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1411 Reorganize target-specific sim-hardware checks.
1412 * configure: rebuilt.
1413 * interp.c (sim_open): For tx39 target boards, set
1414 OPERATING_ENVIRONMENT, add tx3904sio devices.
1415 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1416 ROM executables. Install dv-sockser into sim-modules list.
1417
1418 * dv-tx3904irc.c: Compiler warning clean-up.
1419 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1420 frequent hw-trace messages.
1421
1422Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1423
1424 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1425
1426Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1427
1428 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1429
1430 * vr.igen: New file.
1431 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1432 * mips.igen: Define vr4100 model. Include vr.igen.
1433Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1434
1435 * mips.igen (check_mf_hilo): Correct check.
1436
1437Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1438
1439 * sim-main.h (interrupt_event): Add prototype.
1440
1441 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1442 register_ptr, register_value.
1443 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1444
1445 * sim-main.h (tracefh): Make extern.
1446
1447Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1448
1449 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1450 Reduce unnecessarily high timer event frequency.
1451 * dv-tx3904cpu.c: Ditto for interrupt event.
1452
1453Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1454
1455 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1456 to allay warnings.
1457 (interrupt_event): Made non-static.
1458
1459 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1460 interchange of configuration values for external vs. internal
1461 clock dividers.
1462
1463Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1464
1465 * mips.igen (BREAK): Moved code to here for
1466 simulator-reserved break instructions.
1467 * gencode.c (build_instruction): Ditto.
1468 * interp.c (signal_exception): Code moved from here. Non-
1469 reserved instructions now use exception vector, rather
1470 than halting sim.
1471 * sim-main.h: Moved magic constants to here.
1472
1473Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1474
1475 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1476 register upon non-zero interrupt event level, clear upon zero
1477 event value.
1478 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1479 by passing zero event value.
1480 (*_io_{read,write}_buffer): Endianness fixes.
1481 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1482 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1483
1484 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1485 serial I/O and timer module at base address 0xFFFF0000.
1486
1487Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1488
1489 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1490 and BigEndianCPU.
1491
1492Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1493
1494 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1495 parts.
1496 * configure: Update.
1497
1498Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1499
1500 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1501 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1502 * configure.in: Include tx3904tmr in hw_device list.
1503 * configure: Rebuilt.
1504 * interp.c (sim_open): Instantiate three timer instances.
1505 Fix address typo of tx3904irc instance.
1506
1507Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1508
1509 * interp.c (signal_exception): SystemCall exception now uses
1510 the exception vector.
1511
1512Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1513
1514 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1515 to allay warnings.
1516
1517Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1518
1519 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1520
1521Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1522
1523 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1524
1525 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1526 sim-main.h. Declare a struct hw_descriptor instead of struct
1527 hw_device_descriptor.
1528
1529Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1530
1531 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1532 right bits and then re-align left hand bytes to correct byte
1533 lanes. Fix incorrect computation in do_store_left when loading
1534 bytes from second word.
1535
1536Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1537
1538 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1539 * interp.c (sim_open): Only create a device tree when HW is
1540 enabled.
1541
1542 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1543 * interp.c (signal_exception): Ditto.
1544
1545Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1546
1547 * gencode.c: Mark BEGEZALL as LIKELY.
1548
1549Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1550
1551 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1552 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1553
1554Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1555
1556 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1557 modules. Recognize TX39 target with "mips*tx39" pattern.
1558 * configure: Rebuilt.
1559 * sim-main.h (*): Added many macros defining bits in
1560 TX39 control registers.
1561 (SignalInterrupt): Send actual PC instead of NULL.
1562 (SignalNMIReset): New exception type.
1563 * interp.c (board): New variable for future use to identify
1564 a particular board being simulated.
1565 (mips_option_handler,mips_options): Added "--board" option.
1566 (interrupt_event): Send actual PC.
1567 (sim_open): Make memory layout conditional on board setting.
1568 (signal_exception): Initial implementation of hardware interrupt
1569 handling. Accept another break instruction variant for simulator
1570 exit.
1571 (decode_coproc): Implement RFE instruction for TX39.
1572 (mips.igen): Decode RFE instruction as such.
1573 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1574 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1575 bbegin to implement memory map.
1576 * dv-tx3904cpu.c: New file.
1577 * dv-tx3904irc.c: New file.
1578
1579Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1580
1581 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1582
1583Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1584
1585 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1586 with calls to check_div_hilo.
1587
1588Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1589
1590 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1591 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1592 Add special r3900 version of do_mult_hilo.
1593 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1594 with calls to check_mult_hilo.
1595 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1596 with calls to check_div_hilo.
1597
1598Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1599
1600 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1601 Document a replacement.
1602
1603Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1604
1605 * interp.c (sim_monitor): Make mon_printf work.
1606
1607Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1608
1609 * sim-main.h (INSN_NAME): New arg `cpu'.
1610
1611Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1612
1613 * configure: Regenerated to track ../common/aclocal.m4 changes.
1614
1615Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1616
1617 * configure: Regenerated to track ../common/aclocal.m4 changes.
1618 * config.in: Ditto.
1619
1620Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1621
1622 * acconfig.h: New file.
1623 * configure.in: Reverted change of Apr 24; use sinclude again.
1624
1625Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1626
1627 * configure: Regenerated to track ../common/aclocal.m4 changes.
1628 * config.in: Ditto.
1629
1630Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1631
1632 * configure.in: Don't call sinclude.
1633
1634Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1635
1636 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1637
1638Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1639
1640 * mips.igen (ERET): Implement.
1641
1642 * interp.c (decode_coproc): Return sign-extended EPC.
1643
1644 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1645
1646 * interp.c (signal_exception): Do not ignore Trap.
1647 (signal_exception): On TRAP, restart at exception address.
1648 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1649 (signal_exception): Update.
1650 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1651 so that TRAP instructions are caught.
1652
1653Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1654
1655 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1656 contains HI/LO access history.
1657 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1658 (HIACCESS, LOACCESS): Delete, replace with
1659 (HIHISTORY, LOHISTORY): New macros.
1660 (CHECKHILO): Delete all, moved to mips.igen
1661
1662 * gencode.c (build_instruction): Do not generate checks for
1663 correct HI/LO register usage.
1664
1665 * interp.c (old_engine_run): Delete checks for correct HI/LO
1666 register usage.
1667
1668 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1669 check_mf_cycles): New functions.
1670 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1671 do_divu, domultx, do_mult, do_multu): Use.
1672
1673 * tx.igen ("madd", "maddu"): Use.
1674
1675Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1676
1677 * mips.igen (DSRAV): Use function do_dsrav.
1678 (SRAV): Use new function do_srav.
1679
1680 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1681 (B): Sign extend 11 bit immediate.
1682 (EXT-B*): Shift 16 bit immediate left by 1.
1683 (ADDIU*): Don't sign extend immediate value.
1684
1685Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1686
1687 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1688
1689 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1690 functions.
1691
1692 * mips.igen (delayslot32, nullify_next_insn): New functions.
1693 (m16.igen): Always include.
1694 (do_*): Add more tracing.
1695
1696 * m16.igen (delayslot16): Add NIA argument, could be called by a
1697 32 bit MIPS16 instruction.
1698
1699 * interp.c (ifetch16): Move function from here.
1700 * sim-main.c (ifetch16): To here.
1701
1702 * sim-main.c (ifetch16, ifetch32): Update to match current
1703 implementations of LH, LW.
1704 (signal_exception): Don't print out incorrect hex value of illegal
1705 instruction.
1706
1707Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1708
1709 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1710 instruction.
1711
1712 * m16.igen: Implement MIPS16 instructions.
1713
1714 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1715 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1716 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1717 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1718 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1719 bodies of corresponding code from 32 bit insn to these. Also used
1720 by MIPS16 versions of functions.
1721
1722 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1723 (IMEM16): Drop NR argument from macro.
1724
1725Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1726
1727 * Makefile.in (SIM_OBJS): Add sim-main.o.
1728
1729 * sim-main.h (address_translation, load_memory, store_memory,
1730 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1731 as INLINE_SIM_MAIN.
1732 (pr_addr, pr_uword64): Declare.
1733 (sim-main.c): Include when H_REVEALS_MODULE_P.
1734
1735 * interp.c (address_translation, load_memory, store_memory,
1736 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1737 from here.
1738 * sim-main.c: To here. Fix compilation problems.
1739
1740 * configure.in: Enable inlining.
1741 * configure: Re-config.
1742
1743Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1744
1745 * configure: Regenerated to track ../common/aclocal.m4 changes.
1746
1747Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1748
1749 * mips.igen: Include tx.igen.
1750 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1751 * tx.igen: New file, contains MADD and MADDU.
1752
1753 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1754 the hardwired constant `7'.
1755 (store_memory): Ditto.
1756 (LOADDRMASK): Move definition to sim-main.h.
1757
1758 mips.igen (MTC0): Enable for r3900.
1759 (ADDU): Add trace.
1760
1761 mips.igen (do_load_byte): Delete.
1762 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1763 do_store_right): New functions.
1764 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1765
1766 configure.in: Let the tx39 use igen again.
1767 configure: Update.
1768
1769Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1770
1771 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1772 not an address sized quantity. Return zero for cache sizes.
1773
1774Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1775
1776 * mips.igen (r3900): r3900 does not support 64 bit integer
1777 operations.
1778
1779Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1780
1781 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1782 than igen one.
1783 * configure : Rebuild.
1784
1785Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1786
1787 * configure: Regenerated to track ../common/aclocal.m4 changes.
1788
1789Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1790
1791 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1792
1793Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1794
1795 * configure: Regenerated to track ../common/aclocal.m4 changes.
1796 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1797
1798Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1799
1800 * configure: Regenerated to track ../common/aclocal.m4 changes.
1801
1802Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1803
1804 * interp.c (Max, Min): Comment out functions. Not yet used.
1805
1806Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1807
1808 * configure: Regenerated to track ../common/aclocal.m4 changes.
1809
1810Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1811
1812 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1813 configurable settings for stand-alone simulator.
1814
1815 * configure.in: Added X11 search, just in case.
1816
1817 * configure: Regenerated.
1818
1819Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1820
1821 * interp.c (sim_write, sim_read, load_memory, store_memory):
1822 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1823
1824Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1825
1826 * sim-main.h (GETFCC): Return an unsigned value.
1827
1828Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1829
1830 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1831 (DADD): Result destination is RD not RT.
1832
1833Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1834
1835 * sim-main.h (HIACCESS, LOACCESS): Always define.
1836
1837 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1838
1839 * interp.c (sim_info): Delete.
1840
1841Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1842
1843 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1844 (mips_option_handler): New argument `cpu'.
1845 (sim_open): Update call to sim_add_option_table.
1846
1847Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1848
1849 * mips.igen (CxC1): Add tracing.
1850
1851Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1852
1853 * sim-main.h (Max, Min): Declare.
1854
1855 * interp.c (Max, Min): New functions.
1856
1857 * mips.igen (BC1): Add tracing.
1858
1859Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1860
1861 * interp.c Added memory map for stack in vr4100
1862
1863Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1864
1865 * interp.c (load_memory): Add missing "break"'s.
1866
1867Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1868
1869 * interp.c (sim_store_register, sim_fetch_register): Pass in
1870 length parameter. Return -1.
1871
1872Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1873
1874 * interp.c: Added hardware init hook, fixed warnings.
1875
1876Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1877
1878 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1879
1880Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1881
1882 * interp.c (ifetch16): New function.
1883
1884 * sim-main.h (IMEM32): Rename IMEM.
1885 (IMEM16_IMMED): Define.
1886 (IMEM16): Define.
1887 (DELAY_SLOT): Update.
1888
1889 * m16run.c (sim_engine_run): New file.
1890
1891 * m16.igen: All instructions except LB.
1892 (LB): Call do_load_byte.
1893 * mips.igen (do_load_byte): New function.
1894 (LB): Call do_load_byte.
1895
1896 * mips.igen: Move spec for insn bit size and high bit from here.
1897 * Makefile.in (tmp-igen, tmp-m16): To here.
1898
1899 * m16.dc: New file, decode mips16 instructions.
1900
1901 * Makefile.in (SIM_NO_ALL): Define.
1902 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1903
1904Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1905
1906 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1907 point unit to 32 bit registers.
1908 * configure: Re-generate.
1909
1910Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1911
1912 * configure.in (sim_use_gen): Make IGEN the default simulator
1913 generator for generic 32 and 64 bit mips targets.
1914 * configure: Re-generate.
1915
1916Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1917
1918 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1919 bitsize.
1920
1921 * interp.c (sim_fetch_register, sim_store_register): Read/write
1922 FGR from correct location.
1923 (sim_open): Set size of FGR's according to
1924 WITH_TARGET_FLOATING_POINT_BITSIZE.
1925
1926 * sim-main.h (FGR): Store floating point registers in a separate
1927 array.
1928
1929Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1930
1931 * configure: Regenerated to track ../common/aclocal.m4 changes.
1932
1933Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1934
1935 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1936
1937 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1938
1939 * interp.c (pending_tick): New function. Deliver pending writes.
1940
1941 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1942 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1943 it can handle mixed sized quantites and single bits.
1944
1945Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1946
1947 * interp.c (oengine.h): Do not include when building with IGEN.
1948 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1949 (sim_info): Ditto for PROCESSOR_64BIT.
1950 (sim_monitor): Replace ut_reg with unsigned_word.
1951 (*): Ditto for t_reg.
1952 (LOADDRMASK): Define.
1953 (sim_open): Remove defunct check that host FP is IEEE compliant,
1954 using software to emulate floating point.
1955 (value_fpr, ...): Always compile, was conditional on HASFPU.
1956
1957Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1958
1959 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1960 size.
1961
1962 * interp.c (SD, CPU): Define.
1963 (mips_option_handler): Set flags in each CPU.
1964 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1965 (sim_close): Do not clear STATE, deleted anyway.
1966 (sim_write, sim_read): Assume CPU zero's vm should be used for
1967 data transfers.
1968 (sim_create_inferior): Set the PC for all processors.
1969 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1970 argument.
1971 (mips16_entry): Pass correct nr of args to store_word, load_word.
1972 (ColdReset): Cold reset all cpu's.
1973 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1974 (sim_monitor, load_memory, store_memory, signal_exception): Use
1975 `CPU' instead of STATE_CPU.
1976
1977
1978 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1979 SD or CPU_.
1980
1981 * sim-main.h (signal_exception): Add sim_cpu arg.
1982 (SignalException*): Pass both SD and CPU to signal_exception.
1983 * interp.c (signal_exception): Update.
1984
1985 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1986 Ditto
1987 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1988 address_translation): Ditto
1989 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1990
1991Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1992
1993 * configure: Regenerated to track ../common/aclocal.m4 changes.
1994
1995Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1996
1997 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1998
1999 * mips.igen (model): Map processor names onto BFD name.
2000
2001 * sim-main.h (CPU_CIA): Delete.
2002 (SET_CIA, GET_CIA): Define
2003
2004Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2005
2006 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2007 regiser.
2008
2009 * configure.in (default_endian): Configure a big-endian simulator
2010 by default.
2011 * configure: Re-generate.
2012
2013Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2014
2015 * configure: Regenerated to track ../common/aclocal.m4 changes.
2016
2017Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2018
2019 * interp.c (sim_monitor): Handle Densan monitor outbyte
2020 and inbyte functions.
2021
20221997-12-29 Felix Lee <flee@cygnus.com>
2023
2024 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2025
2026Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2027
2028 * Makefile.in (tmp-igen): Arrange for $zero to always be
2029 reset to zero after every instruction.
2030
2031Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2032
2033 * configure: Regenerated to track ../common/aclocal.m4 changes.
2034 * config.in: Ditto.
2035
2036Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2037
2038 * mips.igen (MSUB): Fix to work like MADD.
2039 * gencode.c (MSUB): Similarly.
2040
2041Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2042
2043 * configure: Regenerated to track ../common/aclocal.m4 changes.
2044
2045Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2046
2047 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2048
2049Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2050
2051 * sim-main.h (sim-fpu.h): Include.
2052
2053 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2054 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2055 using host independant sim_fpu module.
2056
2057Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2058
2059 * interp.c (signal_exception): Report internal errors with SIGABRT
2060 not SIGQUIT.
2061
2062 * sim-main.h (C0_CONFIG): New register.
2063 (signal.h): No longer include.
2064
2065 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2066
2067Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2068
2069 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2070
2071Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2072
2073 * mips.igen: Tag vr5000 instructions.
2074 (ANDI): Was missing mipsIV model, fix assembler syntax.
2075 (do_c_cond_fmt): New function.
2076 (C.cond.fmt): Handle mips I-III which do not support CC field
2077 separatly.
2078 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2079 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2080 in IV3.2 spec.
2081 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2082 vr5000 which saves LO in a GPR separatly.
2083
2084 * configure.in (enable-sim-igen): For vr5000, select vr5000
2085 specific instructions.
2086 * configure: Re-generate.
2087
2088Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2089
2090 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2091
2092 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2093 fmt_uninterpreted_64 bit cases to switch. Convert to
2094 fmt_formatted,
2095
2096 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2097
2098 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2099 as specified in IV3.2 spec.
2100 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2101
2102Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2103
2104 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2105 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2106 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2107 PENDING_FILL versions of instructions. Simplify.
2108 (X): New function.
2109 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2110 instructions.
2111 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2112 a signed value.
2113 (MTHI, MFHI): Disable code checking HI-LO.
2114
2115 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2116 global.
2117 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2118
2119Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2120
2121 * gencode.c (build_mips16_operands): Replace IPC with cia.
2122
2123 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2124 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2125 IPC to `cia'.
2126 (UndefinedResult): Replace function with macro/function
2127 combination.
2128 (sim_engine_run): Don't save PC in IPC.
2129
2130 * sim-main.h (IPC): Delete.
2131
2132
2133 * interp.c (signal_exception, store_word, load_word,
2134 address_translation, load_memory, store_memory, cache_op,
2135 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2136 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2137 current instruction address - cia - argument.
2138 (sim_read, sim_write): Call address_translation directly.
2139 (sim_engine_run): Rename variable vaddr to cia.
2140 (signal_exception): Pass cia to sim_monitor
2141
2142 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2143 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2144 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2145
2146 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2147 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2148 SIM_ASSERT.
2149
2150 * interp.c (signal_exception): Pass restart address to
2151 sim_engine_restart.
2152
2153 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2154 idecode.o): Add dependency.
2155
2156 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2157 Delete definitions
2158 (DELAY_SLOT): Update NIA not PC with branch address.
2159 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2160
2161 * mips.igen: Use CIA not PC in branch calculations.
2162 (illegal): Call SignalException.
2163 (BEQ, ADDIU): Fix assembler.
2164
2165Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2166
2167 * m16.igen (JALX): Was missing.
2168
2169 * configure.in (enable-sim-igen): New configuration option.
2170 * configure: Re-generate.
2171
2172 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2173
2174 * interp.c (load_memory, store_memory): Delete parameter RAW.
2175 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2176 bypassing {load,store}_memory.
2177
2178 * sim-main.h (ByteSwapMem): Delete definition.
2179
2180 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2181
2182 * interp.c (sim_do_command, sim_commands): Delete mips specific
2183 commands. Handled by module sim-options.
2184
2185 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2186 (WITH_MODULO_MEMORY): Define.
2187
2188 * interp.c (sim_info): Delete code printing memory size.
2189
2190 * interp.c (mips_size): Nee sim_size, delete function.
2191 (power2): Delete.
2192 (monitor, monitor_base, monitor_size): Delete global variables.
2193 (sim_open, sim_close): Delete code creating monitor and other
2194 memory regions. Use sim-memopts module, via sim_do_commandf, to
2195 manage memory regions.
2196 (load_memory, store_memory): Use sim-core for memory model.
2197
2198 * interp.c (address_translation): Delete all memory map code
2199 except line forcing 32 bit addresses.
2200
2201Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2202
2203 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2204 trace options.
2205
2206 * interp.c (logfh, logfile): Delete globals.
2207 (sim_open, sim_close): Delete code opening & closing log file.
2208 (mips_option_handler): Delete -l and -n options.
2209 (OPTION mips_options): Ditto.
2210
2211 * interp.c (OPTION mips_options): Rename option trace to dinero.
2212 (mips_option_handler): Update.
2213
2214Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2215
2216 * interp.c (fetch_str): New function.
2217 (sim_monitor): Rewrite using sim_read & sim_write.
2218 (sim_open): Check magic number.
2219 (sim_open): Write monitor vectors into memory using sim_write.
2220 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2221 (sim_read, sim_write): Simplify - transfer data one byte at a
2222 time.
2223 (load_memory, store_memory): Clarify meaning of parameter RAW.
2224
2225 * sim-main.h (isHOST): Defete definition.
2226 (isTARGET): Mark as depreciated.
2227 (address_translation): Delete parameter HOST.
2228
2229 * interp.c (address_translation): Delete parameter HOST.
2230
2231Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2232
2233 * mips.igen:
2234
2235 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2236 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2237
2238Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2239
2240 * mips.igen: Add model filter field to records.
2241
2242Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2243
2244 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2245
2246 interp.c (sim_engine_run): Do not compile function sim_engine_run
2247 when WITH_IGEN == 1.
2248
2249 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2250 target architecture.
2251
2252 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2253 igen. Replace with configuration variables sim_igen_flags /
2254 sim_m16_flags.
2255
2256 * m16.igen: New file. Copy mips16 insns here.
2257 * mips.igen: From here.
2258
2259Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2260
2261 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2262 to top.
2263 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2264
2265Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2266
2267 * gencode.c (build_instruction): Follow sim_write's lead in using
2268 BigEndianMem instead of !ByteSwapMem.
2269
2270Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2271
2272 * configure.in (sim_gen): Dependent on target, select type of
2273 generator. Always select old style generator.
2274
2275 configure: Re-generate.
2276
2277 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2278 targets.
2279 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2280 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2281 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2282 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2283 SIM_@sim_gen@_*, set by autoconf.
2284
2285Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2286
2287 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2288
2289 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2290 CURRENT_FLOATING_POINT instead.
2291
2292 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2293 (address_translation): Raise exception InstructionFetch when
2294 translation fails and isINSTRUCTION.
2295
2296 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2297 sim_engine_run): Change type of of vaddr and paddr to
2298 address_word.
2299 (address_translation, prefetch, load_memory, store_memory,
2300 cache_op): Change type of vAddr and pAddr to address_word.
2301
2302 * gencode.c (build_instruction): Change type of vaddr and paddr to
2303 address_word.
2304
2305Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2306
2307 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2308 macro to obtain result of ALU op.
2309
2310Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2311
2312 * interp.c (sim_info): Call profile_print.
2313
2314Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2315
2316 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2317
2318 * sim-main.h (WITH_PROFILE): Do not define, defined in
2319 common/sim-config.h. Use sim-profile module.
2320 (simPROFILE): Delete defintion.
2321
2322 * interp.c (PROFILE): Delete definition.
2323 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2324 (sim_close): Delete code writing profile histogram.
2325 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2326 Delete.
2327 (sim_engine_run): Delete code profiling the PC.
2328
2329Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2330
2331 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2332
2333 * interp.c (sim_monitor): Make register pointers of type
2334 unsigned_word*.
2335
2336 * sim-main.h: Make registers of type unsigned_word not
2337 signed_word.
2338
2339Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2340
2341 * interp.c (sync_operation): Rename from SyncOperation, make
2342 global, add SD argument.
2343 (prefetch): Rename from Prefetch, make global, add SD argument.
2344 (decode_coproc): Make global.
2345
2346 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2347
2348 * gencode.c (build_instruction): Generate DecodeCoproc not
2349 decode_coproc calls.
2350
2351 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2352 (SizeFGR): Move to sim-main.h
2353 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2354 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2355 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2356 sim-main.h.
2357 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2358 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2359 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2360 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2361 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2362 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2363
2364 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2365 exception.
2366 (sim-alu.h): Include.
2367 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2368 (sim_cia): Typedef to instruction_address.
2369
2370Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2371
2372 * Makefile.in (interp.o): Rename generated file engine.c to
2373 oengine.c.
2374
2375 * interp.c: Update.
2376
2377Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2378
2379 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2380
2381Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2382
2383 * gencode.c (build_instruction): For "FPSQRT", output correct
2384 number of arguments to Recip.
2385
2386Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2387
2388 * Makefile.in (interp.o): Depends on sim-main.h
2389
2390 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2391
2392 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2393 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2394 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2395 STATE, DSSTATE): Define
2396 (GPR, FGRIDX, ..): Define.
2397
2398 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2399 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2400 (GPR, FGRIDX, ...): Delete macros.
2401
2402 * interp.c: Update names to match defines from sim-main.h
2403
2404Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2405
2406 * interp.c (sim_monitor): Add SD argument.
2407 (sim_warning): Delete. Replace calls with calls to
2408 sim_io_eprintf.
2409 (sim_error): Delete. Replace calls with sim_io_error.
2410 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2411 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2412 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2413 argument.
2414 (mips_size): Rename from sim_size. Add SD argument.
2415
2416 * interp.c (simulator): Delete global variable.
2417 (callback): Delete global variable.
2418 (mips_option_handler, sim_open, sim_write, sim_read,
2419 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2420 sim_size,sim_monitor): Use sim_io_* not callback->*.
2421 (sim_open): ZALLOC simulator struct.
2422 (PROFILE): Do not define.
2423
2424Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2425
2426 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2427 support.h with corresponding code.
2428
2429 * sim-main.h (word64, uword64), support.h: Move definition to
2430 sim-main.h.
2431 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2432
2433 * support.h: Delete
2434 * Makefile.in: Update dependencies
2435 * interp.c: Do not include.
2436
2437Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2438
2439 * interp.c (address_translation, load_memory, store_memory,
2440 cache_op): Rename to from AddressTranslation et.al., make global,
2441 add SD argument
2442
2443 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2444 CacheOp): Define.
2445
2446 * interp.c (SignalException): Rename to signal_exception, make
2447 global.
2448
2449 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2450
2451 * sim-main.h (SignalException, SignalExceptionInterrupt,
2452 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2453 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2454 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2455 Define.
2456
2457 * interp.c, support.h: Use.
2458
2459Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2460
2461 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2462 to value_fpr / store_fpr. Add SD argument.
2463 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2464 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2465
2466 * sim-main.h (ValueFPR, StoreFPR): Define.
2467
2468Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2469
2470 * interp.c (sim_engine_run): Check consistency between configure
2471 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2472 and HASFPU.
2473
2474 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2475 (mips_fpu): Configure WITH_FLOATING_POINT.
2476 (mips_endian): Configure WITH_TARGET_ENDIAN.
2477 * configure: Update.
2478
2479Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2480
2481 * configure: Regenerated to track ../common/aclocal.m4 changes.
2482
2483Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2484
2485 * configure: Regenerated.
2486
2487Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2488
2489 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2490
2491Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2492
2493 * gencode.c (print_igen_insn_models): Assume certain architectures
2494 include all mips* instructions.
2495 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2496 instruction.
2497
2498 * Makefile.in (tmp.igen): Add target. Generate igen input from
2499 gencode file.
2500
2501 * gencode.c (FEATURE_IGEN): Define.
2502 (main): Add --igen option. Generate output in igen format.
2503 (process_instructions): Format output according to igen option.
2504 (print_igen_insn_format): New function.
2505 (print_igen_insn_models): New function.
2506 (process_instructions): Only issue warnings and ignore
2507 instructions when no FEATURE_IGEN.
2508
2509Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2510
2511 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2512 MIPS targets.
2513
2514Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2515
2516 * configure: Regenerated to track ../common/aclocal.m4 changes.
2517
2518Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2519
2520 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2521 SIM_RESERVED_BITS): Delete, moved to common.
2522 (SIM_EXTRA_CFLAGS): Update.
2523
2524Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2525
2526 * configure.in: Configure non-strict memory alignment.
2527 * configure: Regenerated to track ../common/aclocal.m4 changes.
2528
2529Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2530
2531 * configure: Regenerated to track ../common/aclocal.m4 changes.
2532
2533Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2534
2535 * gencode.c (SDBBP,DERET): Added (3900) insns.
2536 (RFE): Turn on for 3900.
2537 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2538 (dsstate): Made global.
2539 (SUBTARGET_R3900): Added.
2540 (CANCELDELAYSLOT): New.
2541 (SignalException): Ignore SystemCall rather than ignore and
2542 terminate. Add DebugBreakPoint handling.
2543 (decode_coproc): New insns RFE, DERET; and new registers Debug
2544 and DEPC protected by SUBTARGET_R3900.
2545 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2546 bits explicitly.
2547 * Makefile.in,configure.in: Add mips subtarget option.
2548 * configure: Update.
2549
2550Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2551
2552 * gencode.c: Add r3900 (tx39).
2553
2554
2555Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2556
2557 * gencode.c (build_instruction): Don't need to subtract 4 for
2558 JALR, just 2.
2559
2560Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2561
2562 * interp.c: Correct some HASFPU problems.
2563
2564Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2565
2566 * configure: Regenerated to track ../common/aclocal.m4 changes.
2567
2568Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2569
2570 * interp.c (mips_options): Fix samples option short form, should
2571 be `x'.
2572
2573Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2574
2575 * interp.c (sim_info): Enable info code. Was just returning.
2576
2577Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2578
2579 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2580 MFC0.
2581
2582Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2583
2584 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2585 constants.
2586 (build_instruction): Ditto for LL.
2587
2588Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2589
2590 * configure: Regenerated to track ../common/aclocal.m4 changes.
2591
2592Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2593
2594 * configure: Regenerated to track ../common/aclocal.m4 changes.
2595 * config.in: Ditto.
2596
2597Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2598
2599 * interp.c (sim_open): Add call to sim_analyze_program, update
2600 call to sim_config.
2601
2602Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2603
2604 * interp.c (sim_kill): Delete.
2605 (sim_create_inferior): Add ABFD argument. Set PC from same.
2606 (sim_load): Move code initializing trap handlers from here.
2607 (sim_open): To here.
2608 (sim_load): Delete, use sim-hload.c.
2609
2610 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2611
2612Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2613
2614 * configure: Regenerated to track ../common/aclocal.m4 changes.
2615 * config.in: Ditto.
2616
2617Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2618
2619 * interp.c (sim_open): Add ABFD argument.
2620 (sim_load): Move call to sim_config from here.
2621 (sim_open): To here. Check return status.
2622
2623Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2624
2625 * gencode.c (build_instruction): Two arg MADD should
2626 not assign result to $0.
2627
2628Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2629
2630 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2631 * sim/mips/configure.in: Regenerate.
2632
2633Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2634
2635 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2636 signed8, unsigned8 et.al. types.
2637
2638 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2639 hosts when selecting subreg.
2640
2641Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2642
2643 * interp.c (sim_engine_run): Reset the ZERO register to zero
2644 regardless of FEATURE_WARN_ZERO.
2645 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2646
2647Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2648
2649 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2650 (SignalException): For BreakPoints ignore any mode bits and just
2651 save the PC.
2652 (SignalException): Always set the CAUSE register.
2653
2654Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2655
2656 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2657 exception has been taken.
2658
2659 * interp.c: Implement the ERET and mt/f sr instructions.
2660
2661Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2662
2663 * interp.c (SignalException): Don't bother restarting an
2664 interrupt.
2665
2666Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2667
2668 * interp.c (SignalException): Really take an interrupt.
2669 (interrupt_event): Only deliver interrupts when enabled.
2670
2671Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2672
2673 * interp.c (sim_info): Only print info when verbose.
2674 (sim_info) Use sim_io_printf for output.
2675
2676Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2677
2678 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2679 mips architectures.
2680
2681Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2682
2683 * interp.c (sim_do_command): Check for common commands if a
2684 simulator specific command fails.
2685
2686Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2687
2688 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2689 and simBE when DEBUG is defined.
2690
2691Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2692
2693 * interp.c (interrupt_event): New function. Pass exception event
2694 onto exception handler.
2695
2696 * configure.in: Check for stdlib.h.
2697 * configure: Regenerate.
2698
2699 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2700 variable declaration.
2701 (build_instruction): Initialize memval1.
2702 (build_instruction): Add UNUSED attribute to byte, bigend,
2703 reverse.
2704 (build_operands): Ditto.
2705
2706 * interp.c: Fix GCC warnings.
2707 (sim_get_quit_code): Delete.
2708
2709 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2710 * Makefile.in: Ditto.
2711 * configure: Re-generate.
2712
2713 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2714
2715Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2716
2717 * interp.c (mips_option_handler): New function parse argumes using
2718 sim-options.
2719 (myname): Replace with STATE_MY_NAME.
2720 (sim_open): Delete check for host endianness - performed by
2721 sim_config.
2722 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2723 (sim_open): Move much of the initialization from here.
2724 (sim_load): To here. After the image has been loaded and
2725 endianness set.
2726 (sim_open): Move ColdReset from here.
2727 (sim_create_inferior): To here.
2728 (sim_open): Make FP check less dependant on host endianness.
2729
2730 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2731 run.
2732 * interp.c (sim_set_callbacks): Delete.
2733
2734 * interp.c (membank, membank_base, membank_size): Replace with
2735 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2736 (sim_open): Remove call to callback->init. gdb/run do this.
2737
2738 * interp.c: Update
2739
2740 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2741
2742 * interp.c (big_endian_p): Delete, replaced by
2743 current_target_byte_order.
2744
2745Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2746
2747 * interp.c (host_read_long, host_read_word, host_swap_word,
2748 host_swap_long): Delete. Using common sim-endian.
2749 (sim_fetch_register, sim_store_register): Use H2T.
2750 (pipeline_ticks): Delete. Handled by sim-events.
2751 (sim_info): Update.
2752 (sim_engine_run): Update.
2753
2754Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2755
2756 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2757 reason from here.
2758 (SignalException): To here. Signal using sim_engine_halt.
2759 (sim_stop_reason): Delete, moved to common.
2760
2761Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2762
2763 * interp.c (sim_open): Add callback argument.
2764 (sim_set_callbacks): Delete SIM_DESC argument.
2765 (sim_size): Ditto.
2766
2767Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2768
2769 * Makefile.in (SIM_OBJS): Add common modules.
2770
2771 * interp.c (sim_set_callbacks): Also set SD callback.
2772 (set_endianness, xfer_*, swap_*): Delete.
2773 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2774 Change to functions using sim-endian macros.
2775 (control_c, sim_stop): Delete, use common version.
2776 (simulate): Convert into.
2777 (sim_engine_run): This function.
2778 (sim_resume): Delete.
2779
2780 * interp.c (simulation): New variable - the simulator object.
2781 (sim_kind): Delete global - merged into simulation.
2782 (sim_load): Cleanup. Move PC assignment from here.
2783 (sim_create_inferior): To here.
2784
2785 * sim-main.h: New file.
2786 * interp.c (sim-main.h): Include.
2787
2788Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2789
2790 * configure: Regenerated to track ../common/aclocal.m4 changes.
2791
2792Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2793
2794 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2795
2796Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2797
2798 * gencode.c (build_instruction): DIV instructions: check
2799 for division by zero and integer overflow before using
2800 host's division operation.
2801
2802Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2803
2804 * Makefile.in (SIM_OBJS): Add sim-load.o.
2805 * interp.c: #include bfd.h.
2806 (target_byte_order): Delete.
2807 (sim_kind, myname, big_endian_p): New static locals.
2808 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2809 after argument parsing. Recognize -E arg, set endianness accordingly.
2810 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2811 load file into simulator. Set PC from bfd.
2812 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2813 (set_endianness): Use big_endian_p instead of target_byte_order.
2814
2815Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2816
2817 * interp.c (sim_size): Delete prototype - conflicts with
2818 definition in remote-sim.h. Correct definition.
2819
2820Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2821
2822 * configure: Regenerated to track ../common/aclocal.m4 changes.
2823 * config.in: Ditto.
2824
2825Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2826
2827 * interp.c (sim_open): New arg `kind'.
2828
2829 * configure: Regenerated to track ../common/aclocal.m4 changes.
2830
2831Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2832
2833 * configure: Regenerated to track ../common/aclocal.m4 changes.
2834
2835Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2836
2837 * interp.c (sim_open): Set optind to 0 before calling getopt.
2838
2839Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2840
2841 * configure: Regenerated to track ../common/aclocal.m4 changes.
2842
2843Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2844
2845 * interp.c : Replace uses of pr_addr with pr_uword64
2846 where the bit length is always 64 independent of SIM_ADDR.
2847 (pr_uword64) : added.
2848
2849Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2850
2851 * configure: Re-generate.
2852
2853Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2854
2855 * configure: Regenerate to track ../common/aclocal.m4 changes.
2856
2857Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2858
2859 * interp.c (sim_open): New SIM_DESC result. Argument is now
2860 in argv form.
2861 (other sim_*): New SIM_DESC argument.
2862
2863Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2864
2865 * interp.c: Fix printing of addresses for non-64-bit targets.
2866 (pr_addr): Add function to print address based on size.
2867
2868Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2869
2870 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2871
2872Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2873
2874 * gencode.c (build_mips16_operands): Correct computation of base
2875 address for extended PC relative instruction.
2876
2877Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2878
2879 * interp.c (mips16_entry): Add support for floating point cases.
2880 (SignalException): Pass floating point cases to mips16_entry.
2881 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2882 registers.
2883 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2884 or fmt_word.
2885 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2886 and then set the state to fmt_uninterpreted.
2887 (COP_SW): Temporarily set the state to fmt_word while calling
2888 ValueFPR.
2889
2890Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2891
2892 * gencode.c (build_instruction): The high order may be set in the
2893 comparison flags at any ISA level, not just ISA 4.
2894
2895Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2896
2897 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2898 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2899 * configure.in: sinclude ../common/aclocal.m4.
2900 * configure: Regenerated.
2901
2902Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2903
2904 * configure: Rebuild after change to aclocal.m4.
2905
2906Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2907
2908 * configure configure.in Makefile.in: Update to new configure
2909 scheme which is more compatible with WinGDB builds.
2910 * configure.in: Improve comment on how to run autoconf.
2911 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2912 * Makefile.in: Use autoconf substitution to install common
2913 makefile fragment.
2914
2915Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2916
2917 * gencode.c (build_instruction): Use BigEndianCPU instead of
2918 ByteSwapMem.
2919
2920Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2921
2922 * interp.c (sim_monitor): Make output to stdout visible in
2923 wingdb's I/O log window.
2924
2925Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2926
2927 * support.h: Undo previous change to SIGTRAP
2928 and SIGQUIT values.
2929
2930Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2931
2932 * interp.c (store_word, load_word): New static functions.
2933 (mips16_entry): New static function.
2934 (SignalException): Look for mips16 entry and exit instructions.
2935 (simulate): Use the correct index when setting fpr_state after
2936 doing a pending move.
2937
2938Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2939
2940 * interp.c: Fix byte-swapping code throughout to work on
2941 both little- and big-endian hosts.
2942
2943Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2944
2945 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2946 with gdb/config/i386/xm-windows.h.
2947
2948Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2949
2950 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2951 that messes up arithmetic shifts.
2952
2953Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2954
2955 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2956 SIGTRAP and SIGQUIT for _WIN32.
2957
2958Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2959
2960 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2961 force a 64 bit multiplication.
2962 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2963 destination register is 0, since that is the default mips16 nop
2964 instruction.
2965
2966Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2967
2968 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2969 (build_endian_shift): Don't check proc64.
2970 (build_instruction): Always set memval to uword64. Cast op2 to
2971 uword64 when shifting it left in memory instructions. Always use
2972 the same code for stores--don't special case proc64.
2973
2974 * gencode.c (build_mips16_operands): Fix base PC value for PC
2975 relative operands.
2976 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2977 jal instruction.
2978 * interp.c (simJALDELAYSLOT): Define.
2979 (JALDELAYSLOT): Define.
2980 (INDELAYSLOT, INJALDELAYSLOT): Define.
2981 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2982
2983Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2984
2985 * interp.c (sim_open): add flush_cache as a PMON routine
2986 (sim_monitor): handle flush_cache by ignoring it
2987
2988Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2989
2990 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2991 BigEndianMem.
2992 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2993 (BigEndianMem): Rename to ByteSwapMem and change sense.
2994 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2995 BigEndianMem references to !ByteSwapMem.
2996 (set_endianness): New function, with prototype.
2997 (sim_open): Call set_endianness.
2998 (sim_info): Use simBE instead of BigEndianMem.
2999 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3000 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3001 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3002 ifdefs, keeping the prototype declaration.
3003 (swap_word): Rewrite correctly.
3004 (ColdReset): Delete references to CONFIG. Delete endianness related
3005 code; moved to set_endianness.
3006
3007Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3008
3009 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3010 * interp.c (CHECKHILO): Define away.
3011 (simSIGINT): New macro.
3012 (membank_size): Increase from 1MB to 2MB.
3013 (control_c): New function.
3014 (sim_resume): Rename parameter signal to signal_number. Add local
3015 variable prev. Call signal before and after simulate.
3016 (sim_stop_reason): Add simSIGINT support.
3017 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3018 functions always.
3019 (sim_warning): Delete call to SignalException. Do call printf_filtered
3020 if logfh is NULL.
3021 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3022 a call to sim_warning.
3023
3024Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3025
3026 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3027 16 bit instructions.
3028
3029Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3030
3031 Add support for mips16 (16 bit MIPS implementation):
3032 * gencode.c (inst_type): Add mips16 instruction encoding types.
3033 (GETDATASIZEINSN): Define.
3034 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3035 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3036 mtlo.
3037 (MIPS16_DECODE): New table, for mips16 instructions.
3038 (bitmap_val): New static function.
3039 (struct mips16_op): Define.
3040 (mips16_op_table): New table, for mips16 operands.
3041 (build_mips16_operands): New static function.
3042 (process_instructions): If PC is odd, decode a mips16
3043 instruction. Break out instruction handling into new
3044 build_instruction function.
3045 (build_instruction): New static function, broken out of
3046 process_instructions. Check modifiers rather than flags for SHIFT
3047 bit count and m[ft]{hi,lo} direction.
3048 (usage): Pass program name to fprintf.
3049 (main): Remove unused variable this_option_optind. Change
3050 ``*loptarg++'' to ``loptarg++''.
3051 (my_strtoul): Parenthesize && within ||.
3052 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3053 (simulate): If PC is odd, fetch a 16 bit instruction, and
3054 increment PC by 2 rather than 4.
3055 * configure.in: Add case for mips16*-*-*.
3056 * configure: Rebuild.
3057
3058Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3059
3060 * interp.c: Allow -t to enable tracing in standalone simulator.
3061 Fix garbage output in trace file and error messages.
3062
3063Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3064
3065 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3066 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3067 * configure.in: Simplify using macros in ../common/aclocal.m4.
3068 * configure: Regenerated.
3069 * tconfig.in: New file.
3070
3071Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3072
3073 * interp.c: Fix bugs in 64-bit port.
3074 Use ansi function declarations for msvc compiler.
3075 Initialize and test file pointer in trace code.
3076 Prevent duplicate definition of LAST_EMED_REGNUM.
3077
3078Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3079
3080 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3081
3082Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3083
3084 * interp.c (SignalException): Check for explicit terminating
3085 breakpoint value.
3086 * gencode.c: Pass instruction value through SignalException()
3087 calls for Trap, Breakpoint and Syscall.
3088
3089Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3090
3091 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3092 only used on those hosts that provide it.
3093 * configure.in: Add sqrt() to list of functions to be checked for.
3094 * config.in: Re-generated.
3095 * configure: Re-generated.
3096
3097Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3098
3099 * gencode.c (process_instructions): Call build_endian_shift when
3100 expanding STORE RIGHT, to fix swr.
3101 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3102 clear the high bits.
3103 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3104 Fix float to int conversions to produce signed values.
3105
3106Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3107
3108 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3109 (process_instructions): Correct handling of nor instruction.
3110 Correct shift count for 32 bit shift instructions. Correct sign
3111 extension for arithmetic shifts to not shift the number of bits in
3112 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3113 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3114 Fix madd.
3115 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3116 It's OK to have a mult follow a mult. What's not OK is to have a
3117 mult follow an mfhi.
3118 (Convert): Comment out incorrect rounding code.
3119
3120Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3121
3122 * interp.c (sim_monitor): Improved monitor printf
3123 simulation. Tidied up simulator warnings, and added "--log" option
3124 for directing warning message output.
3125 * gencode.c: Use sim_warning() rather than WARNING macro.
3126
3127Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3128
3129 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3130 getopt1.o, rather than on gencode.c. Link objects together.
3131 Don't link against -liberty.
3132 (gencode.o, getopt.o, getopt1.o): New targets.
3133 * gencode.c: Include <ctype.h> and "ansidecl.h".
3134 (AND): Undefine after including "ansidecl.h".
3135 (ULONG_MAX): Define if not defined.
3136 (OP_*): Don't define macros; now defined in opcode/mips.h.
3137 (main): Call my_strtoul rather than strtoul.
3138 (my_strtoul): New static function.
3139
3140Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3141
3142 * gencode.c (process_instructions): Generate word64 and uword64
3143 instead of `long long' and `unsigned long long' data types.
3144 * interp.c: #include sysdep.h to get signals, and define default
3145 for SIGBUS.
3146 * (Convert): Work around for Visual-C++ compiler bug with type
3147 conversion.
3148 * support.h: Make things compile under Visual-C++ by using
3149 __int64 instead of `long long'. Change many refs to long long
3150 into word64/uword64 typedefs.
3151
3152Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3153
3154 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3155 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3156 (docdir): Removed.
3157 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3158 (AC_PROG_INSTALL): Added.
3159 (AC_PROG_CC): Moved to before configure.host call.
3160 * configure: Rebuilt.
3161
3162Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3163
3164 * configure.in: Define @SIMCONF@ depending on mips target.
3165 * configure: Rebuild.
3166 * Makefile.in (run): Add @SIMCONF@ to control simulator
3167 construction.
3168 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3169 * interp.c: Remove some debugging, provide more detailed error
3170 messages, update memory accesses to use LOADDRMASK.
3171
3172Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3173
3174 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3175 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3176 stamp-h.
3177 * configure: Rebuild.
3178 * config.in: New file, generated by autoheader.
3179 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3180 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3181 HAVE_ANINT and HAVE_AINT, as appropriate.
3182 * Makefile.in (run): Use @LIBS@ rather than -lm.
3183 (interp.o): Depend upon config.h.
3184 (Makefile): Just rebuild Makefile.
3185 (clean): Remove stamp-h.
3186 (mostlyclean): Make the same as clean, not as distclean.
3187 (config.h, stamp-h): New targets.
3188
3189Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3190
3191 * interp.c (ColdReset): Fix boolean test. Make all simulator
3192 globals static.
3193
3194Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3195
3196 * interp.c (xfer_direct_word, xfer_direct_long,
3197 swap_direct_word, swap_direct_long, xfer_big_word,
3198 xfer_big_long, xfer_little_word, xfer_little_long,
3199 swap_word,swap_long): Added.
3200 * interp.c (ColdReset): Provide function indirection to
3201 host<->simulated_target transfer routines.
3202 * interp.c (sim_store_register, sim_fetch_register): Updated to
3203 make use of indirected transfer routines.
3204
3205Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3206
3207 * gencode.c (process_instructions): Ensure FP ABS instruction
3208 recognised.
3209 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3210 system call support.
3211
3212Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3213
3214 * interp.c (sim_do_command): Complain if callback structure not
3215 initialised.
3216
3217Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3218
3219 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3220 support for Sun hosts.
3221 * Makefile.in (gencode): Ensure the host compiler and libraries
3222 used for cross-hosted build.
3223
3224Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3225
3226 * interp.c, gencode.c: Some more (TODO) tidying.
3227
3228Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3229
3230 * gencode.c, interp.c: Replaced explicit long long references with
3231 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3232 * support.h (SET64LO, SET64HI): Macros added.
3233
3234Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3235
3236 * configure: Regenerate with autoconf 2.7.
3237
3238Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3239
3240 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3241 * support.h: Remove superfluous "1" from #if.
3242 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3243
3244Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3245
3246 * interp.c (StoreFPR): Control UndefinedResult() call on
3247 WARN_RESULT manifest.
3248
3249Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3250
3251 * gencode.c: Tidied instruction decoding, and added FP instruction
3252 support.
3253
3254 * interp.c: Added dineroIII, and BSD profiling support. Also
3255 run-time FP handling.
3256
3257Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3258
3259 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3260 gencode.c, interp.c, support.h: created.
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