]>
Commit | Line | Data |
---|---|---|
d1cbd70a AC |
1 | Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com> |
2 | ||
3 | * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK | |
4 | insn as a debug breakpoint. | |
5 | ||
6 | * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as | |
7 | pending.slot_size. | |
8 | (PENDING_SCHED): Clean up trace statement. | |
9 | (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL. | |
10 | (PENDING_FILL): Delay write by only one cycle. | |
11 | (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE. | |
12 | ||
13 | * sim-main.c (pending_tick): Clean up trace statements. Add trace | |
14 | of pending writes. | |
15 | (pending_tick): Fix sizes in switch statements, 4 & 8 instead of | |
16 | 32 & 64. | |
17 | (pending_tick): Move incrementing of index to FOR statement. | |
18 | (pending_tick): Only update PENDING_OUT after a write has occured. | |
19 | ||
20 | * configure.in: Add explicit mips-lsi-* target. Use gencode to | |
21 | build simulator. | |
22 | * configure: Re-generate. | |
23 | ||
24 | * interp.c (sim_engine_run OLD): Delete explicit call to | |
25 | PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK. | |
26 | ||
dd0f6109 | 27 | start-sanitize-r5900 |
7d88afe6 AC |
28 | Wed Nov 11 16:53:57 1998 Andrew Cagney <cagney@b1.cygnus.com> |
29 | ||
30 | * r5900.igen (RSQRT): Set both I/SI and D/SD when div-0. | |
31 | ||
210a903b FCE |
32 | Thu Nov 5 10:29:42 EST 1998 Frank Ch. Eigler <fche@cygnus.com> |
33 | ||
34 | * r5900.igen (r59fp_opdiv): Correct erroneous FGR[FD] reference. | |
35 | ||
dd0f6109 AC |
36 | Thu Nov 5 19:40:12 1998 Andrew Cagney <cagney@b1.cygnus.com> |
37 | ||
38 | * r5900.igen (DIV): Do not clear clear SO/SU when already set. | |
39 | ||
40 | * r5900.igen (RSQRT.S): Do not compute 1/srqt(abs(T)) when T | |
41 | negative, compute S/sqrt(abs(T)) instead. Correctly set FCSR | |
42 | bits. | |
43 | ||
44 | * r5900.igen (RSQRT.S): Handle overflow/underflow better. Check | |
45 | sign of FT not FS. | |
46 | (r59fp_store): Clarify "bad value" abort messages. | |
47 | ||
48 | end-sanitize-r5900 | |
0ec51df9 | 49 | start-sanitize-tx3904 |
fd0e83b6 | 50 | Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com> |
0ec51df9 FCE |
51 | |
52 | * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy | |
53 | interrupt level number to match changed SignalExceptionInterrupt | |
54 | macro. | |
55 | ||
56 | end-sanitize-tx3904 | |
fd6e6422 FCE |
57 | start-sanitize-sky |
58 | Thu Oct 29 12:47:46 1998 Frank Ch. Eigler <fche@cygnus.com> | |
59 | ||
60 | * sim-main.c (tlb_try_match): Include physical address in | |
61 | scratchpad non-mapping warning. | |
62 | ||
63 | end-sanitize-sky | |
3ac7980b FCE |
64 | start-sanitize-r5900 |
65 | Thu Oct 29 11:06:30 EST 1998 Frank Ch. Eigler <fche@cygnus.com> | |
66 | ||
67 | * r5900.igen: Fix PSRLVW, MULTU1, PADSBH instructions, | |
68 | as per customer patch. | |
69 | ||
70 | end-sanitize-r5900 | |
3b5f4257 DE |
71 | Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com> |
72 | ||
73 | * interp.c: #include "itable.h" if WITH_IGEN. | |
74 | (get_insn_name): New function. | |
75 | (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS. | |
fda83b67 | 76 | * sim-main.h (MAX_INSNS,INSN_NAME): Delete. |
3b5f4257 | 77 | |
fda83b67 FCE |
78 | start-sanitize-sky |
79 | Tue Sep 22 10:35:37 1998 Frank Ch. Eigler <fche@cygnus.com> | |
80 | ||
81 | * sim-main.c (tlb_try_match): Specially match virtual | |
82 | pages mapped to scratchpad RAM, an unimplemented feature. | |
83 | ||
84 | end-sanitize-sky | |
85 | start-sanitize-r5900 | |
86 | Fri Sep 18 11:31:16 1998 Frank Ch. Eigler <fche@cygnus.com> | |
87 | ||
88 | * r5900.igen (prot3w): Correct rotation sequence; patch | |
89 | from customer. | |
90 | ||
91 | end-sanitize-r5900 | |
3b5f4257 DE |
92 | Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com> |
93 | ||
94 | * configure: Rebuilt to inhale new common/aclocal.m4. | |
95 | ||
9ade226a | 96 | start-sanitize-r5900 |
4d87923e DE |
97 | Thu Sep 10 11:50:54 1998 Doug Evans <devans@canuck.cygnus.com> |
98 | ||
99 | * r5900.igen (plzcw): Make `i' signed. | |
100 | ||
fda83b67 FCE |
101 | Wed Sep 9 15:02:10 1998 Doug Evans <devans@canuck.cygnus.com> |
102 | ||
103 | * sim-main.h (COP0_COUNT,COP0_COMPARE,status_IM7): New macros. | |
104 | * sky-engine.c (cpu_issue): Increment COP0_COUNT and signal an | |
105 | interrupt if == COP0_COMPARE and interrupt masks/enables allow it. | |
106 | * interp.c (signal_exception, sky version): Handle INT 2. | |
107 | ||
323f833d RU |
108 | Wed Sep 9 11:28:20 1998 Ron Unrau <runrau@cygnus.com> |
109 | ||
110 | * sim-main.h: track COP0 registers | |
111 | * interp.c (sim_{fetch,store}_register): read/write COP0 registers | |
112 | ||
9ade226a FCE |
113 | Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com> |
114 | ||
115 | * r5900.igen (mtsab): Correct typo in input register. | |
116 | ||
117 | * sim-main.h (TMP_*): New macros for accessing local 128-bit | |
118 | temporary for multimedia instructions. | |
119 | * r5900.igen (*): Convert most instructions to use new TMP | |
120 | macros to store output result during computation. | |
121 | ||
122 | end-sanitize-r5900 | |
78b871ec FCE |
123 | start-sanitize-tx3904 |
124 | Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com> | |
125 | ||
126 | * dv-tx3904sio.c: Include sim-assert.h. | |
127 | ||
128 | Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com> | |
129 | ||
130 | * dv-tx3904sio.c: New file: tx3904 serial I/O module. | |
131 | * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target. | |
132 | Reorganize target-specific sim-hardware checks. | |
133 | * configure: rebuilt. | |
134 | * interp.c (sim_open): For tx39 target boards, set | |
135 | OPERATING_ENVIRONMENT, add tx3904sio devices. | |
136 | * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading | |
137 | ROM executables. Install dv-sockser into sim-modules list. | |
138 | ||
139 | * dv-tx3904irc.c: Compiler warning clean-up. | |
140 | * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly | |
141 | frequent hw-trace messages. | |
142 | ||
143 | end-sanitize-tx3904 | |
fda83b67 FCE |
144 | start-sanitize-sky |
145 | Tue Aug 11 13:52:16 1998 Frank Ch. Eigler <fche@cygnus.com> | |
146 | ||
147 | * interp.c (signal_exception): Set IP3 bit in CAUSE on | |
148 | sky interrupt. | |
149 | ||
150 | end-sanitize-sky | |
78b871ec FCE |
151 | Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com> |
152 | ||
153 | * vr.igen (MulAcc): Identify as a vr4100 specific function. | |
154 | ||
e1b20d30 AC |
155 | Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com> |
156 | ||
78b871ec FCE |
157 | * Makefile.in (IGEN_INCLUDE): Add vr.igen. |
158 | ||
e1b20d30 AC |
159 | * vr.igen: New file. |
160 | (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c. | |
161 | * mips.igen: Define vr4100 model. Include vr.igen. | |
78b871ec FCE |
162 | start-sanitize-cygnus |
163 | * vr5400.igen: Move instructions to vr.igen | |
164 | * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen. | |
165 | end-sanitize-cygnus | |
166 | start-sanitize-vr4320 | |
167 | * vr4320.igen: Move instructions to vr.igen. | |
168 | * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen. | |
fda83b67 | 169 | |
78b871ec | 170 | end-sanitize-vr4320 |
fda83b67 FCE |
171 | start-sanitize-sky |
172 | Fri Jul 24 16:01:03 1998 Ian Carmichael <iancarm@cygnus.com> | |
173 | ||
174 | * interp.c (MONITOR_SIZE): Make 1MB monitor for SKY. | |
175 | * mips.igen (BREAK): Fix 0xffff2 monitor call. Slightly less | |
176 | confusing message if not enough --load-next options appear. | |
177 | ||
178 | * sky-pke.h (VUx_MEMx_SRCADDR_START): Move to 0x19800000 range. | |
179 | * sim-main.c (GDB_COMM_AREA): Move to 0x19810000. | |
180 | * sky-gdb.c (init_fifo_bp_cache): Use VIO_BASE when reading GDB area. | |
181 | (resume_handler): Same. | |
182 | (suspend_handler): Same. | |
183 | ||
184 | Wed Jul 22 13:04:13 1998 Frank Ch. Eigler <fche@cygnus.com> | |
185 | ||
186 | * mips.igen (break): Implement LOAD_INSTRUCTION ("break 0xffff1") | |
187 | to trigger multi-phase load. | |
188 | ||
189 | * sim-main.c: Include sim-assert.h for ASSERT macro. | |
190 | * sim-main.h (PRINTF_INSTRUCTION): Correct bit pattern for | |
191 | "break 0xffff2". | |
192 | ||
193 | Tue Jul 21 18:37:36 1998 Ian Carmichael <iancarm@cygnus.com> | |
194 | ||
195 | MMU support. | |
196 | * interp.c (sim_open): Initialize TLB. | |
197 | * interp.c (signal_exceptions): New 5900 handling. | |
198 | * r5900.igen (TLBWR, TLBWI, TLBR, TLBP): Make these work. | |
199 | * sim-main.c (tlb_try_match, tlb_lookup): New functions. | |
200 | (address_translation): Use the TLB. | |
201 | * sim-main.h (r4000_tlb_entry_t): New type. | |
202 | (TLB_*): New constants. | |
203 | (COP0_*): New register names. | |
204 | ||
205 | Sky character I/O device. | |
206 | * sky-psio.c: New file. | |
207 | * sky-psio.h: New file. | |
208 | * Makefile.in: Add sky-psio.o. | |
e1b20d30 | 209 | |
fda83b67 | 210 | end-sanitize-sky |
e1b20d30 AC |
211 | start-sanitize-r5900 |
212 | Tue Jul 14 16:10:45 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
213 | ||
214 | * r5900.igen (r59fp_overflow): Replace argument ANS with argument | |
215 | SIGN_P. | |
216 | (r59fp_zero): Ditto. | |
217 | (r59fp_store): Update calls. | |
218 | (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0. | |
219 | ||
220 | end-sanitize-r5900 | |
221 | start-sanitize-branchbug4011 | |
222 | Mon Jun 29 09:31:27 1998 Gavin Koch <gavin@cygnus.com> | |
223 | ||
224 | * interp.c (OPTION_BRANCH_BUG_4011): Add. | |
225 | (mips_option_handler): Handle OPTION_BRANCH_BUG_4011. | |
226 | (mips_options): Define the option. | |
227 | * mips.igen (check_4011_branch_bug): New. | |
228 | (mark_4011_branch_bug): New. | |
229 | (all branch insn): Call mark_branch_bug, and check_branch_bug. | |
230 | * sim-main.h (branchbug4011_option, branchbug4011_last_target, | |
231 | branchbug4011_last_cia, BRANCHBUG4011_OPTION, | |
232 | BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA, | |
233 | check_branch_bug, mark_branch_bug): Define. | |
234 | ||
235 | end-sanitize-branchbug4011 | |
aaa2c908 GRK |
236 | Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com> |
237 | ||
238 | * mips.igen (check_mf_hilo): Correct check. | |
239 | ||
240 | start-sanitize-r5900 | |
241 | Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
242 | ||
243 | * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP, | |
244 | COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general | |
245 | purpose registers, add 8 COP0 break-point registers, add 64 COP0 | |
246 | performance registers. | |
247 | ||
248 | * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP* | |
249 | MFP* instructions. Just transfer value to/from corresponding | |
250 | register. | |
251 | ||
252 | * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0 | |
253 | status is always true. | |
254 | (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP. | |
255 | (EI, DI): Set/clear Status-EIE bit. | |
256 | ||
257 | end-sanitize-r5900 | |
258 | start-sanitize-sky | |
259 | Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
260 | ||
261 | * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to | |
262 | r5900.igen. | |
263 | ||
264 | end-sanitize-sky | |
265 | Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
266 | ||
267 | start-sanitize-sky | |
268 | * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call | |
269 | ASSERT not assert. | |
270 | * sky-gdb.c: Include "sim-assert.h". | |
271 | ||
272 | end-sanitize-sky | |
273 | * sim-main.h (interrupt_event): Add prototype. | |
274 | ||
275 | start-sanitize-tx3904 | |
276 | * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused | |
277 | register_ptr, register_value. | |
278 | (deliver_tx3904tmr_tick): Fix types passed to printf fmt. | |
279 | ||
280 | end-sanitize-tx3904 | |
281 | * sim-main.h (tracefh): Make extern. | |
282 | ||
702968c5 FCE |
283 | start-sanitize-tx3904 |
284 | Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com> | |
285 | ||
286 | * dv-tx3904tmr.c: Deschedule timer event after dispatching. | |
287 | Reduce unnecessarily high timer event frequency. | |
288 | * dv-tx3904cpu.c: Ditto for interrupt event. | |
289 | ||
290 | end-sanitize-tx3904 | |
291 | start-sanitize-sky | |
292 | Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com> | |
293 | ||
294 | * interp.c (decode_coproc): Removed COP2 branches. | |
295 | * r5900.igen: Moved COP2 branch instructions here. | |
296 | * mips.igen: Restricted COPz == COP2 bit pattern to | |
297 | exclude COP2 branches. | |
298 | ||
299 | end-sanitize-sky | |
b8790963 FCE |
300 | Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com> |
301 | ||
302 | * interp.c (decode_coproc): For TX39, add stub COP0 register #7, | |
303 | to allay warnings. | |
304 | (interrupt_event): Made non-static. | |
305 | start-sanitize-tx3904 | |
306 | ||
307 | * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental | |
308 | interchange of configuration values for external vs. internal | |
309 | clock dividers. | |
310 | end-sanitize-tx3904 | |
b8790963 | 311 | |
0001bce1 IC |
312 | Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com> |
313 | ||
314 | * mips.igen (BREAK): Moved code to here for | |
315 | simulator-reserved break instructions. | |
316 | * gencode.c (build_instruction): Ditto. | |
317 | * interp.c (signal_exception): Code moved from here. Non- | |
318 | reserved instructions now use exception vector, rather | |
319 | than halting sim. | |
320 | * sim-main.h: Moved magic constants to here. | |
321 | ||
cc9bc932 FCE |
322 | start-sanitize-tx3904 |
323 | Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com> | |
324 | ||
325 | * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE | |
326 | register upon non-zero interrupt event level, clear upon zero | |
327 | event value. | |
328 | * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal | |
329 | by passing zero event value. | |
330 | (*_io_{read,write}_buffer): Endianness fixes. | |
331 | * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes. | |
332 | (deliver_*_tick): Reduce sim event interval to 75% of count interval. | |
333 | ||
334 | * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based | |
335 | serial I/O and timer module at base address 0xFFFF0000. | |
336 | ||
337 | end-sanitize-tx3904 | |
2b5d87df GRK |
338 | Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com> |
339 | ||
340 | * mips.igen (SWC1) : Correct the handling of ReverseEndian | |
341 | and BigEndianCPU. | |
342 | ||
55ad270f GRK |
343 | Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com> |
344 | ||
345 | * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips | |
346 | parts. | |
347 | * configure: Update. | |
348 | ||
da040f2a FCE |
349 | start-sanitize-tx3904 |
350 | Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com> | |
351 | ||
352 | * dv-tx3904tmr.c: New file - implements tx3904 timer. | |
353 | * dv-tx3904{irc,cpu}.c: Mild reformatting. | |
354 | * configure.in: Include tx3904tmr in hw_device list. | |
355 | * configure: Rebuilt. | |
356 | * interp.c (sim_open): Instantiate three timer instances. | |
357 | Fix address typo of tx3904irc instance. | |
358 | ||
359 | end-sanitize-tx3904 | |
0e797366 AC |
360 | start-sanitize-r5900 |
361 | Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
362 | ||
363 | * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO. | |
364 | Select corresponding check_mt_hilo function. | |
365 | (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo): | |
366 | Ditto. | |
367 | ||
368 | * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark | |
369 | as r5900 specific. | |
370 | ||
371 | end-sanitize-r5900 | |
8e3a0b59 IC |
372 | Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com> |
373 | ||
374 | * interp.c (signal_exception): SystemCall exception now uses | |
375 | the exception vector. | |
376 | ||
29b5afe9 FCE |
377 | Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> |
378 | ||
379 | * interp.c (decode_coproc): For TX39, add stub COP0 register #3, | |
380 | to allay warnings. | |
381 | ||
fb0ea2b9 JL |
382 | start-sanitize-r5900 |
383 | Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com) | |
384 | ||
385 | * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1. | |
386 | (sqrt.s): Likewise. | |
387 | ||
388 | end-sanitize-r5900 | |
df26156d AC |
389 | Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com> |
390 | ||
391 | * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39. | |
392 | ||
393 | start-sanitize-tx3904 | |
394 | Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
395 | ||
396 | * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method. | |
397 | ||
398 | * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and | |
399 | sim-main.h. Declare a struct hw_descriptor instead of struct | |
400 | hw_device_descriptor. | |
401 | ||
402 | end-sanitize-tx3904 | |
ce823781 AC |
403 | Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com> |
404 | ||
405 | * mips.igen (do_store_left, do_load_left): Compute nr of left and | |
406 | right bits and then re-align left hand bytes to correct byte | |
407 | lanes. Fix incorrect computation in do_store_left when loading | |
408 | bytes from second word. | |
409 | ||
f872d0d6 AC |
410 | start-sanitize-tx3904 |
411 | Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
412 | ||
413 | * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904. | |
414 | * interp.c (sim_open): Only create a device tree when HW is | |
415 | enabled. | |
416 | ||
417 | * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC. | |
418 | * interp.c (signal_exception): Ditto. | |
419 | ||
420 | end-sanitize-tx3904 | |
5e34097b GRK |
421 | Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com> |
422 | ||
423 | * gencode.c: Mark BEGEZALL as LIKELY. | |
424 | ||
26feb3a8 AC |
425 | Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com> |
426 | ||
427 | * sim-main.h (ALU32_END): Sign extend 32 bit results. | |
428 | * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace. | |
429 | ||
84048259 AC |
430 | start-sanitize-r5900 |
431 | Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
432 | ||
433 | * interp.c (sim_fetch_register): Convert internal r5900 regs to | |
434 | target byte order | |
435 | ||
436 | end-sanitize-r5900 | |
3fa454e9 FCE |
437 | Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> |
438 | ||
439 | * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware | |
440 | modules. Recognize TX39 target with "mips*tx39" pattern. | |
441 | * configure: Rebuilt. | |
442 | * sim-main.h (*): Added many macros defining bits in | |
443 | TX39 control registers. | |
444 | (SignalInterrupt): Send actual PC instead of NULL. | |
445 | (SignalNMIReset): New exception type. | |
446 | * interp.c (board): New variable for future use to identify | |
447 | a particular board being simulated. | |
448 | (mips_option_handler,mips_options): Added "--board" option. | |
449 | (interrupt_event): Send actual PC. | |
450 | (sim_open): Make memory layout conditional on board setting. | |
451 | (signal_exception): Initial implementation of hardware interrupt | |
452 | handling. Accept another break instruction variant for simulator | |
453 | exit. | |
454 | (decode_coproc): Implement RFE instruction for TX39. | |
455 | (mips.igen): Decode RFE instruction as such. | |
456 | start-sanitize-tx3904 | |
457 | * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. | |
458 | * interp.c: Define "jmr3904" and "jmr3904debug" board types and | |
459 | bbegin to implement memory map. | |
460 | * dv-tx3904cpu.c: New file. | |
461 | * dv-tx3904irc.c: New file. | |
462 | end-sanitize-tx3904 | |
463 | ||
464 | Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com> | |
465 | ||
466 | * mips.igen (check_mt_hilo): Create a separate r3900 version. | |
467 | ||
32d41f6d | 468 | start-sanitize-r5900 |
7d2c0e8c GRK |
469 | Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com> |
470 | ||
471 | * r5900.igen: Replace the calls and the definition of the | |
472 | function check_op_hilo_hi1lo1 with the pair | |
473 | check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1. | |
474 | ||
32d41f6d | 475 | end-sanitize-r5900 |
afc5e7f2 GRK |
476 | Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com> |
477 | ||
478 | * tx.igen (madd,maddu): Replace calls to check_op_hilo | |
479 | with calls to check_div_hilo. | |
480 | ||
94dda41a GRK |
481 | Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com> |
482 | ||
483 | * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo): | |
484 | Replace check_op_hilo with check_mult_hilo and check_div_hilo. | |
485 | Add special r3900 version of do_mult_hilo. | |
486 | (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo | |
487 | with calls to check_mult_hilo. | |
488 | (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo | |
489 | with calls to check_div_hilo. | |
490 | ||
1a89994e AC |
491 | Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com> |
492 | ||
493 | * configure.in (SUBTARGET_R3900): Define for mipstx39 target. | |
494 | Document a replacement. | |
495 | ||
496 | Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com> | |
497 | ||
498 | * interp.c (sim_monitor): Make mon_printf work. | |
499 | ||
eb00d706 DE |
500 | Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com> |
501 | ||
502 | * sim-main.h (INSN_NAME): New arg `cpu'. | |
503 | ||
504 | start-sanitize-sky | |
505 | Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
506 | ||
507 | * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with | |
508 | r59fp_mula. | |
509 | ||
510 | end-sanitize-sky | |
511 | start-sanitize-r5900 | |
512 | Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
513 | ||
514 | * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define. | |
515 | * r5900.igen (r59fp_overflow): Use. | |
516 | ||
517 | * r5900.igen (r59fp_op3): Rename to | |
518 | (r59fp_mula): This, delete opm argument. | |
519 | (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update. | |
520 | (r59fp_mula): Overflowing product propogates through to result. | |
521 | (r59fp_mula): ACC to the MAX propogates to result. | |
522 | (r59fp_mula): Underflow during multiply only sets SU. | |
523 | ||
524 | end-sanitize-r5900 | |
9d45df1b GN |
525 | Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com> |
526 | ||
527 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
528 | ||
5da9ce07 TT |
529 | Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche> |
530 | ||
531 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
532 | * config.in: Ditto. | |
533 | ||
534 | Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com> | |
535 | ||
536 | * acconfig.h: New file. | |
537 | * configure.in: Reverted change of Apr 24; use sinclude again. | |
538 | ||
b1df34b9 TT |
539 | Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche> |
540 | ||
541 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
542 | * config.in: Ditto. | |
543 | ||
544 | Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com> | |
545 | ||
546 | * configure.in: Don't call sinclude. | |
547 | ||
ca61710b AC |
548 | Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com> |
549 | ||
550 | * mips.igen (do_store_left): Pass 0 not NULL to store_memory. | |
551 | ||
97f4d183 AC |
552 | Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com> |
553 | ||
554 | * mips.igen (ERET): Implement. | |
555 | ||
556 | * interp.c (decode_coproc): Return sign-extended EPC. | |
557 | ||
558 | * mips.igen (ANDI, LUI, MFC0): Add tracing code. | |
559 | ||
560 | * interp.c (signal_exception): Do not ignore Trap. | |
561 | (signal_exception): On TRAP, restart at exception address. | |
562 | (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define. | |
563 | (signal_exception): Update. | |
515125b7 AC |
564 | (sim_open): Patch V_COMMON interrupt vector with an abort sequence |
565 | so that TRAP instructions are caught. | |
97f4d183 | 566 | |
421cbaae AC |
567 | Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com> |
568 | ||
569 | * sim-main.h (struct hilo_access, struct hilo_history): Define, | |
570 | contains HI/LO access history. | |
571 | (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access. | |
572 | (HIACCESS, LOACCESS): Delete, replace with | |
573 | (HIHISTORY, LOHISTORY): New macros. | |
574 | (start-sanitize-r5900): | |
575 | (struct sim_5900_cpu): Make hi1access, lo1access of type | |
576 | hilo_access. | |
577 | (HI1ACCESS, LO1ACCESS): Delete, replace with | |
578 | (HI1HISTORY, LO1HISTORY): New macros. | |
579 | (end-sanitize-r5900): | |
580 | (CHECKHILO): Delete all, moved to mips.igen | |
581 | ||
582 | * gencode.c (build_instruction): Do not generate checks for | |
583 | correct HI/LO register usage. | |
584 | ||
585 | * interp.c (old_engine_run): Delete checks for correct HI/LO | |
586 | register usage. | |
587 | ||
588 | * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo, | |
589 | check_mf_cycles): New functions. | |
590 | (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div, | |
591 | do_divu, domultx, do_mult, do_multu): Use. | |
592 | ||
593 | * tx.igen ("madd", "maddu"): Use. | |
594 | (start-sanitize-r5900): | |
595 | ||
596 | r5900.igen: Update all HI/LO checks. | |
597 | ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl", | |
598 | "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO. | |
599 | ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw", | |
600 | "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw", | |
601 | "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"): | |
602 | Check HI/LO op. | |
603 | (end-sanitize-r5900): | |
604 | ||
605 | start-sanitize-sky | |
606 | Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com> | |
607 | ||
608 | * interp.c (decode_coproc): Correct CMFC2/QMTC2 | |
609 | GPR access. | |
610 | ||
611 | * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses | |
612 | instead of a single 128-bit access. | |
613 | ||
614 | end-sanitize-sky | |
fc4e5b84 | 615 | start-sanitize-sky |
f8998e77 FCE |
616 | Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com> |
617 | ||
618 | * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords. | |
619 | * interp.c (cop_[ls]q): Fixes corresponding to above. | |
620 | ||
621 | end-sanitize-sky | |
622 | start-sanitize-sky | |
fc4e5b84 FCE |
623 | Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com> |
624 | ||
625 | * interp.c (decode_coproc): Adapt COP2 micro interlock to | |
626 | clarified specs. Reset "M" bit; exit also on "E" bit. | |
627 | ||
628 | end-sanitize-sky | |
7d93d538 AC |
629 | start-sanitize-r5900 |
630 | Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
631 | ||
632 | * r5900.igen (CFC1, CTC1): Implement R5900 specific version. | |
633 | * mips.igen (CFC1, CTC1): R5900 des not use generic version. | |
634 | ||
635 | * r5900.igen (r59fp_unpack): New function. | |
636 | (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S, | |
637 | RSQRT.S, SQRT.S): Use. | |
638 | (r59fp_zero): New function. | |
639 | (r59fp_overflow): Generate r5900 specific overflow value. | |
640 | (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow | |
641 | to zero. | |
642 | (CVT.S.W, CVT.W.S): Exchange implementations. | |
643 | ||
644 | * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile. | |
645 | ||
646 | end-sanitize-r5900 | |
c58fa2cc AC |
647 | start-sanitize-tx19 |
648 | Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
649 | ||
650 | * configure.in (tx19, sim_use_gen): Switch to igen. | |
651 | * configure: Re-build. | |
652 | ||
653 | end-sanitize-tx19 | |
654 | start-sanitize-sky | |
46399a00 FCE |
655 | Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com> |
656 | ||
657 | * interp.c (decode_coproc): Make COP2 branch code compile after | |
658 | igen signature changes. | |
659 | ||
660 | end-sanitize-sky | |
74025eee AC |
661 | Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com> |
662 | ||
663 | * mips.igen (DSRAV): Use function do_dsrav. | |
664 | (SRAV): Use new function do_srav. | |
665 | ||
666 | * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX]. | |
667 | (B): Sign extend 11 bit immediate. | |
668 | (EXT-B*): Shift 16 bit immediate left by 1. | |
669 | (ADDIU*): Don't sign extend immediate value. | |
670 | ||
f3bdd368 AC |
671 | Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com> |
672 | ||
673 | * m16run.c (sim_engine_run): Restore CIA after handling an event. | |
674 | ||
675 | start-sanitize-tx19 | |
676 | * mips.igen (mtc0): Valid tx19 instruction. | |
677 | ||
678 | end-sanitize-tx19 | |
679 | * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use | |
680 | functions. | |
681 | ||
682 | * mips.igen (delayslot32, nullify_next_insn): New functions. | |
683 | (m16.igen): Always include. | |
684 | (do_*): Add more tracing. | |
685 | ||
686 | * m16.igen (delayslot16): Add NIA argument, could be called by a | |
687 | 32 bit MIPS16 instruction. | |
688 | ||
689 | * interp.c (ifetch16): Move function from here. | |
690 | * sim-main.c (ifetch16): To here. | |
691 | ||
692 | * sim-main.c (ifetch16, ifetch32): Update to match current | |
693 | implementations of LH, LW. | |
694 | (signal_exception): Don't print out incorrect hex value of illegal | |
695 | instruction. | |
696 | ||
c0a4c3ba AC |
697 | Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com> |
698 | ||
699 | * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an | |
700 | instruction. | |
701 | ||
702 | * m16.igen: Implement MIPS16 instructions. | |
703 | ||
704 | * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu, | |
705 | do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav, | |
706 | do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or, | |
707 | do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra, | |
708 | do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move | |
709 | bodies of corresponding code from 32 bit insn to these. Also used | |
710 | by MIPS16 versions of functions. | |
711 | ||
712 | * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define. | |
713 | (IMEM16): Drop NR argument from macro. | |
714 | ||
96a4eb30 | 715 | start-sanitize-sky |
c0a4c3ba | 716 | Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com> |
96a4eb30 FCE |
717 | |
718 | * interp.c (decode_coproc): Add proper 1000000 bit-string at top | |
719 | of VU lower instruction. | |
720 | ||
721 | end-sanitize-sky | |
b0b39eb2 FCE |
722 | start-sanitize-sky |
723 | Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com> | |
724 | ||
725 | * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses | |
726 | instead of QUADWORD. | |
727 | ||
728 | * sim-main.h: Removed attempt at allowing 128-bit access. | |
729 | ||
730 | end-sanitize-sky | |
11c47f31 | 731 | start-sanitize-sky |
c0a4c3ba | 732 | Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com> |
11c47f31 FCE |
733 | |
734 | * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o. | |
735 | ||
736 | * interp.c (decode_coproc): Refer to VU CIA as a "special" | |
737 | register, not as a "misc" register. Aha. Add activity | |
738 | assertions after VCALLMS* instructions. | |
739 | ||
740 | end-sanitize-sky | |
174ff224 | 741 | start-sanitize-sky |
c0a4c3ba | 742 | Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com> |
174ff224 FCE |
743 | |
744 | * interp.c (decode_coproc): Do not apply superfluous E (end) flag | |
745 | to upper code of generated VU instruction. | |
746 | ||
747 | end-sanitize-sky | |
2ebb2a68 FCE |
748 | start-sanitize-sky |
749 | Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com> | |
750 | ||
751 | * interp.c (cop_[ls]q): Replaced stub with proper COP2 code. | |
752 | ||
753 | * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses | |
754 | for TARGET_SKY. | |
755 | ||
756 | * r5900.igen (SQC2): Thinko. | |
757 | ||
758 | end-sanitize-sky | |
ebcfd86a FCE |
759 | start-sanitize-sky |
760 | Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> | |
761 | ||
762 | * interp.c (*): Adapt code to merged VU device & state structs. | |
763 | (decode_coproc): Execute COP2 each macroinstruction without | |
764 | pipelining, by stepping VU to completion state. Adapted to | |
765 | read_vu_*_reg style of register access. | |
766 | ||
767 | * mips.igen ([SL]QC2): Removed these COP2 instructions. | |
768 | ||
769 | * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. | |
770 | ||
771 | * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. | |
772 | ||
773 | end-sanitize-sky | |
64ed8b6a AC |
774 | Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com> |
775 | ||
776 | * Makefile.in (SIM_OBJS): Add sim-main.o. | |
777 | ||
778 | * sim-main.h (address_translation, load_memory, store_memory, | |
779 | cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark | |
780 | as INLINE_SIM_MAIN. | |
781 | (pr_addr, pr_uword64): Declare. | |
782 | (sim-main.c): Include when H_REVEALS_MODULE_P. | |
783 | ||
784 | * interp.c (address_translation, load_memory, store_memory, | |
785 | cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move | |
786 | from here. | |
787 | * sim-main.c: To here. Fix compilation problems. | |
788 | ||
789 | * configure.in: Enable inlining. | |
790 | * configure: Re-config. | |
791 | ||
278bda40 AC |
792 | Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com> |
793 | ||
794 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
795 | ||
796 | Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
797 | ||
798 | * mips.igen: Include tx.igen. | |
799 | * Makefile.in (IGEN_INCLUDE): Add tx.igen. | |
800 | * tx.igen: New file, contains MADD and MADDU. | |
801 | ||
802 | * interp.c (load_memory): When shifting bytes, use LOADDRMASK not | |
803 | the hardwired constant `7'. | |
804 | (store_memory): Ditto. | |
805 | (LOADDRMASK): Move definition to sim-main.h. | |
806 | ||
807 | mips.igen (MTC0): Enable for r3900. | |
808 | (ADDU): Add trace. | |
809 | ||
810 | mips.igen (do_load_byte): Delete. | |
811 | (do_load, do_store, do_load_left, do_load_write, do_store_left, | |
812 | do_store_right): New functions. | |
813 | (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use. | |
814 | ||
815 | configure.in: Let the tx39 use igen again. | |
816 | configure: Update. | |
817 | ||
725fc5d9 AC |
818 | Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com> |
819 | ||
820 | * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity, | |
821 | not an address sized quantity. Return zero for cache sizes. | |
822 | ||
823 | Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
824 | ||
825 | * mips.igen (r3900): r3900 does not support 64 bit integer | |
826 | operations. | |
827 | ||
6b0c51c9 FCE |
828 | start-sanitize-sky |
829 | Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com> | |
830 | ||
831 | * mips.igen (SQC2/LQC2): Make bodies sky-target-only also. | |
6b0c51c9 | 832 | |
725fc5d9 | 833 | end-sanitize-sky |
6ed00b06 FCE |
834 | start-sanitize-sky |
835 | Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> | |
836 | ||
837 | * interp.c (decode_coproc): Continuing COP2 work. | |
6b0c51c9 | 838 | (cop_[ls]q): Make sky-target-only. |
6ed00b06 | 839 | |
6b0c51c9 | 840 | * sim-main.h (COP_[LS]Q): Make sky-target-only. |
6ed00b06 | 841 | end-sanitize-sky |
34f51d87 GRK |
842 | Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com> |
843 | ||
844 | * configure.in (mipstx39*-*-*): Use gencode simulator rather | |
845 | than igen one. | |
846 | * configure : Rebuild. | |
847 | ||
7dd4a466 FCE |
848 | start-sanitize-sky |
849 | Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com> | |
850 | ||
851 | * interp.c (decode_coproc): Added a missing TARGET_SKY check | |
852 | around COP2 implementation skeleton. | |
853 | ||
854 | end-sanitize-sky | |
7dba069e | 855 | start-sanitize-sky |
15232df4 FCE |
856 | Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> |
857 | ||
15232df4 FCE |
858 | * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. |
859 | ||
860 | * interp.c (sim_{load,store}_register): Use new vu[01]_device | |
861 | static to access VU registers. | |
862 | (decode_coproc): Added skeleton of sky COP2 (VU) instruction | |
863 | decoding. Work in progress. | |
864 | ||
865 | * mips.igen (LDCzz, SDCzz): Removed *5900 case for this | |
866 | overlapping/redundant bit pattern. | |
867 | (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in | |
868 | progress. | |
869 | ||
870 | * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for | |
871 | status register. | |
872 | ||
15232df4 FCE |
873 | * interp.c (cop_lq, cop_sq): New functions for future 128-bit |
874 | access to coprocessor registers. | |
875 | ||
876 | * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. | |
6ed00b06 | 877 | end-sanitize-sky |
d8f53049 AC |
878 | Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com> |
879 | ||
880 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
881 | ||
82ea14fd AC |
882 | Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com> |
883 | ||
884 | * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS. | |
885 | ||
886 | Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com> | |
887 | ||
888 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
889 | * config.in: Regenerated to track ../common/aclocal.m4 changes. | |
890 | ||
d89fa2d8 AC |
891 | Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com> |
892 | ||
893 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
894 | ||
612a649e AC |
895 | Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com> |
896 | ||
897 | * interp.c (Max, Min): Comment out functions. Not yet used. | |
898 | ||
899 | start-sanitize-vr4320 | |
900 | Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
901 | ||
902 | * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format. | |
903 | ||
904 | end-sanitize-vr4320 | |
905 | Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
906 | ||
907 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
908 | ||
9b23b76d FCE |
909 | Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com> |
910 | ||
911 | * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added | |
912 | configurable settings for stand-alone simulator. | |
913 | ||
914 | start-sanitize-sky | |
915 | * configure.in: Added --with-sim-gpu2 option to specify path of | |
916 | sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and | |
917 | links/compiles stand-alone simulator with this library. | |
918 | ||
919 | * interp.c (MEM_SIZE): Increased default sky memory size to 16MB. | |
920 | end-sanitize-sky | |
9b23b76d FCE |
921 | * configure.in: Added X11 search, just in case. |
922 | ||
923 | * configure: Regenerated. | |
924 | ||
925 | Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
926 | ||
927 | * interp.c (sim_write, sim_read, load_memory, store_memory): | |
928 | Replace sim_core_*_map with read_map, write_map, exec_map resp. | |
929 | ||
5fa71251 GRK |
930 | start-sanitize-vr4320 |
931 | Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com> | |
932 | ||
933 | * vr4320.igen (clz,dclz) : Added. | |
934 | (dmac): Replaced 99, with LO. | |
935 | ||
936 | end-sanitize-vr4320 | |
78b871ec | 937 | start-sanitize-cygnus |
6ba4c153 AC |
938 | Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com> |
939 | ||
940 | * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields. | |
941 | ||
78b871ec | 942 | end-sanitize-cygnus |
dd15abd5 GRK |
943 | start-sanitize-vr4320 |
944 | Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com> | |
945 | ||
946 | * vr4320.igen: New file. | |
947 | * Makefile.in (vr4320.igen) : Added. | |
948 | * configure.in (mips64vr4320-*-*): Added. | |
949 | * configure : Rebuilt. | |
950 | * mips.igen : Correct the bfd-names in the mips-ISA model entries. | |
951 | Add the vr4320 model entry and mark the vr4320 insn as necessary. | |
952 | ||
953 | end-sanitize-vr4320 | |
ca6f76d1 AC |
954 | Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com> |
955 | ||
956 | * sim-main.h (GETFCC): Return an unsigned value. | |
957 | ||
958 | start-sanitize-r5900 | |
959 | * r5900.igen: Use an unsigned array index variable `i'. | |
960 | (QFSRV): Ditto for variable bytes. | |
961 | ||
962 | end-sanitize-r5900 | |
963 | Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
964 | ||
965 | * mips.igen (DIV): Fix check for -1 / MIN_INT. | |
966 | (DADD): Result destination is RD not RT. | |
967 | ||
968 | start-sanitize-r5900 | |
969 | * r5900.igen (DIV1): Fix check for -1 / MIN_INT. | |
970 | (DIVU1): Don't check for MIN_INT / -1 as performing unsigned | |
971 | divide. | |
972 | ||
973 | end-sanitize-r5900 | |
0e701ac3 AC |
974 | Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com> |
975 | ||
976 | * sim-main.h (HIACCESS, LOACCESS): Always define. | |
977 | ||
978 | * mdmx.igen (Maxi, Mini): Rename Max, Min. | |
979 | ||
980 | * interp.c (sim_info): Delete. | |
981 | ||
7c5d88c1 DE |
982 | Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com> |
983 | ||
984 | * interp.c (DECLARE_OPTION_HANDLER): Use it. | |
985 | (mips_option_handler): New argument `cpu'. | |
986 | (sim_open): Update call to sim_add_option_table. | |
987 | ||
f89c0689 AC |
988 | Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com> |
989 | ||
990 | * mips.igen (CxC1): Add tracing. | |
991 | ||
992 | start-sanitize-r5900 | |
993 | Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
994 | ||
995 | * r5900.igen (StoreFP): Delete. | |
996 | (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3): | |
997 | New functions. | |
998 | (rsqrt.s, sqrt.s): Implement. | |
999 | (r59cond): New function. | |
1000 | (C.COND.S): Call r59cond in assembler line. | |
1001 | (cvt.w.s, cvt.s.w): Implement. | |
1002 | ||
1003 | * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900 | |
1004 | instruction set. | |
1005 | ||
1006 | * sim-main.h: Define an enum of r5900 FCSR bit fields. | |
1007 | ||
1008 | end-sanitize-r5900 | |
a48e8c8d | 1009 | start-sanitize-r5900 |
d3e1d594 AC |
1010 | Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1011 | ||
1012 | * r5900.igen: Add tracing to all p* instructions. | |
1013 | ||
a48e8c8d AC |
1014 | Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1015 | ||
1016 | * interp.c (sim_store_register, sim_fetch_register): Pull swifty | |
1017 | to get gdb talking to re-aranged sim_cpu register structure. | |
1018 | ||
1019 | end-sanitize-r5900 | |
1020 | Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1021 | ||
1022 | * sim-main.h (Max, Min): Declare. | |
1023 | ||
1024 | * interp.c (Max, Min): New functions. | |
1025 | ||
1026 | * mips.igen (BC1): Add tracing. | |
1027 | ||
78b871ec | 1028 | start-sanitize-cygnus |
a48e8c8d AC |
1029 | Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1030 | ||
1031 | * mdmx.igen: Tag all functions as requiring either with mdmx or | |
1032 | vr5400 processor. | |
1033 | ||
78b871ec | 1034 | end-sanitize-cygnus |
a48e8c8d AC |
1035 | start-sanitize-r5900 |
1036 | Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1037 | ||
1038 | * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size | |
1039 | to 32. | |
1040 | (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32. | |
1041 | ||
1042 | * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set. | |
1043 | ||
1044 | * r5900.igen: Rewrite. | |
1045 | ||
1046 | * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu | |
1047 | struct. | |
1048 | (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD): | |
1049 | Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1 | |
1050 | ||
1051 | end-sanitize-r5900 | |
1052 | Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com> | |
1053 | ||
1054 | * interp.c Added memory map for stack in vr4100 | |
1055 | ||
f319bab2 GRK |
1056 | Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com> |
1057 | ||
1058 | * interp.c (load_memory): Add missing "break"'s. | |
1059 | ||
1060 | Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1061 | ||
1062 | * interp.c (sim_store_register, sim_fetch_register): Pass in | |
1063 | length parameter. Return -1. | |
1064 | ||
1065 | Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com> | |
1066 | ||
1067 | * interp.c: Added hardware init hook, fixed warnings. | |
1068 | ||
452b3808 AC |
1069 | Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1070 | ||
1071 | * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL. | |
1072 | ||
37379a25 AC |
1073 | Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1074 | ||
1075 | * interp.c (ifetch16): New function. | |
1076 | ||
1077 | * sim-main.h (IMEM32): Rename IMEM. | |
1078 | (IMEM16_IMMED): Define. | |
1079 | (IMEM16): Define. | |
1080 | (DELAY_SLOT): Update. | |
1081 | ||
1082 | * m16run.c (sim_engine_run): New file. | |
1083 | ||
1084 | * m16.igen: All instructions except LB. | |
1085 | (LB): Call do_load_byte. | |
1086 | * mips.igen (do_load_byte): New function. | |
1087 | (LB): Call do_load_byte. | |
1088 | ||
1089 | * mips.igen: Move spec for insn bit size and high bit from here. | |
1090 | * Makefile.in (tmp-igen, tmp-m16): To here. | |
1091 | ||
1092 | * m16.dc: New file, decode mips16 instructions. | |
1093 | ||
1094 | * Makefile.in (SIM_NO_ALL): Define. | |
1095 | (tmp-m16): Generate both 16 bit and 32 bit simulator engines. | |
1096 | ||
1097 | start-sanitize-tx19 | |
1098 | * m16.igen: Mark all mips16 insns as being part of the tx19 insn | |
1099 | set. | |
1100 | ||
1101 | end-sanitize-tx19 | |
1102 | Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1103 | ||
1104 | * configure.in (mips_fpu_bitsize): For tx39, restrict floating | |
1105 | point unit to 32 bit registers. | |
1106 | * configure: Re-generate. | |
1107 | ||
1108 | Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1109 | ||
1110 | * configure.in (sim_use_gen): Make IGEN the default simulator | |
1111 | generator for generic 32 and 64 bit mips targets. | |
1112 | * configure: Re-generate. | |
1113 | ||
a97f304b AC |
1114 | Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1115 | ||
1116 | * sim-main.h (SizeFGR): Determine from floating-point and not gpr | |
1117 | bitsize. | |
1118 | ||
1119 | * interp.c (sim_fetch_register, sim_store_register): Read/write | |
1120 | FGR from correct location. | |
1121 | (sim_open): Set size of FGR's according to | |
1122 | WITH_TARGET_FLOATING_POINT_BITSIZE. | |
1123 | ||
1124 | * sim-main.h (FGR): Store floating point registers in a separate | |
1125 | array. | |
1126 | ||
1127 | Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1128 | ||
1129 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1130 | ||
78b871ec | 1131 | start-sanitize-cygnus |
a97f304b AC |
1132 | * mdmx.igen: Mark all instructions as 64bit/fp specific. |
1133 | ||
78b871ec | 1134 | end-sanitize-cygnus |
2acd126a AC |
1135 | Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1136 | ||
1137 | * interp.c (ColdReset): Call PENDING_INVALIDATE. | |
1138 | ||
1139 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK. | |
1140 | ||
1141 | * interp.c (pending_tick): New function. Deliver pending writes. | |
1142 | ||
1143 | * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED, | |
1144 | PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that | |
1145 | it can handle mixed sized quantites and single bits. | |
1146 | ||
192ae475 AC |
1147 | Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1148 | ||
1149 | * interp.c (oengine.h): Do not include when building with IGEN. | |
1150 | (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE. | |
1151 | (sim_info): Ditto for PROCESSOR_64BIT. | |
1152 | (sim_monitor): Replace ut_reg with unsigned_word. | |
1153 | (*): Ditto for t_reg. | |
1154 | (LOADDRMASK): Define. | |
1155 | (sim_open): Remove defunct check that host FP is IEEE compliant, | |
1156 | using software to emulate floating point. | |
1157 | (value_fpr, ...): Always compile, was conditional on HASFPU. | |
1158 | ||
01737f42 AC |
1159 | Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1160 | ||
1161 | * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in | |
1162 | size. | |
1163 | ||
1164 | * interp.c (SD, CPU): Define. | |
1165 | (mips_option_handler): Set flags in each CPU. | |
1166 | (interrupt_event): Assume CPU 0 is the one being iterrupted. | |
1167 | (sim_close): Do not clear STATE, deleted anyway. | |
1168 | (sim_write, sim_read): Assume CPU zero's vm should be used for | |
1169 | data transfers. | |
1170 | (sim_create_inferior): Set the PC for all processors. | |
1171 | (sim_monitor, store_word, load_word, mips16_entry): Add cpu | |
1172 | argument. | |
1173 | (mips16_entry): Pass correct nr of args to store_word, load_word. | |
1174 | (ColdReset): Cold reset all cpu's. | |
1175 | (signal_exception): Pass cpu to sim_monitor & mips16_entry. | |
1176 | (sim_monitor, load_memory, store_memory, signal_exception): Use | |
1177 | `CPU' instead of STATE_CPU. | |
1178 | ||
1179 | ||
1180 | * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with | |
1181 | SD or CPU_. | |
1182 | ||
1183 | * sim-main.h (signal_exception): Add sim_cpu arg. | |
1184 | (SignalException*): Pass both SD and CPU to signal_exception. | |
1185 | * interp.c (signal_exception): Update. | |
1186 | ||
1187 | * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c: | |
1188 | Ditto | |
1189 | (sync_operation, prefetch, cache_op, store_memory, load_memory, | |
1190 | address_translation): Ditto | |
1191 | (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto. | |
1192 | ||
78b871ec | 1193 | start-sanitize-cygnus |
01737f42 AC |
1194 | * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of |
1195 | `sd'. | |
1196 | (ByteAlign): Use StoreFPR, pass args in correct order. | |
1197 | ||
78b871ec | 1198 | end-sanitize-cygnus |
01737f42 AC |
1199 | start-sanitize-r5900 |
1200 | Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
1201 | ||
1202 | * configure.in (sim_igen_filter): For r5900, configure as SMP. | |
1203 | ||
1204 | end-sanitize-r5900 | |
412c4e94 AC |
1205 | Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1206 | ||
1207 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1208 | ||
9ec6741b AC |
1209 | Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1210 | ||
c4db5b04 AC |
1211 | start-sanitize-r5900 |
1212 | * configure.in (sim_igen_filter): For r5900, use igen. | |
1213 | * configure: Re-generate. | |
1214 | ||
1215 | end-sanitize-r5900 | |
9ec6741b AC |
1216 | * interp.c (sim_engine_run): Add `nr_cpus' argument. |
1217 | ||
1218 | * mips.igen (model): Map processor names onto BFD name. | |
1219 | ||
1220 | * sim-main.h (CPU_CIA): Delete. | |
1221 | (SET_CIA, GET_CIA): Define | |
1222 | ||
2d44e12a AC |
1223 | Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com> |
1224 | ||
1225 | * sim-main.h (GPR_SET): Define, used by igen when zeroing a | |
1226 | regiser. | |
1227 | ||
1228 | * configure.in (default_endian): Configure a big-endian simulator | |
1229 | by default. | |
1230 | * configure: Re-generate. | |
1231 | ||
462cfbc4 DE |
1232 | Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba> |
1233 | ||
1234 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1235 | ||
e0e0fc76 MA |
1236 | Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com> |
1237 | ||
1238 | * interp.c (sim_monitor): Handle Densan monitor outbyte | |
1239 | and inbyte functions. | |
1240 | ||
76ef4165 FL |
1241 | 1997-12-29 Felix Lee <flee@cygnus.com> |
1242 | ||
1243 | * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c). | |
1244 | ||
1245 | Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com) | |
1246 | ||
1247 | * Makefile.in (tmp-igen): Arrange for $zero to always be | |
1248 | reset to zero after every instruction. | |
1249 | ||
9c8ec16d AC |
1250 | Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1251 | ||
1252 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1253 | * config.in: Ditto. | |
1254 | ||
78b871ec | 1255 | start-sanitize-cygnus |
b17d2d14 AC |
1256 | Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1257 | ||
1258 | * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32 | |
1259 | bit values. | |
1260 | ||
255cbbf1 JL |
1261 | Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com) |
1262 | ||
1263 | * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or | |
1264 | vr5400 with the vr5000 as the default. | |
1265 | ||
78b871ec | 1266 | end-sanitize-cygnus |
23850e92 JL |
1267 | Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com) |
1268 | ||
1269 | * mips.igen (MSUB): Fix to work like MADD. | |
1270 | * gencode.c (MSUB): Similarly. | |
1271 | ||
78b871ec | 1272 | start-sanitize-cygnus |
c02ed6a8 AC |
1273 | Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1274 | ||
1275 | * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or | |
1276 | vr5400. | |
1277 | ||
78b871ec | 1278 | end-sanitize-cygnus |
6e51f990 DE |
1279 | Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com> |
1280 | ||
1281 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1282 | ||
35c246c9 AC |
1283 | Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1284 | ||
1285 | * mips.igen (LWC1): Correct assembler - lwc1 not swc1. | |
1286 | ||
78b871ec | 1287 | start-sanitize-cygnus |
0d5d0d10 | 1288 | * mdmx.igen (value_vr): Correct sim_io_eprintf format argument. |
0931ce5a | 1289 | (value_cc, store_cc): Implement. |
0d5d0d10 | 1290 | |
35c246c9 AC |
1291 | * sim-main.h: Add 8*3*8 bit accumulator. |
1292 | ||
1293 | * vr5400.igen: Move mdmx instructins from here | |
1294 | * mdmx.igen: To here - new file. Add/fix missing instructions. | |
1295 | * mips.igen: Include mdmx.igen. | |
0931ce5a | 1296 | * Makefile.in (IGEN_INCLUDE): Add mdmx.igen. |
35c246c9 | 1297 | |
78b871ec | 1298 | end-sanitize-cygnus |
58fb5d0a AC |
1299 | Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1300 | ||
1301 | * sim-main.h (sim-fpu.h): Include. | |
1302 | ||
1303 | * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub, | |
1304 | Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite | |
1305 | using host independant sim_fpu module. | |
1306 | ||
a09a30d2 AC |
1307 | Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1308 | ||
232156de AC |
1309 | * interp.c (signal_exception): Report internal errors with SIGABRT |
1310 | not SIGQUIT. | |
a09a30d2 | 1311 | |
232156de AC |
1312 | * sim-main.h (C0_CONFIG): New register. |
1313 | (signal.h): No longer include. | |
1314 | ||
1315 | * interp.c (decode_coproc): Allow access C0_CONFIG to register. | |
a09a30d2 | 1316 | |
486740ce DE |
1317 | Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com> |
1318 | ||
1319 | * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). | |
1320 | ||
f23e93da AC |
1321 | Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1322 | ||
1323 | * mips.igen: Tag vr5000 instructions. | |
1324 | (ANDI): Was missing mipsIV model, fix assembler syntax. | |
1325 | (do_c_cond_fmt): New function. | |
1326 | (C.cond.fmt): Handle mips I-III which do not support CC field | |
1327 | separatly. | |
1328 | (bc1): Handle mips IV which do not have a delaed FCC separatly. | |
1329 | (SDR): Mask paddr when BigEndianMem, not the converse as specified | |
1330 | in IV3.2 spec. | |
1331 | (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle | |
1332 | vr5000 which saves LO in a GPR separatly. | |
1333 | ||
1334 | * configure.in (enable-sim-igen): For vr5000, select vr5000 | |
1335 | specific instructions. | |
1336 | * configure: Re-generate. | |
1337 | ||
1338 | Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1339 | ||
1340 | * Makefile.in (SIM_OBJS): Add sim-fpu module. | |
1341 | ||
1342 | * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and | |
1343 | fmt_uninterpreted_64 bit cases to switch. Convert to | |
1344 | fmt_formatted, | |
1345 | ||
1346 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define, | |
1347 | ||
1348 | * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse | |
1349 | as specified in IV3.2 spec. | |
1350 | (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR. | |
1351 | ||
030843d7 AC |
1352 | Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1353 | ||
1354 | * mips.igen: Delay slot branches add OFFSET to NIA not CIA. | |
1355 | (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement. | |
1356 | (start-sanitize-r5900): | |
1357 | (LWXC1, SWXC1): Delete from r5900 instruction set. | |
1358 | (end-sanitize-r5900): | |
1359 | (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non | |
a94c5493 | 1360 | PENDING_FILL versions of instructions. Simplify. |
030843d7 AC |
1361 | (X): New function. |
1362 | (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of | |
1363 | instructions. | |
a94c5493 AC |
1364 | (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to |
1365 | a signed value. | |
030843d7 AC |
1366 | (MTHI, MFHI): Disable code checking HI-LO. |
1367 | ||
1368 | * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh | |
1369 | global. | |
1370 | (NULLIFY_NEXT_INSTRUCTION): Call dotrace. | |
1371 | ||
7ce8b917 AC |
1372 | Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1373 | ||
95469ceb AC |
1374 | * gencode.c (build_mips16_operands): Replace IPC with cia. |
1375 | ||
1376 | * interp.c (sim_monitor, signal_exception, cache_op, store_fpr, | |
1377 | value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace | |
1378 | IPC to `cia'. | |
1379 | (UndefinedResult): Replace function with macro/function | |
1380 | combination. | |
1381 | (sim_engine_run): Don't save PC in IPC. | |
1382 | ||
1383 | * sim-main.h (IPC): Delete. | |
1384 | ||
78b871ec | 1385 | start-sanitize-cygnus |
95469ceb AC |
1386 | * vr5400.igen (vr): Add missing cia argument to value_fpr. |
1387 | (do_select): Rename function select. | |
78b871ec | 1388 | end-sanitize-cygnus |
95469ceb | 1389 | |
7ce8b917 AC |
1390 | * interp.c (signal_exception, store_word, load_word, |
1391 | address_translation, load_memory, store_memory, cache_op, | |
1392 | prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert, | |
95469ceb AC |
1393 | cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add |
1394 | current instruction address - cia - argument. | |
7ce8b917 AC |
1395 | (sim_read, sim_write): Call address_translation directly. |
1396 | (sim_engine_run): Rename variable vaddr to cia. | |
95469ceb AC |
1397 | (signal_exception): Pass cia to sim_monitor |
1398 | ||
7ce8b917 AC |
1399 | * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp, |
1400 | Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW, | |
1401 | COP_LD, COP_SW, COP_SD, DecodeCoproc): Update. | |
1402 | ||
1403 | * sim-main.h (SignalExceptionSimulatorFault): Delete definition. | |
1404 | * interp.c (sim_open): Replace SignalExceptionSimulatorFault with | |
1405 | SIM_ASSERT. | |
1406 | ||
1407 | * interp.c (signal_exception): Pass restart address to | |
1408 | sim_engine_restart. | |
1409 | ||
1410 | * Makefile.in (semantics.o, engine.o, support.o, itable.o, | |
1411 | idecode.o): Add dependency. | |
1412 | ||
1413 | * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK): | |
1414 | Delete definitions | |
1415 | (DELAY_SLOT): Update NIA not PC with branch address. | |
1416 | (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next. | |
1417 | ||
1418 | * mips.igen: Use CIA not PC in branch calculations. | |
1419 | (illegal): Call SignalException. | |
1420 | (BEQ, ADDIU): Fix assembler. | |
1421 | ||
63be8feb AC |
1422 | Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1423 | ||
44b8585a AC |
1424 | * m16.igen (JALX): Was missing. |
1425 | ||
1426 | * configure.in (enable-sim-igen): New configuration option. | |
1427 | * configure: Re-generate. | |
1428 | ||
63be8feb AC |
1429 | * sim-main.h (MAX_INSNS, INSN_NAME): Define. |
1430 | ||
1431 | * interp.c (load_memory, store_memory): Delete parameter RAW. | |
1432 | (sim_read, sim_write): Use sim_core_{read,write}_buffer directly | |
1433 | bypassing {load,store}_memory. | |
1434 | ||
1435 | * sim-main.h (ByteSwapMem): Delete definition. | |
1436 | ||
1437 | * Makefile.in (SIM_OBJS): Add sim-memopt module. | |
1438 | ||
1439 | * interp.c (sim_do_command, sim_commands): Delete mips specific | |
1440 | commands. Handled by module sim-options. | |
1441 | ||
1442 | * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module. | |
1443 | (WITH_MODULO_MEMORY): Define. | |
1444 | ||
1445 | * interp.c (sim_info): Delete code printing memory size. | |
1446 | ||
1447 | * interp.c (mips_size): Nee sim_size, delete function. | |
1448 | (power2): Delete. | |
1449 | (monitor, monitor_base, monitor_size): Delete global variables. | |
1450 | (sim_open, sim_close): Delete code creating monitor and other | |
1451 | memory regions. Use sim-memopts module, via sim_do_commandf, to | |
1452 | manage memory regions. | |
1453 | (load_memory, store_memory): Use sim-core for memory model. | |
1454 | ||
1455 | * interp.c (address_translation): Delete all memory map code | |
1456 | except line forcing 32 bit addresses. | |
1457 | ||
22de994d AC |
1458 | Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1459 | ||
1460 | * sim-main.h (WITH_TRACE): Delete definition. Enables common | |
1461 | trace options. | |
1462 | ||
1463 | * interp.c (logfh, logfile): Delete globals. | |
1464 | (sim_open, sim_close): Delete code opening & closing log file. | |
1465 | (mips_option_handler): Delete -l and -n options. | |
1466 | (OPTION mips_options): Ditto. | |
1467 | ||
1468 | * interp.c (OPTION mips_options): Rename option trace to dinero. | |
1469 | (mips_option_handler): Update. | |
1470 | ||
525d929e AC |
1471 | Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1472 | ||
1473 | * interp.c (fetch_str): New function. | |
1474 | (sim_monitor): Rewrite using sim_read & sim_write. | |
1475 | (sim_open): Check magic number. | |
1476 | (sim_open): Write monitor vectors into memory using sim_write. | |
1477 | (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define. | |
1478 | (sim_read, sim_write): Simplify - transfer data one byte at a | |
1479 | time. | |
1480 | (load_memory, store_memory): Clarify meaning of parameter RAW. | |
1481 | ||
1482 | * sim-main.h (isHOST): Defete definition. | |
1483 | (isTARGET): Mark as depreciated. | |
1484 | (address_translation): Delete parameter HOST. | |
1485 | ||
1486 | * interp.c (address_translation): Delete parameter HOST. | |
1487 | ||
6205f379 GRK |
1488 | start-sanitize-tx49 |
1489 | Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com> | |
1490 | ||
1491 | * gencode.c: Add tx49 configury and insns. | |
1492 | * configure.in: Add tx49 configury. | |
1493 | * configure: Update. | |
1494 | ||
1495 | end-sanitize-tx49 | |
01b9cd49 AC |
1496 | Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1497 | ||
1498 | * mips.igen: | |
1499 | ||
1500 | * Makefile.in (IGEN_INCLUDE): Files included by mips.igen. | |
1501 | (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE. | |
1502 | ||
89d09738 AC |
1503 | Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1504 | ||
1505 | * mips.igen: Add model filter field to records. | |
1506 | ||
16bd5d6e AC |
1507 | Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1508 | ||
1509 | * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0. | |
1510 | ||
1511 | interp.c (sim_engine_run): Do not compile function sim_engine_run | |
1512 | when WITH_IGEN == 1. | |
1513 | ||
1514 | * configure.in (sim_igen_flags, sim_m16_flags): Set according to | |
1515 | target architecture. | |
1516 | ||
1517 | Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to | |
1518 | igen. Replace with configuration variables sim_igen_flags / | |
1519 | sim_m16_flags. | |
1520 | ||
16bd5d6e | 1521 | start-sanitize-r5900 |
8c31916d AC |
1522 | * r5900.igen: New file. Copy r5900 insns here. |
1523 | end-sanitize-r5900 | |
78b871ec | 1524 | start-sanitize-cygnus |
58fb5d0a | 1525 | * vr5400.igen: New file. |
78b871ec | 1526 | end-sanitize-cygnus |
16bd5d6e AC |
1527 | * m16.igen: New file. Copy mips16 insns here. |
1528 | * mips.igen: From here. | |
1529 | ||
90ad43b2 AC |
1530 | Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1531 | ||
78b871ec | 1532 | start-sanitize-cygnus |
90ad43b2 AC |
1533 | * mips.igen: Tag all mipsIV instructions with vr5400 model. |
1534 | ||
1535 | * configure.in: Add mips64vr5400 target. | |
1536 | * configure: Re-generate. | |
1537 | ||
78b871ec | 1538 | end-sanitize-cygnus |
90ad43b2 AC |
1539 | * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ |
1540 | to top. | |
1541 | (tmp-igen, tmp-m16): Pass -I srcdir to igen. | |
1542 | ||
635ae9cb GRK |
1543 | Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com> |
1544 | ||
1545 | * gencode.c (build_instruction): Follow sim_write's lead in using | |
1546 | BigEndianMem instead of !ByteSwapMem. | |
1547 | ||
122edc03 AC |
1548 | Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1549 | ||
1550 | * configure.in (sim_gen): Dependent on target, select type of | |
1551 | generator. Always select old style generator. | |
1552 | ||
1553 | configure: Re-generate. | |
1554 | ||
1555 | Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New | |
1556 | targets. | |
1557 | (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16, | |
1558 | SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN, | |
1559 | IGEN_TRACE, IGEN_INSN, IGEN_DC): Define | |
1560 | (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member | |
1561 | SIM_@sim_gen@_*, set by autoconf. | |
1562 | ||
dad6f1f3 AC |
1563 | Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1564 | ||
1565 | * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define. | |
1566 | ||
1567 | * interp.c (ColdReset): Remove #ifdef HASFPU, check | |
1568 | CURRENT_FLOATING_POINT instead. | |
1569 | ||
1570 | * interp.c (ifetch32): New function. Fetch 32 bit instruction. | |
1571 | (address_translation): Raise exception InstructionFetch when | |
1572 | translation fails and isINSTRUCTION. | |
1573 | ||
1574 | * interp.c (sim_open, sim_write, sim_monitor, store_word, | |
1575 | sim_engine_run): Change type of of vaddr and paddr to | |
1576 | address_word. | |
1577 | (address_translation, prefetch, load_memory, store_memory, | |
1578 | cache_op): Change type of vAddr and pAddr to address_word. | |
1579 | ||
1580 | * gencode.c (build_instruction): Change type of vaddr and paddr to | |
1581 | address_word. | |
1582 | ||
92ad193b AC |
1583 | Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1584 | ||
1585 | * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT | |
1586 | macro to obtain result of ALU op. | |
1587 | ||
aa324b9b AC |
1588 | Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1589 | ||
1590 | * interp.c (sim_info): Call profile_print. | |
1591 | ||
e2f8ffb7 AC |
1592 | Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1593 | ||
1594 | * Makefile.in (SIM_OBJS): Add sim-profile.o module. | |
1595 | ||
1596 | * sim-main.h (WITH_PROFILE): Do not define, defined in | |
1597 | common/sim-config.h. Use sim-profile module. | |
1598 | (simPROFILE): Delete defintion. | |
1599 | ||
1600 | * interp.c (PROFILE): Delete definition. | |
1601 | (mips_option_handler): Delete 'p', 'y' and 'x' profile options. | |
1602 | (sim_close): Delete code writing profile histogram. | |
1603 | (mips_set_profile, mips_set_profile_size, writeout16, writeout32): | |
1604 | Delete. | |
1605 | (sim_engine_run): Delete code profiling the PC. | |
1606 | ||
fb5a2a3e AC |
1607 | Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1608 | ||
1609 | * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word. | |
1610 | ||
1611 | * interp.c (sim_monitor): Make register pointers of type | |
1612 | unsigned_word*. | |
1613 | ||
1614 | * sim-main.h: Make registers of type unsigned_word not | |
1615 | signed_word. | |
1616 | ||
ea985d24 AC |
1617 | Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1618 | ||
1619 | start-sanitize-r5900 | |
1620 | * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB, | |
1621 | ...): Move to sim-main.h | |
1622 | ||
1623 | end-sanitize-r5900 | |
1624 | * interp.c (sync_operation): Rename from SyncOperation, make | |
1625 | global, add SD argument. | |
1626 | (prefetch): Rename from Prefetch, make global, add SD argument. | |
1627 | (decode_coproc): Make global. | |
1628 | ||
1629 | * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define. | |
1630 | ||
1631 | * gencode.c (build_instruction): Generate DecodeCoproc not | |
1632 | decode_coproc calls. | |
1633 | ||
1634 | * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h | |
1635 | (SizeFGR): Move to sim-main.h | |
1636 | (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT, | |
1637 | simSIGINT, simJALDELAYSLOT): Move to sim-main.h | |
1638 | (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to | |
1639 | sim-main.h. | |
1640 | (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF, | |
1641 | FP_RM_TOMINF, GETRM): Move to sim-main.h. | |
1642 | (Uncached, CachedNoncoherent, CachedCoherent, Cached, | |
1643 | isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h. | |
1644 | (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian, | |
1645 | BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h | |
1646 | ||
1647 | * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise | |
1648 | exception. | |
1649 | (sim-alu.h): Include. | |
1650 | (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define. | |
1651 | (sim_cia): Typedef to instruction_address. | |
1652 | ||
284e759d AC |
1653 | Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1654 | ||
1655 | * Makefile.in (interp.o): Rename generated file engine.c to | |
1656 | oengine.c. | |
1657 | ||
1658 | * interp.c: Update. | |
1659 | ||
339fb149 AC |
1660 | Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1661 | ||
1662 | * gencode.c (build_instruction): Use FPR_STATE not fpr_state. | |
1663 | ||
8b70f837 AC |
1664 | Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1665 | ||
1666 | * gencode.c (build_instruction): For "FPSQRT", output correct | |
1667 | number of arguments to Recip. | |
1668 | ||
0c2c5f61 AC |
1669 | Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1670 | ||
1671 | * Makefile.in (interp.o): Depends on sim-main.h | |
1672 | ||
1673 | * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers. | |
1674 | ||
1675 | * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state, | |
1676 | ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields. | |
1677 | (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*, | |
1678 | STATE, DSSTATE): Define | |
1679 | (GPR, FGRIDX, ..): Define. | |
1680 | ||
1681 | * interp.c (registers, register_widths, fpr_state, ipc, dspc, | |
1682 | pending_*, hiaccess, loaccess, state, dsstate): Delete globals. | |
1683 | (GPR, FGRIDX, ...): Delete macros. | |
1684 | ||
1685 | * interp.c: Update names to match defines from sim-main.h | |
1686 | ||
18c64df6 AC |
1687 | Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1688 | ||
1689 | * interp.c (sim_monitor): Add SD argument. | |
1690 | (sim_warning): Delete. Replace calls with calls to | |
1691 | sim_io_eprintf. | |
1692 | (sim_error): Delete. Replace calls with sim_io_error. | |
1693 | (open_trace, writeout32, writeout16, getnum): Add SD argument. | |
1694 | (mips_set_profile): Rename from sim_set_profile. Add SD argument. | |
1695 | (mips_set_profile_size): Rename from sim_set_profile_size. Add SD | |
1696 | argument. | |
1697 | (mips_size): Rename from sim_size. Add SD argument. | |
1698 | ||
1699 | * interp.c (simulator): Delete global variable. | |
1700 | (callback): Delete global variable. | |
1701 | (mips_option_handler, sim_open, sim_write, sim_read, | |
1702 | sim_store_register, sim_fetch_register, sim_info, sim_do_command, | |
1703 | sim_size,sim_monitor): Use sim_io_* not callback->*. | |
1704 | (sim_open): ZALLOC simulator struct. | |
1705 | (PROFILE): Do not define. | |
1706 | ||
1707 | Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1708 | ||
1709 | * interp.c (sim_open), support.h: Replace CHECKSIM macro found in | |
1710 | support.h with corresponding code. | |
1711 | ||
1712 | * sim-main.h (word64, uword64), support.h: Move definition to | |
1713 | sim-main.h. | |
1714 | (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto. | |
1715 | ||
1716 | * support.h: Delete | |
1717 | * Makefile.in: Update dependencies | |
1718 | * interp.c: Do not include. | |
1719 | ||
1720 | Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1721 | ||
1722 | * interp.c (address_translation, load_memory, store_memory, | |
1723 | cache_op): Rename to from AddressTranslation et.al., make global, | |
1724 | add SD argument | |
1725 | ||
1726 | * sim-main.h (AddressTranslation, LoadMemory, StoreMemory, | |
1727 | CacheOp): Define. | |
1728 | ||
1729 | * interp.c (SignalException): Rename to signal_exception, make | |
1730 | global. | |
1731 | ||
1732 | * interp.c (Interrupt, ...): Move definitions to sim-main.h. | |
1733 | ||
1734 | * sim-main.h (SignalException, SignalExceptionInterrupt, | |
1735 | SignalExceptionInstructionFetch, SignalExceptionAddressStore, | |
1736 | SignalExceptionAddressLoad, SignalExceptionSimulatorFault, | |
1737 | SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable): | |
1738 | Define. | |
1739 | ||
1740 | * interp.c, support.h: Use. | |
1741 | ||
1742 | Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1743 | ||
1744 | * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename | |
1745 | to value_fpr / store_fpr. Add SD argument. | |
1746 | (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub, | |
1747 | Multiply, Divide, Recip, SquareRoot, Convert): Make global. | |
1748 | ||
1749 | * sim-main.h (ValueFPR, StoreFPR): Define. | |
1750 | ||
1751 | Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1752 | ||
1753 | * interp.c (sim_engine_run): Check consistency between configure | |
1754 | WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN | |
1755 | and HASFPU. | |
1756 | ||
1757 | * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE. | |
1758 | (mips_fpu): Configure WITH_FLOATING_POINT. | |
1759 | (mips_endian): Configure WITH_TARGET_ENDIAN. | |
1760 | * configure: Update. | |
1761 | ||
1762 | Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1763 | ||
1764 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1765 | ||
adf4739e AC |
1766 | start-sanitize-r5900 |
1767 | Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1768 | ||
1769 | * interp.c (MAX_REG): Allow up-to 128 registers. | |
1770 | (LO1, HI1): Define value that matches REGISTER_NAMES in gdb. | |
1771 | (REGISTER_SA): Ditto. | |
1772 | (sim_open): Initialize register_widths for r5900 specific | |
1773 | registers. | |
1774 | (sim_fetch_register, sim_store_register): Check for request of | |
1775 | r5900 specific SA register. Check for request for hi 64 bits of | |
1776 | r5900 specific registers. | |
1777 | ||
1778 | end-sanitize-r5900 | |
26b20b0a BM |
1779 | Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com> |
1780 | ||
1781 | * configure: Regenerated. | |
1782 | ||
6eedf3f4 MA |
1783 | Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com> |
1784 | ||
1785 | * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. | |
1786 | ||
e63bc706 AC |
1787 | Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1788 | ||
6eedf3f4 MA |
1789 | * gencode.c (print_igen_insn_models): Assume certain architectures |
1790 | include all mips* instructions. | |
1791 | (print_igen_insn_format): Use data_size==-1 as marker for MIPS16 | |
1792 | instruction. | |
1793 | ||
e63bc706 AC |
1794 | * Makefile.in (tmp.igen): Add target. Generate igen input from |
1795 | gencode file. | |
1796 | ||
1797 | * gencode.c (FEATURE_IGEN): Define. | |
1798 | (main): Add --igen option. Generate output in igen format. | |
1799 | (process_instructions): Format output according to igen option. | |
1800 | (print_igen_insn_format): New function. | |
1801 | (print_igen_insn_models): New function. | |
1802 | (process_instructions): Only issue warnings and ignore | |
1803 | instructions when no FEATURE_IGEN. | |
1804 | ||
eb2e3c85 AC |
1805 | Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1806 | ||
1807 | * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some | |
1808 | MIPS targets. | |
1809 | ||
92f91d1f AC |
1810 | Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1811 | ||
1812 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1813 | ||
1814 | Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1815 | ||
1816 | * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN, | |
1817 | SIM_RESERVED_BITS): Delete, moved to common. | |
1818 | (SIM_EXTRA_CFLAGS): Update. | |
1819 | ||
794e9ac9 AC |
1820 | Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1821 | ||
76a6247f | 1822 | * configure.in: Configure non-strict memory alignment. |
794e9ac9 AC |
1823 | * configure: Regenerated to track ../common/aclocal.m4 changes. |
1824 | ||
b45caf05 AC |
1825 | Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1826 | ||
1827 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1828 | ||
1829 | Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com> | |
1830 | ||
1831 | * gencode.c (SDBBP,DERET): Added (3900) insns. | |
1832 | (RFE): Turn on for 3900. | |
1833 | * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added. | |
1834 | (dsstate): Made global. | |
1835 | (SUBTARGET_R3900): Added. | |
1836 | (CANCELDELAYSLOT): New. | |
1837 | (SignalException): Ignore SystemCall rather than ignore and | |
1838 | terminate. Add DebugBreakPoint handling. | |
1839 | (decode_coproc): New insns RFE, DERET; and new registers Debug | |
1840 | and DEPC protected by SUBTARGET_R3900. | |
1841 | (sim_engine_run): Use CANCELDELAYSLOT rather than clearing | |
1842 | bits explicitly. | |
1843 | * Makefile.in,configure.in: Add mips subtarget option. | |
1844 | * configure: Update. | |
1845 | ||
7afa8d4e GRK |
1846 | Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com> |
1847 | ||
1848 | * gencode.c: Add r3900 (tx39). | |
1849 | ||
1850 | start-sanitize-tx19 | |
1851 | * gencode.c: Fix some configuration problems by improving | |
1852 | the relationship between tx19 and tx39. | |
1853 | end-sanitize-tx19 | |
1854 | ||
667065d0 GRK |
1855 | Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com> |
1856 | ||
1857 | * gencode.c (build_instruction): Don't need to subtract 4 for | |
1858 | JALR, just 2. | |
1859 | ||
9cb8397f GRK |
1860 | Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com> |
1861 | ||
1862 | * interp.c: Correct some HASFPU problems. | |
1863 | ||
a2ab5e65 AC |
1864 | Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1865 | ||
1866 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1867 | ||
11ac69e0 AC |
1868 | Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1869 | ||
1870 | * interp.c (mips_options): Fix samples option short form, should | |
1871 | be `x'. | |
1872 | ||
972f3a34 AC |
1873 | Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1874 | ||
1875 | * interp.c (sim_info): Enable info code. Was just returning. | |
1876 | ||
9eeaaefa AC |
1877 | Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1878 | ||
1879 | * interp.c (decode_coproc): Clarify warning about unsuported MTC0, | |
1880 | MFC0. | |
1881 | ||
c31c13b4 AC |
1882 | Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1883 | ||
1884 | * gencode.c (build_instruction): Use SIGNED64 for 64 bit | |
1885 | constants. | |
1886 | (build_instruction): Ditto for LL. | |
1887 | ||
b637f306 GRK |
1888 | start-sanitize-tx19 |
1889 | Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com> | |
1890 | ||
1891 | * mips/configure.in, mips/gencode: Add tx19/r1900. | |
1892 | ||
1893 | end-sanitize-tx19 | |
6fea4763 DE |
1894 | Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba> |
1895 | ||
1896 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1897 | ||
52352d38 AC |
1898 | start-sanitize-r5900 |
1899 | Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1900 | ||
1901 | * gencode.c (build_instruction): For "pabsw" and "pabsh", check | |
1902 | for overflow due to ABS of MININT, set result to MAXINT. | |
1903 | (build_instruction): For "psrlvw", signextend bit 31. | |
1904 | ||
1905 | end-sanitize-r5900 | |
88117054 AC |
1906 | Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1907 | ||
1908 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1909 | * config.in: Ditto. | |
1910 | ||
fafce69a AC |
1911 | Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1912 | ||
1913 | * interp.c (sim_open): Add call to sim_analyze_program, update | |
1914 | call to sim_config. | |
1915 | ||
7230ff0f AC |
1916 | Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1917 | ||
1918 | * interp.c (sim_kill): Delete. | |
fafce69a AC |
1919 | (sim_create_inferior): Add ABFD argument. Set PC from same. |
1920 | (sim_load): Move code initializing trap handlers from here. | |
1921 | (sim_open): To here. | |
1922 | (sim_load): Delete, use sim-hload.c. | |
1923 | ||
1924 | * Makefile.in (SIM_OBJS): Add sim-hload.o module. | |
7230ff0f | 1925 | |
247fccde AC |
1926 | Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com> |
1927 | ||
1928 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
1929 | * config.in: Ditto. | |
1930 | ||
1931 | Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1932 | ||
1933 | * interp.c (sim_open): Add ABFD argument. | |
1934 | (sim_load): Move call to sim_config from here. | |
1935 | (sim_open): To here. Check return status. | |
1936 | ||
1937 | start-sanitize-r5900 | |
1938 | * gencode.c (build_instruction): Do not define x8000000000000000, | |
1939 | x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000. | |
1940 | ||
1941 | end-sanitize-r5900 | |
1942 | start-sanitize-r5900 | |
1943 | Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
1944 | ||
1945 | * gencode.c (build_instruction): For "pdivw", "pdivbw" and | |
1946 | "pdivuw" check for overflow due to signed divide by -1. | |
1947 | ||
1948 | end-sanitize-r5900 | |
c12e2e4c GRK |
1949 | Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com> |
1950 | ||
1951 | * gencode.c (build_instruction): Two arg MADD should | |
1952 | not assign result to $0. | |
1953 | ||
1e851d2c AC |
1954 | start-sanitize-r5900 |
1955 | Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com> | |
1956 | ||
1957 | * gencode.c (build_instruction): For "ppac5" use unsigned | |
1958 | arrithmetic so that the sign bit doesn't smear when right shifted. | |
1959 | (build_instruction): For "pdiv" perform sign extension when | |
1960 | storing results in HI and LO. | |
1961 | (build_instructions): For "pdiv" and "pdivbw" check for | |
1962 | divide-by-zero. | |
1963 | (build_instruction): For "pmfhl.slw" update hi part of dest | |
1964 | register as well as low part. | |
1965 | (build_instruction): For "pmfhl" portably handle long long values. | |
1966 | (build_instruction): For "pmfhl.sh" correctly negative values. | |
1967 | Store half words 2 and three in the correct place. | |
1968 | (build_instruction): For "psllvw", sign extend value after shift. | |
1969 | ||
1970 | end-sanitize-r5900 | |
1971 | Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com) | |
1972 | ||
1973 | * sim/mips/configure: Change default_sim_endian to 0 (bi-endian) | |
1974 | * sim/mips/configure.in: Regenerate. | |
1975 | ||
1976 | Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com> | |
1977 | ||
1978 | * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit | |
1979 | signed8, unsigned8 et.al. types. | |
1980 | ||
1981 | start-sanitize-r5900 | |
1982 | * gencode.c (build_instruction): For PMULTU* do not sign extend | |
1983 | registers. Make generated code easier to debug. | |
1984 | ||
1985 | end-sanitize-r5900 | |
1986 | * interp.c (SUB_REG_FETCH): Handle both little and big endian | |
1987 | hosts when selecting subreg. | |
1988 | ||
1989 | start-sanitize-r5900 | |
1990 | Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com> | |
1991 | ||
1992 | * gencode.c (type_for_data_len): For 32bit operations concerned | |
1993 | with overflow, perform op using 64bits. | |
1994 | (build_instruction): For PADD, always compute operation using type | |
1995 | returned by type_for_data_len. | |
1996 | (build_instruction): For PSUBU, when overflow, saturate to zero as | |
1997 | actually underflow. | |
1998 | ||
1999 | end-sanitize-r5900 | |
ae19b07b JL |
2000 | Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com) |
2001 | ||
649625bb | 2002 | start-sanitize-r5900 |
64435234 JL |
2003 | * gencode.c (build_instruction): Handle "pext5" according to |
2004 | version 1.95 of the r5900 ISA. | |
2005 | ||
649625bb JL |
2006 | * gencode.c (build_instruction): Handle "ppac5" according to |
2007 | version 1.95 of the r5900 ISA. | |
649625bb | 2008 | |
1e851d2c | 2009 | end-sanitize-r5900 |
05d1322f JL |
2010 | * interp.c (sim_engine_run): Reset the ZERO register to zero |
2011 | regardless of FEATURE_WARN_ZERO. | |
ae19b07b JL |
2012 | * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO. |
2013 | ||
2014 | Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2015 | ||
2016 | * interp.c (decode_coproc): Implement MTC0 N, CAUSE. | |
2017 | (SignalException): For BreakPoints ignore any mode bits and just | |
2018 | save the PC. | |
2019 | (SignalException): Always set the CAUSE register. | |
2020 | ||
56e7c849 AC |
2021 | Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com> |
2022 | ||
2023 | * interp.c (SignalException): Clear the simDELAYSLOT flag when an | |
2024 | exception has been taken. | |
2025 | ||
2026 | * interp.c: Implement the ERET and mt/f sr instructions. | |
2027 | ||
ae19b07b | 2028 | start-sanitize-r5900 |
56e7c849 AC |
2029 | Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com> |
2030 | ||
2031 | * gencode.c (build_instruction): For paddu, extract unsigned | |
2032 | sub-fields. | |
2033 | ||
2034 | * gencode.c (build_instruction): Saturate padds instead of padd | |
2035 | instructions. | |
2036 | ||
2037 | end-sanitize-r5900 | |
2038 | Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2039 | ||
2040 | * interp.c (SignalException): Don't bother restarting an | |
2041 | interrupt. | |
2042 | ||
2043 | Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2044 | ||
2045 | * interp.c (SignalException): Really take an interrupt. | |
2046 | (interrupt_event): Only deliver interrupts when enabled. | |
2047 | ||
2048 | Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2049 | ||
2050 | * interp.c (sim_info): Only print info when verbose. | |
2051 | (sim_info) Use sim_io_printf for output. | |
2052 | ||
2f2e6c5d AC |
2053 | Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> |
2054 | ||
2055 | * interp.c (CoProcPresent): Add UNUSED attribute - not used by all | |
2056 | mips architectures. | |
2057 | ||
2058 | Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2059 | ||
2060 | * interp.c (sim_do_command): Check for common commands if a | |
2061 | simulator specific command fails. | |
2062 | ||
d3d2a9f7 GRK |
2063 | Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com> |
2064 | ||
2065 | * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP | |
2066 | and simBE when DEBUG is defined. | |
2067 | ||
50a2a691 AC |
2068 | Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com> |
2069 | ||
2070 | * interp.c (interrupt_event): New function. Pass exception event | |
2071 | onto exception handler. | |
2072 | ||
2073 | * configure.in: Check for stdlib.h. | |
2074 | * configure: Regenerate. | |
2075 | ||
2076 | * gencode.c (build_instruction): Add UNUSED attribute to tempS | |
2077 | variable declaration. | |
2078 | (build_instruction): Initialize memval1. | |
2079 | (build_instruction): Add UNUSED attribute to byte, bigend, | |
2080 | reverse. | |
2081 | (build_operands): Ditto. | |
2082 | ||
2083 | * interp.c: Fix GCC warnings. | |
2084 | (sim_get_quit_code): Delete. | |
2085 | ||
2086 | * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS. | |
2087 | * Makefile.in: Ditto. | |
2088 | * configure: Re-generate. | |
2089 | ||
2090 | * Makefile.in (SIM_OBJS): Add sim-watch.o module. | |
2091 | ||
2092 | Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2093 | ||
2094 | * interp.c (mips_option_handler): New function parse argumes using | |
2095 | sim-options. | |
2096 | (myname): Replace with STATE_MY_NAME. | |
2097 | (sim_open): Delete check for host endianness - performed by | |
2098 | sim_config. | |
2099 | (simHOSTBE, simBE): Delete, replaced by sim-endian flags. | |
2100 | (sim_open): Move much of the initialization from here. | |
2101 | (sim_load): To here. After the image has been loaded and | |
2102 | endianness set. | |
2103 | (sim_open): Move ColdReset from here. | |
2104 | (sim_create_inferior): To here. | |
2105 | (sim_open): Make FP check less dependant on host endianness. | |
2106 | ||
2107 | * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or | |
2108 | run. | |
2109 | * interp.c (sim_set_callbacks): Delete. | |
2110 | ||
2111 | * interp.c (membank, membank_base, membank_size): Replace with | |
2112 | STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE. | |
2113 | (sim_open): Remove call to callback->init. gdb/run do this. | |
2114 | ||
2115 | * interp.c: Update | |
2116 | ||
2117 | * sim-main.h (SIM_HAVE_FLATMEM): Define. | |
2118 | ||
2119 | * interp.c (big_endian_p): Delete, replaced by | |
2120 | current_target_byte_order. | |
2121 | ||
2122 | Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2123 | ||
2124 | * interp.c (host_read_long, host_read_word, host_swap_word, | |
2125 | host_swap_long): Delete. Using common sim-endian. | |
2126 | (sim_fetch_register, sim_store_register): Use H2T. | |
2127 | (pipeline_ticks): Delete. Handled by sim-events. | |
2128 | (sim_info): Update. | |
2129 | (sim_engine_run): Update. | |
2130 | ||
2131 | Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
2132 | ||
2133 | * interp.c (sim_stop_reason): Move code determining simEXCEPTION | |
2134 | reason from here. | |
2135 | (SignalException): To here. Signal using sim_engine_halt. | |
2136 | (sim_stop_reason): Delete, moved to common. | |
2137 | ||
2138 | Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com> | |
2139 | ||
2140 | * interp.c (sim_open): Add callback argument. | |
2141 | (sim_set_callbacks): Delete SIM_DESC argument. | |
2142 | (sim_size): Ditto. | |
2143 | ||
2e61a3ad AC |
2144 | Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com> |
2145 | ||
2146 | * Makefile.in (SIM_OBJS): Add common modules. | |
2147 | ||
2148 | * interp.c (sim_set_callbacks): Also set SD callback. | |
2149 | (set_endianness, xfer_*, swap_*): Delete. | |
2150 | (host_read_word, host_read_long, host_swap_word, host_swap_long): | |
2151 | Change to functions using sim-endian macros. | |
2152 | (control_c, sim_stop): Delete, use common version. | |
2153 | (simulate): Convert into. | |
2154 | (sim_engine_run): This function. | |
2155 | (sim_resume): Delete. | |
2156 | ||
2157 | * interp.c (simulation): New variable - the simulator object. | |
2158 | (sim_kind): Delete global - merged into simulation. | |
2159 | (sim_load): Cleanup. Move PC assignment from here. | |
2160 | (sim_create_inferior): To here. | |
2161 | ||
2162 | * sim-main.h: New file. | |
2163 | * interp.c (sim-main.h): Include. | |
2164 | ||
2165 | Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> | |
2166 | ||
2167 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2168 | ||
3be0e228 DE |
2169 | Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com> |
2170 | ||
2171 | * tconfig.in (SIM_HAVE_BIENDIAN): Define. | |
2172 | ||
d654ba0a GRK |
2173 | Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com> |
2174 | ||
2175 | * gencode.c (build_instruction): DIV instructions: check | |
2176 | for division by zero and integer overflow before using | |
2177 | host's division operation. | |
2178 | ||
9d52bcb7 DE |
2179 | Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com> |
2180 | ||
2181 | * Makefile.in (SIM_OBJS): Add sim-load.o. | |
2182 | * interp.c: #include bfd.h. | |
2183 | (target_byte_order): Delete. | |
2184 | (sim_kind, myname, big_endian_p): New static locals. | |
2185 | (sim_open): Set sim_kind, myname. Move call to set_endianness to | |
2186 | after argument parsing. Recognize -E arg, set endianness accordingly. | |
2187 | (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to | |
2188 | load file into simulator. Set PC from bfd. | |
2189 | (sim_create_inferior): Return SIM_RC. Delete arg start_address. | |
2190 | (set_endianness): Use big_endian_p instead of target_byte_order. | |
2191 | ||
87e43259 AC |
2192 | Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com> |
2193 | ||
2194 | * interp.c (sim_size): Delete prototype - conflicts with | |
2195 | definition in remote-sim.h. Correct definition. | |
2196 | ||
2197 | Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
2198 | ||
2199 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2200 | * config.in: Ditto. | |
2201 | ||
fbda74b1 DE |
2202 | Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> |
2203 | ||
8a7c3105 DE |
2204 | * interp.c (sim_open): New arg `kind'. |
2205 | ||
fbda74b1 DE |
2206 | * configure: Regenerated to track ../common/aclocal.m4 changes. |
2207 | ||
a35e91c3 AC |
2208 | Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com> |
2209 | ||
2210 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2211 | ||
2212 | Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com> | |
2213 | ||
2214 | * interp.c (sim_open): Set optind to 0 before calling getopt. | |
2215 | ||
2216 | Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
2217 | ||
2218 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
2219 | ||
6efa34d8 GRK |
2220 | Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com> |
2221 | ||
2222 | * interp.c : Replace uses of pr_addr with pr_uword64 | |
2223 | where the bit length is always 64 independent of SIM_ADDR. | |
2224 | (pr_uword64) : added. | |
2225 | ||
a77aa7ec AC |
2226 | Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> |
2227 | ||
2228 | * configure: Re-generate. | |
2229 | ||
601fb8ae MM |
2230 | Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com> |
2231 | ||
2232 | * configure: Regenerate to track ../common/aclocal.m4 changes. | |
2233 | ||
53b9417e DE |
2234 | Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com> |
2235 | ||
2236 | * interp.c (sim_open): New SIM_DESC result. Argument is now | |
2237 | in argv form. | |
2238 | (other sim_*): New SIM_DESC argument. | |
2239 | ||
2240 | start-sanitize-r5900 | |
2241 | Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com> | |
2242 | ||
2243 | * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR): | |
2244 | Change values to avoid overloading DOUBLEWORD which is tested | |
2245 | for all insns. | |
2246 | * gencode.c: reinstate "offending code". | |
53b9417e | 2247 | |
56e7c849 | 2248 | end-sanitize-r5900 |
53b9417e DE |
2249 | Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com> |
2250 | ||
2251 | * interp.c: Fix printing of addresses for non-64-bit targets. | |
2252 | (pr_addr): Add function to print address based on size. | |
2253 | start-sanitize-r5900 | |
2254 | * gencode.c: #ifdef out offending code until a permanent fix | |
2255 | can be added. Code is causing build errors for non-5900 mips targets. | |
2256 | end-sanitize-r5900 | |
2257 | ||
2258 | start-sanitize-r5900 | |
2259 | Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com> | |
2260 | ||
2261 | * gencode.c (process_instructions): Correct test for ISA dependent | |
2262 | architecture bits in isa field of MIPS_DECODE. | |
2263 | ||
2264 | end-sanitize-r5900 | |
7e05106d MA |
2265 | Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com> |
2266 | ||
2267 | * interp.c (simopen): Add support for LSI MiniRISC PMON vectors. | |
2268 | ||
2d18fbc6 | 2269 | start-sanitize-r5900 |
53b9417e | 2270 | Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com> |
2d18fbc6 GRK |
2271 | |
2272 | * gencode.c (MIPS_DECODE): Correct instruction feature flags for | |
2273 | PMADDUW. | |
2274 | ||
2275 | end-sanitize-r5900 | |
2276 | Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com> | |
2277 | ||
2278 | * gencode.c (build_mips16_operands): Correct computation of base | |
2279 | address for extended PC relative instruction. | |
2280 | ||
276c2d7d GRK |
2281 | start-sanitize-r5900 |
2282 | Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com> | |
2d18fbc6 GRK |
2283 | |
2284 | * Makefile.in, configure, configure.in, gencode.c, | |
2285 | interp.c, support.h: add r5900. | |
2286 | ||
276c2d7d | 2287 | end-sanitize-r5900 |
da0bce9c ILT |
2288 | Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com> |
2289 | ||
2290 | * interp.c (mips16_entry): Add support for floating point cases. | |
2291 | (SignalException): Pass floating point cases to mips16_entry. | |
2292 | (ValueFPR): Don't restrict fmt_single and fmt_word to even | |
2293 | registers. | |
2294 | (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single | |
2295 | or fmt_word. | |
2296 | (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, | |
2297 | and then set the state to fmt_uninterpreted. | |
2298 | (COP_SW): Temporarily set the state to fmt_word while calling | |
2299 | ValueFPR. | |
2300 | ||
6389d856 ILT |
2301 | Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com> |
2302 | ||
2303 | * gencode.c (build_instruction): The high order may be set in the | |
2304 | comparison flags at any ISA level, not just ISA 4. | |
2305 | ||
19c5af72 DE |
2306 | Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com> |
2307 | ||
2308 | * Makefile.in (@COMMON_MAKEFILE_FRAG): Use | |
2309 | COMMON_{PRE,POST}_CONFIG_FRAG instead. | |
2310 | * configure.in: sinclude ../common/aclocal.m4. | |
2311 | * configure: Regenerated. | |
2312 | ||
736a306c ILT |
2313 | Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com> |
2314 | ||
2315 | * configure: Rebuild after change to aclocal.m4. | |
2316 | ||
295dbbe4 SG |
2317 | Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) |
2318 | ||
2319 | * configure configure.in Makefile.in: Update to new configure | |
2320 | scheme which is more compatible with WinGDB builds. | |
2321 | * configure.in: Improve comment on how to run autoconf. | |
2322 | * configure: Re-run autoconf to get new ../common/aclocal.m4. | |
2323 | * Makefile.in: Use autoconf substitution to install common | |
2324 | makefile fragment. | |
2325 | ||
2326 | Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com> | |
2327 | ||
2328 | * gencode.c (build_instruction): Use BigEndianCPU instead of | |
2329 | ByteSwapMem. | |
2330 | ||
e1db0d47 MA |
2331 | Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com> |
2332 | ||
2333 | * interp.c (sim_monitor): Make output to stdout visible in | |
2334 | wingdb's I/O log window. | |
2335 | ||
2902e8ab MA |
2336 | Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com> |
2337 | ||
2338 | * support.h: Undo previous change to SIGTRAP | |
2339 | and SIGQUIT values. | |
2340 | ||
7e6c297e ILT |
2341 | Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com> |
2342 | ||
2343 | * interp.c (store_word, load_word): New static functions. | |
2344 | (mips16_entry): New static function. | |
2345 | (SignalException): Look for mips16 entry and exit instructions. | |
2346 | (simulate): Use the correct index when setting fpr_state after | |
2347 | doing a pending move. | |
2348 | ||
0049ba7a MA |
2349 | Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com> |
2350 | ||
2351 | * interp.c: Fix byte-swapping code throughout to work on | |
2352 | both little- and big-endian hosts. | |
2353 | ||
2510786b MA |
2354 | Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com> |
2355 | ||
2356 | * support.h: Make definitions of SIGTRAP and SIGQUIT consistent | |
2357 | with gdb/config/i386/xm-windows.h. | |
2358 | ||
39bf0ef4 MA |
2359 | Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com> |
2360 | ||
2361 | * gencode.c (build_instruction): Work around MSVC++ code gen bug | |
2362 | that messes up arithmetic shifts. | |
2363 | ||
dbeec768 SG |
2364 | Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com) |
2365 | ||
2366 | * support.h: Use _WIN32 instead of __WIN32__. Also add defs for | |
2367 | SIGTRAP and SIGQUIT for _WIN32. | |
2368 | ||
deffd638 ILT |
2369 | Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com> |
2370 | ||
2371 | * gencode.c (build_instruction) [MUL]: Cast operands to word64, to | |
2372 | force a 64 bit multiplication. | |
2373 | (build_instruction) [OR]: In mips16 mode, don't do anything if the | |
2374 | destination register is 0, since that is the default mips16 nop | |
2375 | instruction. | |
2376 | ||
aaff8437 ILT |
2377 | Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com> |
2378 | ||
063443cf ILT |
2379 | * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI. |
2380 | (build_endian_shift): Don't check proc64. | |
2381 | (build_instruction): Always set memval to uword64. Cast op2 to | |
2382 | uword64 when shifting it left in memory instructions. Always use | |
2383 | the same code for stores--don't special case proc64. | |
2384 | ||
aaff8437 ILT |
2385 | * gencode.c (build_mips16_operands): Fix base PC value for PC |
2386 | relative operands. | |
2387 | (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a | |
2388 | jal instruction. | |
2389 | * interp.c (simJALDELAYSLOT): Define. | |
2390 | (JALDELAYSLOT): Define. | |
2391 | (INDELAYSLOT, INJALDELAYSLOT): Define. | |
2392 | (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared. | |
2393 | ||
280f90e1 AMT |
2394 | Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com) |
2395 | ||
2396 | * interp.c (sim_open): add flush_cache as a PMON routine | |
2397 | (sim_monitor): handle flush_cache by ignoring it | |
2398 | ||
aaff8437 ILT |
2399 | Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com> |
2400 | ||
2401 | * gencode.c (build_instruction): Use !ByteSwapMem instead of | |
2402 | BigEndianMem. | |
2403 | * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete. | |
2404 | (BigEndianMem): Rename to ByteSwapMem and change sense. | |
2405 | (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change | |
2406 | BigEndianMem references to !ByteSwapMem. | |
2407 | (set_endianness): New function, with prototype. | |
2408 | (sim_open): Call set_endianness. | |
2409 | (sim_info): Use simBE instead of BigEndianMem. | |
2410 | (xfer_direct_word, xfer_direct_long, swap_direct_word, | |
2411 | swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, | |
2412 | xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER | |
2413 | ifdefs, keeping the prototype declaration. | |
2414 | (swap_word): Rewrite correctly. | |
2415 | (ColdReset): Delete references to CONFIG. Delete endianness related | |
2416 | code; moved to set_endianness. | |
2417 | ||
6429b296 JW |
2418 | Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com> |
2419 | ||
2420 | * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. | |
2421 | * interp.c (CHECKHILO): Define away. | |
2422 | (simSIGINT): New macro. | |
2423 | (membank_size): Increase from 1MB to 2MB. | |
2424 | (control_c): New function. | |
2425 | (sim_resume): Rename parameter signal to signal_number. Add local | |
2426 | variable prev. Call signal before and after simulate. | |
2427 | (sim_stop_reason): Add simSIGINT support. | |
2428 | (sim_warning, sim_error, dotrace, SignalException): Define as stdarg | |
2429 | functions always. | |
2430 | (sim_warning): Delete call to SignalException. Do call printf_filtered | |
2431 | if logfh is NULL. | |
2432 | (AddressTranslation): Add #ifdef DEBUG around debugging message and | |
2433 | a call to sim_warning. | |
2434 | ||
2435 | Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com> | |
2436 | ||
2437 | * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD | |
2438 | 16 bit instructions. | |
2439 | ||
831f59a2 ILT |
2440 | Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com> |
2441 | ||
2442 | Add support for mips16 (16 bit MIPS implementation): | |
2443 | * gencode.c (inst_type): Add mips16 instruction encoding types. | |
2444 | (GETDATASIZEINSN): Define. | |
2445 | (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add | |
2446 | jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and | |
2447 | mtlo. | |
2448 | (MIPS16_DECODE): New table, for mips16 instructions. | |
2449 | (bitmap_val): New static function. | |
2450 | (struct mips16_op): Define. | |
2451 | (mips16_op_table): New table, for mips16 operands. | |
2452 | (build_mips16_operands): New static function. | |
2453 | (process_instructions): If PC is odd, decode a mips16 | |
2454 | instruction. Break out instruction handling into new | |
2455 | build_instruction function. | |
2456 | (build_instruction): New static function, broken out of | |
2457 | process_instructions. Check modifiers rather than flags for SHIFT | |
2458 | bit count and m[ft]{hi,lo} direction. | |
2459 | (usage): Pass program name to fprintf. | |
2460 | (main): Remove unused variable this_option_optind. Change | |
2461 | ``*loptarg++'' to ``loptarg++''. | |
2462 | (my_strtoul): Parenthesize && within ||. | |
350d33b8 | 2463 | * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd. |
831f59a2 ILT |
2464 | (simulate): If PC is odd, fetch a 16 bit instruction, and |
2465 | increment PC by 2 rather than 4. | |
2466 | * configure.in: Add case for mips16*-*-*. | |
2467 | * configure: Rebuild. | |
2468 | ||
2469 | Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com> | |
2470 | ||
2471 | * interp.c: Allow -t to enable tracing in standalone simulator. | |
2472 | Fix garbage output in trace file and error messages. | |
2473 | ||
e3d12c65 DE |
2474 | Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com> |
2475 | ||
2476 | * Makefile.in: Delete stuff moved to ../common/Make-common.in. | |
2477 | (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. | |
2478 | * configure.in: Simplify using macros in ../common/aclocal.m4. | |
2479 | * configure: Regenerated. | |
2480 | * tconfig.in: New file. | |
2481 | ||
2482 | Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com> | |
2483 | ||
2484 | * interp.c: Fix bugs in 64-bit port. | |
2485 | Use ansi function declarations for msvc compiler. | |
2486 | Initialize and test file pointer in trace code. | |
2487 | Prevent duplicate definition of LAST_EMED_REGNUM. | |
2488 | ||
2489 | Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com> | |
2490 | ||
2491 | * interp.c (xfer_big_long): Prevent unwanted sign extension. | |
2492 | ||
2493 | Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk> | |
2494 | ||
2495 | * interp.c (SignalException): Check for explicit terminating | |
2496 | breakpoint value. | |
2497 | * gencode.c: Pass instruction value through SignalException() | |
2498 | calls for Trap, Breakpoint and Syscall. | |
2499 | ||
2500 | Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk> | |
2501 | ||
2502 | * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is | |
2503 | only used on those hosts that provide it. | |
2504 | * configure.in: Add sqrt() to list of functions to be checked for. | |
2505 | * config.in: Re-generated. | |
2506 | * configure: Re-generated. | |
2507 | ||
2508 | Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
2509 | ||
2510 | * gencode.c (process_instructions): Call build_endian_shift when | |
2511 | expanding STORE RIGHT, to fix swr. | |
2512 | * support.h (SIGNEXTEND): If the sign bit is not set, explicitly | |
2513 | clear the high bits. | |
2514 | * interp.c (Convert): Fix fmt_single to fmt_long to not truncate. | |
2515 | Fix float to int conversions to produce signed values. | |
2516 | ||
cc5201d7 ILT |
2517 | Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com> |
2518 | ||
458e1f58 ILT |
2519 | * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction. |
2520 | (process_instructions): Correct handling of nor instruction. | |
2521 | Correct shift count for 32 bit shift instructions. Correct sign | |
2522 | extension for arithmetic shifts to not shift the number of bits in | |
2523 | the type. Fix 64 bit multiply high word calculation. Fix 32 bit | |
2524 | unsigned multiply. Fix ldxc1 and friends to use coprocessor 1. | |
2525 | Fix madd. | |
c05d1721 ILT |
2526 | * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC. |
2527 | It's OK to have a mult follow a mult. What's not OK is to have a | |
2528 | mult follow an mfhi. | |
458e1f58 | 2529 | (Convert): Comment out incorrect rounding code. |
cc5201d7 | 2530 | |
f24b7b69 JSC |
2531 | Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> |
2532 | ||
2533 | * interp.c (sim_monitor): Improved monitor printf | |
2534 | simulation. Tidied up simulator warnings, and added "--log" option | |
2535 | for directing warning message output. | |
2536 | * gencode.c: Use sim_warning() rather than WARNING macro. | |
2537 | ||
2538 | Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
2539 | ||
2540 | * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and | |
2541 | getopt1.o, rather than on gencode.c. Link objects together. | |
2542 | Don't link against -liberty. | |
2543 | (gencode.o, getopt.o, getopt1.o): New targets. | |
2544 | * gencode.c: Include <ctype.h> and "ansidecl.h". | |
2545 | (AND): Undefine after including "ansidecl.h". | |
2546 | (ULONG_MAX): Define if not defined. | |
2547 | (OP_*): Don't define macros; now defined in opcode/mips.h. | |
2548 | (main): Call my_strtoul rather than strtoul. | |
2549 | (my_strtoul): New static function. | |
2550 | ||
2551 | Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com) | |
2552 | ||
2553 | * gencode.c (process_instructions): Generate word64 and uword64 | |
2554 | instead of `long long' and `unsigned long long' data types. | |
2555 | * interp.c: #include sysdep.h to get signals, and define default | |
2556 | for SIGBUS. | |
2557 | * (Convert): Work around for Visual-C++ compiler bug with type | |
2558 | conversion. | |
2559 | * support.h: Make things compile under Visual-C++ by using | |
2560 | __int64 instead of `long long'. Change many refs to long long | |
2561 | into word64/uword64 typedefs. | |
2562 | ||
a271d1d9 JM |
2563 | Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) |
2564 | ||
2565 | * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, | |
2566 | INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. | |
2567 | (docdir): Removed. | |
2568 | * configure.in (AC_PREREQ): autoconf 2.5 or higher. | |
2569 | (AC_PROG_INSTALL): Added. | |
2570 | (AC_PROG_CC): Moved to before configure.host call. | |
2571 | * configure: Rebuilt. | |
2572 | ||
2573 | Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk> | |
2574 | ||
2575 | * configure.in: Define @SIMCONF@ depending on mips target. | |
2576 | * configure: Rebuild. | |
2577 | * Makefile.in (run): Add @SIMCONF@ to control simulator | |
2578 | construction. | |
2579 | * gencode.c: Change LOADDRMASK to 64bit memory model only. | |
2580 | * interp.c: Remove some debugging, provide more detailed error | |
2581 | messages, update memory accesses to use LOADDRMASK. | |
2582 | ||
4fa134be ILT |
2583 | Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com> |
2584 | ||
2585 | * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS, | |
2586 | AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set | |
2587 | stamp-h. | |
2588 | * configure: Rebuild. | |
2589 | * config.in: New file, generated by autoheader. | |
2590 | * interp.c: Include "config.h". Include <stdlib.h>, <string.h>, | |
2591 | and <strings.h> if they exist. Replace #ifdef sun with #ifdef | |
2592 | HAVE_ANINT and HAVE_AINT, as appropriate. | |
2593 | * Makefile.in (run): Use @LIBS@ rather than -lm. | |
2594 | (interp.o): Depend upon config.h. | |
2595 | (Makefile): Just rebuild Makefile. | |
2596 | (clean): Remove stamp-h. | |
2597 | (mostlyclean): Make the same as clean, not as distclean. | |
2598 | (config.h, stamp-h): New targets. | |
2599 | ||
2600 | Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk> | |
2601 | ||
2602 | * interp.c (ColdReset): Fix boolean test. Make all simulator | |
2603 | globals static. | |
2604 | ||
f7481d45 JSC |
2605 | Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk> |
2606 | ||
2607 | * interp.c (xfer_direct_word, xfer_direct_long, | |
2608 | swap_direct_word, swap_direct_long, xfer_big_word, | |
2609 | xfer_big_long, xfer_little_word, xfer_little_long, | |
2610 | swap_word,swap_long): Added. | |
2611 | * interp.c (ColdReset): Provide function indirection to | |
2612 | host<->simulated_target transfer routines. | |
2613 | * interp.c (sim_store_register, sim_fetch_register): Updated to | |
2614 | make use of indirected transfer routines. | |
2615 | ||
2616 | Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> | |
2617 | ||
2618 | * gencode.c (process_instructions): Ensure FP ABS instruction | |
2619 | recognised. | |
2620 | * interp.c (AbsoluteValue): Add routine. Also provide simple PMON | |
2621 | system call support. | |
2622 | ||
8b554809 JSC |
2623 | Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk> |
2624 | ||
2625 | * interp.c (sim_do_command): Complain if callback structure not | |
2626 | initialised. | |
2627 | ||
d0757082 JSC |
2628 | Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk> |
2629 | ||
2630 | * interp.c (Convert): Provide round-to-nearest and round-to-zero | |
2631 | support for Sun hosts. | |
2632 | * Makefile.in (gencode): Ensure the host compiler and libraries | |
2633 | used for cross-hosted build. | |
2634 | ||
e871dd18 JSC |
2635 | Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> |
2636 | ||
2637 | * interp.c, gencode.c: Some more (TODO) tidying. | |
2638 | ||
2639 | Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk> | |
2640 | ||
2641 | * gencode.c, interp.c: Replaced explicit long long references with | |
2642 | WORD64HI, WORD64LO, SET64HI and SET64LO macro calls. | |
2643 | * support.h (SET64LO, SET64HI): Macros added. | |
2644 | ||
5c59ec43 ILT |
2645 | Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com> |
2646 | ||
2647 | * configure: Regenerate with autoconf 2.7. | |
2648 | ||
2649 | Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com> | |
2650 | ||
2651 | * interp.c (LoadMemory): Enclose text following #endif in /* */. | |
2652 | * support.h: Remove superfluous "1" from #if. | |
2653 | * support.h (CHECKSIM): Remove stray 'a' at end of line. | |
2654 | ||
2655 | Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com> | |
2656 | ||
2657 | * interp.c (StoreFPR): Control UndefinedResult() call on | |
2658 | WARN_RESULT manifest. | |
2659 | ||
8bae0a0c JSC |
2660 | Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk> |
2661 | ||
2662 | * gencode.c: Tidied instruction decoding, and added FP instruction | |
2663 | support. | |
2664 | ||
2665 | * interp.c: Added dineroIII, and BSD profiling support. Also | |
2666 | run-time FP handling. | |
2667 | ||
2668 | Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> | |
2669 | ||
2670 | * Changelog, Makefile.in, README.Cygnus, configure, configure.in, | |
2671 | gencode.c, interp.c, support.h: created. |