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2002-03-01 Chris Demetriou <cgd@broadcom.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
fff8d27d
CD		 12002-03-01 Chris Demetriou <cgd@broadcom.com>
2
3 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
4 DSRL32, do_dsrlv): Trace inputs and results.
5
0d3e762b
CD		 62002-03-01 Chris Demetriou <cgd@broadcom.com>
7
8 * mips.igen (CACHE): Provide instruction-printing string.
9
10 * interp.c (signal_exception): Comment tokens after #endif.
11
eb5fcf93
CD		 122002-02-28 Chris Demetriou <cgd@broadcom.com>
13
14 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
15 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
16 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
17 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
18 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
19 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
20 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
21 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
22
bb22bd7d
CD		 232002-02-28 Chris Demetriou <cgd@broadcom.com>
24
25 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
26 instruction-printing string.
27 (LWU): Use '64' as the filter flag.
28
91a177cf
CD		 292002-02-28 Chris Demetriou <cgd@broadcom.com>
30
31 * mips.igen (SDXC1): Fix instruction-printing string.
32
387f484a
CD		 332002-02-28 Chris Demetriou <cgd@broadcom.com>
34
35 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
36 filter flags "32,f".
37
3d81f391
CD		 382002-02-27 Chris Demetriou <cgd@broadcom.com>
39
40 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
41 as the filter flag.
42
af5107af
CD		 432002-02-27 Chris Demetriou <cgd@broadcom.com>
44
45 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
46 add a comma) so that it more closely match the MIPS ISA
47 documentation opcode partitioning.
48 (PREF): Put useful names on opcode fields, and include
49 instruction-printing string.
50
ca971540
CD		 512002-02-27 Chris Demetriou <cgd@broadcom.com>
52
53 * mips.igen (check_u64): New function which in the future will
54 check whether 64-bit instructions are usable and signal an
55 exception if not. Currently a no-op.
56 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
57 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
58 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
59 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
60
61 * mips.igen (check_fpu): New function which in the future will
62 check whether FPU instructions are usable and signal an exception
63 if not. Currently a no-op.
64 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
65 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
66 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
67 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
68 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
69 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
70 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
71 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
72
1c47a468
CD		 732002-02-27 Chris Demetriou <cgd@broadcom.com>
74
75 * mips.igen (do_load_left, do_load_right): Move to be immediately
76 following do_load.
77 (do_store_left, do_store_right): Move to be immediately following
78 do_store.
79
603a98e7
CD		 802002-02-27 Chris Demetriou <cgd@broadcom.com>
81
82 * mips.igen (mipsV): New model name. Also, add it to
83 all instructions and functions where it is appropriate.
84
c5d00cc7
CD		 852002-02-18 Chris Demetriou <cgd@broadcom.com>
86
87 * mips.igen: For all functions and instructions, list model
88 names that support that instruction one per line.
89
074e9cb8
CD		 902002-02-11 Chris Demetriou <cgd@broadcom.com>
91
92 * mips.igen: Add some additional comments about supported
93 models, and about which instructions go where.
94 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
95 order as is used in the rest of the file.
96
9805e229
CD		 972002-02-11 Chris Demetriou <cgd@broadcom.com>
98
99 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
100 indicating that ALU32_END or ALU64_END are there to check
101 for overflow.
102 (DADD): Likewise, but also remove previous comment about
103 overflow checking.
104
f701dad2
CD		 1052002-02-10 Chris Demetriou <cgd@broadcom.com>
106
107 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
108 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
109 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
110 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
111 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
112 fields (i.e., add and move commas) so that they more closely
113 match the MIPS ISA documentation opcode partitioning.
114
1152002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 116
117 * mips.igen (ADDI): Print immediate value.
118 (BREAK): Print code.
119 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
120 (SLL): Print "nop" specially, and don't run the code
121 that does the shift for the "nop" case.
122
9e52972e
FF		 1232001-11-17 Fred Fish <fnf@redhat.com>
124
125 * sim-main.h (float_operation): Move enum declaration outside
126 of _sim_cpu struct declaration.
127
c0efbca4
JB		 1282001-04-12 Jim Blandy <jimb@redhat.com>
129
130 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
131 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
132 set of the FCSR.
133 * sim-main.h (COCIDX): Remove definition; this isn't supported by
134 PENDING_FILL, and you can get the intended effect gracefully by
135 calling PENDING_SCHED directly.
136
fb891446
BE		 1372001-02-23 Ben Elliston <bje@redhat.com>
138
139 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
140 already defined elsewhere.
141
8030f857
BE		 1422001-02-19 Ben Elliston <bje@redhat.com>
143
144 * sim-main.h (sim_monitor): Return an int.
145 * interp.c (sim_monitor): Add return values.
146 (signal_exception): Handle error conditions from sim_monitor.
147
56b48a7a
CD		 1482001-02-08 Ben Elliston <bje@redhat.com>
149
150 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
151 (store_memory): Likewise, pass cia to sim_core_write*.
152
d3ee60d9
FCE		 1532000-10-19 Frank Ch. Eigler <fche@redhat.com>
154
155 On advice from Chris G. Demetriou <cgd@sibyte.com>:
156 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
157
071da002
AC		 158Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
159
160 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
161 * Makefile.in: Don't delete *.igen when cleaning directory.
162
a28c02cd
AC		 163Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
164
165 * m16.igen (break): Call SignalException not sim_engine_halt.
166
80ee11fa
AC		 167Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
168
169 From Jason Eckhardt:
170 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
171
673388c0
AC		 172Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
173
174 * mips.igen (MxC1, DMxC1): Fix printf formatting.
175
4c0deff4
NC		 1762000-05-24 Michael Hayes <mhayes@cygnus.com>
177
178 * mips.igen (do_dmultx): Fix typo.
179
eb2d80b4
AC		 180Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
181
182 * configure: Regenerated to track ../common/aclocal.m4 changes.
183
dd37a34b
AC		 184Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
185
186 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
187
4c0deff4
NC		 1882000-04-12 Frank Ch. Eigler <fche@redhat.com>
189
190 * sim-main.h (GPR_CLEAR): Define macro.
191
e30db738
AC		 192Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
193
194 * interp.c (decode_coproc): Output long using %lx and not %s.
195
cb7450ea
FCE		 1962000-03-21 Frank Ch. Eigler <fche@redhat.com>
197
198 * interp.c (sim_open): Sort & extend dummy memory regions for
199 --board=jmr3904 for eCos.
200
a3027dd7
FCE		 2012000-03-02 Frank Ch. Eigler <fche@redhat.com>
202
203 * configure: Regenerated.
204
205Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
206
207 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
208 calls, conditional on the simulator being in verbose mode.
209
dfcd3bfb
JM		 210Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
211
212 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
213 cache don't get ReservedInstruction traps.
214
c2d11a7d
JM		 2151999-11-29 Mark Salter <msalter@cygnus.com>
216
217 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
218 to clear status bits in sdisr register. This is how the hardware works.
219
220 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
221 being used by cygmon.
222
4ce44c66
JM		 2231999-11-11 Andrew Haley <aph@cygnus.com>
224
225 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
226 instructions.
227
cff3e48b
JM		 228Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
229
230 * mips.igen (MULT): Correct previous mis-applied patch.
231
d4f3574e
SS		 232Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
233
234 * mips.igen (delayslot32): Handle sequence like
235 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
236 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
237 (MULT): Actually pass the third register...
238
2391999-09-03 Mark Salter <msalter@cygnus.com>
240
241 * interp.c (sim_open): Added more memory aliases for additional
242 hardware being touched by cygmon on jmr3904 board.
243
244Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
245
246 * configure: Regenerated to track ../common/aclocal.m4 changes.
247
a0b3c4fd
JM		 248Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
249
250 * interp.c (sim_store_register): Handle case where client - GDB -
251 specifies that a 4 byte register is 8 bytes in size.
252 (sim_fetch_register): Ditto.
253
adf40b2e
JM		 2541999-07-14 Frank Ch. Eigler <fche@cygnus.com>
255
256 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
257 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
258 (idt_monitor_base): Base address for IDT monitor traps.
259 (pmon_monitor_base): Ditto for PMON.
260 (lsipmon_monitor_base): Ditto for LSI PMON.
261 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
262 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
263 (sim_firmware_command): New function.
264 (mips_option_handler): Call it for OPTION_FIRMWARE.
265 (sim_open): Allocate memory for idt_monitor region. If "--board"
266 option was given, add no monitor by default. Add BREAK hooks only if
267 monitors are also there.
268
43e526b9
JM		 269Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
270
271 * interp.c (sim_monitor): Flush output before reading input.
272
273Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
274
275 * tconfig.in (SIM_HANDLES_LMA): Always define.
276
277Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
278
279 From Mark Salter <msalter@cygnus.com>:
280 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
281 (sim_open): Add setup for BSP board.
282
9846de1b
JM		 283Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
284
285 * mips.igen (MULT, MULTU): Add syntax for two operand version.
286 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
287 them as unimplemented.
288
cd0fc7c3
SS		 2891999-05-08 Felix Lee <flee@cygnus.com>
290
291 * configure: Regenerated to track ../common/aclocal.m4 changes.
292
7a292a7a
SS		 2931999-04-21 Frank Ch. Eigler <fche@cygnus.com>
294
295 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
296
297Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
298
299 * configure.in: Any mips64vr5*-*-* target should have
300 -DTARGET_ENABLE_FR=1.
301 (default_endian): Any mips64vr*el-*-* target should default to
302 LITTLE_ENDIAN.
303 * configure: Re-generate.
304
3051999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
306
307 * mips.igen (ldl): Extend from _16_, not 32.
308
309Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
310
311 * interp.c (sim_store_register): Force registers written to by GDB
312 into an un-interpreted state.
313
c906108c
SS		 3141999-02-05 Frank Ch. Eigler <fche@cygnus.com>
315
316 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
317 CPU, start periodic background I/O polls.
318 (tx3904sio_poll): New function: periodic I/O poller.
319
3201998-12-30 Frank Ch. Eigler <fche@cygnus.com>
321
322 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
323
324Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
325
326 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
327 case statement.
328
3291998-12-29 Frank Ch. Eigler <fche@cygnus.com>
330
331 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
332 (load_word): Call SIM_CORE_SIGNAL hook on error.
333 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
334 starting. For exception dispatching, pass PC instead of NULL_CIA.
335 (decode_coproc): Use COP0_BADVADDR to store faulting address.
336 * sim-main.h (COP0_BADVADDR): Define.
337 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
338 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
339 (_sim_cpu): Add exc_* fields to store register value snapshots.
340 * mips.igen (*): Replace memory-related SignalException* calls
341 with references to SIM_CORE_SIGNAL hook.
342
343 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
344 fix.
345 * sim-main.c (*): Minor warning cleanups.
346
3471998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
348
349 * m16.igen (DADDIU5): Correct type-o.
350
351Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
352
353 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
354 variables.
355
356Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
357
358 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
359 to include path.
360 (interp.o): Add dependency on itable.h
361 (oengine.c, gencode): Delete remaining references.
362 (BUILT_SRC_FROM_GEN): Clean up.
363
3641998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
365
366 * vr4run.c: New.
367 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
368 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
369 tmp-run-hack) : New.
370 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
371 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
372 Drop the "64" qualifier to get the HACK generator working.
373 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
374 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
375 qualifier to get the hack generator working.
376 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
377 (DSLL): Use do_dsll.
378 (DSLLV): Use do_dsllv.
379 (DSRA): Use do_dsra.
380 (DSRL): Use do_dsrl.
381 (DSRLV): Use do_dsrlv.
382 (BC1): Move *vr4100 to get the HACK generator working.
383 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
384 get the HACK generator working.
385 (MACC) Rename to get the HACK generator working.
386 (DMACC,MACCS,DMACCS): Add the 64.
387
3881998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
389
390 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
391 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
392
3931998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
394
395 * mips/interp.c (DEBUG): Cleanups.
396
3971998-12-10 Frank Ch. Eigler <fche@cygnus.com>
398
399 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
400 (tx3904sio_tickle): fflush after a stdout character output.
401
4021998-12-03 Frank Ch. Eigler <fche@cygnus.com>
403
404 * interp.c (sim_close): Uninstall modules.
405
406Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
407
408 * sim-main.h, interp.c (sim_monitor): Change to global
409 function.
410
411Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
412
413 * configure.in (vr4100): Only include vr4100 instructions in
414 simulator.
415 * configure: Re-generate.
416 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
417
418Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
419
420 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
421 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
422 true alternative.
423
424 * configure.in (sim_default_gen, sim_use_gen): Replace with
425 sim_gen.
426 (--enable-sim-igen): Delete config option. Always using IGEN.
427 * configure: Re-generate.
428
429 * Makefile.in (gencode): Kill, kill, kill.
430 * gencode.c: Ditto.
431
432Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
433
434 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
435 bit mips16 igen simulator.
436 * configure: Re-generate.
437
438 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
439 as part of vr4100 ISA.
440 * vr.igen: Mark all instructions as 64 bit only.
441
442Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
443
444 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
445 Pacify GCC.
446
447Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
448
449 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
450 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
451 * configure: Re-generate.
452
453 * m16.igen (BREAK): Define breakpoint instruction.
454 (JALX32): Mark instruction as mips16 and not r3900.
455 * mips.igen (C.cond.fmt): Fix typo in instruction format.
456
457 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
458
459Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
460
461 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
462 insn as a debug breakpoint.
463
464 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
465 pending.slot_size.
466 (PENDING_SCHED): Clean up trace statement.
467 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
468 (PENDING_FILL): Delay write by only one cycle.
469 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
470
471 * sim-main.c (pending_tick): Clean up trace statements. Add trace
472 of pending writes.
473 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
474 32 & 64.
475 (pending_tick): Move incrementing of index to FOR statement.
476 (pending_tick): Only update PENDING_OUT after a write has occured.
477
478 * configure.in: Add explicit mips-lsi-* target. Use gencode to
479 build simulator.
480 * configure: Re-generate.
481
482 * interp.c (sim_engine_run OLD): Delete explicit call to
483 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
484
485Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
486
487 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
488 interrupt level number to match changed SignalExceptionInterrupt
489 macro.
490
491Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
492
493 * interp.c: #include "itable.h" if WITH_IGEN.
494 (get_insn_name): New function.
495 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
496 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
497
498Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
499
500 * configure: Rebuilt to inhale new common/aclocal.m4.
501
502Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
503
504 * dv-tx3904sio.c: Include sim-assert.h.
505
506Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
507
508 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
509 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
510 Reorganize target-specific sim-hardware checks.
511 * configure: rebuilt.
512 * interp.c (sim_open): For tx39 target boards, set
513 OPERATING_ENVIRONMENT, add tx3904sio devices.
514 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
515 ROM executables. Install dv-sockser into sim-modules list.
516
517 * dv-tx3904irc.c: Compiler warning clean-up.
518 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
519 frequent hw-trace messages.
520
521Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
522
523 * vr.igen (MulAcc): Identify as a vr4100 specific function.
524
525Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
526
527 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
528
529 * vr.igen: New file.
530 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
531 * mips.igen: Define vr4100 model. Include vr.igen.
532Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
533
534 * mips.igen (check_mf_hilo): Correct check.
535
536Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
537
538 * sim-main.h (interrupt_event): Add prototype.
539
540 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
541 register_ptr, register_value.
542 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
543
544 * sim-main.h (tracefh): Make extern.
545
546Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
547
548 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
549 Reduce unnecessarily high timer event frequency.
550 * dv-tx3904cpu.c: Ditto for interrupt event.
551
552Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
553
554 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
555 to allay warnings.
556 (interrupt_event): Made non-static.
557
558 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
559 interchange of configuration values for external vs. internal
560 clock dividers.
561
562Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
563
564 * mips.igen (BREAK): Moved code to here for
565 simulator-reserved break instructions.
566 * gencode.c (build_instruction): Ditto.
567 * interp.c (signal_exception): Code moved from here. Non-
568 reserved instructions now use exception vector, rather
569 than halting sim.
570 * sim-main.h: Moved magic constants to here.
571
572Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
573
574 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
575 register upon non-zero interrupt event level, clear upon zero
576 event value.
577 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
578 by passing zero event value.
579 (*_io_{read,write}_buffer): Endianness fixes.
580 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
581 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
582
583 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
584 serial I/O and timer module at base address 0xFFFF0000.
585
586Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
587
588 * mips.igen (SWC1) : Correct the handling of ReverseEndian
589 and BigEndianCPU.
590
591Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
592
593 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
594 parts.
595 * configure: Update.
596
597Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
598
599 * dv-tx3904tmr.c: New file - implements tx3904 timer.
600 * dv-tx3904{irc,cpu}.c: Mild reformatting.
601 * configure.in: Include tx3904tmr in hw_device list.
602 * configure: Rebuilt.
603 * interp.c (sim_open): Instantiate three timer instances.
604 Fix address typo of tx3904irc instance.
605
606Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
607
608 * interp.c (signal_exception): SystemCall exception now uses
609 the exception vector.
610
611Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
612
613 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
614 to allay warnings.
615
616Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
617
618 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
619
620Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
621
622 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
623
624 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
625 sim-main.h. Declare a struct hw_descriptor instead of struct
626 hw_device_descriptor.
627
628Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
629
630 * mips.igen (do_store_left, do_load_left): Compute nr of left and
631 right bits and then re-align left hand bytes to correct byte
632 lanes. Fix incorrect computation in do_store_left when loading
633 bytes from second word.
634
635Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
636
637 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
638 * interp.c (sim_open): Only create a device tree when HW is
639 enabled.
640
641 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
642 * interp.c (signal_exception): Ditto.
643
644Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
645
646 * gencode.c: Mark BEGEZALL as LIKELY.
647
648Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
649
650 * sim-main.h (ALU32_END): Sign extend 32 bit results.
651 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
652
653Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
654
655 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
656 modules. Recognize TX39 target with "mips*tx39" pattern.
657 * configure: Rebuilt.
658 * sim-main.h (*): Added many macros defining bits in
659 TX39 control registers.
660 (SignalInterrupt): Send actual PC instead of NULL.
661 (SignalNMIReset): New exception type.
662 * interp.c (board): New variable for future use to identify
663 a particular board being simulated.
664 (mips_option_handler,mips_options): Added "--board" option.
665 (interrupt_event): Send actual PC.
666 (sim_open): Make memory layout conditional on board setting.
667 (signal_exception): Initial implementation of hardware interrupt
668 handling. Accept another break instruction variant for simulator
669 exit.
670 (decode_coproc): Implement RFE instruction for TX39.
671 (mips.igen): Decode RFE instruction as such.
672 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
673 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
674 bbegin to implement memory map.
675 * dv-tx3904cpu.c: New file.
676 * dv-tx3904irc.c: New file.
677
678Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
679
680 * mips.igen (check_mt_hilo): Create a separate r3900 version.
681
682Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
683
684 * tx.igen (madd,maddu): Replace calls to check_op_hilo
685 with calls to check_div_hilo.
686
687Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
688
689 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
690 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
691 Add special r3900 version of do_mult_hilo.
692 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
693 with calls to check_mult_hilo.
694 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
695 with calls to check_div_hilo.
696
697Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
698
699 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
700 Document a replacement.
701
702Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
703
704 * interp.c (sim_monitor): Make mon_printf work.
705
706Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
707
708 * sim-main.h (INSN_NAME): New arg `cpu'.
709
710Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
711
712 * configure: Regenerated to track ../common/aclocal.m4 changes.
713
714Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
715
716 * configure: Regenerated to track ../common/aclocal.m4 changes.
717 * config.in: Ditto.
718
719Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
720
721 * acconfig.h: New file.
722 * configure.in: Reverted change of Apr 24; use sinclude again.
723
724Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
725
726 * configure: Regenerated to track ../common/aclocal.m4 changes.
727 * config.in: Ditto.
728
729Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
730
731 * configure.in: Don't call sinclude.
732
733Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
734
735 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
736
737Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
738
739 * mips.igen (ERET): Implement.
740
741 * interp.c (decode_coproc): Return sign-extended EPC.
742
743 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
744
745 * interp.c (signal_exception): Do not ignore Trap.
746 (signal_exception): On TRAP, restart at exception address.
747 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
748 (signal_exception): Update.
749 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
750 so that TRAP instructions are caught.
751
752Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
753
754 * sim-main.h (struct hilo_access, struct hilo_history): Define,
755 contains HI/LO access history.
756 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
757 (HIACCESS, LOACCESS): Delete, replace with
758 (HIHISTORY, LOHISTORY): New macros.
759 (CHECKHILO): Delete all, moved to mips.igen
760
761 * gencode.c (build_instruction): Do not generate checks for
762 correct HI/LO register usage.
763
764 * interp.c (old_engine_run): Delete checks for correct HI/LO
765 register usage.
766
767 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
768 check_mf_cycles): New functions.
769 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
770 do_divu, domultx, do_mult, do_multu): Use.
771
772 * tx.igen ("madd", "maddu"): Use.
773
774Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
775
776 * mips.igen (DSRAV): Use function do_dsrav.
777 (SRAV): Use new function do_srav.
778
779 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
780 (B): Sign extend 11 bit immediate.
781 (EXT-B*): Shift 16 bit immediate left by 1.
782 (ADDIU*): Don't sign extend immediate value.
783
784Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
785
786 * m16run.c (sim_engine_run): Restore CIA after handling an event.
787
788 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
789 functions.
790
791 * mips.igen (delayslot32, nullify_next_insn): New functions.
792 (m16.igen): Always include.
793 (do_*): Add more tracing.
794
795 * m16.igen (delayslot16): Add NIA argument, could be called by a
796 32 bit MIPS16 instruction.
797
798 * interp.c (ifetch16): Move function from here.
799 * sim-main.c (ifetch16): To here.
800
801 * sim-main.c (ifetch16, ifetch32): Update to match current
802 implementations of LH, LW.
803 (signal_exception): Don't print out incorrect hex value of illegal
804 instruction.
805
806Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
807
808 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
809 instruction.
810
811 * m16.igen: Implement MIPS16 instructions.
812
813 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
814 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
815 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
816 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
817 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
818 bodies of corresponding code from 32 bit insn to these. Also used
819 by MIPS16 versions of functions.
820
821 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
822 (IMEM16): Drop NR argument from macro.
823
824Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
825
826 * Makefile.in (SIM_OBJS): Add sim-main.o.
827
828 * sim-main.h (address_translation, load_memory, store_memory,
829 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
830 as INLINE_SIM_MAIN.
831 (pr_addr, pr_uword64): Declare.
832 (sim-main.c): Include when H_REVEALS_MODULE_P.
833
834 * interp.c (address_translation, load_memory, store_memory,
835 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
836 from here.
837 * sim-main.c: To here. Fix compilation problems.
838
839 * configure.in: Enable inlining.
840 * configure: Re-config.
841
842Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
843
844 * configure: Regenerated to track ../common/aclocal.m4 changes.
845
846Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
847
848 * mips.igen: Include tx.igen.
849 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
850 * tx.igen: New file, contains MADD and MADDU.
851
852 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
853 the hardwired constant `7'.
854 (store_memory): Ditto.
855 (LOADDRMASK): Move definition to sim-main.h.
856
857 mips.igen (MTC0): Enable for r3900.
858 (ADDU): Add trace.
859
860 mips.igen (do_load_byte): Delete.
861 (do_load, do_store, do_load_left, do_load_write, do_store_left,
862 do_store_right): New functions.
863 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
864
865 configure.in: Let the tx39 use igen again.
866 configure: Update.
867
868Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
869
870 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
871 not an address sized quantity. Return zero for cache sizes.
872
873Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
874
875 * mips.igen (r3900): r3900 does not support 64 bit integer
876 operations.
877
878Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
879
880 * configure.in (mipstx39*-*-*): Use gencode simulator rather
881 than igen one.
882 * configure : Rebuild.
883
884Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
885
886 * configure: Regenerated to track ../common/aclocal.m4 changes.
887
888Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
889
890 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
891
892Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
893
894 * configure: Regenerated to track ../common/aclocal.m4 changes.
895 * config.in: Regenerated to track ../common/aclocal.m4 changes.
896
897Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
898
899 * configure: Regenerated to track ../common/aclocal.m4 changes.
900
901Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
902
903 * interp.c (Max, Min): Comment out functions. Not yet used.
904
905Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
906
907 * configure: Regenerated to track ../common/aclocal.m4 changes.
908
909Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
910
911 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
912 configurable settings for stand-alone simulator.
913
914 * configure.in: Added X11 search, just in case.
915
916 * configure: Regenerated.
917
918Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
919
920 * interp.c (sim_write, sim_read, load_memory, store_memory):
921 Replace sim_core_*_map with read_map, write_map, exec_map resp.
922
923Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
924
925 * sim-main.h (GETFCC): Return an unsigned value.
926
927Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
928
929 * mips.igen (DIV): Fix check for -1 / MIN_INT.
930 (DADD): Result destination is RD not RT.
931
932Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
933
934 * sim-main.h (HIACCESS, LOACCESS): Always define.
935
936 * mdmx.igen (Maxi, Mini): Rename Max, Min.
937
938 * interp.c (sim_info): Delete.
939
940Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
941
942 * interp.c (DECLARE_OPTION_HANDLER): Use it.
943 (mips_option_handler): New argument `cpu'.
944 (sim_open): Update call to sim_add_option_table.
945
946Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
947
948 * mips.igen (CxC1): Add tracing.
949
950Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
951
952 * sim-main.h (Max, Min): Declare.
953
954 * interp.c (Max, Min): New functions.
955
956 * mips.igen (BC1): Add tracing.
957
958Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
959
960 * interp.c Added memory map for stack in vr4100
961
962Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
963
964 * interp.c (load_memory): Add missing "break"'s.
965
966Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
967
968 * interp.c (sim_store_register, sim_fetch_register): Pass in
969 length parameter. Return -1.
970
971Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
972
973 * interp.c: Added hardware init hook, fixed warnings.
974
975Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
976
977 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
978
979Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
980
981 * interp.c (ifetch16): New function.
982
983 * sim-main.h (IMEM32): Rename IMEM.
984 (IMEM16_IMMED): Define.
985 (IMEM16): Define.
986 (DELAY_SLOT): Update.
987
988 * m16run.c (sim_engine_run): New file.
989
990 * m16.igen: All instructions except LB.
991 (LB): Call do_load_byte.
992 * mips.igen (do_load_byte): New function.
993 (LB): Call do_load_byte.
994
995 * mips.igen: Move spec for insn bit size and high bit from here.
996 * Makefile.in (tmp-igen, tmp-m16): To here.
997
998 * m16.dc: New file, decode mips16 instructions.
999
1000 * Makefile.in (SIM_NO_ALL): Define.
1001 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1002
1003Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1004
1005 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1006 point unit to 32 bit registers.
1007 * configure: Re-generate.
1008
1009Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1010
1011 * configure.in (sim_use_gen): Make IGEN the default simulator
1012 generator for generic 32 and 64 bit mips targets.
1013 * configure: Re-generate.
1014
1015Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1016
1017 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1018 bitsize.
1019
1020 * interp.c (sim_fetch_register, sim_store_register): Read/write
1021 FGR from correct location.
1022 (sim_open): Set size of FGR's according to
1023 WITH_TARGET_FLOATING_POINT_BITSIZE.
1024
1025 * sim-main.h (FGR): Store floating point registers in a separate
1026 array.
1027
1028Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1029
1030 * configure: Regenerated to track ../common/aclocal.m4 changes.
1031
1032Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1033
1034 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1035
1036 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1037
1038 * interp.c (pending_tick): New function. Deliver pending writes.
1039
1040 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1041 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1042 it can handle mixed sized quantites and single bits.
1043
1044Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1045
1046 * interp.c (oengine.h): Do not include when building with IGEN.
1047 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1048 (sim_info): Ditto for PROCESSOR_64BIT.
1049 (sim_monitor): Replace ut_reg with unsigned_word.
1050 (*): Ditto for t_reg.
1051 (LOADDRMASK): Define.
1052 (sim_open): Remove defunct check that host FP is IEEE compliant,
1053 using software to emulate floating point.
1054 (value_fpr, ...): Always compile, was conditional on HASFPU.
1055
1056Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1057
1058 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1059 size.
1060
1061 * interp.c (SD, CPU): Define.
1062 (mips_option_handler): Set flags in each CPU.
1063 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1064 (sim_close): Do not clear STATE, deleted anyway.
1065 (sim_write, sim_read): Assume CPU zero's vm should be used for
1066 data transfers.
1067 (sim_create_inferior): Set the PC for all processors.
1068 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1069 argument.
1070 (mips16_entry): Pass correct nr of args to store_word, load_word.
1071 (ColdReset): Cold reset all cpu's.
1072 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1073 (sim_monitor, load_memory, store_memory, signal_exception): Use
1074 `CPU' instead of STATE_CPU.
1075
1076
1077 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1078 SD or CPU_.
1079
1080 * sim-main.h (signal_exception): Add sim_cpu arg.
1081 (SignalException*): Pass both SD and CPU to signal_exception.
1082 * interp.c (signal_exception): Update.
1083
1084 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1085 Ditto
1086 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1087 address_translation): Ditto
1088 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1089
1090Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1091
1092 * configure: Regenerated to track ../common/aclocal.m4 changes.
1093
1094Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1095
1096 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1097
1098 * mips.igen (model): Map processor names onto BFD name.
1099
1100 * sim-main.h (CPU_CIA): Delete.
1101 (SET_CIA, GET_CIA): Define
1102
1103Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1104
1105 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1106 regiser.
1107
1108 * configure.in (default_endian): Configure a big-endian simulator
1109 by default.
1110 * configure: Re-generate.
1111
1112Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1113
1114 * configure: Regenerated to track ../common/aclocal.m4 changes.
1115
1116Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1117
1118 * interp.c (sim_monitor): Handle Densan monitor outbyte
1119 and inbyte functions.
1120
11211997-12-29 Felix Lee <flee@cygnus.com>
1122
1123 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1124
1125Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1126
1127 * Makefile.in (tmp-igen): Arrange for $zero to always be
1128 reset to zero after every instruction.
1129
1130Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1131
1132 * configure: Regenerated to track ../common/aclocal.m4 changes.
1133 * config.in: Ditto.
1134
1135Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1136
1137 * mips.igen (MSUB): Fix to work like MADD.
1138 * gencode.c (MSUB): Similarly.
1139
1140Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1141
1142 * configure: Regenerated to track ../common/aclocal.m4 changes.
1143
1144Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1145
1146 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1147
1148Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1149
1150 * sim-main.h (sim-fpu.h): Include.
1151
1152 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1153 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1154 using host independant sim_fpu module.
1155
1156Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1157
1158 * interp.c (signal_exception): Report internal errors with SIGABRT
1159 not SIGQUIT.
1160
1161 * sim-main.h (C0_CONFIG): New register.
1162 (signal.h): No longer include.
1163
1164 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1165
1166Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1167
1168 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1169
1170Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1171
1172 * mips.igen: Tag vr5000 instructions.
1173 (ANDI): Was missing mipsIV model, fix assembler syntax.
1174 (do_c_cond_fmt): New function.
1175 (C.cond.fmt): Handle mips I-III which do not support CC field
1176 separatly.
1177 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1178 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1179 in IV3.2 spec.
1180 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1181 vr5000 which saves LO in a GPR separatly.
1182
1183 * configure.in (enable-sim-igen): For vr5000, select vr5000
1184 specific instructions.
1185 * configure: Re-generate.
1186
1187Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1188
1189 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1190
1191 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1192 fmt_uninterpreted_64 bit cases to switch. Convert to
1193 fmt_formatted,
1194
1195 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1196
1197 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1198 as specified in IV3.2 spec.
1199 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1200
1201Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1202
1203 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1204 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1205 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1206 PENDING_FILL versions of instructions. Simplify.
1207 (X): New function.
1208 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1209 instructions.
1210 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1211 a signed value.
1212 (MTHI, MFHI): Disable code checking HI-LO.
1213
1214 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1215 global.
1216 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1217
1218Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1219
1220 * gencode.c (build_mips16_operands): Replace IPC with cia.
1221
1222 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1223 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1224 IPC to `cia'.
1225 (UndefinedResult): Replace function with macro/function
1226 combination.
1227 (sim_engine_run): Don't save PC in IPC.
1228
1229 * sim-main.h (IPC): Delete.
1230
1231
1232 * interp.c (signal_exception, store_word, load_word,
1233 address_translation, load_memory, store_memory, cache_op,
1234 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1235 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1236 current instruction address - cia - argument.
1237 (sim_read, sim_write): Call address_translation directly.
1238 (sim_engine_run): Rename variable vaddr to cia.
1239 (signal_exception): Pass cia to sim_monitor
1240
1241 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1242 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1243 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1244
1245 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1246 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1247 SIM_ASSERT.
1248
1249 * interp.c (signal_exception): Pass restart address to
1250 sim_engine_restart.
1251
1252 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1253 idecode.o): Add dependency.
1254
1255 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1256 Delete definitions
1257 (DELAY_SLOT): Update NIA not PC with branch address.
1258 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1259
1260 * mips.igen: Use CIA not PC in branch calculations.
1261 (illegal): Call SignalException.
1262 (BEQ, ADDIU): Fix assembler.
1263
1264Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1265
1266 * m16.igen (JALX): Was missing.
1267
1268 * configure.in (enable-sim-igen): New configuration option.
1269 * configure: Re-generate.
1270
1271 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1272
1273 * interp.c (load_memory, store_memory): Delete parameter RAW.
1274 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1275 bypassing {load,store}_memory.
1276
1277 * sim-main.h (ByteSwapMem): Delete definition.
1278
1279 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1280
1281 * interp.c (sim_do_command, sim_commands): Delete mips specific
1282 commands. Handled by module sim-options.
1283
1284 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1285 (WITH_MODULO_MEMORY): Define.
1286
1287 * interp.c (sim_info): Delete code printing memory size.
1288
1289 * interp.c (mips_size): Nee sim_size, delete function.
1290 (power2): Delete.
1291 (monitor, monitor_base, monitor_size): Delete global variables.
1292 (sim_open, sim_close): Delete code creating monitor and other
1293 memory regions. Use sim-memopts module, via sim_do_commandf, to
1294 manage memory regions.
1295 (load_memory, store_memory): Use sim-core for memory model.
1296
1297 * interp.c (address_translation): Delete all memory map code
1298 except line forcing 32 bit addresses.
1299
1300Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1301
1302 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1303 trace options.
1304
1305 * interp.c (logfh, logfile): Delete globals.
1306 (sim_open, sim_close): Delete code opening & closing log file.
1307 (mips_option_handler): Delete -l and -n options.
1308 (OPTION mips_options): Ditto.
1309
1310 * interp.c (OPTION mips_options): Rename option trace to dinero.
1311 (mips_option_handler): Update.
1312
1313Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1314
1315 * interp.c (fetch_str): New function.
1316 (sim_monitor): Rewrite using sim_read & sim_write.
1317 (sim_open): Check magic number.
1318 (sim_open): Write monitor vectors into memory using sim_write.
1319 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1320 (sim_read, sim_write): Simplify - transfer data one byte at a
1321 time.
1322 (load_memory, store_memory): Clarify meaning of parameter RAW.
1323
1324 * sim-main.h (isHOST): Defete definition.
1325 (isTARGET): Mark as depreciated.
1326 (address_translation): Delete parameter HOST.
1327
1328 * interp.c (address_translation): Delete parameter HOST.
1329
1330Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1331
1332 * mips.igen:
1333
1334 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1335 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1336
1337Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1338
1339 * mips.igen: Add model filter field to records.
1340
1341Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1342
1343 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1344
1345 interp.c (sim_engine_run): Do not compile function sim_engine_run
1346 when WITH_IGEN == 1.
1347
1348 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1349 target architecture.
1350
1351 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1352 igen. Replace with configuration variables sim_igen_flags /
1353 sim_m16_flags.
1354
1355 * m16.igen: New file. Copy mips16 insns here.
1356 * mips.igen: From here.
1357
1358Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1359
1360 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1361 to top.
1362 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1363
1364Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1365
1366 * gencode.c (build_instruction): Follow sim_write's lead in using
1367 BigEndianMem instead of !ByteSwapMem.
1368
1369Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1370
1371 * configure.in (sim_gen): Dependent on target, select type of
1372 generator. Always select old style generator.
1373
1374 configure: Re-generate.
1375
1376 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1377 targets.
1378 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1379 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1380 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1381 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1382 SIM_@sim_gen@_*, set by autoconf.
1383
1384Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1385
1386 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1387
1388 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1389 CURRENT_FLOATING_POINT instead.
1390
1391 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1392 (address_translation): Raise exception InstructionFetch when
1393 translation fails and isINSTRUCTION.
1394
1395 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1396 sim_engine_run): Change type of of vaddr and paddr to
1397 address_word.
1398 (address_translation, prefetch, load_memory, store_memory,
1399 cache_op): Change type of vAddr and pAddr to address_word.
1400
1401 * gencode.c (build_instruction): Change type of vaddr and paddr to
1402 address_word.
1403
1404Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1405
1406 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1407 macro to obtain result of ALU op.
1408
1409Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1410
1411 * interp.c (sim_info): Call profile_print.
1412
1413Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1414
1415 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1416
1417 * sim-main.h (WITH_PROFILE): Do not define, defined in
1418 common/sim-config.h. Use sim-profile module.
1419 (simPROFILE): Delete defintion.
1420
1421 * interp.c (PROFILE): Delete definition.
1422 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1423 (sim_close): Delete code writing profile histogram.
1424 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1425 Delete.
1426 (sim_engine_run): Delete code profiling the PC.
1427
1428Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1429
1430 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1431
1432 * interp.c (sim_monitor): Make register pointers of type
1433 unsigned_word*.
1434
1435 * sim-main.h: Make registers of type unsigned_word not
1436 signed_word.
1437
1438Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1439
1440 * interp.c (sync_operation): Rename from SyncOperation, make
1441 global, add SD argument.
1442 (prefetch): Rename from Prefetch, make global, add SD argument.
1443 (decode_coproc): Make global.
1444
1445 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1446
1447 * gencode.c (build_instruction): Generate DecodeCoproc not
1448 decode_coproc calls.
1449
1450 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1451 (SizeFGR): Move to sim-main.h
1452 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1453 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1454 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1455 sim-main.h.
1456 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1457 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1458 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1459 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1460 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1461 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1462
1463 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1464 exception.
1465 (sim-alu.h): Include.
1466 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1467 (sim_cia): Typedef to instruction_address.
1468
1469Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1470
1471 * Makefile.in (interp.o): Rename generated file engine.c to
1472 oengine.c.
1473
1474 * interp.c: Update.
1475
1476Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1477
1478 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1479
1480Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1481
1482 * gencode.c (build_instruction): For "FPSQRT", output correct
1483 number of arguments to Recip.
1484
1485Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1486
1487 * Makefile.in (interp.o): Depends on sim-main.h
1488
1489 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1490
1491 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1492 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1493 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1494 STATE, DSSTATE): Define
1495 (GPR, FGRIDX, ..): Define.
1496
1497 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1498 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1499 (GPR, FGRIDX, ...): Delete macros.
1500
1501 * interp.c: Update names to match defines from sim-main.h
1502
1503Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1504
1505 * interp.c (sim_monitor): Add SD argument.
1506 (sim_warning): Delete. Replace calls with calls to
1507 sim_io_eprintf.
1508 (sim_error): Delete. Replace calls with sim_io_error.
1509 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1510 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1511 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1512 argument.
1513 (mips_size): Rename from sim_size. Add SD argument.
1514
1515 * interp.c (simulator): Delete global variable.
1516 (callback): Delete global variable.
1517 (mips_option_handler, sim_open, sim_write, sim_read,
1518 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1519 sim_size,sim_monitor): Use sim_io_* not callback->*.
1520 (sim_open): ZALLOC simulator struct.
1521 (PROFILE): Do not define.
1522
1523Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1524
1525 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1526 support.h with corresponding code.
1527
1528 * sim-main.h (word64, uword64), support.h: Move definition to
1529 sim-main.h.
1530 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1531
1532 * support.h: Delete
1533 * Makefile.in: Update dependencies
1534 * interp.c: Do not include.
1535
1536Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1537
1538 * interp.c (address_translation, load_memory, store_memory,
1539 cache_op): Rename to from AddressTranslation et.al., make global,
1540 add SD argument
1541
1542 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1543 CacheOp): Define.
1544
1545 * interp.c (SignalException): Rename to signal_exception, make
1546 global.
1547
1548 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1549
1550 * sim-main.h (SignalException, SignalExceptionInterrupt,
1551 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1552 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1553 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1554 Define.
1555
1556 * interp.c, support.h: Use.
1557
1558Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1559
1560 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1561 to value_fpr / store_fpr. Add SD argument.
1562 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1563 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1564
1565 * sim-main.h (ValueFPR, StoreFPR): Define.
1566
1567Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1568
1569 * interp.c (sim_engine_run): Check consistency between configure
1570 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1571 and HASFPU.
1572
1573 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1574 (mips_fpu): Configure WITH_FLOATING_POINT.
1575 (mips_endian): Configure WITH_TARGET_ENDIAN.
1576 * configure: Update.
1577
1578Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1579
1580 * configure: Regenerated to track ../common/aclocal.m4 changes.
1581
1582Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1583
1584 * configure: Regenerated.
1585
1586Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1587
1588 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1589
1590Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1591
1592 * gencode.c (print_igen_insn_models): Assume certain architectures
1593 include all mips* instructions.
1594 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1595 instruction.
1596
1597 * Makefile.in (tmp.igen): Add target. Generate igen input from
1598 gencode file.
1599
1600 * gencode.c (FEATURE_IGEN): Define.
1601 (main): Add --igen option. Generate output in igen format.
1602 (process_instructions): Format output according to igen option.
1603 (print_igen_insn_format): New function.
1604 (print_igen_insn_models): New function.
1605 (process_instructions): Only issue warnings and ignore
1606 instructions when no FEATURE_IGEN.
1607
1608Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1609
1610 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1611 MIPS targets.
1612
1613Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1614
1615 * configure: Regenerated to track ../common/aclocal.m4 changes.
1616
1617Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1620 SIM_RESERVED_BITS): Delete, moved to common.
1621 (SIM_EXTRA_CFLAGS): Update.
1622
1623Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1624
1625 * configure.in: Configure non-strict memory alignment.
1626 * configure: Regenerated to track ../common/aclocal.m4 changes.
1627
1628Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1629
1630 * configure: Regenerated to track ../common/aclocal.m4 changes.
1631
1632Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1633
1634 * gencode.c (SDBBP,DERET): Added (3900) insns.
1635 (RFE): Turn on for 3900.
1636 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1637 (dsstate): Made global.
1638 (SUBTARGET_R3900): Added.
1639 (CANCELDELAYSLOT): New.
1640 (SignalException): Ignore SystemCall rather than ignore and
1641 terminate. Add DebugBreakPoint handling.
1642 (decode_coproc): New insns RFE, DERET; and new registers Debug
1643 and DEPC protected by SUBTARGET_R3900.
1644 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1645 bits explicitly.
1646 * Makefile.in,configure.in: Add mips subtarget option.
1647 * configure: Update.
1648
1649Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1650
1651 * gencode.c: Add r3900 (tx39).
1652
1653
1654Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1655
1656 * gencode.c (build_instruction): Don't need to subtract 4 for
1657 JALR, just 2.
1658
1659Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1660
1661 * interp.c: Correct some HASFPU problems.
1662
1663Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1664
1665 * configure: Regenerated to track ../common/aclocal.m4 changes.
1666
1667Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1668
1669 * interp.c (mips_options): Fix samples option short form, should
1670 be `x'.
1671
1672Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1673
1674 * interp.c (sim_info): Enable info code. Was just returning.
1675
1676Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1677
1678 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1679 MFC0.
1680
1681Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1682
1683 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1684 constants.
1685 (build_instruction): Ditto for LL.
1686
1687Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1688
1689 * configure: Regenerated to track ../common/aclocal.m4 changes.
1690
1691Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1692
1693 * configure: Regenerated to track ../common/aclocal.m4 changes.
1694 * config.in: Ditto.
1695
1696Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1697
1698 * interp.c (sim_open): Add call to sim_analyze_program, update
1699 call to sim_config.
1700
1701Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1702
1703 * interp.c (sim_kill): Delete.
1704 (sim_create_inferior): Add ABFD argument. Set PC from same.
1705 (sim_load): Move code initializing trap handlers from here.
1706 (sim_open): To here.
1707 (sim_load): Delete, use sim-hload.c.
1708
1709 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1710
1711Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1712
1713 * configure: Regenerated to track ../common/aclocal.m4 changes.
1714 * config.in: Ditto.
1715
1716Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1717
1718 * interp.c (sim_open): Add ABFD argument.
1719 (sim_load): Move call to sim_config from here.
1720 (sim_open): To here. Check return status.
1721
1722Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1723
1724 * gencode.c (build_instruction): Two arg MADD should
1725 not assign result to $0.
1726
1727Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1728
1729 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1730 * sim/mips/configure.in: Regenerate.
1731
1732Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1733
1734 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1735 signed8, unsigned8 et.al. types.
1736
1737 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1738 hosts when selecting subreg.
1739
1740Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1741
1742 * interp.c (sim_engine_run): Reset the ZERO register to zero
1743 regardless of FEATURE_WARN_ZERO.
1744 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1745
1746Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1747
1748 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1749 (SignalException): For BreakPoints ignore any mode bits and just
1750 save the PC.
1751 (SignalException): Always set the CAUSE register.
1752
1753Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1754
1755 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1756 exception has been taken.
1757
1758 * interp.c: Implement the ERET and mt/f sr instructions.
1759
1760Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761
1762 * interp.c (SignalException): Don't bother restarting an
1763 interrupt.
1764
1765Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1766
1767 * interp.c (SignalException): Really take an interrupt.
1768 (interrupt_event): Only deliver interrupts when enabled.
1769
1770Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1771
1772 * interp.c (sim_info): Only print info when verbose.
1773 (sim_info) Use sim_io_printf for output.
1774
1775Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1776
1777 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1778 mips architectures.
1779
1780Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1781
1782 * interp.c (sim_do_command): Check for common commands if a
1783 simulator specific command fails.
1784
1785Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1786
1787 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1788 and simBE when DEBUG is defined.
1789
1790Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1791
1792 * interp.c (interrupt_event): New function. Pass exception event
1793 onto exception handler.
1794
1795 * configure.in: Check for stdlib.h.
1796 * configure: Regenerate.
1797
1798 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1799 variable declaration.
1800 (build_instruction): Initialize memval1.
1801 (build_instruction): Add UNUSED attribute to byte, bigend,
1802 reverse.
1803 (build_operands): Ditto.
1804
1805 * interp.c: Fix GCC warnings.
1806 (sim_get_quit_code): Delete.
1807
1808 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1809 * Makefile.in: Ditto.
1810 * configure: Re-generate.
1811
1812 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1813
1814Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1815
1816 * interp.c (mips_option_handler): New function parse argumes using
1817 sim-options.
1818 (myname): Replace with STATE_MY_NAME.
1819 (sim_open): Delete check for host endianness - performed by
1820 sim_config.
1821 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1822 (sim_open): Move much of the initialization from here.
1823 (sim_load): To here. After the image has been loaded and
1824 endianness set.
1825 (sim_open): Move ColdReset from here.
1826 (sim_create_inferior): To here.
1827 (sim_open): Make FP check less dependant on host endianness.
1828
1829 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1830 run.
1831 * interp.c (sim_set_callbacks): Delete.
1832
1833 * interp.c (membank, membank_base, membank_size): Replace with
1834 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1835 (sim_open): Remove call to callback->init. gdb/run do this.
1836
1837 * interp.c: Update
1838
1839 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1840
1841 * interp.c (big_endian_p): Delete, replaced by
1842 current_target_byte_order.
1843
1844Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1845
1846 * interp.c (host_read_long, host_read_word, host_swap_word,
1847 host_swap_long): Delete. Using common sim-endian.
1848 (sim_fetch_register, sim_store_register): Use H2T.
1849 (pipeline_ticks): Delete. Handled by sim-events.
1850 (sim_info): Update.
1851 (sim_engine_run): Update.
1852
1853Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1856 reason from here.
1857 (SignalException): To here. Signal using sim_engine_halt.
1858 (sim_stop_reason): Delete, moved to common.
1859
1860Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1861
1862 * interp.c (sim_open): Add callback argument.
1863 (sim_set_callbacks): Delete SIM_DESC argument.
1864 (sim_size): Ditto.
1865
1866Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1867
1868 * Makefile.in (SIM_OBJS): Add common modules.
1869
1870 * interp.c (sim_set_callbacks): Also set SD callback.
1871 (set_endianness, xfer_*, swap_*): Delete.
1872 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1873 Change to functions using sim-endian macros.
1874 (control_c, sim_stop): Delete, use common version.
1875 (simulate): Convert into.
1876 (sim_engine_run): This function.
1877 (sim_resume): Delete.
1878
1879 * interp.c (simulation): New variable - the simulator object.
1880 (sim_kind): Delete global - merged into simulation.
1881 (sim_load): Cleanup. Move PC assignment from here.
1882 (sim_create_inferior): To here.
1883
1884 * sim-main.h: New file.
1885 * interp.c (sim-main.h): Include.
1886
1887Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1888
1889 * configure: Regenerated to track ../common/aclocal.m4 changes.
1890
1891Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1892
1893 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1894
1895Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1896
1897 * gencode.c (build_instruction): DIV instructions: check
1898 for division by zero and integer overflow before using
1899 host's division operation.
1900
1901Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1902
1903 * Makefile.in (SIM_OBJS): Add sim-load.o.
1904 * interp.c: #include bfd.h.
1905 (target_byte_order): Delete.
1906 (sim_kind, myname, big_endian_p): New static locals.
1907 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1908 after argument parsing. Recognize -E arg, set endianness accordingly.
1909 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1910 load file into simulator. Set PC from bfd.
1911 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1912 (set_endianness): Use big_endian_p instead of target_byte_order.
1913
1914Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1915
1916 * interp.c (sim_size): Delete prototype - conflicts with
1917 definition in remote-sim.h. Correct definition.
1918
1919Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1920
1921 * configure: Regenerated to track ../common/aclocal.m4 changes.
1922 * config.in: Ditto.
1923
1924Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1925
1926 * interp.c (sim_open): New arg `kind'.
1927
1928 * configure: Regenerated to track ../common/aclocal.m4 changes.
1929
1930Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1931
1932 * configure: Regenerated to track ../common/aclocal.m4 changes.
1933
1934Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1935
1936 * interp.c (sim_open): Set optind to 0 before calling getopt.
1937
1938Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1939
1940 * configure: Regenerated to track ../common/aclocal.m4 changes.
1941
1942Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1943
1944 * interp.c : Replace uses of pr_addr with pr_uword64
1945 where the bit length is always 64 independent of SIM_ADDR.
1946 (pr_uword64) : added.
1947
1948Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1949
1950 * configure: Re-generate.
1951
1952Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1953
1954 * configure: Regenerate to track ../common/aclocal.m4 changes.
1955
1956Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1957
1958 * interp.c (sim_open): New SIM_DESC result. Argument is now
1959 in argv form.
1960 (other sim_*): New SIM_DESC argument.
1961
1962Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1963
1964 * interp.c: Fix printing of addresses for non-64-bit targets.
1965 (pr_addr): Add function to print address based on size.
1966
1967Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1968
1969 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1970
1971Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1972
1973 * gencode.c (build_mips16_operands): Correct computation of base
1974 address for extended PC relative instruction.
1975
1976Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1977
1978 * interp.c (mips16_entry): Add support for floating point cases.
1979 (SignalException): Pass floating point cases to mips16_entry.
1980 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1981 registers.
1982 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1983 or fmt_word.
1984 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1985 and then set the state to fmt_uninterpreted.
1986 (COP_SW): Temporarily set the state to fmt_word while calling
1987 ValueFPR.
1988
1989Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1990
1991 * gencode.c (build_instruction): The high order may be set in the
1992 comparison flags at any ISA level, not just ISA 4.
1993
1994Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1995
1996 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1997 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1998 * configure.in: sinclude ../common/aclocal.m4.
1999 * configure: Regenerated.
2000
2001Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2002
2003 * configure: Rebuild after change to aclocal.m4.
2004
2005Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2006
2007 * configure configure.in Makefile.in: Update to new configure
2008 scheme which is more compatible with WinGDB builds.
2009 * configure.in: Improve comment on how to run autoconf.
2010 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2011 * Makefile.in: Use autoconf substitution to install common
2012 makefile fragment.
2013
2014Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2015
2016 * gencode.c (build_instruction): Use BigEndianCPU instead of
2017 ByteSwapMem.
2018
2019Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2020
2021 * interp.c (sim_monitor): Make output to stdout visible in
2022 wingdb's I/O log window.
2023
2024Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2025
2026 * support.h: Undo previous change to SIGTRAP
2027 and SIGQUIT values.
2028
2029Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2030
2031 * interp.c (store_word, load_word): New static functions.
2032 (mips16_entry): New static function.
2033 (SignalException): Look for mips16 entry and exit instructions.
2034 (simulate): Use the correct index when setting fpr_state after
2035 doing a pending move.
2036
2037Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2038
2039 * interp.c: Fix byte-swapping code throughout to work on
2040 both little- and big-endian hosts.
2041
2042Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2043
2044 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2045 with gdb/config/i386/xm-windows.h.
2046
2047Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2048
2049 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2050 that messes up arithmetic shifts.
2051
2052Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2053
2054 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2055 SIGTRAP and SIGQUIT for _WIN32.
2056
2057Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2058
2059 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2060 force a 64 bit multiplication.
2061 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2062 destination register is 0, since that is the default mips16 nop
2063 instruction.
2064
2065Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2066
2067 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2068 (build_endian_shift): Don't check proc64.
2069 (build_instruction): Always set memval to uword64. Cast op2 to
2070 uword64 when shifting it left in memory instructions. Always use
2071 the same code for stores--don't special case proc64.
2072
2073 * gencode.c (build_mips16_operands): Fix base PC value for PC
2074 relative operands.
2075 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2076 jal instruction.
2077 * interp.c (simJALDELAYSLOT): Define.
2078 (JALDELAYSLOT): Define.
2079 (INDELAYSLOT, INJALDELAYSLOT): Define.
2080 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2081
2082Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2083
2084 * interp.c (sim_open): add flush_cache as a PMON routine
2085 (sim_monitor): handle flush_cache by ignoring it
2086
2087Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2088
2089 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2090 BigEndianMem.
2091 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2092 (BigEndianMem): Rename to ByteSwapMem and change sense.
2093 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2094 BigEndianMem references to !ByteSwapMem.
2095 (set_endianness): New function, with prototype.
2096 (sim_open): Call set_endianness.
2097 (sim_info): Use simBE instead of BigEndianMem.
2098 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2099 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2100 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2101 ifdefs, keeping the prototype declaration.
2102 (swap_word): Rewrite correctly.
2103 (ColdReset): Delete references to CONFIG. Delete endianness related
2104 code; moved to set_endianness.
2105
2106Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2107
2108 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2109 * interp.c (CHECKHILO): Define away.
2110 (simSIGINT): New macro.
2111 (membank_size): Increase from 1MB to 2MB.
2112 (control_c): New function.
2113 (sim_resume): Rename parameter signal to signal_number. Add local
2114 variable prev. Call signal before and after simulate.
2115 (sim_stop_reason): Add simSIGINT support.
2116 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2117 functions always.
2118 (sim_warning): Delete call to SignalException. Do call printf_filtered
2119 if logfh is NULL.
2120 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2121 a call to sim_warning.
2122
2123Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2124
2125 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2126 16 bit instructions.
2127
2128Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2129
2130 Add support for mips16 (16 bit MIPS implementation):
2131 * gencode.c (inst_type): Add mips16 instruction encoding types.
2132 (GETDATASIZEINSN): Define.
2133 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2134 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2135 mtlo.
2136 (MIPS16_DECODE): New table, for mips16 instructions.
2137 (bitmap_val): New static function.
2138 (struct mips16_op): Define.
2139 (mips16_op_table): New table, for mips16 operands.
2140 (build_mips16_operands): New static function.
2141 (process_instructions): If PC is odd, decode a mips16
2142 instruction. Break out instruction handling into new
2143 build_instruction function.
2144 (build_instruction): New static function, broken out of
2145 process_instructions. Check modifiers rather than flags for SHIFT
2146 bit count and m[ft]{hi,lo} direction.
2147 (usage): Pass program name to fprintf.
2148 (main): Remove unused variable this_option_optind. Change
2149 ``*loptarg++'' to ``loptarg++''.
2150 (my_strtoul): Parenthesize && within ||.
2151 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2152 (simulate): If PC is odd, fetch a 16 bit instruction, and
2153 increment PC by 2 rather than 4.
2154 * configure.in: Add case for mips16*-*-*.
2155 * configure: Rebuild.
2156
2157Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2158
2159 * interp.c: Allow -t to enable tracing in standalone simulator.
2160 Fix garbage output in trace file and error messages.
2161
2162Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2163
2164 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2165 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2166 * configure.in: Simplify using macros in ../common/aclocal.m4.
2167 * configure: Regenerated.
2168 * tconfig.in: New file.
2169
2170Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2171
2172 * interp.c: Fix bugs in 64-bit port.
2173 Use ansi function declarations for msvc compiler.
2174 Initialize and test file pointer in trace code.
2175 Prevent duplicate definition of LAST_EMED_REGNUM.
2176
2177Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2178
2179 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2180
2181Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2182
2183 * interp.c (SignalException): Check for explicit terminating
2184 breakpoint value.
2185 * gencode.c: Pass instruction value through SignalException()
2186 calls for Trap, Breakpoint and Syscall.
2187
2188Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2189
2190 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2191 only used on those hosts that provide it.
2192 * configure.in: Add sqrt() to list of functions to be checked for.
2193 * config.in: Re-generated.
2194 * configure: Re-generated.
2195
2196Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2197
2198 * gencode.c (process_instructions): Call build_endian_shift when
2199 expanding STORE RIGHT, to fix swr.
2200 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2201 clear the high bits.
2202 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2203 Fix float to int conversions to produce signed values.
2204
2205Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2206
2207 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2208 (process_instructions): Correct handling of nor instruction.
2209 Correct shift count for 32 bit shift instructions. Correct sign
2210 extension for arithmetic shifts to not shift the number of bits in
2211 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2212 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2213 Fix madd.
2214 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2215 It's OK to have a mult follow a mult. What's not OK is to have a
2216 mult follow an mfhi.
2217 (Convert): Comment out incorrect rounding code.
2218
2219Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2220
2221 * interp.c (sim_monitor): Improved monitor printf
2222 simulation. Tidied up simulator warnings, and added "--log" option
2223 for directing warning message output.
2224 * gencode.c: Use sim_warning() rather than WARNING macro.
2225
2226Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2227
2228 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2229 getopt1.o, rather than on gencode.c. Link objects together.
2230 Don't link against -liberty.
2231 (gencode.o, getopt.o, getopt1.o): New targets.
2232 * gencode.c: Include <ctype.h> and "ansidecl.h".
2233 (AND): Undefine after including "ansidecl.h".
2234 (ULONG_MAX): Define if not defined.
2235 (OP_*): Don't define macros; now defined in opcode/mips.h.
2236 (main): Call my_strtoul rather than strtoul.
2237 (my_strtoul): New static function.
2238
2239Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2240
2241 * gencode.c (process_instructions): Generate word64 and uword64
2242 instead of `long long' and `unsigned long long' data types.
2243 * interp.c: #include sysdep.h to get signals, and define default
2244 for SIGBUS.
2245 * (Convert): Work around for Visual-C++ compiler bug with type
2246 conversion.
2247 * support.h: Make things compile under Visual-C++ by using
2248 __int64 instead of `long long'. Change many refs to long long
2249 into word64/uword64 typedefs.
2250
2251Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2252
2253 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2254 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2255 (docdir): Removed.
2256 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2257 (AC_PROG_INSTALL): Added.
2258 (AC_PROG_CC): Moved to before configure.host call.
2259 * configure: Rebuilt.
2260
2261Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2262
2263 * configure.in: Define @SIMCONF@ depending on mips target.
2264 * configure: Rebuild.
2265 * Makefile.in (run): Add @SIMCONF@ to control simulator
2266 construction.
2267 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2268 * interp.c: Remove some debugging, provide more detailed error
2269 messages, update memory accesses to use LOADDRMASK.
2270
2271Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2272
2273 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2274 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2275 stamp-h.
2276 * configure: Rebuild.
2277 * config.in: New file, generated by autoheader.
2278 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2279 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2280 HAVE_ANINT and HAVE_AINT, as appropriate.
2281 * Makefile.in (run): Use @LIBS@ rather than -lm.
2282 (interp.o): Depend upon config.h.
2283 (Makefile): Just rebuild Makefile.
2284 (clean): Remove stamp-h.
2285 (mostlyclean): Make the same as clean, not as distclean.
2286 (config.h, stamp-h): New targets.
2287
2288Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2289
2290 * interp.c (ColdReset): Fix boolean test. Make all simulator
2291 globals static.
2292
2293Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2294
2295 * interp.c (xfer_direct_word, xfer_direct_long,
2296 swap_direct_word, swap_direct_long, xfer_big_word,
2297 xfer_big_long, xfer_little_word, xfer_little_long,
2298 swap_word,swap_long): Added.
2299 * interp.c (ColdReset): Provide function indirection to
2300 host<->simulated_target transfer routines.
2301 * interp.c (sim_store_register, sim_fetch_register): Updated to
2302 make use of indirected transfer routines.
2303
2304Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2305
2306 * gencode.c (process_instructions): Ensure FP ABS instruction
2307 recognised.
2308 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2309 system call support.
2310
2311Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2312
2313 * interp.c (sim_do_command): Complain if callback structure not
2314 initialised.
2315
2316Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2317
2318 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2319 support for Sun hosts.
2320 * Makefile.in (gencode): Ensure the host compiler and libraries
2321 used for cross-hosted build.
2322
2323Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2324
2325 * interp.c, gencode.c: Some more (TODO) tidying.
2326
2327Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2328
2329 * gencode.c, interp.c: Replaced explicit long long references with
2330 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2331 * support.h (SET64LO, SET64HI): Macros added.
2332
2333Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2334
2335 * configure: Regenerate with autoconf 2.7.
2336
2337Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2338
2339 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2340 * support.h: Remove superfluous "1" from #if.
2341 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2342
2343Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2344
2345 * interp.c (StoreFPR): Control UndefinedResult() call on
2346 WARN_RESULT manifest.
2347
2348Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2349
2350 * gencode.c: Tidied instruction decoding, and added FP instruction
2351 support.
2352
2353 * interp.c: Added dineroIII, and BSD profiling support. Also
2354 run-time FP handling.
2355
2356Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2357
2358 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2359 gencode.c, interp.c, support.h: created.
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