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Commit | Line | Data |
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c906108c | 1 | #include "sim-main.h" |
61a0c964 | 2 | #include "sim-syscall.h" |
c906108c SS |
3 | #include "targ-vals.h" |
4 | ||
5 | #ifdef HAVE_UTIME_H | |
6 | #include <utime.h> | |
7 | #endif | |
c906108c | 8 | #include <time.h> |
c906108c SS |
9 | #ifdef HAVE_UNISTD_H |
10 | #include <unistd.h> | |
11 | #endif | |
c906108c | 12 | #include <string.h> |
c906108c SS |
13 | #include <sys/stat.h> |
14 | #include <sys/times.h> | |
15 | #include <sys/time.h> | |
16 | ||
17 | ||
18 | ||
19 | #define REG0(X) ((X) & 0x3) | |
20 | #define REG1(X) (((X) & 0xc) >> 2) | |
21 | #define REG0_4(X) (((X) & 0x30) >> 4) | |
22 | #define REG0_8(X) (((X) & 0x300) >> 8) | |
23 | #define REG1_8(X) (((X) & 0xc00) >> 10) | |
24 | #define REG0_16(X) (((X) & 0x30000) >> 16) | |
25 | #define REG1_16(X) (((X) & 0xc0000) >> 18) | |
26 | ||
27 | ||
28 | INLINE_SIM_MAIN (void) | |
24a39d88 | 29 | genericAdd(unsigned32 source, unsigned32 destReg) |
c906108c SS |
30 | { |
31 | int z, c, n, v; | |
24a39d88 | 32 | unsigned32 dest, sum; |
c906108c SS |
33 | |
34 | dest = State.regs[destReg]; | |
35 | sum = source + dest; | |
36 | State.regs[destReg] = sum; | |
37 | ||
38 | z = (sum == 0); | |
39 | n = (sum & 0x80000000); | |
40 | c = (sum < source) || (sum < dest); | |
41 | v = ((dest & 0x80000000) == (source & 0x80000000) | |
42 | && (dest & 0x80000000) != (sum & 0x80000000)); | |
43 | ||
44 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
45 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
46 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
47 | } | |
48 | ||
49 | ||
50 | ||
51 | ||
52 | INLINE_SIM_MAIN (void) | |
24a39d88 | 53 | genericSub(unsigned32 source, unsigned32 destReg) |
c906108c SS |
54 | { |
55 | int z, c, n, v; | |
24a39d88 | 56 | unsigned32 dest, difference; |
c906108c SS |
57 | |
58 | dest = State.regs[destReg]; | |
59 | difference = dest - source; | |
60 | State.regs[destReg] = difference; | |
61 | ||
62 | z = (difference == 0); | |
63 | n = (difference & 0x80000000); | |
64 | c = (source > dest); | |
65 | v = ((dest & 0x80000000) != (source & 0x80000000) | |
66 | && (dest & 0x80000000) != (difference & 0x80000000)); | |
67 | ||
68 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
69 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
70 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
71 | } | |
72 | ||
73 | INLINE_SIM_MAIN (void) | |
24a39d88 | 74 | genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd) |
c906108c SS |
75 | { |
76 | int z, c, n, v; | |
24a39d88 | 77 | unsigned32 value; |
c906108c SS |
78 | |
79 | value = rightOpnd - leftOpnd; | |
80 | ||
81 | z = (value == 0); | |
82 | n = (value & 0x80000000); | |
83 | c = (leftOpnd > rightOpnd); | |
84 | v = ((rightOpnd & 0x80000000) != (leftOpnd & 0x80000000) | |
85 | && (rightOpnd & 0x80000000) != (value & 0x80000000)); | |
86 | ||
87 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
88 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
89 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
90 | } | |
91 | ||
92 | ||
93 | INLINE_SIM_MAIN (void) | |
24a39d88 | 94 | genericOr(unsigned32 source, unsigned32 destReg) |
c906108c SS |
95 | { |
96 | int n, z; | |
97 | ||
98 | State.regs[destReg] |= source; | |
99 | z = (State.regs[destReg] == 0); | |
100 | n = (State.regs[destReg] & 0x80000000) != 0; | |
101 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
102 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
103 | } | |
104 | ||
105 | ||
106 | INLINE_SIM_MAIN (void) | |
24a39d88 | 107 | genericXor(unsigned32 source, unsigned32 destReg) |
c906108c SS |
108 | { |
109 | int n, z; | |
110 | ||
111 | State.regs[destReg] ^= source; | |
112 | z = (State.regs[destReg] == 0); | |
113 | n = (State.regs[destReg] & 0x80000000) != 0; | |
114 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
115 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
116 | } | |
117 | ||
118 | ||
119 | INLINE_SIM_MAIN (void) | |
24a39d88 | 120 | genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd) |
c906108c | 121 | { |
24a39d88 | 122 | unsigned32 temp; |
c906108c SS |
123 | int z, n; |
124 | ||
125 | temp = rightOpnd; | |
126 | temp &= leftOpnd; | |
127 | n = (temp & 0x80000000) != 0; | |
128 | z = (temp == 0); | |
129 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
130 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
131 | } | |
132 | ||
c906108c SS |
133 | /* syscall */ |
134 | INLINE_SIM_MAIN (void) | |
489503ee | 135 | do_syscall (void) |
c906108c | 136 | { |
7d5c6c43 MF |
137 | /* Registers passed to trap 0. */ |
138 | ||
139 | /* Function number. */ | |
140 | reg_t func = State.regs[0]; | |
141 | /* Parameters. */ | |
142 | reg_t parm1 = State.regs[1]; | |
143 | reg_t parm2 = load_word (State.regs[REG_SP] + 12); | |
144 | reg_t parm3 = load_word (State.regs[REG_SP] + 16); | |
145 | reg_t parm4 = load_word (State.regs[REG_SP] + 20); | |
c906108c SS |
146 | |
147 | /* We use this for simulated system calls; we may need to change | |
148 | it to a reserved instruction if we conflict with uses at | |
149 | Matsushita. */ | |
150 | int save_errno = errno; | |
151 | errno = 0; | |
152 | ||
7d5c6c43 | 153 | if (func == TARGET_SYS_exit) |
c906108c | 154 | { |
7d5c6c43 | 155 | /* EXIT - caller can look in parm1 to work out the reason */ |
96eaf29e | 156 | sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, |
7d5c6c43 | 157 | (parm1 == 0xdead ? SIM_SIGABRT : sim_exited), parm1); |
c906108c SS |
158 | } |
159 | else | |
160 | { | |
7d5c6c43 MF |
161 | long result, result2; |
162 | int errcode; | |
c906108c | 163 | |
7d5c6c43 MF |
164 | sim_syscall_multi (STATE_CPU (simulator, 0), func, parm1, parm2, |
165 | parm3, parm4, &result, &result2, &errcode); | |
166 | ||
167 | /* Registers set by trap 0. */ | |
168 | State.regs[0] = errcode; | |
169 | State.regs[1] = result; | |
170 | } | |
c906108c SS |
171 | |
172 | errno = save_errno; | |
173 | } |