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sim: msp430: set initial PC to ELF entry if available
[thirdparty/binutils-gdb.git] / sim / msp430 / msp430-sim.c
CommitLineData
3346cfda
NC		 1/* Simulator for TI MSP430 and MSP430X
2
ecd75fc8 3 Copyright (C) 2013-2014 Free Software Foundation, Inc.
3346cfda
NC		 4 Contributed by Red Hat.
5 Based on sim/bfin/bfin-sim.c which was contributed by Analog Devices, Inc.
6
7 This file is part of simulators.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "config.h"
23#include <stdio.h>
24#include <stdlib.h>
25#include <string.h>
26#include <inttypes.h>
27#include <assert.h>
28#include "bfd.h"
29#include "opcode/msp430-decode.h"
30#include "sim-main.h"
31#include "dis-asm.h"
32#include "targ-vals.h"
33
34static int
35loader_write_mem (SIM_DESC sd,
36 SIM_ADDR taddr,
37 const unsigned char *buf,
38 int bytes)
39{
40 SIM_CPU *cpu = MSP430_CPU (sd);
41 return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
42}
43
44static sim_cia
45msp430_pc_fetch (SIM_CPU *cpu)
46{
47 return cpu->state.regs[0];
48}
49
50static void
51msp430_pc_store (SIM_CPU *cpu, sim_cia newpc)
52{
53 cpu->state.regs[0] = newpc;
54}
55
56static long
57lookup_symbol (SIM_DESC sd, const char *name)
58{
59 struct bfd *abfd = STATE_PROG_BFD (sd);
60 asymbol **symbol_table = STATE_SYMBOL_TABLE (sd);
61 long number_of_symbols = STATE_NUM_SYMBOLS (sd);
62 long i;
63
64 if (symbol_table == NULL)
65 {
66 long storage_needed;
67
68 storage_needed = bfd_get_symtab_upper_bound (abfd);
69 if (storage_needed <= 0)
70 return -1;
71
72 STATE_SYMBOL_TABLE (sd) = symbol_table = xmalloc (storage_needed);
73 STATE_NUM_SYMBOLS (sd) = number_of_symbols =
74 bfd_canonicalize_symtab (abfd, symbol_table);
75 }
76
77 for (i = 0; i < number_of_symbols; i++)
78 if (strcmp (symbol_table[i]->name, name) == 0)
79 {
80 long val = symbol_table[i]->section->vma + symbol_table[i]->value;
81 return val;
82 }
83 return -1;
84}
85
86static int
87msp430_reg_fetch (SIM_CPU *cpu, int regno, unsigned char *buf, int len)
88{
89 if (0 <= regno && regno < 16)
90 {
91 if (len == 2)
92 {
93 int val = cpu->state.regs[regno];
94 buf[0] = val & 0xff;
95 buf[1] = (val >> 8) & 0xff;
96 return 0;
97 }
98 else if (len == 4)
99 {
100 int val = cpu->state.regs[regno];
101 buf[0] = val & 0xff;
102 buf[1] = (val >> 8) & 0xff;
103 buf[2] = (val >> 16) & 0x0f; /* Registers are only 20 bits wide. */
104 buf[3] = 0;
105 return 0;
106 }
107 else
108 return -1;
109 }
110 else
111 return -1;
112}
113
114static int
115msp430_reg_store (SIM_CPU *cpu, int regno, unsigned char *buf, int len)
116{
117 if (0 <= regno && regno < 16)
118 {
119 if (len == 2)
120 {
121 cpu->state.regs[regno] = (buf[1] << 8) | buf[0];
122 return len;
123 }
124
125 if (len == 4)
126 {
127 cpu->state.regs[regno] = ((buf[2] << 16) & 0xf0000)
128 | (buf[1] << 8) | buf[0];
129 return len;
130 }
131 }
132
133 return -1;
134}
135
136static inline void
137msp430_initialize_cpu (SIM_DESC sd, SIM_CPU *cpu)
138{
139 memset (&cpu->state, 0, sizeof (cpu->state));
140}
141
142SIM_DESC
143sim_open (SIM_OPEN_KIND kind,
144 struct host_callback_struct *callback,
145 struct bfd *abfd,
146 char **argv)
147{
148 SIM_DESC sd = sim_state_alloc (kind, callback);
149 char c;
150 struct bfd *prog_bfd;
151
152 /* Initialise the simulator. */
153
154 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
155 {
156 sim_state_free (sd);
157 return 0;
158 }
159
160 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
161 {
162 sim_state_free (sd);
163 return 0;
164 }
165
166 if (sim_parse_args (sd, argv) != SIM_RC_OK)
167 {
168 sim_state_free (sd);
169 return 0;
170 }
171
172 CPU_PC_FETCH (MSP430_CPU (sd)) = msp430_pc_fetch;
173 CPU_PC_STORE (MSP430_CPU (sd)) = msp430_pc_store;
174 CPU_REG_FETCH (MSP430_CPU (sd)) = msp430_reg_fetch;
175 CPU_REG_STORE (MSP430_CPU (sd)) = msp430_reg_store;
176
177 /* Allocate memory if none specified by user. */
178 if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x200, 1) == 0)
179 sim_do_commandf (sd, "memory-region 0,0x10000");
180 if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0xfffe, 1) == 0)
181 sim_do_commandf (sd, "memory-region 0xfffe,2");
182 if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x10000, 1) == 0)
183 sim_do_commandf (sd, "memory-region 0x10000,0x100000");
184
185 /* Check for/establish the a reference program image. */
186 if (sim_analyze_program (sd,
187 (STATE_PROG_ARGV (sd) != NULL
188 ? *STATE_PROG_ARGV (sd)
189 : NULL), abfd) != SIM_RC_OK)
190 {
191 sim_state_free (sd);
192 return 0;
193 }
194
195 prog_bfd = sim_load_file (sd, argv[0], callback,
196 "the program",
197 STATE_PROG_BFD (sd),
198 0 /* verbose */,
199 1 /* use LMA instead of VMA */,
200 loader_write_mem);
201 if (prog_bfd == NULL)
202 {
203 sim_state_free (sd);
204 return 0;
205 }
206
207 /* Establish any remaining configuration options. */
208 if (sim_config (sd) != SIM_RC_OK)
209 {
210 sim_state_free (sd);
211 return 0;
212 }
213
214 if (sim_post_argv_init (sd) != SIM_RC_OK)
215 {
216 sim_state_free (sd);
217 return 0;
218 }
219
220 /* CPU specific initialization. */
221 assert (MAX_NR_PROCESSORS == 1);
222 msp430_initialize_cpu (sd, MSP430_CPU (sd));
223
224 msp430_trace_init (STATE_PROG_BFD (sd));
225
226 MSP430_CPU (sd)->state.cio_breakpoint = lookup_symbol (sd, "C$$IO$$");
227 MSP430_CPU (sd)->state.cio_buffer = lookup_symbol (sd, "__CIOBUF__");
228 if (MSP430_CPU (sd)->state.cio_buffer == -1)
229 MSP430_CPU (sd)->state.cio_buffer = lookup_symbol (sd, "_CIOBUF_");
230
231 return sd;
232}
233
234void
235sim_close (SIM_DESC sd,
236 int quitting)
237{
238 free (STATE_SYMBOL_TABLE (sd));
239 sim_state_free (sd);
240}
241
242SIM_RC
243sim_create_inferior (SIM_DESC sd,
244 struct bfd *abfd,
245 char **argv,
246 char **env)
247{
248 unsigned char resetv[2];
249 int c;
250 int new_pc;
251
7b0278dc 252 /* Set the PC to the default reset vector if available. */
3346cfda 253 c = sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, resetv, 0xfffe, 2);
3346cfda 254 new_pc = resetv[0] + 256 * resetv[1];
7b0278dc
MF		 255
256 /* If the reset vector isn't initialized, then use the ELF entry. */
257 if (abfd != NULL && !new_pc)
258 new_pc = bfd_get_start_address (abfd);
259
3346cfda
NC		 260 sim_pc_set (MSP430_CPU (sd), new_pc);
261 msp430_pc_store (MSP430_CPU (sd), new_pc);
262
263 return SIM_RC_OK;
264}
265
266typedef struct
267{
268 SIM_DESC sd;
269 int gb_addr;
270} Get_Byte_Local_Data;
271
272static int
273msp430_getbyte (void *vld)
274{
275 Get_Byte_Local_Data *ld = (Get_Byte_Local_Data *)vld;
276 char buf[1];
277 SIM_DESC sd = ld->sd;
278
279 sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, ld->gb_addr, 1);
280 ld->gb_addr ++;
281 return buf[0];
282}
283
284#define REG(N) MSP430_CPU (sd)->state.regs[(N)]
285#define PC REG(MSR_PC)
286#define SP REG(MSR_SP)
287#define SR REG(MSR_SR)
288
289static const char *
290register_names[] =
291{
292 "PC", "SP", "SR", "CG", "R4", "R5", "R6", "R7", "R8",
293 "R9", "R10", "R11", "R12", "R13", "R14", "R15"
294};
295
296static void
297trace_reg_put (SIM_DESC sd, int n, unsigned int v)
298{
299 if (TRACE_VPU_P (MSP430_CPU (sd)))
300 trace_generic (sd, MSP430_CPU (sd), TRACE_VPU_IDX,
301 "PUT: %#x -> %s", v, register_names [n]);
302 REG (n) = v;
303}
304
305static unsigned int
306trace_reg_get (SIM_DESC sd, int n)
307{
308 if (TRACE_VPU_P (MSP430_CPU (sd)))
309 trace_generic (sd, MSP430_CPU (sd), TRACE_VPU_IDX,
310 "GET: %s -> %#x", register_names [n], REG (n));
311 return REG (n);
312}
313
314#define REG_PUT(N,V) trace_reg_put (sd, N, V)
315#define REG_GET(N) trace_reg_get (sd, N)
316
317static int
318get_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n)
319{
320 MSP430_Opcode_Operand *op = opc->op + n;
321 int rv;
322 int addr;
323 unsigned char buf[4];
324 int incval = 0;
325
326 switch (op->type)
327 {
328 case MSP430_Operand_Immediate:
329 rv = op->addend;
330 break;
331 case MSP430_Operand_Register:
332 rv = REG_GET (op->reg);
333 break;
334 case MSP430_Operand_Indirect:
335 case MSP430_Operand_Indirect_Postinc:
336 addr = op->addend;
337 if (op->reg != MSR_None)
338 {
339 int reg;
340 /* Index values are signed, but the sum is limited to 16
341 bits if the register < 64k, for MSP430 compatibility in
342 MSP430X chips. */
343 if (addr & 0x8000)
344 addr |= -1 << 16;
345 reg = REG_GET (op->reg);
346 addr += reg;
347 if (reg < 0x10000 && ! opc->ofs_430x)
348 addr &= 0xffff;
349 }
350 addr &= 0xfffff;
351 switch (opc->size)
352 {
353 case 8:
354 sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 1);
355 rv = buf[0];
356 break;
357 case 16:
358 sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 2);
359 rv = buf[0] | (buf[1] << 8);
360 break;
361 case 20:
362 case 32:
363 sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 4);
364 rv = buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
365 break;
366 default:
367 assert (! opc->size);
368 break;
369 }
370#if 0
371 /* Hack - MSP430X5438 serial port status register. */
372 if (addr == 0x5dd)
373 rv = 2;
374#endif
375 if (TRACE_MEMORY_P (MSP430_CPU (sd)))
376 trace_generic (sd, MSP430_CPU (sd), TRACE_MEMORY_IDX,
377 "GET: [%#x].%d -> %#x", addr, opc->size, rv);
378 break;
379 default:
380 fprintf (stderr, "invalid operand %d type %d\n", n, op->type);
381 abort ();
382 }
383
384 switch (opc->size)
385 {
386 case 8:
387 rv &= 0xff;
388 incval = 1;
389 break;
390 case 16:
391 rv &= 0xffff;
392 incval = 2;
393 break;
394 case 20:
395 rv &= 0xfffff;
396 incval = 4;
397 break;
398 case 32:
399 rv &= 0xffffffff;
400 incval = 4;
401 break;
402 }
403
404 if (op->type == MSP430_Operand_Indirect_Postinc)
405 REG_PUT (op->reg, REG_GET (op->reg) + incval);
406
407 return rv;
408}
409
410static int
411put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val)
412{
413 MSP430_Opcode_Operand *op = opc->op + n;
414 int rv;
415 int addr;
416 unsigned char buf[4];
417 int incval = 0;
418
419 switch (opc->size)
420 {
421 case 8:
422 val &= 0xff;
423 break;
424 case 16:
425 val &= 0xffff;
426 break;
427 case 20:
428 val &= 0xfffff;
429 break;
430 case 32:
431 val &= 0xffffffff;
432 break;
433 }
434
435 switch (op->type)
436 {
437 case MSP430_Operand_Register:
438 REG (op->reg) = val;
439 REG_PUT (op->reg, val);
440 break;
441 case MSP430_Operand_Indirect:
442 case MSP430_Operand_Indirect_Postinc:
443 addr = op->addend;
444 if (op->reg != MSR_None)
445 {
446 int reg;
447 /* Index values are signed, but the sum is limited to 16
448 bits if the register < 64k, for MSP430 compatibility in
449 MSP430X chips. */
450 if (addr & 0x8000)
451 addr |= -1 << 16;
452 reg = REG_GET (op->reg);
453 addr += reg;
454 if (reg < 0x10000)
455 addr &= 0xffff;
456 }
457 addr &= 0xfffff;
458
459 if (TRACE_MEMORY_P (MSP430_CPU (sd)))
460 trace_generic (sd, MSP430_CPU (sd), TRACE_MEMORY_IDX,
461 "PUT: [%#x].%d <- %#x", addr, opc->size, val);
462#if 0
463 /* Hack - MSP430X5438 serial port transmit register. */
464 if (addr == 0x5ce)
465 putchar (val);
466#endif
467 switch (opc->size)
468 {
469 case 8:
470 buf[0] = val;
471 sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 1);
472 break;
473 case 16:
474 buf[0] = val;
475 buf[1] = val >> 8;
476 sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 2);
477 break;
478 case 20:
479 case 32:
480 buf[0] = val;
481 buf[1] = val >> 8;
482 buf[2] = val >> 16;
483 buf[3] = val >> 24;
484 sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 4);
485 break;
486 default:
487 assert (! opc->size);
488 break;
489 }
490 break;
491 default:
492 fprintf (stderr, "invalid operand %d type %d\n", n, op->type);
493 abort ();
494 }
495
496 switch (opc->size)
497 {
498 case 8:
499 rv &= 0xff;
500 incval = 1;
501 break;
502 case 16:
503 rv &= 0xffff;
504 incval = 2;
505 break;
506 case 20:
507 rv &= 0xfffff;
508 incval = 4;
509 break;
510 case 32:
511 rv &= 0xffffffff;
512 incval = 4;
513 break;
514 }
515
516 if (op->type == MSP430_Operand_Indirect_Postinc)
517 {
518 int new_val = REG_GET (op->reg) + incval;
519 /* SP is always word-aligned. */
520 if (op->reg == MSR_SP && (new_val & 1))
521 new_val ++;
522 REG_PUT (op->reg, new_val);
523 }
524
525 return rv;
526}
527
528static void
529mem_put_val (SIM_DESC sd, int addr, int val, int bits)
530{
531 MSP430_Opcode_Decoded opc;
532
533 opc.size = bits;
534 opc.op[0].type = MSP430_Operand_Indirect;
535 opc.op[0].addend = addr;
536 opc.op[0].reg = MSR_None;
537 put_op (sd, &opc, 0, val);
538}
539
540static int
541mem_get_val (SIM_DESC sd, int addr, int bits)
542{
543 MSP430_Opcode_Decoded opc;
544
545 opc.size = bits;
546 opc.op[0].type = MSP430_Operand_Indirect;
547 opc.op[0].addend = addr;
548 opc.op[0].reg = MSR_None;
549 return get_op (sd, &opc, 0);
550}
551
552#define CIO_OPEN (0xF0)
553#define CIO_CLOSE (0xF1)
554#define CIO_READ (0xF2)
555#define CIO_WRITE (0xF3)
556#define CIO_LSEEK (0xF4)
557#define CIO_UNLINK (0xF5)
558#define CIO_GETENV (0xF6)
559#define CIO_RENAME (0xF7)
560#define CIO_GETTIME (0xF8)
561#define CIO_GETCLK (0xF9)
562#define CIO_SYNC (0xFF)
563
564#define CIO_I(n) (parms[(n)] + parms[(n)+1] * 256)
565#define CIO_L(n) (parms[(n)] + parms[(n)+1] * 256 \
566 + parms[(n)+2] * 65536 + parms[(n)+3] * 16777216)
567
568static void
569msp430_cio (SIM_DESC sd)
570{
571 /* A block of data at __CIOBUF__ describes the I/O operation to
572 perform. */
573
574 unsigned char raw_parms[13];
575 unsigned char parms[8];
576 long length;
577 int command;
578 unsigned char buffer[512];
579 long ret_buflen = 0;
580 long fd, addr, len, rv;
581
582 sim_core_read_buffer (sd, MSP430_CPU (sd), 0, parms,
583 MSP430_CPU (sd)->state.cio_buffer, 5);
584 length = CIO_I (0);
585 command = parms[2];
586
587 sim_core_read_buffer (sd, MSP430_CPU (sd), 0, parms,
588 MSP430_CPU (sd)->state.cio_buffer + 3, 8);
589
590 sim_core_read_buffer (sd, MSP430_CPU (sd), 0, buffer,
591 MSP430_CPU (sd)->state.cio_buffer + 11, length);
592
593 switch (command)
594 {
595 case CIO_WRITE:
596 fd = CIO_I (0);
597 len = CIO_I (2);
598
599 rv = write (fd, buffer, len);
600 parms[0] = rv & 0xff;
601 parms[1] = rv >> 8;
602
603 break;
604 }
605
606 sim_core_write_buffer (sd, MSP430_CPU (sd), 0, parms,
607 MSP430_CPU (sd)->state.cio_buffer + 4, 8);
608 if (ret_buflen)
609 sim_core_write_buffer (sd, MSP430_CPU (sd), 0, buffer,
610 MSP430_CPU (sd)->state.cio_buffer + 12, ret_buflen);
611}
612
613#define SRC get_op (sd, opcode, 1)
614#define DSRC get_op (sd, opcode, 0)
615#define DEST(V) put_op (sd, opcode, 0, (V))
616
617static int
618msp430_dis_read (bfd_vma memaddr,
619 bfd_byte *myaddr,
620 unsigned int length,
621 struct disassemble_info *dinfo)
622{
623 SIM_DESC sd = dinfo->private_data;
624 sim_core_read_buffer (sd, MSP430_CPU (sd), 0, myaddr, memaddr, length);
625 return 0;
626}
627
628#define DO_ALU(OP,SOP,MORE) \
629 { \
630 int s1 = DSRC; \
631 int s2 = SRC; \
632 int result = s1 OP s2 MORE; \
633 if (TRACE_ALU_P (MSP430_CPU (sd))) \
634 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, \
635 "ALU: %#x %s %#x %s = %#x", s1, SOP, s2, #MORE, result); \
636 DEST (result); \
637 }
638
639#define SIGN (1 << (opcode->size - 1))
640#define POS(x) (((x) & SIGN) ? 0 : 1)
641#define NEG(x) (((x) & SIGN) ? 1 : 0)
642
643static int
644zero_ext (int v, int bits)
645{
646 v &= ((1 << bits) - 1);
647 return v;
648}
649
650static int
651sign_ext (int v, int bits)
652{
653 int sb = 1 << (bits-1); /* Sign bit. */
654 int mb = (1 << (bits-1)) - 1; /* Mantissa bits. */
655
656 if (v & sb)
657 v = v | ~mb;
658 else
659 v = v & mb;
660 return v;
661}
662
663#define SX(v) sign_ext (v, opcode->size)
664#define ZX(v) zero_ext (v, opcode->size)
665
666static char *
667flags2string (int f)
668{
669 static char buf[2][6];
670 static int bi = 0;
671 char *bp = buf[bi];
672
673 bi = (bi + 1) % 2;
674
675 bp[0] = f & MSP430_FLAG_V ? 'V' : '-';
676 bp[1] = f & MSP430_FLAG_N ? 'N' : '-';
677 bp[2] = f & MSP430_FLAG_Z ? 'Z' : '-';
678 bp[3] = f & MSP430_FLAG_C ? 'C' : '-';
679 bp[4] = 0;
680 return bp;
681}
682
683/* Random number that won't show up in our usual logic. */
684#define MAGIC_OVERFLOW 0x55000F
685
686static void
687do_flags (SIM_DESC sd,
688 MSP430_Opcode_Decoded *opcode,
689 int vnz_val, /* Signed result. */
690 int carry,
691 int overflow)
692{
693 int f = SR;
694 int new_f = 0;
695 int signbit = 1 << (opcode->size - 1);
696
697 f &= ~opcode->flags_0;
698 f &= ~opcode->flags_set;
699 f |= opcode->flags_1;
700
701 if (vnz_val & signbit)
702 new_f |= MSP430_FLAG_N;
703 if (! (vnz_val & ((signbit << 1) - 1)))
704 new_f |= MSP430_FLAG_Z;
705 if (overflow == MAGIC_OVERFLOW)
706 {
707 if (vnz_val != SX (vnz_val))
708 new_f |= MSP430_FLAG_V;
709 }
710 else
711 if (overflow)
712 new_f |= MSP430_FLAG_V;
713 if (carry)
714 new_f |= MSP430_FLAG_C;
715
716 new_f = f | (new_f & opcode->flags_set);
717 if (TRACE_ALU_P (MSP430_CPU (sd)))
718 {
719 if (SR != new_f)
720 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
721 "FLAGS: %s -> %s", flags2string (SR),
722 flags2string (new_f));
723 else
724 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
725 "FLAGS: %s", flags2string (new_f));
726 }
727 SR = new_f;
728}
729
730#define FLAGS(vnz,c) do_flags (sd, opcode, vnz, c, MAGIC_OVERFLOW)
731#define FLAGSV(vnz,c,v) do_flags (sd, opcode, vnz, c, v)
732
733/* These two assume unsigned 16-bit (four digit) words.
734 Mask off unwanted bits for byte operations. */
735
736static int
737bcd_to_binary (int v)
738{
739 int r = ( ((v >> 0) & 0xf) * 1
740 + ((v >> 4) & 0xf) * 10
741 + ((v >> 8) & 0xf) * 100
742 + ((v >> 12) & 0xf) * 1000);
743 return r;
744}
745
746static int
747binary_to_bcd (int v)
748{
749 int r = ( ((v / 1) % 10) << 0
750 | ((v / 10) % 10) << 4
751 | ((v / 100) % 10) << 8
752 | ((v / 1000) % 10) << 12);
753 return r;
754}
755
756static int
757syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
758 unsigned long taddr, char *buf, int bytes)
759{
760 SIM_DESC sd = (SIM_DESC) sc->p1;
761 SIM_CPU *cpu = (SIM_CPU *) sc->p2;
762
763 return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
764}
765
766static int
767syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
768 unsigned long taddr, const char *buf, int bytes)
769{
770 SIM_DESC sd = (SIM_DESC) sc->p1;
771 SIM_CPU *cpu = (SIM_CPU *) sc->p2;
772
773 return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
774}
775
776static const char *
777cond_string (int cond)
778{
779 switch (cond)
780 {
781 case MSC_nz:
782 return "NZ";
783 case MSC_z:
784 return "Z";
785 case MSC_nc:
786 return "NC";
787 case MSC_c:
788 return "C";
789 case MSC_n:
790 return "N";
791 case MSC_ge:
792 return "GE";
793 case MSC_l:
794 return "L";
795 case MSC_true:
796 return "MP";
797 default:
798 return "??";
799 }
800}
801
802/* Checks a CALL to address CALL_ADDR. If this is a special
803 syscall address then the call is simulated and non-zero is
804 returned. Otherwise 0 is returned. */
805
806static int
807maybe_perform_syscall (SIM_DESC sd, int call_addr)
808{
809 if (call_addr == 0x00160)
810 {
811 int i;
812
813 for (i = 0; i < 16; i++)
814 {
815 if (i % 4 == 0)
816 fprintf (stderr, "\t");
817 fprintf (stderr, "R%-2d %05x ", i, MSP430_CPU (sd)->state.regs[i]);
818 if (i % 4 == 3)
819 {
820 int sp = SP + (3 - (i / 4)) * 2;
821 unsigned char buf[2];
822
823 sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, sp, 2);
824
825 fprintf (stderr, "\tSP%+d: %04x", sp - SP,
826 buf[0] + buf[1] * 256);
827
828 if (i / 4 == 0)
829 {
830 int flags = SR;
831
832 fprintf (stderr, flags & 0x100 ? " V" : " -");
833 fprintf (stderr, flags & 0x004 ? "N" : "-");
834 fprintf (stderr, flags & 0x002 ? "Z" : "-");
835 fprintf (stderr, flags & 0x001 ? "C" : "-");
836 }
837
838 fprintf (stderr, "\n");
839 }
840 }
841 return 1;
842 }
843
844 if ((call_addr & ~0x3f) == 0x00180)
845 {
846 /* Syscall! */
847 int syscall_num = call_addr & 0x3f;
848 host_callback *cb = STATE_CALLBACK (sd);
849 CB_SYSCALL sc;
850
851 CB_SYSCALL_INIT (&sc);
852
853 sc.func = syscall_num;
854 sc.arg1 = MSP430_CPU (sd)->state.regs[12];
855 sc.arg2 = MSP430_CPU (sd)->state.regs[13];
856 sc.arg3 = MSP430_CPU (sd)->state.regs[14];
857 sc.arg4 = MSP430_CPU (sd)->state.regs[15];
858
859 if (TRACE_SYSCALL_P (MSP430_CPU (sd)))
860 {
861 const char *syscall_name = "*unknown*";
862
863 switch (syscall_num)
864 {
865 case TARGET_SYS_exit:
866 syscall_name = "exit(%d)";
867 break;
868 case TARGET_SYS_open:
869 syscall_name = "open(%#x,%#x)";
870 break;
871 case TARGET_SYS_close:
872 syscall_name = "close(%d)";
873 break;
874 case TARGET_SYS_read:
875 syscall_name = "read(%d,%#x,%d)";
876 break;
877 case TARGET_SYS_write:
878 syscall_name = "write(%d,%#x,%d)";
879 break;
880 }
881 trace_generic (sd, MSP430_CPU (sd), TRACE_SYSCALL_IDX,
882 syscall_name, sc.arg1, sc.arg2, sc.arg3, sc.arg4);
883 }
884
885 /* Handle SYS_exit here. */
886 if (syscall_num == 1)
887 {
888 sim_engine_halt (sd, MSP430_CPU (sd), NULL,
889 MSP430_CPU (sd)->state.regs[0],
890 sim_exited, sc.arg1);
891 return 1;
892 }
893
894 sc.p1 = sd;
895 sc.p2 = MSP430_CPU (sd);
896 sc.read_mem = syscall_read_mem;
897 sc.write_mem = syscall_write_mem;
898
899 cb_syscall (cb, &sc);
900
901 if (TRACE_SYSCALL_P (MSP430_CPU (sd)))
902 trace_generic (sd, MSP430_CPU (sd), TRACE_SYSCALL_IDX,
a3271a3e 903 "returns %ld", sc.result);
3346cfda
NC		 904
905 MSP430_CPU (sd)->state.regs[12] = sc.result;
906 return 1;
907 }
908
909 return 0;
910}
911
912static void
913msp430_step_once (SIM_DESC sd)
914{
915 Get_Byte_Local_Data ld;
916 unsigned char buf[100];
917 int i;
918 int opsize;
919 unsigned int opcode_pc;
920 MSP430_Opcode_Decoded opcode_buf;
921 MSP430_Opcode_Decoded *opcode = &opcode_buf;
922 int s1, s2, result;
923 int u1, u2, uresult;
924 int c, reg;
925 int sp;
926 int carry_to_use;
927 int n_repeats;
928 int rept;
929 int op_bytes, op_bits;
930
931 PC &= 0xfffff;
932 opcode_pc = PC;
933
934 if (opcode_pc < 0x10)
935 {
936 fprintf (stderr, "Fault: PC(%#x) is less than 0x10\n", opcode_pc);
937 sim_engine_halt (sd, MSP430_CPU (sd), NULL,
938 MSP430_CPU (sd)->state.regs[0],
939 sim_exited, -1);
940 return;
941 }
942
943 if (PC == MSP430_CPU (sd)->state.cio_breakpoint
944 && STATE_OPEN_KIND (sd) != SIM_OPEN_DEBUG)
945 msp430_cio (sd);
946
947 ld.sd = sd;
948 ld.gb_addr = PC;
949 opsize = msp430_decode_opcode (MSP430_CPU (sd)->state.regs[0],
950 opcode, msp430_getbyte, &ld);
951 PC += opsize;
952 if (opsize <= 0)
953 {
954 fprintf (stderr, "Fault: undecodable opcode at %#x\n", opcode_pc);
955 sim_engine_halt (sd, MSP430_CPU (sd), NULL,
956 MSP430_CPU (sd)->state.regs[0],
957 sim_exited, -1);
958 return;
959 }
960
961 if (opcode->repeat_reg)
962 n_repeats = (MSP430_CPU (sd)->state.regs[opcode->repeats] & 0x000f) + 1;
963 else
964 n_repeats = opcode->repeats + 1;
965
966 op_bits = opcode->size;
967 switch (op_bits)
968 {
969 case 8:
970 op_bytes = 1;
971 break;
972 case 16:
973 op_bytes = 2;
974 break;
975 case 20:
976 case 32:
977 op_bytes = 4;
978 break;
979 }
980
981 if (TRACE_INSN_P (MSP430_CPU (sd)))
982 {
983 disassemble_info info;
984 unsigned char b[10];
985
986 msp430_trace_one (opcode_pc);
987
988 sim_core_read_buffer (sd, MSP430_CPU (sd), 0, b, opcode_pc, opsize);
989
a3271a3e 990 init_disassemble_info (&info, stderr, (fprintf_ftype) fprintf);
3346cfda
NC		 991 info.private_data = sd;
992 info.read_memory_func = msp430_dis_read;
993 fprintf (stderr, "%#8x ", opcode_pc);
994 for (i = 0; i < opsize; i += 2)
995 fprintf (stderr, " %02x%02x", b[i+1], b[i]);
996 for (; i < 6; i += 2)
997 fprintf (stderr, " ");
998 fprintf (stderr, " ");
999 print_insn_msp430 (opcode_pc, &info);
1000 fprintf (stderr, "\n");
1001 fflush (stdout);
1002 }
1003
1004 if (TRACE_ANY_P (MSP430_CPU (sd)))
1005 trace_prefix (sd, MSP430_CPU (sd), NULL_CIA, opcode_pc,
1006 TRACE_LINENUM_P (MSP430_CPU (sd)), NULL, 0, "");
1007
1008 carry_to_use = 0;
1009 switch (opcode->id)
1010 {
1011 case MSO_unknown:
1012 break;
1013
1014 /* Double-operand instructions. */
1015 case MSO_mov:
1016 if (opcode->n_bytes == 2
1017 && opcode->op[0].type == MSP430_Operand_Register
1018 && opcode->op[0].reg == MSR_CG
1019 && opcode->op[1].type == MSP430_Operand_Immediate
1020 && opcode->op[1].addend == 0
1021 /* A 16-bit write of #0 is a NOP; an 8-bit write is a BRK. */
1022 && opcode->size == 8)
1023 {
1024 /* This is the designated software breakpoint instruction. */
1025 PC -= opsize;
1026 sim_engine_halt (sd, MSP430_CPU (sd), NULL,
1027 MSP430_CPU (sd)->state.regs[0],
1028 sim_stopped, SIM_SIGTRAP);
1029
1030 }
1031 else
1032 {
1033 /* Otherwise, do the move. */
1034 for (rept = 0; rept < n_repeats; rept ++)
1035 {
1036 DEST (SRC);
1037 }
1038 }
1039 break;
1040
1041 case MSO_addc:
1042 for (rept = 0; rept < n_repeats; rept ++)
1043 {
1044 carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0;
1045 u1 = DSRC;
1046 u2 = SRC;
1047 s1 = SX (u1);
1048 s2 = SX (u2);
1049 uresult = u1 + u2 + carry_to_use;
1050 result = s1 + s2 + carry_to_use;
1051 if (TRACE_ALU_P (MSP430_CPU (sd)))
1052 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1053 "ADDC: %#x + %#x + %d = %#x",
1054 u1, u2, carry_to_use, uresult);
1055 DEST (result);
1056 FLAGS (result, uresult != ZX (uresult));
1057 }
1058 break;
1059
1060 case MSO_add:
1061 for (rept = 0; rept < n_repeats; rept ++)
1062 {
1063 u1 = DSRC;
1064 u2 = SRC;
1065 s1 = SX (u1);
1066 s2 = SX (u2);
1067 uresult = u1 + u2;
1068 result = s1 + s2;
1069 if (TRACE_ALU_P (MSP430_CPU (sd)))
1070 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1071 "ADD: %#x + %#x = %#x",
1072 u1, u2, uresult);
1073 DEST (result);
1074 FLAGS (result, uresult != ZX (uresult));
1075 }
1076 break;
1077
1078 case MSO_subc:
1079 for (rept = 0; rept < n_repeats; rept ++)
1080 {
1081 carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0;
1082 u1 = DSRC;
1083 u2 = SRC;
1084 s1 = SX (u1);
1085 s2 = SX (u2);
1086 uresult = ZX (~u2) + u1 + carry_to_use;
1087 result = s1 - s2 + (carry_to_use - 1);
1088 if (TRACE_ALU_P (MSP430_CPU (sd)))
1089 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1090 "SUBC: %#x - %#x + %d = %#x",
1091 u1, u2, carry_to_use, uresult);
1092 DEST (result);
1093 FLAGS (result, uresult != ZX (uresult));
1094 }
1095 break;
1096
1097 case MSO_sub:
1098 for (rept = 0; rept < n_repeats; rept ++)
1099 {
1100 u1 = DSRC;
1101 u2 = SRC;
1102 s1 = SX (u1);
1103 s2 = SX (u2);
1104 uresult = ZX (~u2) + u1 + 1;
1105 result = SX (uresult);
1106 if (TRACE_ALU_P (MSP430_CPU (sd)))
1107 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1108 "SUB: %#x - %#x = %#x",
1109 u1, u2, uresult);
1110 DEST (result);
1111 FLAGS (result, uresult != ZX (uresult));
1112 }
1113 break;
1114
1115 case MSO_cmp:
1116 for (rept = 0; rept < n_repeats; rept ++)
1117 {
1118 u1 = DSRC;
1119 u2 = SRC;
1120 s1 = SX (u1);
1121 s2 = SX (u2);
1122 uresult = ZX (~u2) + u1 + 1;
1123 result = s1 - s2;
1124 if (TRACE_ALU_P (MSP430_CPU (sd)))
1125 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1126 "CMP: %#x - %#x = %x",
1127 u1, u2, uresult);
1128 FLAGS (result, uresult != ZX (uresult));
1129 }
1130 break;
1131
1132 case MSO_dadd:
1133 for (rept = 0; rept < n_repeats; rept ++)
1134 {
1135 carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0;
1136 u1 = DSRC;
1137 u2 = SRC;
1138 uresult = bcd_to_binary (u1) + bcd_to_binary (u2) + carry_to_use;
1139 result = binary_to_bcd (uresult);
1140 if (TRACE_ALU_P (MSP430_CPU (sd)))
1141 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1142 "DADD: %#x + %#x + %d = %#x",
1143 u1, u2, carry_to_use, result);
1144 DEST (result);
1145 FLAGS (result, uresult > ((opcode->size == 8) ? 99 : 9999));
1146 }
1147 break;
1148
1149 case MSO_and:
1150 for (rept = 0; rept < n_repeats; rept ++)
1151 {
1152 u1 = DSRC;
1153 u2 = SRC;
1154 uresult = u1 & u2;
1155 if (TRACE_ALU_P (MSP430_CPU (sd)))
1156 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1157 "AND: %#x & %#x = %#x",
1158 u1, u2, uresult);
1159 DEST (uresult);
1160 FLAGS (uresult, uresult != 0);
1161 }
1162 break;
1163
1164 case MSO_bit:
1165 for (rept = 0; rept < n_repeats; rept ++)
1166 {
1167 u1 = DSRC;
1168 u2 = SRC;
1169 uresult = u1 & u2;
1170 if (TRACE_ALU_P (MSP430_CPU (sd)))
1171 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1172 "BIT: %#x & %#x -> %#x",
1173 u1, u2, uresult);
1174 FLAGS (uresult, uresult != 0);
1175 }
1176 break;
1177
1178 case MSO_bic:
1179 for (rept = 0; rept < n_repeats; rept ++)
1180 {
1181 u1 = DSRC;
1182 u2 = SRC;
1183 uresult = u1 & ~ u2;
1184 if (TRACE_ALU_P (MSP430_CPU (sd)))
1185 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1186 "BIC: %#x & ~ %#x = %#x",
1187 u1, u2, uresult);
1188 DEST (uresult);
1189 }
1190 break;
1191
1192 case MSO_bis:
1193 for (rept = 0; rept < n_repeats; rept ++)
1194 {
1195 u1 = DSRC;
1196 u2 = SRC;
1197 uresult = u1 | u2;
1198 if (TRACE_ALU_P (MSP430_CPU (sd)))
1199 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1200 "BIS: %#x | %#x = %#x",
1201 u1, u2, uresult);
1202 DEST (uresult);
1203 }
1204 break;
1205
1206 case MSO_xor:
1207 for (rept = 0; rept < n_repeats; rept ++)
1208 {
1209 s1 = 1 << (opcode->size - 1);
1210 u1 = DSRC;
1211 u2 = SRC;
1212 uresult = u1 ^ u2;
1213 if (TRACE_ALU_P (MSP430_CPU (sd)))
1214 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1215 "XOR: %#x & %#x = %#x",
1216 u1, u2, uresult);
1217 DEST (uresult);
1218 FLAGSV (uresult, uresult != 0, (u1 & s1) && (u2 & s1));
1219 }
1220 break;
1221
1222 /* Single-operand instructions. Note: the decoder puts the same
1223 operand in SRC as in DEST, for our convenience. */
1224
1225 case MSO_rrc:
1226 for (rept = 0; rept < n_repeats; rept ++)
1227 {
1228 u1 = SRC;
1229 carry_to_use = u1 & 1;
1230 uresult = u1 >> 1;
1231 if (SR & MSP430_FLAG_C)
1232 uresult |= (1 << (opcode->size - 1));
1233 if (TRACE_ALU_P (MSP430_CPU (sd)))
1234 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1235 "RRC: %#x >>= %#x",
1236 u1, uresult);
1237 DEST (uresult);
1238 FLAGS (uresult, carry_to_use);
1239 }
1240 break;
1241
1242 case MSO_swpb:
1243 for (rept = 0; rept < n_repeats; rept ++)
1244 {
1245 u1 = SRC;
1246 uresult = ((u1 >> 8) & 0x00ff) | ((u1 << 8) & 0xff00);
1247 if (TRACE_ALU_P (MSP430_CPU (sd)))
1248 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1249 "SWPB: %#x -> %#x",
1250 u1, uresult);
1251 DEST (uresult);
1252 }
1253 break;
1254
1255 case MSO_rra:
1256 for (rept = 0; rept < n_repeats; rept ++)
1257 {
1258 u1 = SRC;
1259 c = u1 & 1;
1260 s1 = 1 << (opcode->size - 1);
1261 uresult = (u1 >> 1) | (u1 & s1);
1262 if (TRACE_ALU_P (MSP430_CPU (sd)))
1263 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1264 "RRA: %#x >>= %#x",
1265 u1, uresult);
1266 DEST (uresult);
1267 FLAGS (uresult, c);
1268 }
1269 break;
1270
1271 case MSO_rru:
1272 for (rept = 0; rept < n_repeats; rept ++)
1273 {
1274 u1 = SRC;
1275 c = u1 & 1;
1276 uresult = (u1 >> 1);
1277 if (TRACE_ALU_P (MSP430_CPU (sd)))
1278 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1279 "RRU: %#x >>= %#x",
1280 u1, uresult);
1281 DEST (uresult);
1282 FLAGS (uresult, c);
1283 }
1284 break;
1285
1286 case MSO_sxt:
1287 for (rept = 0; rept < n_repeats; rept ++)
1288 {
1289 u1 = SRC;
1290 if (u1 & 0x80)
1291 uresult = u1 | 0xfff00;
1292 else
1293 uresult = u1 & 0x000ff;
1294 if (TRACE_ALU_P (MSP430_CPU (sd)))
1295 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1296 "SXT: %#x -> %#x",
1297 u1, uresult);
1298 DEST (uresult);
1299 FLAGS (uresult, c);
1300 }
1301 break;
1302
1303 case MSO_push:
1304 for (rept = 0; rept < n_repeats; rept ++)
1305 {
1306 int new_sp;
1307
1308 new_sp = REG_GET (MSR_SP) - op_bytes;
1309 /* SP is always word-aligned. */
1310 if (new_sp & 1)
1311 new_sp --;
1312 REG_PUT (MSR_SP, new_sp);
1313 u1 = SRC;
1314 mem_put_val (sd, SP, u1, op_bits);
1315 if (opcode->op[1].type == MSP430_Operand_Register)
1316 opcode->op[1].reg --;
1317 }
1318 break;
1319
1320 case MSO_pop:
1321 for (rept = 0; rept < n_repeats; rept ++)
1322 {
1323 int new_sp;
1324
1325 u1 = mem_get_val (sd, SP, op_bits);
1326 DEST (u1);
1327 if (opcode->op[0].type == MSP430_Operand_Register)
1328 opcode->op[0].reg ++;
1329 new_sp = REG_GET (MSR_SP) + op_bytes;
1330 /* SP is always word-aligned. */
1331 if (new_sp & 1)
1332 new_sp ++;
1333 REG_PUT (MSR_SP, new_sp);
1334 }
1335 break;
1336
1337 case MSO_call:
1338 u1 = SRC;
1339
1340 if (maybe_perform_syscall (sd, u1))
1341 break;
1342
1343 REG_PUT (MSR_SP, REG_GET (MSR_SP) - op_bytes);
1344 mem_put_val (sd, SP, PC, op_bits);
1345 if (TRACE_ALU_P (MSP430_CPU (sd)))
1346 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1347 "CALL: func %#x ret %#x, sp %#x",
1348 u1, PC, SP);
1349 REG_PUT (MSR_PC, u1);
1350 break;
1351
1352 case MSO_reti:
1353 SR = mem_get_val (sd, SP, op_bits);
1354 SP += 2;
1355 PC = mem_get_val (sd, SP, op_bits);
1356 SP += 2;
1357 if (TRACE_ALU_P (MSP430_CPU (sd)))
1358 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1359 "RETI: pc %#x sr %#x",
1360 PC, SR);
1361 break;
1362
1363 /* Jumps. */
1364
1365 case MSO_jmp:
1366 i = SRC;
1367 switch (opcode->cond)
1368 {
1369 case MSC_nz:
1370 u1 = (SR & MSP430_FLAG_Z) ? 0 : 1;
1371 break;
1372 case MSC_z:
1373 u1 = (SR & MSP430_FLAG_Z) ? 1 : 0;
1374 break;
1375 case MSC_nc:
1376 u1 = (SR & MSP430_FLAG_C) ? 0 : 1;
1377 break;
1378 case MSC_c:
1379 u1 = (SR & MSP430_FLAG_C) ? 1 : 0;
1380 break;
1381 case MSC_n:
1382 u1 = (SR & MSP430_FLAG_N) ? 1 : 0;
1383 break;
1384 case MSC_ge:
1385 u1 = (!!(SR & MSP430_FLAG_N) == !!(SR & MSP430_FLAG_V)) ? 1 : 0;
1386 break;
1387 case MSC_l:
1388 u1 = (!!(SR & MSP430_FLAG_N) == !!(SR & MSP430_FLAG_V)) ? 0 : 1;
1389 break;
1390 case MSC_true:
1391 u1 = 1;
1392 break;
1393 }
1394
1395 if (u1)
1396 {
1397 if (TRACE_BRANCH_P (MSP430_CPU (sd)))
1398 trace_generic (sd, MSP430_CPU (sd), TRACE_BRANCH_IDX,
1399 "J%s: pc %#x -> %#x sr %#x, taken",
1400 cond_string (opcode->cond), PC, i, SR);
1401 PC = i;
1402 if (PC == opcode_pc)
1403 exit (0);
1404 }
1405 else
1406 if (TRACE_BRANCH_P (MSP430_CPU (sd)))
1407 trace_generic (sd, MSP430_CPU (sd), TRACE_BRANCH_IDX,
1408 "J%s: pc %#x to %#x sr %#x, not taken",
1409 cond_string (opcode->cond), PC, i, SR);
1410 break;
1411
1412 default:
1413 fprintf (stderr, "error: unexpected opcode id %d\n", opcode->id);
1414 exit (1);
1415 }
1416}
1417
1418void
1419sim_engine_run (SIM_DESC sd,
1420 int next_cpu_nr,
1421 int nr_cpus,
1422 int siggnal)
1423{
1424 while (1)
1425 {
1426 msp430_step_once (sd);
1427 if (sim_events_tick (sd))
1428 sim_events_process (sd);
1429 }
1430}
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