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fa8b7c21 | 1 | /* OpenRISC simulator support code header |
1d506c26 | 2 | Copyright (C) 2017-2024 Free Software Foundation, Inc. |
fa8b7c21 SH |
3 | |
4 | This file is part of GDB, the GNU debugger. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
19 | #ifndef OR1K_SIM_H | |
20 | #define OR1K_SIM_H | |
21 | ||
22 | #include "symcat.h" | |
23 | ||
24 | /* GDB register numbers. */ | |
25 | #define PPC_REGNUM 32 | |
26 | #define PC_REGNUM 33 | |
27 | #define SR_REGNUM 34 | |
28 | ||
29 | /* Misc. profile data. */ | |
30 | typedef struct | |
31 | { | |
32 | } OR1K_MISC_PROFILE; | |
33 | ||
34 | /* Nop codes used in nop simulation. */ | |
35 | #define NOP_NOP 0x0 | |
36 | #define NOP_EXIT 0x1 | |
37 | #define NOP_REPORT 0x2 | |
38 | #define NOP_PUTC 0x4 | |
39 | #define NOP_CNT_RESET 0x5 | |
40 | #define NOP_GET_TICKS 0x6 | |
41 | #define NOP_GET_PS 0x7 | |
42 | #define NOP_TRACE_ON 0x8 | |
43 | #define NOP_TRACE_OFF 0x9 | |
44 | #define NOP_RANDOM 0xa | |
45 | #define NOP_OR1KSIM 0xb | |
46 | #define NOP_EXIT_SILENT 0xc | |
47 | ||
48 | #define NUM_SPR 0x20000 | |
49 | #define SPR_GROUP_SHIFT 11 | |
50 | #define SPR_GROUP_FIRST(group) (((UWI) SPR_GROUP_##group) << SPR_GROUP_SHIFT) | |
51 | #define SPR_ADDR(group,index) \ | |
52 | (SPR_GROUP_FIRST(group) | ((UWI) SPR_INDEX_##group##_##index)) | |
53 | ||
54 | /* Define word getters and setter helpers based on those from | |
55 | sim/common/cgen-mem.h. */ | |
56 | #define GETTWI GETTSI | |
57 | #define SETTWI SETTSI | |
58 | ||
59 | void or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr, | |
60 | const USI or1k_upr, const USI or1k_cpucfgr); | |
61 | ||
62 | void or1k32bf_insn_before (sim_cpu* current_cpu, SEM_PC vpc, const IDESC *idesc); | |
63 | void or1k32bf_insn_after (sim_cpu* current_cpu, SEM_PC vpc, const IDESC *idesc); | |
64 | void or1k32bf_fpu_error (CGEN_FPU* fpu, int status); | |
65 | void or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum); | |
66 | void or1k32bf_rfe (sim_cpu *current_cpu); | |
67 | void or1k32bf_nop (sim_cpu *current_cpu, USI uimm16); | |
68 | USI or1k32bf_mfspr (sim_cpu *current_cpu, USI addr); | |
69 | void or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val); | |
70 | ||
ee1cffd3 MF |
71 | int or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, void *buf, int len); |
72 | int or1k32bf_store_register (sim_cpu *current_cpu, int rn, const void *buf, | |
fa8b7c21 | 73 | int len); |
fa8b7c21 SH |
74 | int or1k32bf_model_or1200_u_exec (sim_cpu *current_cpu, const IDESC *idesc, |
75 | int unit_num, int referenced); | |
76 | int or1k32bf_model_or1200nd_u_exec (sim_cpu *current_cpu, const IDESC *idesc, | |
77 | int unit_num, int referenced); | |
78 | void or1k32bf_model_insn_before (sim_cpu *current_cpu, int first_p); | |
79 | void or1k32bf_model_insn_after (sim_cpu *current_cpu, int last_p, int cycles); | |
80 | USI or1k32bf_h_spr_get_raw (sim_cpu *current_cpu, USI addr); | |
81 | void or1k32bf_h_spr_set_raw (sim_cpu *current_cpu, USI addr, USI val); | |
82 | USI or1k32bf_h_spr_field_get_raw (sim_cpu *current_cpu, USI addr, int msb, | |
83 | int lsb); | |
84 | void or1k32bf_h_spr_field_set_raw (sim_cpu *current_cpu, USI addr, int msb, | |
85 | int lsb, USI val); | |
86 | USI or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset, | |
87 | int size); | |
88 | ||
89 | USI or1k32bf_ff1 (sim_cpu *current_cpu, USI val); | |
90 | USI or1k32bf_fl1 (sim_cpu *current_cpu, USI val); | |
91 | ||
f5e82fac MF |
92 | #define OR1K_DEFAULT_MEM_SIZE 0x800000 /* 8M */ |
93 | ||
94 | struct or1k_sim_cpu | |
95 | { | |
96 | OR1K_MISC_PROFILE or1k_misc_profile; | |
97 | #define CPU_OR1K_MISC_PROFILE(cpu) (& OR1K_SIM_CPU (cpu)->or1k_misc_profile) | |
98 | ||
99 | /* CPU specific parts go here. | |
100 | Note that in files that don't need to access these pieces WANT_CPU_FOO | |
101 | won't be defined and thus these parts won't appear. This is ok in the | |
102 | sense that things work. It is a source of bugs though. | |
103 | One has to of course be careful to not take the size of this | |
104 | struct and no structure members accessed in non-cpu specific files can | |
105 | go after here. Oh for a better language. */ | |
106 | UWI spr[NUM_SPR]; | |
107 | ||
108 | /* Next instruction will be in delay slot. */ | |
109 | BI next_delay_slot; | |
110 | /* Currently in delay slot. */ | |
111 | BI delay_slot; | |
112 | ||
113 | #ifdef WANT_CPU_OR1K32BF | |
114 | OR1K32BF_CPU_DATA cpu_data; | |
115 | #endif | |
116 | }; | |
117 | #define OR1K_SIM_CPU(cpu) ((struct or1k_sim_cpu *) CPU_ARCH_DATA (cpu)) | |
118 | ||
fa8b7c21 | 119 | #endif /* OR1K_SIM_H */ |