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Commit | Line | Data |
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6e51bfa7 SH |
1 | /* Simulator instruction semantics for or1k32bf. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
42a4f53d | 5 | Copyright 1996-2019 Free Software Foundation, Inc. |
6e51bfa7 SH |
6 | |
7 | This file is part of the GNU simulators. | |
8 | ||
9 | This file is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | It is distributed in the hope that it will be useful, but WITHOUT | |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #ifdef DEFINE_LABELS | |
26 | ||
27 | /* The labels have the case they have because the enum of insn types | |
28 | is all uppercase and in the non-stdc case the insn symbol is built | |
29 | into the enum name. */ | |
30 | ||
31 | static struct { | |
32 | int index; | |
33 | void *label; | |
34 | } labels[] = { | |
35 | { OR1K32BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, | |
36 | { OR1K32BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, | |
37 | { OR1K32BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, | |
38 | { OR1K32BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, | |
39 | { OR1K32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, | |
40 | { OR1K32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, | |
41 | { OR1K32BF_INSN_L_J, && case_sem_INSN_L_J }, | |
07f5f4c6 | 42 | { OR1K32BF_INSN_L_ADRP, && case_sem_INSN_L_ADRP }, |
6e51bfa7 SH |
43 | { OR1K32BF_INSN_L_JAL, && case_sem_INSN_L_JAL }, |
44 | { OR1K32BF_INSN_L_JR, && case_sem_INSN_L_JR }, | |
45 | { OR1K32BF_INSN_L_JALR, && case_sem_INSN_L_JALR }, | |
46 | { OR1K32BF_INSN_L_BNF, && case_sem_INSN_L_BNF }, | |
47 | { OR1K32BF_INSN_L_BF, && case_sem_INSN_L_BF }, | |
48 | { OR1K32BF_INSN_L_TRAP, && case_sem_INSN_L_TRAP }, | |
49 | { OR1K32BF_INSN_L_SYS, && case_sem_INSN_L_SYS }, | |
50 | { OR1K32BF_INSN_L_MSYNC, && case_sem_INSN_L_MSYNC }, | |
51 | { OR1K32BF_INSN_L_PSYNC, && case_sem_INSN_L_PSYNC }, | |
52 | { OR1K32BF_INSN_L_CSYNC, && case_sem_INSN_L_CSYNC }, | |
53 | { OR1K32BF_INSN_L_RFE, && case_sem_INSN_L_RFE }, | |
54 | { OR1K32BF_INSN_L_NOP_IMM, && case_sem_INSN_L_NOP_IMM }, | |
55 | { OR1K32BF_INSN_L_MOVHI, && case_sem_INSN_L_MOVHI }, | |
56 | { OR1K32BF_INSN_L_MACRC, && case_sem_INSN_L_MACRC }, | |
57 | { OR1K32BF_INSN_L_MFSPR, && case_sem_INSN_L_MFSPR }, | |
58 | { OR1K32BF_INSN_L_MTSPR, && case_sem_INSN_L_MTSPR }, | |
59 | { OR1K32BF_INSN_L_LWZ, && case_sem_INSN_L_LWZ }, | |
60 | { OR1K32BF_INSN_L_LWS, && case_sem_INSN_L_LWS }, | |
61 | { OR1K32BF_INSN_L_LWA, && case_sem_INSN_L_LWA }, | |
62 | { OR1K32BF_INSN_L_LBZ, && case_sem_INSN_L_LBZ }, | |
63 | { OR1K32BF_INSN_L_LBS, && case_sem_INSN_L_LBS }, | |
64 | { OR1K32BF_INSN_L_LHZ, && case_sem_INSN_L_LHZ }, | |
65 | { OR1K32BF_INSN_L_LHS, && case_sem_INSN_L_LHS }, | |
66 | { OR1K32BF_INSN_L_SW, && case_sem_INSN_L_SW }, | |
67 | { OR1K32BF_INSN_L_SB, && case_sem_INSN_L_SB }, | |
68 | { OR1K32BF_INSN_L_SH, && case_sem_INSN_L_SH }, | |
69 | { OR1K32BF_INSN_L_SWA, && case_sem_INSN_L_SWA }, | |
70 | { OR1K32BF_INSN_L_SLL, && case_sem_INSN_L_SLL }, | |
71 | { OR1K32BF_INSN_L_SLLI, && case_sem_INSN_L_SLLI }, | |
72 | { OR1K32BF_INSN_L_SRL, && case_sem_INSN_L_SRL }, | |
73 | { OR1K32BF_INSN_L_SRLI, && case_sem_INSN_L_SRLI }, | |
74 | { OR1K32BF_INSN_L_SRA, && case_sem_INSN_L_SRA }, | |
75 | { OR1K32BF_INSN_L_SRAI, && case_sem_INSN_L_SRAI }, | |
76 | { OR1K32BF_INSN_L_ROR, && case_sem_INSN_L_ROR }, | |
77 | { OR1K32BF_INSN_L_RORI, && case_sem_INSN_L_RORI }, | |
78 | { OR1K32BF_INSN_L_AND, && case_sem_INSN_L_AND }, | |
79 | { OR1K32BF_INSN_L_OR, && case_sem_INSN_L_OR }, | |
80 | { OR1K32BF_INSN_L_XOR, && case_sem_INSN_L_XOR }, | |
81 | { OR1K32BF_INSN_L_ADD, && case_sem_INSN_L_ADD }, | |
82 | { OR1K32BF_INSN_L_SUB, && case_sem_INSN_L_SUB }, | |
83 | { OR1K32BF_INSN_L_ADDC, && case_sem_INSN_L_ADDC }, | |
84 | { OR1K32BF_INSN_L_MUL, && case_sem_INSN_L_MUL }, | |
07f5f4c6 | 85 | { OR1K32BF_INSN_L_MULD, && case_sem_INSN_L_MULD }, |
6e51bfa7 | 86 | { OR1K32BF_INSN_L_MULU, && case_sem_INSN_L_MULU }, |
07f5f4c6 | 87 | { OR1K32BF_INSN_L_MULDU, && case_sem_INSN_L_MULDU }, |
6e51bfa7 SH |
88 | { OR1K32BF_INSN_L_DIV, && case_sem_INSN_L_DIV }, |
89 | { OR1K32BF_INSN_L_DIVU, && case_sem_INSN_L_DIVU }, | |
90 | { OR1K32BF_INSN_L_FF1, && case_sem_INSN_L_FF1 }, | |
91 | { OR1K32BF_INSN_L_FL1, && case_sem_INSN_L_FL1 }, | |
92 | { OR1K32BF_INSN_L_ANDI, && case_sem_INSN_L_ANDI }, | |
93 | { OR1K32BF_INSN_L_ORI, && case_sem_INSN_L_ORI }, | |
94 | { OR1K32BF_INSN_L_XORI, && case_sem_INSN_L_XORI }, | |
95 | { OR1K32BF_INSN_L_ADDI, && case_sem_INSN_L_ADDI }, | |
96 | { OR1K32BF_INSN_L_ADDIC, && case_sem_INSN_L_ADDIC }, | |
97 | { OR1K32BF_INSN_L_MULI, && case_sem_INSN_L_MULI }, | |
98 | { OR1K32BF_INSN_L_EXTHS, && case_sem_INSN_L_EXTHS }, | |
99 | { OR1K32BF_INSN_L_EXTBS, && case_sem_INSN_L_EXTBS }, | |
100 | { OR1K32BF_INSN_L_EXTHZ, && case_sem_INSN_L_EXTHZ }, | |
101 | { OR1K32BF_INSN_L_EXTBZ, && case_sem_INSN_L_EXTBZ }, | |
102 | { OR1K32BF_INSN_L_EXTWS, && case_sem_INSN_L_EXTWS }, | |
103 | { OR1K32BF_INSN_L_EXTWZ, && case_sem_INSN_L_EXTWZ }, | |
104 | { OR1K32BF_INSN_L_CMOV, && case_sem_INSN_L_CMOV }, | |
105 | { OR1K32BF_INSN_L_SFGTS, && case_sem_INSN_L_SFGTS }, | |
106 | { OR1K32BF_INSN_L_SFGTSI, && case_sem_INSN_L_SFGTSI }, | |
107 | { OR1K32BF_INSN_L_SFGTU, && case_sem_INSN_L_SFGTU }, | |
108 | { OR1K32BF_INSN_L_SFGTUI, && case_sem_INSN_L_SFGTUI }, | |
109 | { OR1K32BF_INSN_L_SFGES, && case_sem_INSN_L_SFGES }, | |
110 | { OR1K32BF_INSN_L_SFGESI, && case_sem_INSN_L_SFGESI }, | |
111 | { OR1K32BF_INSN_L_SFGEU, && case_sem_INSN_L_SFGEU }, | |
112 | { OR1K32BF_INSN_L_SFGEUI, && case_sem_INSN_L_SFGEUI }, | |
113 | { OR1K32BF_INSN_L_SFLTS, && case_sem_INSN_L_SFLTS }, | |
114 | { OR1K32BF_INSN_L_SFLTSI, && case_sem_INSN_L_SFLTSI }, | |
115 | { OR1K32BF_INSN_L_SFLTU, && case_sem_INSN_L_SFLTU }, | |
116 | { OR1K32BF_INSN_L_SFLTUI, && case_sem_INSN_L_SFLTUI }, | |
117 | { OR1K32BF_INSN_L_SFLES, && case_sem_INSN_L_SFLES }, | |
118 | { OR1K32BF_INSN_L_SFLESI, && case_sem_INSN_L_SFLESI }, | |
119 | { OR1K32BF_INSN_L_SFLEU, && case_sem_INSN_L_SFLEU }, | |
120 | { OR1K32BF_INSN_L_SFLEUI, && case_sem_INSN_L_SFLEUI }, | |
121 | { OR1K32BF_INSN_L_SFEQ, && case_sem_INSN_L_SFEQ }, | |
122 | { OR1K32BF_INSN_L_SFEQI, && case_sem_INSN_L_SFEQI }, | |
123 | { OR1K32BF_INSN_L_SFNE, && case_sem_INSN_L_SFNE }, | |
124 | { OR1K32BF_INSN_L_SFNEI, && case_sem_INSN_L_SFNEI }, | |
125 | { OR1K32BF_INSN_L_MAC, && case_sem_INSN_L_MAC }, | |
6e51bfa7 | 126 | { OR1K32BF_INSN_L_MACI, && case_sem_INSN_L_MACI }, |
07f5f4c6 RH |
127 | { OR1K32BF_INSN_L_MACU, && case_sem_INSN_L_MACU }, |
128 | { OR1K32BF_INSN_L_MSB, && case_sem_INSN_L_MSB }, | |
129 | { OR1K32BF_INSN_L_MSBU, && case_sem_INSN_L_MSBU }, | |
6e51bfa7 SH |
130 | { OR1K32BF_INSN_L_CUST1, && case_sem_INSN_L_CUST1 }, |
131 | { OR1K32BF_INSN_L_CUST2, && case_sem_INSN_L_CUST2 }, | |
132 | { OR1K32BF_INSN_L_CUST3, && case_sem_INSN_L_CUST3 }, | |
133 | { OR1K32BF_INSN_L_CUST4, && case_sem_INSN_L_CUST4 }, | |
134 | { OR1K32BF_INSN_L_CUST5, && case_sem_INSN_L_CUST5 }, | |
135 | { OR1K32BF_INSN_L_CUST6, && case_sem_INSN_L_CUST6 }, | |
136 | { OR1K32BF_INSN_L_CUST7, && case_sem_INSN_L_CUST7 }, | |
137 | { OR1K32BF_INSN_L_CUST8, && case_sem_INSN_L_CUST8 }, | |
138 | { OR1K32BF_INSN_LF_ADD_S, && case_sem_INSN_LF_ADD_S }, | |
139 | { OR1K32BF_INSN_LF_SUB_S, && case_sem_INSN_LF_SUB_S }, | |
140 | { OR1K32BF_INSN_LF_MUL_S, && case_sem_INSN_LF_MUL_S }, | |
141 | { OR1K32BF_INSN_LF_DIV_S, && case_sem_INSN_LF_DIV_S }, | |
142 | { OR1K32BF_INSN_LF_REM_S, && case_sem_INSN_LF_REM_S }, | |
143 | { OR1K32BF_INSN_LF_ITOF_S, && case_sem_INSN_LF_ITOF_S }, | |
144 | { OR1K32BF_INSN_LF_FTOI_S, && case_sem_INSN_LF_FTOI_S }, | |
145 | { OR1K32BF_INSN_LF_EQ_S, && case_sem_INSN_LF_EQ_S }, | |
146 | { OR1K32BF_INSN_LF_NE_S, && case_sem_INSN_LF_NE_S }, | |
147 | { OR1K32BF_INSN_LF_GE_S, && case_sem_INSN_LF_GE_S }, | |
148 | { OR1K32BF_INSN_LF_GT_S, && case_sem_INSN_LF_GT_S }, | |
149 | { OR1K32BF_INSN_LF_LT_S, && case_sem_INSN_LF_LT_S }, | |
150 | { OR1K32BF_INSN_LF_LE_S, && case_sem_INSN_LF_LE_S }, | |
151 | { OR1K32BF_INSN_LF_MADD_S, && case_sem_INSN_LF_MADD_S }, | |
152 | { OR1K32BF_INSN_LF_CUST1_S, && case_sem_INSN_LF_CUST1_S }, | |
153 | { 0, 0 } | |
154 | }; | |
155 | int i; | |
156 | ||
157 | for (i = 0; labels[i].label != 0; ++i) | |
158 | { | |
159 | #if FAST_P | |
160 | CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; | |
161 | #else | |
162 | CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; | |
163 | #endif | |
164 | } | |
165 | ||
166 | #undef DEFINE_LABELS | |
167 | #endif /* DEFINE_LABELS */ | |
168 | ||
169 | #ifdef DEFINE_SWITCH | |
170 | ||
171 | /* If hyper-fast [well not unnecessarily slow] execution is selected, turn | |
172 | off frills like tracing and profiling. */ | |
173 | /* FIXME: A better way would be to have TRACE_RESULT check for something | |
174 | that can cause it to be optimized out. Another way would be to emit | |
175 | special handlers into the instruction "stream". */ | |
176 | ||
177 | #if FAST_P | |
178 | #undef CGEN_TRACE_RESULT | |
179 | #define CGEN_TRACE_RESULT(cpu, abuf, name, type, val) | |
180 | #endif | |
181 | ||
182 | #undef GET_ATTR | |
183 | #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) | |
184 | ||
185 | { | |
186 | ||
187 | #if WITH_SCACHE_PBB | |
188 | ||
189 | /* Branch to next handler without going around main loop. */ | |
190 | #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case | |
191 | SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) | |
192 | ||
193 | #else /* ! WITH_SCACHE_PBB */ | |
194 | ||
195 | #define NEXT(vpc) BREAK (sem) | |
196 | #ifdef __GNUC__ | |
197 | #if FAST_P | |
198 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) | |
199 | #else | |
200 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) | |
201 | #endif | |
202 | #else | |
203 | SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) | |
204 | #endif | |
205 | ||
206 | #endif /* ! WITH_SCACHE_PBB */ | |
207 | ||
208 | { | |
209 | ||
210 | CASE (sem, INSN_X_INVALID) : /* --invalid-- */ | |
211 | { | |
212 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
213 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
214 | #define FLD(f) abuf->fields.sfmt_empty.f | |
215 | int UNUSED written = 0; | |
216 | IADDR UNUSED pc = abuf->addr; | |
217 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
218 | ||
219 | { | |
220 | /* Update the recorded pc in the cpu state struct. | |
221 | Only necessary for WITH_SCACHE case, but to avoid the | |
222 | conditional compilation .... */ | |
223 | SET_H_PC (pc); | |
224 | /* Virtual insns have zero size. Overwrite vpc with address of next insn | |
225 | using the default-insn-bitsize spec. When executing insns in parallel | |
226 | we may want to queue the fault and continue execution. */ | |
227 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
228 | vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); | |
229 | } | |
230 | ||
231 | #undef FLD | |
232 | } | |
233 | NEXT (vpc); | |
234 | ||
235 | CASE (sem, INSN_X_AFTER) : /* --after-- */ | |
236 | { | |
237 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
238 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
239 | #define FLD(f) abuf->fields.sfmt_empty.f | |
240 | int UNUSED written = 0; | |
241 | IADDR UNUSED pc = abuf->addr; | |
242 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
243 | ||
244 | { | |
245 | #if WITH_SCACHE_PBB_OR1K32BF | |
246 | or1k32bf_pbb_after (current_cpu, sem_arg); | |
247 | #endif | |
248 | } | |
249 | ||
250 | #undef FLD | |
251 | } | |
252 | NEXT (vpc); | |
253 | ||
254 | CASE (sem, INSN_X_BEFORE) : /* --before-- */ | |
255 | { | |
256 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
257 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
258 | #define FLD(f) abuf->fields.sfmt_empty.f | |
259 | int UNUSED written = 0; | |
260 | IADDR UNUSED pc = abuf->addr; | |
261 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
262 | ||
263 | { | |
264 | #if WITH_SCACHE_PBB_OR1K32BF | |
265 | or1k32bf_pbb_before (current_cpu, sem_arg); | |
266 | #endif | |
267 | } | |
268 | ||
269 | #undef FLD | |
270 | } | |
271 | NEXT (vpc); | |
272 | ||
273 | CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ | |
274 | { | |
275 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
276 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
277 | #define FLD(f) abuf->fields.sfmt_empty.f | |
278 | int UNUSED written = 0; | |
279 | IADDR UNUSED pc = abuf->addr; | |
280 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
281 | ||
282 | { | |
283 | #if WITH_SCACHE_PBB_OR1K32BF | |
284 | #ifdef DEFINE_SWITCH | |
285 | vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg, | |
286 | pbb_br_type, pbb_br_npc); | |
287 | BREAK (sem); | |
288 | #else | |
289 | /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ | |
290 | vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg, | |
291 | CPU_PBB_BR_TYPE (current_cpu), | |
292 | CPU_PBB_BR_NPC (current_cpu)); | |
293 | #endif | |
294 | #endif | |
295 | } | |
296 | ||
297 | #undef FLD | |
298 | } | |
299 | NEXT (vpc); | |
300 | ||
301 | CASE (sem, INSN_X_CHAIN) : /* --chain-- */ | |
302 | { | |
303 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
304 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
305 | #define FLD(f) abuf->fields.sfmt_empty.f | |
306 | int UNUSED written = 0; | |
307 | IADDR UNUSED pc = abuf->addr; | |
308 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
309 | ||
310 | { | |
311 | #if WITH_SCACHE_PBB_OR1K32BF | |
312 | vpc = or1k32bf_pbb_chain (current_cpu, sem_arg); | |
313 | #ifdef DEFINE_SWITCH | |
314 | BREAK (sem); | |
315 | #endif | |
316 | #endif | |
317 | } | |
318 | ||
319 | #undef FLD | |
320 | } | |
321 | NEXT (vpc); | |
322 | ||
323 | CASE (sem, INSN_X_BEGIN) : /* --begin-- */ | |
324 | { | |
325 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
326 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
327 | #define FLD(f) abuf->fields.sfmt_empty.f | |
328 | int UNUSED written = 0; | |
329 | IADDR UNUSED pc = abuf->addr; | |
330 | vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
331 | ||
332 | { | |
333 | #if WITH_SCACHE_PBB_OR1K32BF | |
334 | #if defined DEFINE_SWITCH || defined FAST_P | |
335 | /* In the switch case FAST_P is a constant, allowing several optimizations | |
336 | in any called inline functions. */ | |
337 | vpc = or1k32bf_pbb_begin (current_cpu, FAST_P); | |
338 | #else | |
339 | #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ | |
340 | vpc = or1k32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); | |
341 | #else | |
342 | vpc = or1k32bf_pbb_begin (current_cpu, 0); | |
343 | #endif | |
344 | #endif | |
345 | #endif | |
346 | } | |
347 | ||
348 | #undef FLD | |
349 | } | |
350 | NEXT (vpc); | |
351 | ||
352 | CASE (sem, INSN_L_J) : /* l.j ${disp26} */ | |
353 | { | |
354 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
355 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
356 | #define FLD(f) abuf->fields.sfmt_l_j.f | |
357 | int UNUSED written = 0; | |
358 | IADDR UNUSED pc = abuf->addr; | |
359 | SEM_BRANCH_INIT | |
360 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
361 | ||
362 | { | |
363 | { | |
364 | { | |
365 | USI opval = FLD (i_disp26); | |
366 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
367 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
368 | } | |
369 | } | |
370 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
371 | if (1) | |
372 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
373 | } | |
374 | } | |
375 | ||
376 | SEM_BRANCH_FINI (vpc); | |
377 | #undef FLD | |
378 | } | |
379 | NEXT (vpc); | |
380 | ||
07f5f4c6 RH |
381 | CASE (sem, INSN_L_ADRP) : /* l.adrp $rD,${disp21} */ |
382 | { | |
383 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
384 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
385 | #define FLD(f) abuf->fields.sfmt_l_adrp.f | |
386 | int UNUSED written = 0; | |
387 | IADDR UNUSED pc = abuf->addr; | |
388 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
389 | ||
390 | { | |
391 | USI opval = FLD (i_disp21); | |
392 | SET_H_GPR (FLD (f_r1), opval); | |
393 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
394 | } | |
395 | ||
396 | #undef FLD | |
397 | } | |
398 | NEXT (vpc); | |
399 | ||
6e51bfa7 SH |
400 | CASE (sem, INSN_L_JAL) : /* l.jal ${disp26} */ |
401 | { | |
402 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
403 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
404 | #define FLD(f) abuf->fields.sfmt_l_j.f | |
405 | int UNUSED written = 0; | |
406 | IADDR UNUSED pc = abuf->addr; | |
407 | SEM_BRANCH_INIT | |
408 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
409 | ||
410 | { | |
411 | { | |
412 | USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8))); | |
413 | SET_H_GPR (((UINT) 9), opval); | |
414 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
415 | } | |
416 | { | |
417 | { | |
418 | { | |
419 | USI opval = FLD (i_disp26); | |
420 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
421 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
422 | } | |
423 | } | |
424 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
425 | if (1) | |
426 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
427 | } | |
428 | } | |
429 | } | |
430 | ||
431 | SEM_BRANCH_FINI (vpc); | |
432 | #undef FLD | |
433 | } | |
434 | NEXT (vpc); | |
435 | ||
436 | CASE (sem, INSN_L_JR) : /* l.jr $rB */ | |
437 | { | |
438 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
439 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
440 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
441 | int UNUSED written = 0; | |
442 | IADDR UNUSED pc = abuf->addr; | |
443 | SEM_BRANCH_INIT | |
444 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
445 | ||
446 | { | |
447 | { | |
448 | { | |
449 | USI opval = GET_H_GPR (FLD (f_r3)); | |
450 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
451 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
452 | } | |
453 | } | |
454 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
455 | if (1) | |
456 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
457 | } | |
458 | } | |
459 | ||
460 | SEM_BRANCH_FINI (vpc); | |
461 | #undef FLD | |
462 | } | |
463 | NEXT (vpc); | |
464 | ||
465 | CASE (sem, INSN_L_JALR) : /* l.jalr $rB */ | |
466 | { | |
467 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
468 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
469 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
470 | int UNUSED written = 0; | |
471 | IADDR UNUSED pc = abuf->addr; | |
472 | SEM_BRANCH_INIT | |
473 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
474 | ||
475 | { | |
476 | { | |
477 | USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8))); | |
478 | SET_H_GPR (((UINT) 9), opval); | |
479 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
480 | } | |
481 | { | |
482 | { | |
483 | { | |
484 | USI opval = GET_H_GPR (FLD (f_r3)); | |
485 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
486 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
487 | } | |
488 | } | |
489 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
490 | if (1) | |
491 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
492 | } | |
493 | } | |
494 | } | |
495 | ||
496 | SEM_BRANCH_FINI (vpc); | |
497 | #undef FLD | |
498 | } | |
499 | NEXT (vpc); | |
500 | ||
501 | CASE (sem, INSN_L_BNF) : /* l.bnf ${disp26} */ | |
502 | { | |
503 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
504 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
505 | #define FLD(f) abuf->fields.sfmt_l_j.f | |
506 | int UNUSED written = 0; | |
507 | IADDR UNUSED pc = abuf->addr; | |
508 | SEM_BRANCH_INIT | |
509 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
510 | ||
511 | { | |
512 | if (NOTSI (GET_H_SYS_SR_F ())) { | |
513 | { | |
514 | { | |
515 | USI opval = FLD (i_disp26); | |
516 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
517 | written |= (1 << 4); | |
518 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
519 | } | |
520 | } | |
521 | } else { | |
522 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
523 | { | |
524 | { | |
525 | USI opval = ADDSI (pc, 4); | |
526 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
527 | written |= (1 << 4); | |
528 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
529 | } | |
530 | } | |
531 | } | |
532 | } | |
533 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
534 | if (1) | |
535 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
536 | } | |
537 | } | |
538 | ||
539 | abuf->written = written; | |
540 | SEM_BRANCH_FINI (vpc); | |
541 | #undef FLD | |
542 | } | |
543 | NEXT (vpc); | |
544 | ||
545 | CASE (sem, INSN_L_BF) : /* l.bf ${disp26} */ | |
546 | { | |
547 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
548 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
549 | #define FLD(f) abuf->fields.sfmt_l_j.f | |
550 | int UNUSED written = 0; | |
551 | IADDR UNUSED pc = abuf->addr; | |
552 | SEM_BRANCH_INIT | |
553 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
554 | ||
555 | { | |
556 | if (GET_H_SYS_SR_F ()) { | |
557 | { | |
558 | { | |
559 | USI opval = FLD (i_disp26); | |
560 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
561 | written |= (1 << 4); | |
562 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
563 | } | |
564 | } | |
565 | } else { | |
566 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
567 | { | |
568 | { | |
569 | USI opval = ADDSI (pc, 4); | |
570 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
571 | written |= (1 << 4); | |
572 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
573 | } | |
574 | } | |
575 | } | |
576 | } | |
577 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
578 | if (1) | |
579 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
580 | } | |
581 | } | |
582 | ||
583 | abuf->written = written; | |
584 | SEM_BRANCH_FINI (vpc); | |
585 | #undef FLD | |
586 | } | |
587 | NEXT (vpc); | |
588 | ||
589 | CASE (sem, INSN_L_TRAP) : /* l.trap ${uimm16} */ | |
590 | { | |
591 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
592 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
593 | #define FLD(f) abuf->fields.sfmt_empty.f | |
594 | int UNUSED written = 0; | |
595 | IADDR UNUSED pc = abuf->addr; | |
596 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
597 | ||
598 | or1k32bf_exception (current_cpu, pc, EXCEPT_TRAP); | |
599 | ||
600 | #undef FLD | |
601 | } | |
602 | NEXT (vpc); | |
603 | ||
604 | CASE (sem, INSN_L_SYS) : /* l.sys ${uimm16} */ | |
605 | { | |
606 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
607 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
608 | #define FLD(f) abuf->fields.sfmt_empty.f | |
609 | int UNUSED written = 0; | |
610 | IADDR UNUSED pc = abuf->addr; | |
611 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
612 | ||
613 | or1k32bf_exception (current_cpu, pc, EXCEPT_SYSCALL); | |
614 | ||
615 | #undef FLD | |
616 | } | |
617 | NEXT (vpc); | |
618 | ||
619 | CASE (sem, INSN_L_MSYNC) : /* l.msync */ | |
620 | { | |
621 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
622 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
623 | #define FLD(f) abuf->fields.sfmt_empty.f | |
624 | int UNUSED written = 0; | |
625 | IADDR UNUSED pc = abuf->addr; | |
626 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
627 | ||
628 | ((void) 0); /*nop*/ | |
629 | ||
630 | #undef FLD | |
631 | } | |
632 | NEXT (vpc); | |
633 | ||
634 | CASE (sem, INSN_L_PSYNC) : /* l.psync */ | |
635 | { | |
636 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
637 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
638 | #define FLD(f) abuf->fields.sfmt_empty.f | |
639 | int UNUSED written = 0; | |
640 | IADDR UNUSED pc = abuf->addr; | |
641 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
642 | ||
643 | ((void) 0); /*nop*/ | |
644 | ||
645 | #undef FLD | |
646 | } | |
647 | NEXT (vpc); | |
648 | ||
649 | CASE (sem, INSN_L_CSYNC) : /* l.csync */ | |
650 | { | |
651 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
652 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
653 | #define FLD(f) abuf->fields.sfmt_empty.f | |
654 | int UNUSED written = 0; | |
655 | IADDR UNUSED pc = abuf->addr; | |
656 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
657 | ||
658 | ((void) 0); /*nop*/ | |
659 | ||
660 | #undef FLD | |
661 | } | |
662 | NEXT (vpc); | |
663 | ||
664 | CASE (sem, INSN_L_RFE) : /* l.rfe */ | |
665 | { | |
666 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
667 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
668 | #define FLD(f) abuf->fields.sfmt_empty.f | |
669 | int UNUSED written = 0; | |
670 | IADDR UNUSED pc = abuf->addr; | |
671 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
672 | ||
673 | or1k32bf_rfe (current_cpu); | |
674 | ||
675 | #undef FLD | |
676 | } | |
677 | NEXT (vpc); | |
678 | ||
679 | CASE (sem, INSN_L_NOP_IMM) : /* l.nop ${uimm16} */ | |
680 | { | |
681 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
682 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
683 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f | |
684 | int UNUSED written = 0; | |
685 | IADDR UNUSED pc = abuf->addr; | |
686 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
687 | ||
688 | or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16))); | |
689 | ||
690 | #undef FLD | |
691 | } | |
692 | NEXT (vpc); | |
693 | ||
694 | CASE (sem, INSN_L_MOVHI) : /* l.movhi $rD,$uimm16 */ | |
695 | { | |
696 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
697 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
698 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f | |
699 | int UNUSED written = 0; | |
700 | IADDR UNUSED pc = abuf->addr; | |
701 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
702 | ||
703 | { | |
704 | USI opval = SLLSI (ZEXTSISI (FLD (f_uimm16)), 16); | |
705 | SET_H_GPR (FLD (f_r1), opval); | |
706 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
707 | } | |
708 | ||
709 | #undef FLD | |
710 | } | |
711 | NEXT (vpc); | |
712 | ||
713 | CASE (sem, INSN_L_MACRC) : /* l.macrc $rD */ | |
714 | { | |
715 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
716 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
07f5f4c6 | 717 | #define FLD(f) abuf->fields.sfmt_l_adrp.f |
6e51bfa7 SH |
718 | int UNUSED written = 0; |
719 | IADDR UNUSED pc = abuf->addr; | |
720 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
721 | ||
722 | { | |
723 | { | |
724 | USI opval = GET_H_MAC_MACLO (); | |
725 | SET_H_GPR (FLD (f_r1), opval); | |
726 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
727 | } | |
728 | { | |
729 | USI opval = 0; | |
730 | SET_H_MAC_MACLO (opval); | |
731 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
732 | } | |
733 | { | |
734 | USI opval = 0; | |
735 | SET_H_MAC_MACHI (opval); | |
736 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
737 | } | |
738 | } | |
739 | ||
740 | #undef FLD | |
741 | } | |
742 | NEXT (vpc); | |
743 | ||
744 | CASE (sem, INSN_L_MFSPR) : /* l.mfspr $rD,$rA,${uimm16} */ | |
745 | { | |
746 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
747 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
748 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f | |
749 | int UNUSED written = 0; | |
750 | IADDR UNUSED pc = abuf->addr; | |
751 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
752 | ||
753 | { | |
754 | USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)))); | |
755 | SET_H_GPR (FLD (f_r1), opval); | |
756 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
757 | } | |
758 | ||
759 | #undef FLD | |
760 | } | |
761 | NEXT (vpc); | |
762 | ||
763 | CASE (sem, INSN_L_MTSPR) : /* l.mtspr $rA,$rB,${uimm16-split} */ | |
764 | { | |
765 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
766 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
767 | #define FLD(f) abuf->fields.sfmt_l_mtspr.f | |
768 | int UNUSED written = 0; | |
769 | IADDR UNUSED pc = abuf->addr; | |
770 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
771 | ||
772 | or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3))); | |
773 | ||
774 | #undef FLD | |
775 | } | |
776 | NEXT (vpc); | |
777 | ||
778 | CASE (sem, INSN_L_LWZ) : /* l.lwz $rD,${simm16}($rA) */ | |
779 | { | |
780 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
781 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
782 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
783 | int UNUSED written = 0; | |
784 | IADDR UNUSED pc = abuf->addr; | |
785 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
786 | ||
787 | { | |
788 | USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4))); | |
789 | SET_H_GPR (FLD (f_r1), opval); | |
790 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
791 | } | |
792 | ||
793 | #undef FLD | |
794 | } | |
795 | NEXT (vpc); | |
796 | ||
797 | CASE (sem, INSN_L_LWS) : /* l.lws $rD,${simm16}($rA) */ | |
798 | { | |
799 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
800 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
801 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
802 | int UNUSED written = 0; | |
803 | IADDR UNUSED pc = abuf->addr; | |
804 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
805 | ||
806 | { | |
807 | SI opval = EXTSISI (GETMEMSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4))); | |
808 | SET_H_GPR (FLD (f_r1), opval); | |
809 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
810 | } | |
811 | ||
812 | #undef FLD | |
813 | } | |
814 | NEXT (vpc); | |
815 | ||
816 | CASE (sem, INSN_L_LWA) : /* l.lwa $rD,${simm16}($rA) */ | |
817 | { | |
818 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
819 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
820 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
821 | int UNUSED written = 0; | |
822 | IADDR UNUSED pc = abuf->addr; | |
823 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
824 | ||
825 | { | |
826 | { | |
827 | USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4))); | |
828 | SET_H_GPR (FLD (f_r1), opval); | |
829 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
830 | } | |
831 | { | |
832 | BI opval = 1; | |
833 | CPU (h_atomic_reserve) = opval; | |
834 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); | |
835 | } | |
836 | { | |
837 | SI opval = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4); | |
838 | CPU (h_atomic_address) = opval; | |
839 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval); | |
840 | } | |
841 | } | |
842 | ||
843 | #undef FLD | |
844 | } | |
845 | NEXT (vpc); | |
846 | ||
847 | CASE (sem, INSN_L_LBZ) : /* l.lbz $rD,${simm16}($rA) */ | |
848 | { | |
849 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
850 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
851 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
852 | int UNUSED written = 0; | |
853 | IADDR UNUSED pc = abuf->addr; | |
854 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
855 | ||
856 | { | |
857 | USI opval = ZEXTQISI (GETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1))); | |
858 | SET_H_GPR (FLD (f_r1), opval); | |
859 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
860 | } | |
861 | ||
862 | #undef FLD | |
863 | } | |
864 | NEXT (vpc); | |
865 | ||
866 | CASE (sem, INSN_L_LBS) : /* l.lbs $rD,${simm16}($rA) */ | |
867 | { | |
868 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
869 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
870 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
871 | int UNUSED written = 0; | |
872 | IADDR UNUSED pc = abuf->addr; | |
873 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
874 | ||
875 | { | |
876 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1))); | |
877 | SET_H_GPR (FLD (f_r1), opval); | |
878 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
879 | } | |
880 | ||
881 | #undef FLD | |
882 | } | |
883 | NEXT (vpc); | |
884 | ||
885 | CASE (sem, INSN_L_LHZ) : /* l.lhz $rD,${simm16}($rA) */ | |
886 | { | |
887 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
888 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
889 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
890 | int UNUSED written = 0; | |
891 | IADDR UNUSED pc = abuf->addr; | |
892 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
893 | ||
894 | { | |
895 | USI opval = ZEXTHISI (GETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2))); | |
896 | SET_H_GPR (FLD (f_r1), opval); | |
897 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
898 | } | |
899 | ||
900 | #undef FLD | |
901 | } | |
902 | NEXT (vpc); | |
903 | ||
904 | CASE (sem, INSN_L_LHS) : /* l.lhs $rD,${simm16}($rA) */ | |
905 | { | |
906 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
907 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
908 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
909 | int UNUSED written = 0; | |
910 | IADDR UNUSED pc = abuf->addr; | |
911 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
912 | ||
913 | { | |
914 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2))); | |
915 | SET_H_GPR (FLD (f_r1), opval); | |
916 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
917 | } | |
918 | ||
919 | #undef FLD | |
920 | } | |
921 | NEXT (vpc); | |
922 | ||
923 | CASE (sem, INSN_L_SW) : /* l.sw ${simm16-split}($rA),$rB */ | |
924 | { | |
925 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
926 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
927 | #define FLD(f) abuf->fields.sfmt_l_sw.f | |
928 | int UNUSED written = 0; | |
929 | IADDR UNUSED pc = abuf->addr; | |
930 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
931 | ||
932 | { | |
933 | SI tmp_addr; | |
934 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4); | |
935 | { | |
936 | USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3))); | |
937 | SETMEMUSI (current_cpu, pc, tmp_addr, opval); | |
938 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
939 | } | |
940 | if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) { | |
941 | { | |
942 | BI opval = 0; | |
943 | CPU (h_atomic_reserve) = opval; | |
944 | written |= (1 << 4); | |
945 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); | |
946 | } | |
947 | } | |
948 | } | |
949 | ||
950 | abuf->written = written; | |
951 | #undef FLD | |
952 | } | |
953 | NEXT (vpc); | |
954 | ||
955 | CASE (sem, INSN_L_SB) : /* l.sb ${simm16-split}($rA),$rB */ | |
956 | { | |
957 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
958 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
959 | #define FLD(f) abuf->fields.sfmt_l_sw.f | |
960 | int UNUSED written = 0; | |
961 | IADDR UNUSED pc = abuf->addr; | |
962 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
963 | ||
964 | { | |
965 | SI tmp_addr; | |
966 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1); | |
967 | { | |
968 | UQI opval = TRUNCSIQI (GET_H_GPR (FLD (f_r3))); | |
969 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); | |
970 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
971 | } | |
972 | if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) { | |
973 | { | |
974 | BI opval = 0; | |
975 | CPU (h_atomic_reserve) = opval; | |
976 | written |= (1 << 4); | |
977 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); | |
978 | } | |
979 | } | |
980 | } | |
981 | ||
982 | abuf->written = written; | |
983 | #undef FLD | |
984 | } | |
985 | NEXT (vpc); | |
986 | ||
987 | CASE (sem, INSN_L_SH) : /* l.sh ${simm16-split}($rA),$rB */ | |
988 | { | |
989 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
990 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
991 | #define FLD(f) abuf->fields.sfmt_l_sw.f | |
992 | int UNUSED written = 0; | |
993 | IADDR UNUSED pc = abuf->addr; | |
994 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
995 | ||
996 | { | |
997 | SI tmp_addr; | |
998 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2); | |
999 | { | |
1000 | UHI opval = TRUNCSIHI (GET_H_GPR (FLD (f_r3))); | |
1001 | SETMEMUHI (current_cpu, pc, tmp_addr, opval); | |
1002 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
1003 | } | |
1004 | if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) { | |
1005 | { | |
1006 | BI opval = 0; | |
1007 | CPU (h_atomic_reserve) = opval; | |
1008 | written |= (1 << 4); | |
1009 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); | |
1010 | } | |
1011 | } | |
1012 | } | |
1013 | ||
1014 | abuf->written = written; | |
1015 | #undef FLD | |
1016 | } | |
1017 | NEXT (vpc); | |
1018 | ||
1019 | CASE (sem, INSN_L_SWA) : /* l.swa ${simm16-split}($rA),$rB */ | |
1020 | { | |
1021 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1022 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1023 | #define FLD(f) abuf->fields.sfmt_l_sw.f | |
1024 | int UNUSED written = 0; | |
1025 | IADDR UNUSED pc = abuf->addr; | |
1026 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1027 | ||
1028 | { | |
1029 | SI tmp_addr; | |
1030 | BI tmp_flag; | |
1031 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4); | |
1032 | { | |
1033 | USI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address))); | |
1034 | SET_H_SYS_SR_F (opval); | |
1035 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
1036 | } | |
1037 | if (GET_H_SYS_SR_F ()) { | |
1038 | { | |
1039 | USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3))); | |
1040 | SETMEMUSI (current_cpu, pc, tmp_addr, opval); | |
1041 | written |= (1 << 7); | |
1042 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
1043 | } | |
1044 | } | |
1045 | { | |
1046 | BI opval = 0; | |
1047 | CPU (h_atomic_reserve) = opval; | |
1048 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | abuf->written = written; | |
1053 | #undef FLD | |
1054 | } | |
1055 | NEXT (vpc); | |
1056 | ||
1057 | CASE (sem, INSN_L_SLL) : /* l.sll $rD,$rA,$rB */ | |
1058 | { | |
1059 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1060 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1061 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1062 | int UNUSED written = 0; | |
1063 | IADDR UNUSED pc = abuf->addr; | |
1064 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1065 | ||
1066 | { | |
1067 | USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1068 | SET_H_GPR (FLD (f_r1), opval); | |
1069 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1070 | } | |
1071 | ||
1072 | #undef FLD | |
1073 | } | |
1074 | NEXT (vpc); | |
1075 | ||
1076 | CASE (sem, INSN_L_SLLI) : /* l.slli $rD,$rA,${uimm6} */ | |
1077 | { | |
1078 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1079 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1080 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1081 | int UNUSED written = 0; | |
1082 | IADDR UNUSED pc = abuf->addr; | |
1083 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1084 | ||
1085 | { | |
1086 | USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); | |
1087 | SET_H_GPR (FLD (f_r1), opval); | |
1088 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1089 | } | |
1090 | ||
1091 | #undef FLD | |
1092 | } | |
1093 | NEXT (vpc); | |
1094 | ||
1095 | CASE (sem, INSN_L_SRL) : /* l.srl $rD,$rA,$rB */ | |
1096 | { | |
1097 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1098 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1099 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1100 | int UNUSED written = 0; | |
1101 | IADDR UNUSED pc = abuf->addr; | |
1102 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1103 | ||
1104 | { | |
1105 | USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1106 | SET_H_GPR (FLD (f_r1), opval); | |
1107 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1108 | } | |
1109 | ||
1110 | #undef FLD | |
1111 | } | |
1112 | NEXT (vpc); | |
1113 | ||
1114 | CASE (sem, INSN_L_SRLI) : /* l.srli $rD,$rA,${uimm6} */ | |
1115 | { | |
1116 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1117 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1118 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1119 | int UNUSED written = 0; | |
1120 | IADDR UNUSED pc = abuf->addr; | |
1121 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1122 | ||
1123 | { | |
1124 | USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); | |
1125 | SET_H_GPR (FLD (f_r1), opval); | |
1126 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1127 | } | |
1128 | ||
1129 | #undef FLD | |
1130 | } | |
1131 | NEXT (vpc); | |
1132 | ||
1133 | CASE (sem, INSN_L_SRA) : /* l.sra $rD,$rA,$rB */ | |
1134 | { | |
1135 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1136 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1137 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1138 | int UNUSED written = 0; | |
1139 | IADDR UNUSED pc = abuf->addr; | |
1140 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1141 | ||
1142 | { | |
1143 | USI opval = SRASI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1144 | SET_H_GPR (FLD (f_r1), opval); | |
1145 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1146 | } | |
1147 | ||
1148 | #undef FLD | |
1149 | } | |
1150 | NEXT (vpc); | |
1151 | ||
1152 | CASE (sem, INSN_L_SRAI) : /* l.srai $rD,$rA,${uimm6} */ | |
1153 | { | |
1154 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1155 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1156 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1157 | int UNUSED written = 0; | |
1158 | IADDR UNUSED pc = abuf->addr; | |
1159 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1160 | ||
1161 | { | |
1162 | USI opval = SRASI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); | |
1163 | SET_H_GPR (FLD (f_r1), opval); | |
1164 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1165 | } | |
1166 | ||
1167 | #undef FLD | |
1168 | } | |
1169 | NEXT (vpc); | |
1170 | ||
1171 | CASE (sem, INSN_L_ROR) : /* l.ror $rD,$rA,$rB */ | |
1172 | { | |
1173 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1174 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1175 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1176 | int UNUSED written = 0; | |
1177 | IADDR UNUSED pc = abuf->addr; | |
1178 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1179 | ||
1180 | { | |
1181 | USI opval = RORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1182 | SET_H_GPR (FLD (f_r1), opval); | |
1183 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1184 | } | |
1185 | ||
1186 | #undef FLD | |
1187 | } | |
1188 | NEXT (vpc); | |
1189 | ||
1190 | CASE (sem, INSN_L_RORI) : /* l.rori $rD,$rA,${uimm6} */ | |
1191 | { | |
1192 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1193 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1194 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1195 | int UNUSED written = 0; | |
1196 | IADDR UNUSED pc = abuf->addr; | |
1197 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1198 | ||
1199 | { | |
1200 | USI opval = RORSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); | |
1201 | SET_H_GPR (FLD (f_r1), opval); | |
1202 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1203 | } | |
1204 | ||
1205 | #undef FLD | |
1206 | } | |
1207 | NEXT (vpc); | |
1208 | ||
1209 | CASE (sem, INSN_L_AND) : /* l.and $rD,$rA,$rB */ | |
1210 | { | |
1211 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1212 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1213 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1214 | int UNUSED written = 0; | |
1215 | IADDR UNUSED pc = abuf->addr; | |
1216 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1217 | ||
1218 | { | |
1219 | USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1220 | SET_H_GPR (FLD (f_r1), opval); | |
1221 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1222 | } | |
1223 | ||
1224 | #undef FLD | |
1225 | } | |
1226 | NEXT (vpc); | |
1227 | ||
1228 | CASE (sem, INSN_L_OR) : /* l.or $rD,$rA,$rB */ | |
1229 | { | |
1230 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1231 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1232 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1233 | int UNUSED written = 0; | |
1234 | IADDR UNUSED pc = abuf->addr; | |
1235 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1236 | ||
1237 | { | |
1238 | USI opval = ORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1239 | SET_H_GPR (FLD (f_r1), opval); | |
1240 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1241 | } | |
1242 | ||
1243 | #undef FLD | |
1244 | } | |
1245 | NEXT (vpc); | |
1246 | ||
1247 | CASE (sem, INSN_L_XOR) : /* l.xor $rD,$rA,$rB */ | |
1248 | { | |
1249 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1250 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1251 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1252 | int UNUSED written = 0; | |
1253 | IADDR UNUSED pc = abuf->addr; | |
1254 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1255 | ||
1256 | { | |
1257 | USI opval = XORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1258 | SET_H_GPR (FLD (f_r1), opval); | |
1259 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1260 | } | |
1261 | ||
1262 | #undef FLD | |
1263 | } | |
1264 | NEXT (vpc); | |
1265 | ||
1266 | CASE (sem, INSN_L_ADD) : /* l.add $rD,$rA,$rB */ | |
1267 | { | |
1268 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1269 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1270 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1271 | int UNUSED written = 0; | |
1272 | IADDR UNUSED pc = abuf->addr; | |
1273 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1274 | ||
1275 | { | |
1276 | { | |
1277 | { | |
1278 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); | |
1279 | SET_H_SYS_SR_CY (opval); | |
1280 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1281 | } | |
1282 | { | |
1283 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); | |
1284 | SET_H_SYS_SR_OV (opval); | |
1285 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1286 | } | |
1287 | { | |
1288 | USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1289 | SET_H_GPR (FLD (f_r1), opval); | |
1290 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1291 | } | |
1292 | } | |
1293 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1294 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1295 | } | |
1296 | } | |
1297 | ||
1298 | #undef FLD | |
1299 | } | |
1300 | NEXT (vpc); | |
1301 | ||
1302 | CASE (sem, INSN_L_SUB) : /* l.sub $rD,$rA,$rB */ | |
1303 | { | |
1304 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1305 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1306 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1307 | int UNUSED written = 0; | |
1308 | IADDR UNUSED pc = abuf->addr; | |
1309 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1310 | ||
1311 | { | |
1312 | { | |
1313 | { | |
1314 | BI opval = SUBCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); | |
1315 | SET_H_SYS_SR_CY (opval); | |
1316 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1317 | } | |
1318 | { | |
1319 | BI opval = SUBOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); | |
1320 | SET_H_SYS_SR_OV (opval); | |
1321 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1322 | } | |
1323 | { | |
1324 | USI opval = SUBSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1325 | SET_H_GPR (FLD (f_r1), opval); | |
1326 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1327 | } | |
1328 | } | |
1329 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1330 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | #undef FLD | |
1335 | } | |
1336 | NEXT (vpc); | |
1337 | ||
1338 | CASE (sem, INSN_L_ADDC) : /* l.addc $rD,$rA,$rB */ | |
1339 | { | |
1340 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1341 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1342 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1343 | int UNUSED written = 0; | |
1344 | IADDR UNUSED pc = abuf->addr; | |
1345 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1346 | ||
1347 | { | |
1348 | { | |
1349 | BI tmp_tmp_sys_sr_cy; | |
1350 | tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY (); | |
1351 | { | |
1352 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy); | |
1353 | SET_H_SYS_SR_CY (opval); | |
1354 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1355 | } | |
1356 | { | |
1357 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy); | |
1358 | SET_H_SYS_SR_OV (opval); | |
1359 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1360 | } | |
1361 | { | |
1362 | USI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy); | |
1363 | SET_H_GPR (FLD (f_r1), opval); | |
1364 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1365 | } | |
1366 | } | |
1367 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1368 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1369 | } | |
1370 | } | |
1371 | ||
1372 | #undef FLD | |
1373 | } | |
1374 | NEXT (vpc); | |
1375 | ||
1376 | CASE (sem, INSN_L_MUL) : /* l.mul $rD,$rA,$rB */ | |
1377 | { | |
1378 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1379 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1380 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1381 | int UNUSED written = 0; | |
1382 | IADDR UNUSED pc = abuf->addr; | |
1383 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1384 | ||
1385 | { | |
1386 | { | |
1387 | { | |
1388 | BI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1389 | SET_H_SYS_SR_OV (opval); | |
1390 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1391 | } | |
6e51bfa7 SH |
1392 | { |
1393 | USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1394 | SET_H_GPR (FLD (f_r1), opval); | |
1395 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1396 | } | |
1397 | } | |
1398 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1399 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1400 | } | |
1401 | } | |
1402 | ||
1403 | #undef FLD | |
1404 | } | |
1405 | NEXT (vpc); | |
1406 | ||
07f5f4c6 | 1407 | CASE (sem, INSN_L_MULD) : /* l.muld $rA,$rB */ |
6e51bfa7 SH |
1408 | { |
1409 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1410 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1411 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1412 | int UNUSED written = 0; | |
1413 | IADDR UNUSED pc = abuf->addr; | |
1414 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1415 | ||
1416 | { | |
07f5f4c6 RH |
1417 | DI tmp_result; |
1418 | tmp_result = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); | |
6e51bfa7 | 1419 | { |
07f5f4c6 RH |
1420 | SI opval = SUBWORDDISI (tmp_result, 0); |
1421 | SET_H_MAC_MACHI (opval); | |
1422 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
1423 | } | |
1424 | { | |
1425 | SI opval = SUBWORDDISI (tmp_result, 1); | |
1426 | SET_H_MAC_MACLO (opval); | |
1427 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
6e51bfa7 | 1428 | } |
07f5f4c6 RH |
1429 | } |
1430 | ||
1431 | #undef FLD | |
1432 | } | |
1433 | NEXT (vpc); | |
1434 | ||
1435 | CASE (sem, INSN_L_MULU) : /* l.mulu $rD,$rA,$rB */ | |
1436 | { | |
1437 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1438 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1439 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1440 | int UNUSED written = 0; | |
1441 | IADDR UNUSED pc = abuf->addr; | |
1442 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1443 | ||
1444 | { | |
1445 | { | |
6e51bfa7 SH |
1446 | { |
1447 | BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1448 | SET_H_SYS_SR_CY (opval); | |
1449 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1450 | } | |
1451 | { | |
1452 | USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1453 | SET_H_GPR (FLD (f_r1), opval); | |
1454 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1455 | } | |
1456 | } | |
07f5f4c6 | 1457 | if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { |
6e51bfa7 SH |
1458 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
1459 | } | |
1460 | } | |
1461 | ||
1462 | #undef FLD | |
1463 | } | |
1464 | NEXT (vpc); | |
1465 | ||
07f5f4c6 | 1466 | CASE (sem, INSN_L_MULDU) : /* l.muldu $rA,$rB */ |
6e51bfa7 SH |
1467 | { |
1468 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1469 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1470 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1471 | int UNUSED written = 0; | |
1472 | IADDR UNUSED pc = abuf->addr; | |
1473 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1474 | ||
1475 | { | |
07f5f4c6 RH |
1476 | DI tmp_result; |
1477 | tmp_result = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); | |
1478 | { | |
1479 | SI opval = SUBWORDDISI (tmp_result, 0); | |
1480 | SET_H_MAC_MACHI (opval); | |
1481 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
1482 | } | |
1483 | { | |
1484 | SI opval = SUBWORDDISI (tmp_result, 1); | |
1485 | SET_H_MAC_MACLO (opval); | |
1486 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
1487 | } | |
1488 | } | |
1489 | ||
1490 | #undef FLD | |
1491 | } | |
1492 | NEXT (vpc); | |
1493 | ||
1494 | CASE (sem, INSN_L_DIV) : /* l.div $rD,$rA,$rB */ | |
1495 | { | |
1496 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1497 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1498 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1499 | int UNUSED written = 0; | |
1500 | IADDR UNUSED pc = abuf->addr; | |
1501 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1502 | ||
6e51bfa7 SH |
1503 | if (NESI (GET_H_GPR (FLD (f_r3)), 0)) { |
1504 | { | |
1505 | { | |
1506 | BI opval = 0; | |
07f5f4c6 RH |
1507 | SET_H_SYS_SR_OV (opval); |
1508 | written |= (1 << 5); | |
1509 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
6e51bfa7 SH |
1510 | } |
1511 | { | |
1512 | SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1513 | SET_H_GPR (FLD (f_r1), opval); | |
07f5f4c6 | 1514 | written |= (1 << 4); |
6e51bfa7 SH |
1515 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
1516 | } | |
1517 | } | |
1518 | } else { | |
07f5f4c6 | 1519 | { |
6e51bfa7 SH |
1520 | { |
1521 | BI opval = 1; | |
6e51bfa7 | 1522 | SET_H_SYS_SR_OV (opval); |
07f5f4c6 | 1523 | written |= (1 << 5); |
6e51bfa7 SH |
1524 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
1525 | } | |
07f5f4c6 | 1526 | if (GET_H_SYS_SR_OVE ()) { |
6e51bfa7 SH |
1527 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
1528 | } | |
07f5f4c6 | 1529 | } |
6e51bfa7 SH |
1530 | } |
1531 | ||
1532 | abuf->written = written; | |
1533 | #undef FLD | |
1534 | } | |
1535 | NEXT (vpc); | |
1536 | ||
1537 | CASE (sem, INSN_L_DIVU) : /* l.divu $rD,$rA,$rB */ | |
1538 | { | |
1539 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1540 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1541 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1542 | int UNUSED written = 0; | |
1543 | IADDR UNUSED pc = abuf->addr; | |
1544 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1545 | ||
6e51bfa7 SH |
1546 | if (NESI (GET_H_GPR (FLD (f_r3)), 0)) { |
1547 | { | |
1548 | { | |
1549 | BI opval = 0; | |
1550 | SET_H_SYS_SR_CY (opval); | |
07f5f4c6 | 1551 | written |= (1 << 5); |
6e51bfa7 SH |
1552 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
1553 | } | |
1554 | { | |
1555 | USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1556 | SET_H_GPR (FLD (f_r1), opval); | |
07f5f4c6 | 1557 | written |= (1 << 4); |
6e51bfa7 SH |
1558 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
1559 | } | |
1560 | } | |
1561 | } else { | |
07f5f4c6 | 1562 | { |
6e51bfa7 SH |
1563 | { |
1564 | BI opval = 1; | |
1565 | SET_H_SYS_SR_CY (opval); | |
07f5f4c6 | 1566 | written |= (1 << 5); |
6e51bfa7 SH |
1567 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
1568 | } | |
07f5f4c6 | 1569 | if (GET_H_SYS_SR_OVE ()) { |
6e51bfa7 SH |
1570 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
1571 | } | |
07f5f4c6 | 1572 | } |
6e51bfa7 SH |
1573 | } |
1574 | ||
1575 | abuf->written = written; | |
1576 | #undef FLD | |
1577 | } | |
1578 | NEXT (vpc); | |
1579 | ||
1580 | CASE (sem, INSN_L_FF1) : /* l.ff1 $rD,$rA */ | |
1581 | { | |
1582 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1583 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1584 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1585 | int UNUSED written = 0; | |
1586 | IADDR UNUSED pc = abuf->addr; | |
1587 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1588 | ||
1589 | { | |
1590 | USI opval = or1k32bf_ff1 (current_cpu, GET_H_GPR (FLD (f_r2))); | |
1591 | SET_H_GPR (FLD (f_r1), opval); | |
1592 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1593 | } | |
1594 | ||
1595 | #undef FLD | |
1596 | } | |
1597 | NEXT (vpc); | |
1598 | ||
1599 | CASE (sem, INSN_L_FL1) : /* l.fl1 $rD,$rA */ | |
1600 | { | |
1601 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1602 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1603 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1604 | int UNUSED written = 0; | |
1605 | IADDR UNUSED pc = abuf->addr; | |
1606 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1607 | ||
1608 | { | |
1609 | USI opval = or1k32bf_fl1 (current_cpu, GET_H_GPR (FLD (f_r2))); | |
1610 | SET_H_GPR (FLD (f_r1), opval); | |
1611 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1612 | } | |
1613 | ||
1614 | #undef FLD | |
1615 | } | |
1616 | NEXT (vpc); | |
1617 | ||
1618 | CASE (sem, INSN_L_ANDI) : /* l.andi $rD,$rA,$uimm16 */ | |
1619 | { | |
1620 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1621 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1622 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f | |
1623 | int UNUSED written = 0; | |
1624 | IADDR UNUSED pc = abuf->addr; | |
1625 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1626 | ||
1627 | { | |
1628 | USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))); | |
1629 | SET_H_GPR (FLD (f_r1), opval); | |
1630 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1631 | } | |
1632 | ||
1633 | #undef FLD | |
1634 | } | |
1635 | NEXT (vpc); | |
1636 | ||
1637 | CASE (sem, INSN_L_ORI) : /* l.ori $rD,$rA,$uimm16 */ | |
1638 | { | |
1639 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1640 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1641 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f | |
1642 | int UNUSED written = 0; | |
1643 | IADDR UNUSED pc = abuf->addr; | |
1644 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1645 | ||
1646 | { | |
1647 | USI opval = ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))); | |
1648 | SET_H_GPR (FLD (f_r1), opval); | |
1649 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1650 | } | |
1651 | ||
1652 | #undef FLD | |
1653 | } | |
1654 | NEXT (vpc); | |
1655 | ||
1656 | CASE (sem, INSN_L_XORI) : /* l.xori $rD,$rA,$simm16 */ | |
1657 | { | |
1658 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1659 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1660 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1661 | int UNUSED written = 0; | |
1662 | IADDR UNUSED pc = abuf->addr; | |
1663 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1664 | ||
1665 | { | |
1666 | USI opval = XORSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1667 | SET_H_GPR (FLD (f_r1), opval); | |
1668 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1669 | } | |
1670 | ||
1671 | #undef FLD | |
1672 | } | |
1673 | NEXT (vpc); | |
1674 | ||
1675 | CASE (sem, INSN_L_ADDI) : /* l.addi $rD,$rA,$simm16 */ | |
1676 | { | |
1677 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1678 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1679 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1680 | int UNUSED written = 0; | |
1681 | IADDR UNUSED pc = abuf->addr; | |
1682 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1683 | ||
1684 | { | |
1685 | { | |
1686 | { | |
1687 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0); | |
1688 | SET_H_SYS_SR_CY (opval); | |
1689 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1690 | } | |
1691 | { | |
1692 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0); | |
1693 | SET_H_SYS_SR_OV (opval); | |
1694 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1695 | } | |
1696 | { | |
1697 | USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1698 | SET_H_GPR (FLD (f_r1), opval); | |
1699 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1700 | } | |
1701 | } | |
1702 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1703 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1704 | } | |
1705 | } | |
1706 | ||
1707 | #undef FLD | |
1708 | } | |
1709 | NEXT (vpc); | |
1710 | ||
1711 | CASE (sem, INSN_L_ADDIC) : /* l.addic $rD,$rA,$simm16 */ | |
1712 | { | |
1713 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1714 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1715 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1716 | int UNUSED written = 0; | |
1717 | IADDR UNUSED pc = abuf->addr; | |
1718 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1719 | ||
1720 | { | |
1721 | { | |
1722 | BI tmp_tmp_sys_sr_cy; | |
1723 | tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY (); | |
1724 | { | |
1725 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy); | |
1726 | SET_H_SYS_SR_CY (opval); | |
1727 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1728 | } | |
1729 | { | |
1730 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy); | |
1731 | SET_H_SYS_SR_OV (opval); | |
1732 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1733 | } | |
1734 | { | |
1735 | SI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy); | |
1736 | SET_H_GPR (FLD (f_r1), opval); | |
1737 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1738 | } | |
1739 | } | |
1740 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1741 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1742 | } | |
1743 | } | |
1744 | ||
1745 | #undef FLD | |
1746 | } | |
1747 | NEXT (vpc); | |
1748 | ||
1749 | CASE (sem, INSN_L_MULI) : /* l.muli $rD,$rA,$simm16 */ | |
1750 | { | |
1751 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1752 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1753 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1754 | int UNUSED written = 0; | |
1755 | IADDR UNUSED pc = abuf->addr; | |
1756 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1757 | ||
1758 | { | |
1759 | { | |
1760 | { | |
1761 | USI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1762 | SET_H_SYS_SR_OV (opval); | |
1763 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1764 | } | |
6e51bfa7 SH |
1765 | { |
1766 | USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1767 | SET_H_GPR (FLD (f_r1), opval); | |
1768 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1769 | } | |
1770 | } | |
1771 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1772 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1773 | } | |
1774 | } | |
1775 | ||
1776 | #undef FLD | |
1777 | } | |
1778 | NEXT (vpc); | |
1779 | ||
1780 | CASE (sem, INSN_L_EXTHS) : /* l.exths $rD,$rA */ | |
1781 | { | |
1782 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1783 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1784 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1785 | int UNUSED written = 0; | |
1786 | IADDR UNUSED pc = abuf->addr; | |
1787 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1788 | ||
1789 | { | |
1790 | USI opval = EXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2)))); | |
1791 | SET_H_GPR (FLD (f_r1), opval); | |
1792 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1793 | } | |
1794 | ||
1795 | #undef FLD | |
1796 | } | |
1797 | NEXT (vpc); | |
1798 | ||
1799 | CASE (sem, INSN_L_EXTBS) : /* l.extbs $rD,$rA */ | |
1800 | { | |
1801 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1802 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1803 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1804 | int UNUSED written = 0; | |
1805 | IADDR UNUSED pc = abuf->addr; | |
1806 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1807 | ||
1808 | { | |
1809 | USI opval = EXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2)))); | |
1810 | SET_H_GPR (FLD (f_r1), opval); | |
1811 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1812 | } | |
1813 | ||
1814 | #undef FLD | |
1815 | } | |
1816 | NEXT (vpc); | |
1817 | ||
1818 | CASE (sem, INSN_L_EXTHZ) : /* l.exthz $rD,$rA */ | |
1819 | { | |
1820 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1821 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1822 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1823 | int UNUSED written = 0; | |
1824 | IADDR UNUSED pc = abuf->addr; | |
1825 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1826 | ||
1827 | { | |
1828 | USI opval = ZEXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2)))); | |
1829 | SET_H_GPR (FLD (f_r1), opval); | |
1830 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1831 | } | |
1832 | ||
1833 | #undef FLD | |
1834 | } | |
1835 | NEXT (vpc); | |
1836 | ||
1837 | CASE (sem, INSN_L_EXTBZ) : /* l.extbz $rD,$rA */ | |
1838 | { | |
1839 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1840 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1841 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1842 | int UNUSED written = 0; | |
1843 | IADDR UNUSED pc = abuf->addr; | |
1844 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1845 | ||
1846 | { | |
1847 | USI opval = ZEXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2)))); | |
1848 | SET_H_GPR (FLD (f_r1), opval); | |
1849 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1850 | } | |
1851 | ||
1852 | #undef FLD | |
1853 | } | |
1854 | NEXT (vpc); | |
1855 | ||
1856 | CASE (sem, INSN_L_EXTWS) : /* l.extws $rD,$rA */ | |
1857 | { | |
1858 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1859 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1860 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1861 | int UNUSED written = 0; | |
1862 | IADDR UNUSED pc = abuf->addr; | |
1863 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1864 | ||
1865 | { | |
1866 | USI opval = EXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2)))); | |
1867 | SET_H_GPR (FLD (f_r1), opval); | |
1868 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1869 | } | |
1870 | ||
1871 | #undef FLD | |
1872 | } | |
1873 | NEXT (vpc); | |
1874 | ||
1875 | CASE (sem, INSN_L_EXTWZ) : /* l.extwz $rD,$rA */ | |
1876 | { | |
1877 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1878 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1879 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1880 | int UNUSED written = 0; | |
1881 | IADDR UNUSED pc = abuf->addr; | |
1882 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1883 | ||
1884 | { | |
1885 | USI opval = ZEXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2)))); | |
1886 | SET_H_GPR (FLD (f_r1), opval); | |
1887 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1888 | } | |
1889 | ||
1890 | #undef FLD | |
1891 | } | |
1892 | NEXT (vpc); | |
1893 | ||
1894 | CASE (sem, INSN_L_CMOV) : /* l.cmov $rD,$rA,$rB */ | |
1895 | { | |
1896 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1897 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1898 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1899 | int UNUSED written = 0; | |
1900 | IADDR UNUSED pc = abuf->addr; | |
1901 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1902 | ||
1903 | if (GET_H_SYS_SR_F ()) { | |
1904 | { | |
1905 | USI opval = GET_H_GPR (FLD (f_r2)); | |
1906 | SET_H_GPR (FLD (f_r1), opval); | |
1907 | written |= (1 << 3); | |
1908 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1909 | } | |
1910 | } else { | |
1911 | { | |
1912 | USI opval = GET_H_GPR (FLD (f_r3)); | |
1913 | SET_H_GPR (FLD (f_r1), opval); | |
1914 | written |= (1 << 3); | |
1915 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1916 | } | |
1917 | } | |
1918 | ||
1919 | abuf->written = written; | |
1920 | #undef FLD | |
1921 | } | |
1922 | NEXT (vpc); | |
1923 | ||
1924 | CASE (sem, INSN_L_SFGTS) : /* l.sfgts $rA,$rB */ | |
1925 | { | |
1926 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1927 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1928 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1929 | int UNUSED written = 0; | |
1930 | IADDR UNUSED pc = abuf->addr; | |
1931 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1932 | ||
1933 | { | |
1934 | USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1935 | SET_H_SYS_SR_F (opval); | |
1936 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
1937 | } | |
1938 | ||
1939 | #undef FLD | |
1940 | } | |
1941 | NEXT (vpc); | |
1942 | ||
1943 | CASE (sem, INSN_L_SFGTSI) : /* l.sfgtsi $rA,$simm16 */ | |
1944 | { | |
1945 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1946 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1947 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1948 | int UNUSED written = 0; | |
1949 | IADDR UNUSED pc = abuf->addr; | |
1950 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1951 | ||
1952 | { | |
1953 | USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1954 | SET_H_SYS_SR_F (opval); | |
1955 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
1956 | } | |
1957 | ||
1958 | #undef FLD | |
1959 | } | |
1960 | NEXT (vpc); | |
1961 | ||
1962 | CASE (sem, INSN_L_SFGTU) : /* l.sfgtu $rA,$rB */ | |
1963 | { | |
1964 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1965 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1966 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1967 | int UNUSED written = 0; | |
1968 | IADDR UNUSED pc = abuf->addr; | |
1969 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1970 | ||
1971 | { | |
1972 | USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1973 | SET_H_SYS_SR_F (opval); | |
1974 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
1975 | } | |
1976 | ||
1977 | #undef FLD | |
1978 | } | |
1979 | NEXT (vpc); | |
1980 | ||
1981 | CASE (sem, INSN_L_SFGTUI) : /* l.sfgtui $rA,$simm16 */ | |
1982 | { | |
1983 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
1984 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1985 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1986 | int UNUSED written = 0; | |
1987 | IADDR UNUSED pc = abuf->addr; | |
1988 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1989 | ||
1990 | { | |
1991 | USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1992 | SET_H_SYS_SR_F (opval); | |
1993 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
1994 | } | |
1995 | ||
1996 | #undef FLD | |
1997 | } | |
1998 | NEXT (vpc); | |
1999 | ||
2000 | CASE (sem, INSN_L_SFGES) : /* l.sfges $rA,$rB */ | |
2001 | { | |
2002 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2003 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2004 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2005 | int UNUSED written = 0; | |
2006 | IADDR UNUSED pc = abuf->addr; | |
2007 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2008 | ||
2009 | { | |
2010 | USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2011 | SET_H_SYS_SR_F (opval); | |
2012 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2013 | } | |
2014 | ||
2015 | #undef FLD | |
2016 | } | |
2017 | NEXT (vpc); | |
2018 | ||
2019 | CASE (sem, INSN_L_SFGESI) : /* l.sfgesi $rA,$simm16 */ | |
2020 | { | |
2021 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2022 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2023 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2024 | int UNUSED written = 0; | |
2025 | IADDR UNUSED pc = abuf->addr; | |
2026 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2027 | ||
2028 | { | |
2029 | USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2030 | SET_H_SYS_SR_F (opval); | |
2031 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2032 | } | |
2033 | ||
2034 | #undef FLD | |
2035 | } | |
2036 | NEXT (vpc); | |
2037 | ||
2038 | CASE (sem, INSN_L_SFGEU) : /* l.sfgeu $rA,$rB */ | |
2039 | { | |
2040 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2041 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2042 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2043 | int UNUSED written = 0; | |
2044 | IADDR UNUSED pc = abuf->addr; | |
2045 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2046 | ||
2047 | { | |
2048 | USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2049 | SET_H_SYS_SR_F (opval); | |
2050 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2051 | } | |
2052 | ||
2053 | #undef FLD | |
2054 | } | |
2055 | NEXT (vpc); | |
2056 | ||
2057 | CASE (sem, INSN_L_SFGEUI) : /* l.sfgeui $rA,$simm16 */ | |
2058 | { | |
2059 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2060 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2061 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2062 | int UNUSED written = 0; | |
2063 | IADDR UNUSED pc = abuf->addr; | |
2064 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2065 | ||
2066 | { | |
2067 | USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2068 | SET_H_SYS_SR_F (opval); | |
2069 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2070 | } | |
2071 | ||
2072 | #undef FLD | |
2073 | } | |
2074 | NEXT (vpc); | |
2075 | ||
2076 | CASE (sem, INSN_L_SFLTS) : /* l.sflts $rA,$rB */ | |
2077 | { | |
2078 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2079 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2080 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2081 | int UNUSED written = 0; | |
2082 | IADDR UNUSED pc = abuf->addr; | |
2083 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2084 | ||
2085 | { | |
2086 | USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2087 | SET_H_SYS_SR_F (opval); | |
2088 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2089 | } | |
2090 | ||
2091 | #undef FLD | |
2092 | } | |
2093 | NEXT (vpc); | |
2094 | ||
2095 | CASE (sem, INSN_L_SFLTSI) : /* l.sfltsi $rA,$simm16 */ | |
2096 | { | |
2097 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2098 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2099 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2100 | int UNUSED written = 0; | |
2101 | IADDR UNUSED pc = abuf->addr; | |
2102 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2103 | ||
2104 | { | |
2105 | USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2106 | SET_H_SYS_SR_F (opval); | |
2107 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2108 | } | |
2109 | ||
2110 | #undef FLD | |
2111 | } | |
2112 | NEXT (vpc); | |
2113 | ||
2114 | CASE (sem, INSN_L_SFLTU) : /* l.sfltu $rA,$rB */ | |
2115 | { | |
2116 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2117 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2118 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2119 | int UNUSED written = 0; | |
2120 | IADDR UNUSED pc = abuf->addr; | |
2121 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2122 | ||
2123 | { | |
2124 | USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2125 | SET_H_SYS_SR_F (opval); | |
2126 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2127 | } | |
2128 | ||
2129 | #undef FLD | |
2130 | } | |
2131 | NEXT (vpc); | |
2132 | ||
2133 | CASE (sem, INSN_L_SFLTUI) : /* l.sfltui $rA,$simm16 */ | |
2134 | { | |
2135 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2136 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2137 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2138 | int UNUSED written = 0; | |
2139 | IADDR UNUSED pc = abuf->addr; | |
2140 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2141 | ||
2142 | { | |
2143 | USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2144 | SET_H_SYS_SR_F (opval); | |
2145 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2146 | } | |
2147 | ||
2148 | #undef FLD | |
2149 | } | |
2150 | NEXT (vpc); | |
2151 | ||
2152 | CASE (sem, INSN_L_SFLES) : /* l.sfles $rA,$rB */ | |
2153 | { | |
2154 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2155 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2156 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2157 | int UNUSED written = 0; | |
2158 | IADDR UNUSED pc = abuf->addr; | |
2159 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2160 | ||
2161 | { | |
2162 | USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2163 | SET_H_SYS_SR_F (opval); | |
2164 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2165 | } | |
2166 | ||
2167 | #undef FLD | |
2168 | } | |
2169 | NEXT (vpc); | |
2170 | ||
2171 | CASE (sem, INSN_L_SFLESI) : /* l.sflesi $rA,$simm16 */ | |
2172 | { | |
2173 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2174 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2175 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2176 | int UNUSED written = 0; | |
2177 | IADDR UNUSED pc = abuf->addr; | |
2178 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2179 | ||
2180 | { | |
2181 | USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2182 | SET_H_SYS_SR_F (opval); | |
2183 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2184 | } | |
2185 | ||
2186 | #undef FLD | |
2187 | } | |
2188 | NEXT (vpc); | |
2189 | ||
2190 | CASE (sem, INSN_L_SFLEU) : /* l.sfleu $rA,$rB */ | |
2191 | { | |
2192 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2193 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2194 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2195 | int UNUSED written = 0; | |
2196 | IADDR UNUSED pc = abuf->addr; | |
2197 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2198 | ||
2199 | { | |
2200 | USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2201 | SET_H_SYS_SR_F (opval); | |
2202 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2203 | } | |
2204 | ||
2205 | #undef FLD | |
2206 | } | |
2207 | NEXT (vpc); | |
2208 | ||
2209 | CASE (sem, INSN_L_SFLEUI) : /* l.sfleui $rA,$simm16 */ | |
2210 | { | |
2211 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2212 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2213 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2214 | int UNUSED written = 0; | |
2215 | IADDR UNUSED pc = abuf->addr; | |
2216 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2217 | ||
2218 | { | |
2219 | USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2220 | SET_H_SYS_SR_F (opval); | |
2221 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2222 | } | |
2223 | ||
2224 | #undef FLD | |
2225 | } | |
2226 | NEXT (vpc); | |
2227 | ||
2228 | CASE (sem, INSN_L_SFEQ) : /* l.sfeq $rA,$rB */ | |
2229 | { | |
2230 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2231 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2232 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2233 | int UNUSED written = 0; | |
2234 | IADDR UNUSED pc = abuf->addr; | |
2235 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2236 | ||
2237 | { | |
2238 | USI opval = EQSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2239 | SET_H_SYS_SR_F (opval); | |
2240 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2241 | } | |
2242 | ||
2243 | #undef FLD | |
2244 | } | |
2245 | NEXT (vpc); | |
2246 | ||
2247 | CASE (sem, INSN_L_SFEQI) : /* l.sfeqi $rA,$simm16 */ | |
2248 | { | |
2249 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2250 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2251 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2252 | int UNUSED written = 0; | |
2253 | IADDR UNUSED pc = abuf->addr; | |
2254 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2255 | ||
2256 | { | |
2257 | USI opval = EQSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2258 | SET_H_SYS_SR_F (opval); | |
2259 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2260 | } | |
2261 | ||
2262 | #undef FLD | |
2263 | } | |
2264 | NEXT (vpc); | |
2265 | ||
2266 | CASE (sem, INSN_L_SFNE) : /* l.sfne $rA,$rB */ | |
2267 | { | |
2268 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2269 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2270 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2271 | int UNUSED written = 0; | |
2272 | IADDR UNUSED pc = abuf->addr; | |
2273 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2274 | ||
2275 | { | |
2276 | USI opval = NESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2277 | SET_H_SYS_SR_F (opval); | |
2278 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2279 | } | |
2280 | ||
2281 | #undef FLD | |
2282 | } | |
2283 | NEXT (vpc); | |
2284 | ||
2285 | CASE (sem, INSN_L_SFNEI) : /* l.sfnei $rA,$simm16 */ | |
2286 | { | |
2287 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2288 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2289 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2290 | int UNUSED written = 0; | |
2291 | IADDR UNUSED pc = abuf->addr; | |
2292 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2293 | ||
2294 | { | |
2295 | USI opval = NESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2296 | SET_H_SYS_SR_F (opval); | |
2297 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2298 | } | |
2299 | ||
2300 | #undef FLD | |
2301 | } | |
2302 | NEXT (vpc); | |
2303 | ||
2304 | CASE (sem, INSN_L_MAC) : /* l.mac $rA,$rB */ | |
2305 | { | |
2306 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2307 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2308 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2309 | int UNUSED written = 0; | |
2310 | IADDR UNUSED pc = abuf->addr; | |
2311 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2312 | ||
2313 | { | |
07f5f4c6 RH |
2314 | { |
2315 | DI tmp_prod; | |
2316 | DI tmp_mac; | |
2317 | DI tmp_result; | |
2318 | tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); | |
2319 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); | |
2320 | tmp_result = ADDDI (tmp_prod, tmp_mac); | |
2321 | { | |
2322 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2323 | SET_H_MAC_MACHI (opval); | |
2324 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
2325 | } | |
2326 | { | |
2327 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2328 | SET_H_MAC_MACLO (opval); | |
2329 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
2330 | } | |
2331 | { | |
2332 | BI opval = ADDOFDI (tmp_prod, tmp_mac, 0); | |
2333 | SET_H_SYS_SR_OV (opval); | |
2334 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
2335 | } | |
2336 | } | |
2337 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
2338 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
2339 | } | |
2340 | } | |
2341 | ||
2342 | #undef FLD | |
2343 | } | |
2344 | NEXT (vpc); | |
2345 | ||
2346 | CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16} */ | |
2347 | { | |
2348 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2349 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2350 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2351 | int UNUSED written = 0; | |
2352 | IADDR UNUSED pc = abuf->addr; | |
2353 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2354 | ||
2355 | { | |
2356 | { | |
2357 | DI tmp_prod; | |
2358 | DI tmp_mac; | |
2359 | DI tmp_result; | |
2360 | tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (FLD (f_simm16))); | |
2361 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); | |
2362 | tmp_result = ADDDI (tmp_mac, tmp_prod); | |
2363 | { | |
2364 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2365 | SET_H_MAC_MACHI (opval); | |
2366 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
2367 | } | |
2368 | { | |
2369 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2370 | SET_H_MAC_MACLO (opval); | |
2371 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
2372 | } | |
2373 | { | |
2374 | BI opval = ADDOFDI (tmp_prod, tmp_mac, 0); | |
2375 | SET_H_SYS_SR_OV (opval); | |
2376 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
2377 | } | |
2378 | } | |
2379 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
2380 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
2381 | } | |
2382 | } | |
2383 | ||
2384 | #undef FLD | |
2385 | } | |
2386 | NEXT (vpc); | |
2387 | ||
2388 | CASE (sem, INSN_L_MACU) : /* l.macu $rA,$rB */ | |
2389 | { | |
2390 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2391 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2392 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2393 | int UNUSED written = 0; | |
2394 | IADDR UNUSED pc = abuf->addr; | |
2395 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2396 | ||
2397 | { | |
2398 | { | |
2399 | DI tmp_prod; | |
2400 | DI tmp_mac; | |
6e51bfa7 | 2401 | DI tmp_result; |
07f5f4c6 RH |
2402 | tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); |
2403 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); | |
2404 | tmp_result = ADDDI (tmp_prod, tmp_mac); | |
6e51bfa7 SH |
2405 | { |
2406 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2407 | SET_H_MAC_MACHI (opval); | |
2408 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
2409 | } | |
2410 | { | |
2411 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2412 | SET_H_MAC_MACLO (opval); | |
2413 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
2414 | } | |
07f5f4c6 RH |
2415 | { |
2416 | BI opval = ADDCFDI (tmp_prod, tmp_mac, 0); | |
2417 | SET_H_SYS_SR_CY (opval); | |
2418 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
2419 | } | |
2420 | } | |
2421 | if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { | |
2422 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
2423 | } | |
6e51bfa7 SH |
2424 | } |
2425 | ||
2426 | #undef FLD | |
2427 | } | |
2428 | NEXT (vpc); | |
2429 | ||
2430 | CASE (sem, INSN_L_MSB) : /* l.msb $rA,$rB */ | |
2431 | { | |
2432 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2433 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2434 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2435 | int UNUSED written = 0; | |
2436 | IADDR UNUSED pc = abuf->addr; | |
2437 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2438 | ||
2439 | { | |
07f5f4c6 RH |
2440 | { |
2441 | DI tmp_prod; | |
2442 | DI tmp_mac; | |
6e51bfa7 | 2443 | DI tmp_result; |
07f5f4c6 RH |
2444 | tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); |
2445 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); | |
2446 | tmp_result = SUBDI (tmp_mac, tmp_prod); | |
6e51bfa7 SH |
2447 | { |
2448 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2449 | SET_H_MAC_MACHI (opval); | |
2450 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
2451 | } | |
2452 | { | |
2453 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2454 | SET_H_MAC_MACLO (opval); | |
2455 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
2456 | } | |
07f5f4c6 RH |
2457 | { |
2458 | BI opval = SUBOFDI (tmp_mac, tmp_result, 0); | |
2459 | SET_H_SYS_SR_OV (opval); | |
2460 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
2461 | } | |
2462 | } | |
2463 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
2464 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
2465 | } | |
6e51bfa7 SH |
2466 | } |
2467 | ||
2468 | #undef FLD | |
2469 | } | |
2470 | NEXT (vpc); | |
2471 | ||
07f5f4c6 | 2472 | CASE (sem, INSN_L_MSBU) : /* l.msbu $rA,$rB */ |
6e51bfa7 SH |
2473 | { |
2474 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2475 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
07f5f4c6 | 2476 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
6e51bfa7 SH |
2477 | int UNUSED written = 0; |
2478 | IADDR UNUSED pc = abuf->addr; | |
2479 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2480 | ||
2481 | { | |
07f5f4c6 RH |
2482 | { |
2483 | DI tmp_prod; | |
2484 | DI tmp_mac; | |
6e51bfa7 | 2485 | DI tmp_result; |
07f5f4c6 RH |
2486 | tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); |
2487 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); | |
2488 | tmp_result = SUBDI (tmp_mac, tmp_prod); | |
6e51bfa7 SH |
2489 | { |
2490 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2491 | SET_H_MAC_MACHI (opval); | |
2492 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
2493 | } | |
2494 | { | |
2495 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2496 | SET_H_MAC_MACLO (opval); | |
2497 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
2498 | } | |
07f5f4c6 RH |
2499 | { |
2500 | BI opval = SUBCFDI (tmp_mac, tmp_result, 0); | |
2501 | SET_H_SYS_SR_CY (opval); | |
2502 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
2503 | } | |
2504 | } | |
2505 | if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { | |
2506 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
2507 | } | |
6e51bfa7 SH |
2508 | } |
2509 | ||
2510 | #undef FLD | |
2511 | } | |
2512 | NEXT (vpc); | |
2513 | ||
2514 | CASE (sem, INSN_L_CUST1) : /* l.cust1 */ | |
2515 | { | |
2516 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2517 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2518 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2519 | int UNUSED written = 0; | |
2520 | IADDR UNUSED pc = abuf->addr; | |
2521 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2522 | ||
2523 | ((void) 0); /*nop*/ | |
2524 | ||
2525 | #undef FLD | |
2526 | } | |
2527 | NEXT (vpc); | |
2528 | ||
2529 | CASE (sem, INSN_L_CUST2) : /* l.cust2 */ | |
2530 | { | |
2531 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2532 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2533 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2534 | int UNUSED written = 0; | |
2535 | IADDR UNUSED pc = abuf->addr; | |
2536 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2537 | ||
2538 | ((void) 0); /*nop*/ | |
2539 | ||
2540 | #undef FLD | |
2541 | } | |
2542 | NEXT (vpc); | |
2543 | ||
2544 | CASE (sem, INSN_L_CUST3) : /* l.cust3 */ | |
2545 | { | |
2546 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2547 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2548 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2549 | int UNUSED written = 0; | |
2550 | IADDR UNUSED pc = abuf->addr; | |
2551 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2552 | ||
2553 | ((void) 0); /*nop*/ | |
2554 | ||
2555 | #undef FLD | |
2556 | } | |
2557 | NEXT (vpc); | |
2558 | ||
2559 | CASE (sem, INSN_L_CUST4) : /* l.cust4 */ | |
2560 | { | |
2561 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2562 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2563 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2564 | int UNUSED written = 0; | |
2565 | IADDR UNUSED pc = abuf->addr; | |
2566 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2567 | ||
2568 | ((void) 0); /*nop*/ | |
2569 | ||
2570 | #undef FLD | |
2571 | } | |
2572 | NEXT (vpc); | |
2573 | ||
2574 | CASE (sem, INSN_L_CUST5) : /* l.cust5 */ | |
2575 | { | |
2576 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2577 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2578 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2579 | int UNUSED written = 0; | |
2580 | IADDR UNUSED pc = abuf->addr; | |
2581 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2582 | ||
2583 | ((void) 0); /*nop*/ | |
2584 | ||
2585 | #undef FLD | |
2586 | } | |
2587 | NEXT (vpc); | |
2588 | ||
2589 | CASE (sem, INSN_L_CUST6) : /* l.cust6 */ | |
2590 | { | |
2591 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2592 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2593 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2594 | int UNUSED written = 0; | |
2595 | IADDR UNUSED pc = abuf->addr; | |
2596 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2597 | ||
2598 | ((void) 0); /*nop*/ | |
2599 | ||
2600 | #undef FLD | |
2601 | } | |
2602 | NEXT (vpc); | |
2603 | ||
2604 | CASE (sem, INSN_L_CUST7) : /* l.cust7 */ | |
2605 | { | |
2606 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2607 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2608 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2609 | int UNUSED written = 0; | |
2610 | IADDR UNUSED pc = abuf->addr; | |
2611 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2612 | ||
2613 | ((void) 0); /*nop*/ | |
2614 | ||
2615 | #undef FLD | |
2616 | } | |
2617 | NEXT (vpc); | |
2618 | ||
2619 | CASE (sem, INSN_L_CUST8) : /* l.cust8 */ | |
2620 | { | |
2621 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2622 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2623 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2624 | int UNUSED written = 0; | |
2625 | IADDR UNUSED pc = abuf->addr; | |
2626 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2627 | ||
2628 | ((void) 0); /*nop*/ | |
2629 | ||
2630 | #undef FLD | |
2631 | } | |
2632 | NEXT (vpc); | |
2633 | ||
2634 | CASE (sem, INSN_LF_ADD_S) : /* lf.add.s $rDSF,$rASF,$rBSF */ | |
2635 | { | |
2636 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2637 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2638 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2639 | int UNUSED written = 0; | |
2640 | IADDR UNUSED pc = abuf->addr; | |
2641 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2642 | ||
2643 | { | |
2644 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2645 | SET_H_FSR (FLD (f_r1), opval); | |
2646 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2647 | } | |
2648 | ||
2649 | #undef FLD | |
2650 | } | |
2651 | NEXT (vpc); | |
2652 | ||
2653 | CASE (sem, INSN_LF_SUB_S) : /* lf.sub.s $rDSF,$rASF,$rBSF */ | |
2654 | { | |
2655 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2656 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2657 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2658 | int UNUSED written = 0; | |
2659 | IADDR UNUSED pc = abuf->addr; | |
2660 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2661 | ||
2662 | { | |
2663 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2664 | SET_H_FSR (FLD (f_r1), opval); | |
2665 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2666 | } | |
2667 | ||
2668 | #undef FLD | |
2669 | } | |
2670 | NEXT (vpc); | |
2671 | ||
2672 | CASE (sem, INSN_LF_MUL_S) : /* lf.mul.s $rDSF,$rASF,$rBSF */ | |
2673 | { | |
2674 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2675 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2676 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2677 | int UNUSED written = 0; | |
2678 | IADDR UNUSED pc = abuf->addr; | |
2679 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2680 | ||
2681 | { | |
2682 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2683 | SET_H_FSR (FLD (f_r1), opval); | |
2684 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2685 | } | |
2686 | ||
2687 | #undef FLD | |
2688 | } | |
2689 | NEXT (vpc); | |
2690 | ||
2691 | CASE (sem, INSN_LF_DIV_S) : /* lf.div.s $rDSF,$rASF,$rBSF */ | |
2692 | { | |
2693 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2694 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2695 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2696 | int UNUSED written = 0; | |
2697 | IADDR UNUSED pc = abuf->addr; | |
2698 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2699 | ||
2700 | { | |
2701 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2702 | SET_H_FSR (FLD (f_r1), opval); | |
2703 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2704 | } | |
2705 | ||
2706 | #undef FLD | |
2707 | } | |
2708 | NEXT (vpc); | |
2709 | ||
2710 | CASE (sem, INSN_LF_REM_S) : /* lf.rem.s $rDSF,$rASF,$rBSF */ | |
2711 | { | |
2712 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2713 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2714 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2715 | int UNUSED written = 0; | |
2716 | IADDR UNUSED pc = abuf->addr; | |
2717 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2718 | ||
2719 | { | |
2720 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->remsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2721 | SET_H_FSR (FLD (f_r1), opval); | |
2722 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2723 | } | |
2724 | ||
2725 | #undef FLD | |
2726 | } | |
2727 | NEXT (vpc); | |
2728 | ||
2729 | CASE (sem, INSN_LF_ITOF_S) : /* lf.itof.s $rDSF,$rA */ | |
2730 | { | |
2731 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2732 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2733 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
2734 | int UNUSED written = 0; | |
2735 | IADDR UNUSED pc = abuf->addr; | |
2736 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2737 | ||
2738 | { | |
2739 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), TRUNCSISI (GET_H_GPR (FLD (f_r2)))); | |
2740 | SET_H_FSR (FLD (f_r1), opval); | |
2741 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2742 | } | |
2743 | ||
2744 | #undef FLD | |
2745 | } | |
2746 | NEXT (vpc); | |
2747 | ||
2748 | CASE (sem, INSN_LF_FTOI_S) : /* lf.ftoi.s $rD,$rASF */ | |
2749 | { | |
2750 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2751 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2752 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
2753 | int UNUSED written = 0; | |
2754 | IADDR UNUSED pc = abuf->addr; | |
2755 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2756 | ||
2757 | { | |
2758 | SI opval = EXTSISI (CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FSR (FLD (f_r2)))); | |
2759 | SET_H_GPR (FLD (f_r1), opval); | |
2760 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
2761 | } | |
2762 | ||
2763 | #undef FLD | |
2764 | } | |
2765 | NEXT (vpc); | |
2766 | ||
2767 | CASE (sem, INSN_LF_EQ_S) : /* lf.sfeq.s $rASF,$rBSF */ | |
2768 | { | |
2769 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2770 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2771 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2772 | int UNUSED written = 0; | |
2773 | IADDR UNUSED pc = abuf->addr; | |
2774 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2775 | ||
2776 | { | |
2777 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2778 | SET_H_SYS_SR_F (opval); | |
2779 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2780 | } | |
2781 | ||
2782 | #undef FLD | |
2783 | } | |
2784 | NEXT (vpc); | |
2785 | ||
2786 | CASE (sem, INSN_LF_NE_S) : /* lf.sfne.s $rASF,$rBSF */ | |
2787 | { | |
2788 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2789 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2790 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2791 | int UNUSED written = 0; | |
2792 | IADDR UNUSED pc = abuf->addr; | |
2793 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2794 | ||
2795 | { | |
2796 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2797 | SET_H_SYS_SR_F (opval); | |
2798 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2799 | } | |
2800 | ||
2801 | #undef FLD | |
2802 | } | |
2803 | NEXT (vpc); | |
2804 | ||
2805 | CASE (sem, INSN_LF_GE_S) : /* lf.sfge.s $rASF,$rBSF */ | |
2806 | { | |
2807 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2808 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2809 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2810 | int UNUSED written = 0; | |
2811 | IADDR UNUSED pc = abuf->addr; | |
2812 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2813 | ||
2814 | { | |
2815 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2816 | SET_H_SYS_SR_F (opval); | |
2817 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2818 | } | |
2819 | ||
2820 | #undef FLD | |
2821 | } | |
2822 | NEXT (vpc); | |
2823 | ||
2824 | CASE (sem, INSN_LF_GT_S) : /* lf.sfgt.s $rASF,$rBSF */ | |
2825 | { | |
2826 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2827 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2828 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2829 | int UNUSED written = 0; | |
2830 | IADDR UNUSED pc = abuf->addr; | |
2831 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2832 | ||
2833 | { | |
2834 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2835 | SET_H_SYS_SR_F (opval); | |
2836 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2837 | } | |
2838 | ||
2839 | #undef FLD | |
2840 | } | |
2841 | NEXT (vpc); | |
2842 | ||
2843 | CASE (sem, INSN_LF_LT_S) : /* lf.sflt.s $rASF,$rBSF */ | |
2844 | { | |
2845 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2846 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2847 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2848 | int UNUSED written = 0; | |
2849 | IADDR UNUSED pc = abuf->addr; | |
2850 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2851 | ||
2852 | { | |
2853 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2854 | SET_H_SYS_SR_F (opval); | |
2855 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2856 | } | |
2857 | ||
2858 | #undef FLD | |
2859 | } | |
2860 | NEXT (vpc); | |
2861 | ||
2862 | CASE (sem, INSN_LF_LE_S) : /* lf.sfle.s $rASF,$rBSF */ | |
2863 | { | |
2864 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2865 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2866 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2867 | int UNUSED written = 0; | |
2868 | IADDR UNUSED pc = abuf->addr; | |
2869 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2870 | ||
2871 | { | |
2872 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2873 | SET_H_SYS_SR_F (opval); | |
2874 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2875 | } | |
2876 | ||
2877 | #undef FLD | |
2878 | } | |
2879 | NEXT (vpc); | |
2880 | ||
2881 | CASE (sem, INSN_LF_MADD_S) : /* lf.madd.s $rDSF,$rASF,$rBSF */ | |
2882 | { | |
2883 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2884 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2885 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2886 | int UNUSED written = 0; | |
2887 | IADDR UNUSED pc = abuf->addr; | |
2888 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2889 | ||
2890 | { | |
2891 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), GET_H_FSR (FLD (f_r1))); | |
2892 | SET_H_FSR (FLD (f_r1), opval); | |
2893 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2894 | } | |
2895 | ||
2896 | #undef FLD | |
2897 | } | |
2898 | NEXT (vpc); | |
2899 | ||
2900 | CASE (sem, INSN_LF_CUST1_S) : /* lf.cust1.s $rASF,$rBSF */ | |
2901 | { | |
2902 | SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); | |
2903 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2904 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2905 | int UNUSED written = 0; | |
2906 | IADDR UNUSED pc = abuf->addr; | |
2907 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2908 | ||
2909 | ((void) 0); /*nop*/ | |
2910 | ||
2911 | #undef FLD | |
2912 | } | |
2913 | NEXT (vpc); | |
2914 | ||
2915 | ||
2916 | } | |
2917 | ENDSWITCH (sem) /* End of semantic switch. */ | |
2918 | ||
2919 | /* At this point `vpc' contains the next insn to execute. */ | |
2920 | } | |
2921 | ||
2922 | #undef DEFINE_SWITCH | |
2923 | #endif /* DEFINE_SWITCH */ |