[thirdparty/binutils-gdb.git] / sim / sh / sim-main.h

/* Moxie Simulator definition.
   Copyright (C) 2009-2015 Free Software Foundation, Inc.

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef SIM_MAIN_H
#define SIM_MAIN_H

#include "sim-basics.h"

typedef address_word sim_cia;

typedef struct _sim_cpu SIM_CPU;

#include "sim-base.h"

typedef struct
{
  int regs[20];
} regstacktype;

typedef union
{

  struct
  {
    int regs[16];
    int pc;

    /* System registers.  For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
       which are located in fregs, i.e. strictly speaking, these are
       out-of-bounds accesses of sregs.i .  This wart of the code could be
       fixed by making fregs part of sregs, and including pc too - to avoid
       alignment repercussions - but this would cause very onerous union /
       structure nesting, which would only be managable with anonymous
       unions and structs.  */
    union
      {
	struct
	  {
	    int mach;
	    int macl;
	    int pr;
	    int dummy3, dummy4;
	    int fpul; /* A1 for sh-dsp -  but only for movs etc.  */
	    int fpscr; /* dsr for sh-dsp */
	  } named;
	int i[7];
      } sregs;

    /* sh3e / sh-dsp */
    union fregs_u
      {
	float f[16];
	double d[8];
	int i[16];
      }
    fregs[2];

    /* Control registers; on the SH4, ldc / stc is privileged, except when
       accessing gbr.  */
    union
      {
	struct
	  {
	    int sr;
	    int gbr;
	    int vbr;
	    int ssr;
	    int spc;
	    int mod;
	    /* sh-dsp */
	    int rs;
	    int re;
	    /* sh3 */
	    int bank[8];
	    int dbr;		/* debug base register */
	    int sgr;		/* saved gr15 */
	    int ldst;		/* load/store flag (boolean) */
	    int tbr;
	    int ibcr;		/* sh2a bank control register */
	    int ibnr;		/* sh2a bank number register */
	  } named;
	int i[16];
      } cregs;

    unsigned char *insn_end;

    int ticks;
    int stalls;
    int memstalls;
    int cycles;
    int insts;

    int prevlock;
    int thislock;
    int exception;

    int end_of_registers;

    int msize;
#define PROFILE_FREQ 1
#define PROFILE_SHIFT 2
    int profile;
    unsigned short *profile_hist;
    unsigned char *memory;
    int xyram_select, xram_start, yram_start;
    unsigned char *xmem;
    unsigned char *ymem;
    unsigned char *xmem_offset;
    unsigned char *ymem_offset;
    unsigned long bfd_mach;
    regstacktype *regstack;
  } asregs;
  int asints[40];
} saved_state_type;

/* TODO: Move into sim_cpu.  */
extern saved_state_type saved_state;

struct _sim_cpu {

  sim_cpu_base base;
};

struct sim_state {

  sim_cpu *cpu[MAX_NR_PROCESSORS];

  sim_state_base base;
};

#endif
Commit	Line	Data
62454d3d MF	1	/* Moxie Simulator definition.
	2	Copyright (C) 2009-2015 Free Software Foundation, Inc.
	3
	4	This file is part of GDB, the GNU debugger.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 3 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	18
	19	#ifndef SIM_MAIN_H
	20	#define SIM_MAIN_H
	21
	22	#include "sim-basics.h"
	23
	24	typedef address_word sim_cia;
	25
62454d3d MF	26	typedef struct _sim_cpu SIM_CPU;
	27
	28	#include "sim-base.h"
	29
	30	typedef struct
	31	{
	32	int regs[20];
	33	} regstacktype;
	34
	35	typedef union
	36	{
	37
	38	struct
	39	{
	40	int regs[16];
	41	int pc;
	42
	43	/* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
	44	which are located in fregs, i.e. strictly speaking, these are
	45	out-of-bounds accesses of sregs.i . This wart of the code could be
	46	fixed by making fregs part of sregs, and including pc too - to avoid
	47	alignment repercussions - but this would cause very onerous union /
	48	structure nesting, which would only be managable with anonymous
	49	unions and structs. */
	50	union
	51	{
	52	struct
	53	{
	54	int mach;
	55	int macl;
	56	int pr;
	57	int dummy3, dummy4;
	58	int fpul; /* A1 for sh-dsp - but only for movs etc. */
	59	int fpscr; /* dsr for sh-dsp */
	60	} named;
	61	int i[7];
	62	} sregs;
	63
	64	/* sh3e / sh-dsp */
	65	union fregs_u
	66	{
	67	float f[16];
	68	double d[8];
	69	int i[16];
	70	}
	71	fregs[2];
	72
	73	/* Control registers; on the SH4, ldc / stc is privileged, except when
	74	accessing gbr. */
	75	union
	76	{
	77	struct
	78	{
	79	int sr;
	80	int gbr;
	81	int vbr;
	82	int ssr;
	83	int spc;
	84	int mod;
	85	/* sh-dsp */
	86	int rs;
	87	int re;
	88	/* sh3 */
	89	int bank[8];
90	int dbr; /* debug base register */
91	int sgr; /* saved gr15 */
92	int ldst; /* load/store flag (boolean) */
93	int tbr;
94	int ibcr; /* sh2a bank control register */
95	int ibnr; /* sh2a bank number register */
96	} named;
97	int i[16];
98	} cregs;
99
100	unsigned char *insn_end;
101
102	int ticks;
103	int stalls;
104	int memstalls;
105	int cycles;
106	int insts;
107
108	int prevlock;
109	int thislock;
110	int exception;
111
112	int end_of_registers;
113
114	int msize;
115	#define PROFILE_FREQ 1
116	#define PROFILE_SHIFT 2
117	int profile;
118	unsigned short *profile_hist;
119	unsigned char *memory;
120	int xyram_select, xram_start, yram_start;
121	unsigned char *xmem;
122	unsigned char *ymem;
123	unsigned char *xmem_offset;
124	unsigned char *ymem_offset;
125	unsigned long bfd_mach;
126	regstacktype *regstack;
127	} asregs;
128	int asints[40];
129	} saved_state_type;
130
131	/* TODO: Move into sim_cpu. */
132	extern saved_state_type saved_state;
133
134	struct _sim_cpu {
135
136	sim_cpu_base base;
137	};
138
139	struct sim_state {
140
141	sim_cpu *cpu[MAX_NR_PROCESSORS];
62454d3d MF	142
	143	sim_state_base base;
	144	};
	145
	146	#endif