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Commit | Line | Data |
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e8f42b5e JW |
1 | # mach: aarch64 |
2 | ||
3 | # Check the load single 1-element structure to one lane instructions: | |
4 | # ld1, ld2, ld3, ld4. | |
5 | # Check the addressing modes: no offset, post-index immediate offset, | |
6 | # post-index register offset. | |
7 | ||
8 | .include "testutils.inc" | |
9 | ||
10 | input: | |
11 | .word 0x04030201 | |
12 | .word 0x08070605 | |
13 | .word 0x0c0b0a09 | |
14 | .word 0x100f0e0d | |
15 | .word 0x14131211 | |
16 | .word 0x18171615 | |
17 | .word 0x1c1b1a19 | |
18 | .word 0x201f1e1d | |
19 | ||
20 | start | |
21 | adrp x0, input | |
22 | add x0, x0, :lo12:input | |
23 | ||
24 | mov x2, x0 | |
25 | mov x3, #1 | |
26 | mov x4, #4 | |
27 | ld1 {v0.b}[0], [x2], 1 | |
28 | ld1 {v0.b}[1], [x2], x3 | |
29 | ld1 {v0.h}[1], [x2], 2 | |
30 | ld1 {v0.s}[1], [x2], x4 | |
31 | ld1 {v0.d}[1], [x2] | |
32 | addv b1, v0.16b | |
33 | mov x5, v1.d[0] | |
34 | cmp x5, #136 | |
35 | bne .Lfailure | |
36 | ||
37 | mov x2, x0 | |
38 | mov x3, #16 | |
39 | mov x4, #4 | |
40 | ld2 {v0.d, v1.d}[0], [x2], x3 | |
41 | ld2 {v0.s, v1.s}[2], [x2], 8 | |
42 | ld2 {v0.h, v1.h}[6], [x2], x4 | |
43 | ld2 {v0.b, v1.b}[14], [x2], 2 | |
44 | ld2 {v0.b, v1.b}[15], [x2] | |
45 | addv b2, v0.16b | |
46 | addv b3, v1.16b | |
47 | mov x5, v2.d[0] | |
48 | mov x6, v3.d[0] | |
49 | cmp x5, #221 | |
50 | bne .Lfailure | |
2e7e5e28 | 51 | cmp x6, #51 |
e8f42b5e JW |
52 | bne .Lfailure |
53 | ||
54 | mov x2, x0 | |
55 | ld3 {v0.s, v1.s, v2.s}[0], [x2], 12 | |
56 | ld3 {v0.s, v1.s, v2.s}[1], [x2] | |
57 | mov x2, x0 | |
58 | mov x3, #12 | |
59 | ld3 {v0.s, v1.s, v2.s}[2], [x2], x3 | |
60 | ld3 {v0.s, v1.s, v2.s}[3], [x2] | |
61 | addv b3, v0.16b | |
62 | addv b4, v1.16b | |
63 | addv b5, v2.16b | |
64 | mov x4, v3.d[0] | |
65 | mov x5, v4.d[0] | |
66 | mov x6, v5.d[0] | |
67 | cmp x4, #136 | |
68 | bne .Lfailure | |
69 | cmp x5, #200 | |
70 | bne .Lfailure | |
2e7e5e28 | 71 | cmp x6, #8 |
e8f42b5e JW |
72 | bne .Lfailure |
73 | ||
74 | mov x2, x0 | |
75 | ld4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16 | |
76 | ld4 {v0.s, v1.s, v2.s, v3.s}[1], [x2] | |
77 | mov x2, x0 | |
78 | mov x3, #16 | |
79 | ld4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], x3 | |
80 | ld4 {v0.s, v1.s, v2.s, v3.s}[3], [x2] | |
81 | addv b4, v0.16b | |
82 | addv b5, v1.16b | |
83 | addv b6, v2.16b | |
84 | addv b7, v3.16b | |
85 | mov x4, v4.d[0] | |
86 | mov x5, v5.d[0] | |
87 | mov x6, v6.d[0] | |
88 | mov x7, v7.d[0] | |
89 | cmp x4, #168 | |
90 | bne .Lfailure | |
91 | cmp x5, #232 | |
92 | bne .Lfailure | |
2e7e5e28 | 93 | cmp x6, #40 |
e8f42b5e | 94 | bne .Lfailure |
2e7e5e28 | 95 | cmp x7, #104 |
e8f42b5e JW |
96 | bne .Lfailure |
97 | ||
98 | pass | |
99 | .Lfailure: | |
100 | fail |