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1d7b4a70 MF |
1 | //Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp |
2 | # mach: bfin | |
3 | ||
4 | .include "testutils.inc" | |
5 | start | |
6 | ||
7 | ||
8 | // Spec Reference: dsp32shiftimm ashift: mix | |
9 | ||
10 | ||
11 | ||
12 | imm32 r4, 0x00000000; | |
13 | imm32 r5, 0x00000000; | |
14 | imm32 r6, 0x00000000; | |
15 | imm32 r7, 0x00000000; | |
16 | ||
17 | // Ashift : positive data, count (+)=left (half reg) | |
18 | imm32 r0, 0x00010001; | |
19 | imm32 r1, 1; | |
20 | imm32 r2, 0x00020002; | |
21 | imm32 r3, 2; | |
22 | R4.H = R0.H << 1; | |
23 | R4.L = R0.L << 1; /* r4 = 0x00020002 */ | |
24 | R5.H = R2.H << 2; | |
25 | R5.L = R2.L << 2; /* r5 = 0x00080008 */ | |
26 | R6 = R0 << 1 (V); /* r6 = 0x00020002 */ | |
27 | R7 = R2 << 2 (V); /* r7 = 0x00080008 */ | |
28 | CHECKREG r4, 0x00020002; | |
29 | CHECKREG r5, 0x00080008; | |
30 | CHECKREG r6, 0x00020002; | |
31 | CHECKREG r7, 0x00080008; | |
32 | ||
33 | imm32 r1, 3; | |
34 | imm32 r3, 4; | |
35 | R6 = R0 << 3; /* r6 = 0x00080010 */ | |
36 | R7 = R2 << 4; | |
37 | CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ | |
38 | CHECKREG r7, 0x00200020; | |
39 | ||
40 | A0 = 0; | |
41 | A0.L = R0.L; | |
42 | A0.H = R0.H; | |
43 | A0 = A0 << 3; /* a0 = 0x00080008 */ | |
44 | R5 = A0.w; /* r5 = 0x00080008 */ | |
45 | CHECKREG r5, 0x00080008; | |
46 | ||
47 | imm32 r4, 0x30000003; | |
48 | imm32 r1, 1; | |
49 | R5 = R4 << 1; /* r5 = 0x60000006 */ | |
50 | ||
51 | imm32 r1, 2; | |
52 | R6 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */ | |
53 | CHECKREG r5, 0x60000006; | |
54 | CHECKREG r6, 0xc000000c; | |
55 | ||
56 | ||
57 | // Ashift : count (-)=right (half reg) | |
58 | imm32 r0, 0x10001000; | |
59 | imm32 r1, -1; | |
60 | imm32 r2, 0x10001000; | |
61 | imm32 r3, -2; | |
62 | R4.H = R0.H >>> 1; | |
63 | R4.L = R0.L >>> 1; /* r4 = 0x08000800 */ | |
64 | R5.H = R2.H >>> 2; | |
65 | R5.L = R2.L >>> 2; /* r4 = 0x04000400 */ | |
66 | R6 = R0 >>> 1 (V); /* r4 = 0x08000800 */ | |
67 | R7 = R2 >>> 2 (V); /* r4 = 0x04000400 */ | |
68 | CHECKREG r4, 0x08000800; | |
69 | CHECKREG r5, 0x04000400; | |
70 | CHECKREG r6, 0x08000800; | |
71 | CHECKREG r7, 0x04000400; | |
72 | ||
73 | // Ashift : (full reg) | |
74 | imm32 r1, -3; | |
75 | imm32 r3, -4; | |
76 | R6 = R0 >>> 3; /* r6 = 0x02000200 */ | |
77 | R7 = R2 >>> 4; /* r7 = 0x01000100 */ | |
78 | CHECKREG r6, 0x02000200; | |
79 | CHECKREG r7, 0x01000100; | |
80 | ||
81 | // NEGATIVE | |
82 | // Ashift : NEGATIVE data, count (+)=left (half reg) | |
83 | imm32 r0, 0xc00f800f; | |
84 | imm32 r1, 1; | |
85 | imm32 r2, 0xe00fe00f; | |
86 | imm32 r3, 2; | |
87 | R4.H = R0.H << 1; | |
88 | R4.L = R0.L << 1 (S); /* r4 = 0x801e801e */ | |
89 | R5.H = R2.H << 2; | |
90 | R5.L = R2.L << 2; /* r4 = 0x803c803c */ | |
91 | CHECKREG r4, 0x801e8000; | |
92 | CHECKREG r5, 0x803c803c; | |
93 | ||
94 | imm32 r0, 0xc80fe00f; | |
95 | imm32 r2, 0xe40fe00f; | |
96 | imm32 r1, 4; | |
97 | imm32 r3, 5; | |
98 | R6 = R0 << 4; /* r6 = 0x80fe00f0 */ | |
99 | R7 = R2 << 5; /* r7 = 0x81fc01e0 */ | |
100 | CHECKREG r6, 0x80fe00f0; | |
101 | CHECKREG r7, 0x81fc01e0; | |
102 | ||
103 | imm32 r0, 0xf80fe00f; | |
104 | imm32 r2, 0xfc0fe00f; | |
105 | R6 = R0 << 4 (S); /* r6 = 0x80fe00f0 */ | |
106 | R7 = R2 << 5 (S); /* r7 = 0x81fc01e0 */ | |
107 | CHECKREG r6, 0x80fe00f0; | |
108 | CHECKREG r7, 0x81fc01e0; | |
109 | ||
110 | imm32 r0, 0xc80fe00f; | |
111 | imm32 r2, 0xe40fe00f; | |
112 | R6 = R0 << 4 (S); /* r6 = 0x80000000 zero bubble tru MSB */ | |
113 | R7 = R2 << 5 (S); /* r7 = 0x80000000 */ | |
114 | CHECKREG r6, 0x80000000; | |
115 | CHECKREG r7, 0x80000000; | |
116 | ||
6aafca16 MF |
117 | imm32 r0, 0xFFFFFFF4; |
118 | imm32 r2, 0xFFF00001; | |
119 | R6 = R0 << 31 (S); /* r6 = 0x80000000 */ | |
120 | R7 = R2 << 31 (S); /* r7 = 0x80000000 */ | |
121 | CHECKREG r6, 0x80000000; | |
122 | CHECKREG r7, 0x80000000; | |
123 | ||
1d7b4a70 MF |
124 | |
125 | // Ashift : NEGATIVE data, count (-)=right (half reg) Working ok | |
126 | imm32 r0, 0x80f080f0; | |
127 | imm32 r1, -1; | |
128 | imm32 r2, 0x80f080f0; | |
129 | imm32 r3, -2; | |
130 | R4.H = R0.H >>> 1; | |
131 | R4.L = R0.L >>> 1; /* r4 = 0xc078c078 */ | |
132 | R5.H = R2.H >>> 2; | |
133 | R5.L = R2.L >>> 2; /* r4 = 0xe03ce03c */ | |
134 | CHECKREG r4, 0xc078c078; | |
135 | CHECKREG r5, 0xe03ce03c; | |
136 | R6 = R0 >>> 1 (V); /* r6 = 0xc078c078 */ | |
137 | R7 = R2 >>> 2 (V); /* r7 = 0xe03ce03c */ | |
138 | CHECKREG r6, 0xc078c078; | |
139 | CHECKREG r7, 0xe03ce03c; | |
140 | ||
141 | imm32 r1, -3; | |
142 | imm32 r3, -4; | |
143 | R6 = R0 >>> 3; /* r6 = 0xf01e101e */ | |
144 | R7 = R2 >>> 4; /* r7 = 0xf80f080f */ | |
145 | CHECKREG r6, 0xf01e101e; | |
146 | CHECKREG r7, 0xf80f080f; | |
147 | ||
148 | ||
149 | pass |