projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 4a306116 DB |
1 | # frv testcase for caddcc $GRi,$GRj,$GRk,$CCi,$cond |
| 2 | # mach: all | |
| 3 | ||
| 4 | .include "testutils.inc" | |
| 5 | ||
| 6 | start | |
| 7 | ||
| 8 | .global caddcc | |
| 9 | caddcc: | |
| 10 | set_spr_immed 0x1b1b,cccr | |
| 11 | ||
| 12 | set_gr_immed 1,gr7 | |
| 13 | set_gr_immed 2,gr8 | |
| 14 | set_icc 0x0f,0 ; Set mask opposite of expected | |
| 15 | caddcc gr7,gr8,gr8,cc0,1 | |
| 16 | test_icc 0 0 0 0 icc0 | |
| 17 | test_gr_immed 3,gr8 | |
| 18 | ||
| 19 | set_gr_limmed 0x7fff,0xffff,gr7 | |
| 20 | set_gr_immed 1,gr8 | |
| 21 | set_icc 0x05,0 ; Set mask opposite of expected | |
| 22 | caddcc gr7,gr8,gr8,cc0,1 | |
| 23 | test_icc 1 0 1 0 icc0 | |
| 24 | test_gr_limmed 0x8000,0x0000,gr8 | |
| 25 | ||
| 26 | set_icc 0x08,0 ; Set mask opposite of expected | |
| 27 | caddcc gr8,gr8,gr8,cc4,1 | |
| 28 | test_icc 0 1 1 1 icc0 | |
| 29 | test_gr_immed 0,gr8 | |
| 30 | ||
| 31 | set_gr_limmed 0x8000,0x0000,gr8 | |
| 32 | set_icc 0x08,0 ; Set mask opposite of expected | |
| 33 | caddcc gr8,gr8,gr8,cc4,1; test zero, carry and overflow bits | |
| 34 | test_icc 0 1 1 1 icc0 | |
| 35 | test_gr_immed 0,gr8 | |
| 36 | ||
| 37 | set_gr_immed 1,gr7 | |
| 38 | set_gr_immed 2,gr8 | |
| 39 | set_icc 0x0f,0 ; Set mask opposite of expected | |
| 40 | caddcc gr7,gr8,gr8,cc0,0 | |
| 41 | test_icc 1 1 1 1 icc0 | |
| 42 | test_gr_immed 2,gr8 | |
| 43 | ||
| 44 | set_gr_limmed 0x7fff,0xffff,gr7 | |
| 45 | set_gr_immed 1,gr8 | |
| 46 | set_icc 0x05,0 ; Set mask opposite of expected | |
| 47 | caddcc gr7,gr8,gr8,cc0,0 | |
| 48 | test_icc 0 1 0 1 icc0 | |
| 49 | test_gr_immed 1,gr8 | |
| 50 | ||
| 51 | set_icc 0x08,0 ; Set mask opposite of expected | |
| 52 | caddcc gr8,gr8,gr8,cc4,0 | |
| 53 | test_icc 1 0 0 0 icc0 | |
| 54 | test_gr_immed 1,gr8 | |
| 55 | ||
| 56 | set_gr_limmed 0x8000,0x0000,gr8 | |
| 57 | set_icc 0x08,0 ; Set mask opposite of expected | |
| 58 | caddcc gr8,gr8,gr8,cc4,0; test zero, carry and overflow bits | |
| 59 | test_icc 1 0 0 0 icc0 | |
| 60 | test_gr_limmed 0x8000,0x0000,gr8 | |
| 61 | ||
| 62 | set_gr_immed 1,gr7 | |
| 63 | set_gr_immed 2,gr8 | |
| 64 | set_icc 0x0f,1 ; Set mask opposite of expected | |
| 65 | caddcc gr7,gr8,gr8,cc1,0 | |
| 66 | test_icc 0 0 0 0 icc1 | |
| 67 | test_gr_immed 3,gr8 | |
| 68 | ||
| 69 | set_gr_limmed 0x7fff,0xffff,gr7 | |
| 70 | set_gr_immed 1,gr8 | |
| 71 | set_icc 0x05,1 ; Set mask opposite of expected | |
| 72 | caddcc gr7,gr8,gr8,cc1,0 | |
| 73 | test_icc 1 0 1 0 icc1 | |
| 74 | test_gr_limmed 0x8000,0x0000,gr8 | |
| 75 | ||
| 76 | set_icc 0x08,1 ; Set mask opposite of expected | |
| 77 | caddcc gr8,gr8,gr8,cc5,0 | |
| 78 | test_icc 0 1 1 1 icc1 | |
| 79 | test_gr_immed 0,gr8 | |
| 80 | ||
| 81 | set_gr_limmed 0x8000,0x0000,gr8 | |
| 82 | set_icc 0x08,1 ; Set mask opposite of expected | |
| 83 | caddcc gr8,gr8,gr8,cc5,0; test zero, carry and overflow bits | |
| 84 | test_icc 0 1 1 1 icc1 | |
| 85 | test_gr_immed 0,gr8 | |
| 86 | ||
| 87 | set_gr_immed 1,gr7 | |
| 88 | set_gr_immed 2,gr8 | |
| 89 | set_icc 0x0f,1 ; Set mask opposite of expected | |
| 90 | caddcc gr7,gr8,gr8,cc1,1 | |
| 91 | test_icc 1 1 1 1 icc1 | |
| 92 | test_gr_immed 2,gr8 | |
| 93 | ||
| 94 | set_gr_limmed 0x7fff,0xffff,gr7 | |
| 95 | set_gr_immed 1,gr8 | |
| 96 | set_icc 0x05,1 ; Set mask opposite of expected | |
| 97 | caddcc gr7,gr8,gr8,cc1,1 | |
| 98 | test_icc 0 1 0 1 icc1 | |
| 99 | test_gr_immed 1,gr8 | |
| 100 | ||
| 101 | set_icc 0x08,1 ; Set mask opposite of expected | |
| 102 | caddcc gr8,gr8,gr8,cc5,1 | |
| 103 | test_icc 1 0 0 0 icc1 | |
| 104 | test_gr_immed 1,gr8 | |
| 105 | ||
| 106 | set_gr_limmed 0x8000,0x0000,gr8 | |
| 107 | set_icc 0x08,1 ; Set mask opposite of expected | |
| 108 | caddcc gr8,gr8,gr8,cc5,1; test zero, carry and overflow bits | |
| 109 | test_icc 1 0 0 0 icc1 | |
| 110 | test_gr_limmed 0x8000,0x0000,gr8 | |
| 111 | ||
| 112 | set_gr_immed 1,gr7 | |
| 113 | set_gr_immed 2,gr8 | |
| 114 | set_icc 0x0f,2 ; Set mask opposite of expected | |
| 115 | caddcc gr7,gr8,gr8,cc2,0 | |
| 116 | test_icc 1 1 1 1 icc2 | |
| 117 | test_gr_immed 2,gr8 | |
| 118 | ||
| 119 | set_gr_limmed 0x7fff,0xffff,gr7 | |
| 120 | set_gr_immed 1,gr8 | |
| 121 | set_icc 0x05,2 ; Set mask opposite of expected | |
| 122 | caddcc gr7,gr8,gr8,cc2,0 | |
| 123 | test_icc 0 1 0 1 icc2 | |
| 124 | test_gr_immed 1,gr8 | |
| 125 | ||
| 126 | set_icc 0x08,2 ; Set mask opposite of expected | |
| 127 | caddcc gr8,gr8,gr8,cc6,1 | |
| 128 | test_icc 1 0 0 0 icc2 | |
| 129 | test_gr_immed 1,gr8 | |
| 130 | ||
| 131 | set_gr_limmed 0x8000,0x0000,gr8 | |
| 132 | set_icc 0x08,2 ; Set mask opposite of expected | |
| 133 | caddcc gr8,gr8,gr8,cc6,1; test zero, carry and overflow bits | |
| 134 | test_icc 1 0 0 0 icc2 | |
| 135 | test_gr_limmed 0x8000,0x0000,gr8 | |
| 136 | ||
| 137 | set_gr_immed 1,gr7 | |
| 138 | set_gr_immed 2,gr8 | |
| 139 | set_icc 0x0f,3 ; Set mask opposite of expected | |
| 140 | caddcc gr7,gr8,gr8,cc3,0 | |
| 141 | test_icc 1 1 1 1 icc3 | |
| 142 | test_gr_immed 2,gr8 | |
| 143 | ||
| 144 | set_gr_limmed 0x7fff,0xffff,gr7 | |
| 145 | set_gr_immed 1,gr8 | |
| 146 | set_icc 0x05,3 ; Set mask opposite of expected | |
| 147 | caddcc gr7,gr8,gr8,cc3,0 | |
| 148 | test_icc 0 1 0 1 icc3 | |
| 149 | test_gr_immed 1,gr8 | |
| 150 | ||
| 151 | set_icc 0x08,3 ; Set mask opposite of expected | |
| 152 | caddcc gr8,gr8,gr8,cc7,1 | |
| 153 | test_icc 1 0 0 0 icc3 | |
| 154 | test_gr_immed 1,gr8 | |
| 155 | ||
| 156 | set_gr_limmed 0x8000,0x0000,gr8 | |
| 157 | set_icc 0x08,3 ; Set mask opposite of expected | |
| 158 | caddcc gr8,gr8,gr8,cc7,1; test zero, carry and overflow bits | |
| 159 | test_icc 1 0 0 0 icc3 | |
| 160 | test_gr_limmed 0x8000,0x0000,gr8 | |
| 161 | ||
| 162 | ||
| 163 | pass |