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Commit | Line | Data |
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4a306116 DB |
1 | # frv testcase for umulicc $GRi,$GRj,$GRk |
2 | # mach: all | |
3 | ||
4 | .include "testutils.inc" | |
5 | ||
6 | start | |
7 | ||
8 | .global umulicc | |
9 | umulicc: | |
10 | set_gr_immed 3,gr7 ; multiply small numbers | |
11 | set_icc 0x0f,0 ; Set mask opposite of expected | |
12 | umulicc gr7,2,gr8,icc0 | |
13 | test_icc 0 0 1 1 icc0 | |
14 | test_gr_immed 0,gr8 | |
15 | test_gr_immed 6,gr9 | |
16 | ||
17 | set_gr_immed 1,gr7 ; multiply by 1 | |
18 | set_icc 0x0e,0 ; Set mask opposite of expected | |
19 | umulicc gr7,2,gr8,icc0 | |
20 | test_icc 0 0 1 0 icc0 | |
21 | test_gr_immed 0,gr8 | |
22 | test_gr_immed 2,gr9 | |
23 | ||
24 | set_gr_immed 2,gr7 ; multiply by 1 | |
25 | set_icc 0x0f,0 ; Set mask opposite of expected | |
26 | umulicc gr7,1,gr8,icc0 | |
27 | test_icc 0 0 1 1 icc0 | |
28 | test_gr_immed 0,gr8 | |
29 | test_gr_immed 2,gr9 | |
30 | ||
31 | set_gr_immed 0,gr7 ; multiply by 0 | |
32 | set_icc 0x0b,0 ; Set mask opposite of expected | |
33 | umulicc gr7,2,gr8,icc0 | |
34 | test_icc 0 1 1 1 icc0 | |
35 | test_gr_immed 0,gr8 | |
36 | test_gr_immed 0,gr9 | |
37 | ||
38 | set_gr_immed 2,gr7 ; multiply by 0 | |
39 | set_icc 0x0a,0 ; Set mask opposite of expected | |
40 | umulicc gr7,0,gr8,icc0 | |
41 | test_icc 0 1 1 0 icc0 | |
42 | test_gr_immed 0,gr8 | |
43 | test_gr_immed 0,gr9 | |
44 | ||
45 | set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result | |
46 | set_icc 0x0f,0 ; Set mask opposite of expected | |
47 | umulicc gr7,2,gr8,icc0 | |
48 | test_icc 0 0 1 1 icc0 | |
49 | test_gr_immed 0,gr8 | |
50 | test_gr_limmed 0x7fff,0xfffe,gr9 | |
51 | ||
52 | set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result | |
53 | set_icc 0x0e,0 ; Set mask opposite of expected | |
54 | umulicc gr7,2,gr8,icc0 | |
55 | test_icc 0 0 1 0 icc0 | |
56 | test_gr_immed 0,gr8 | |
57 | test_gr_limmed 0x8000,0x0000,gr9 | |
58 | ||
59 | set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result | |
60 | set_icc 0x09,0 ; Set mask opposite of expected | |
61 | umulicc gr7,2,gr8,icc0 | |
62 | test_icc 0 0 0 1 icc0 | |
63 | test_gr_immed 1,gr8 | |
64 | test_gr_immed 0x00000000,gr9 | |
65 | ||
66 | set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result | |
67 | set_icc 0x0d,0 ; Set mask opposite of expected | |
68 | umulicc gr7,0x1ff,gr8,icc0 | |
69 | test_icc 0 0 0 1 icc0 | |
70 | test_gr_immed 0xff,gr8 | |
71 | test_gr_limmed 0x7fff,0xfe01,gr9 | |
72 | ||
73 | set_gr_limmed 0x8000,0x0000,gr7 ; max positive result | |
74 | set_icc 0x09,0 ; Set mask opposite of expected | |
75 | umulicc gr7,-512,gr8,icc0 | |
76 | test_icc 0 0 0 1 icc0 | |
77 | test_gr_limmed 0x7fff,0xff00,gr8 | |
78 | test_gr_limmed 0x0000,0x0000,gr9 | |
79 | ||
80 | set_gr_limmed 0xffff,0xffff,gr7 ; max positive result | |
81 | set_icc 0x05,0 ; Set mask opposite of expected | |
82 | umulicc gr7,-1,gr8,icc0 | |
83 | test_icc 1 0 0 1 icc0 | |
84 | test_gr_limmed 0xffff,0xfffe,gr8 | |
85 | test_gr_immed 1,gr9 | |
86 | ||
87 | pass |