projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 32ebdc4c MS |
1 | # Hitachi H8 testcase 'exts.l, extu.l' |
| 2 | # mach(): h8300h h8300s h8sx | |
| 3 | # as(h8300): --defsym sim_cpu=0 | |
| 4 | # as(h8300h): --defsym sim_cpu=1 | |
| 5 | # as(h8300s): --defsym sim_cpu=2 | |
| 6 | # as(h8sx): --defsym sim_cpu=3 | |
| 7 | # ld(h8300h): -m h8300helf | |
| 8 | # ld(h8300s): -m h8300self | |
| 9 | # ld(h8sx): -m h8300sxelf | |
| 10 | ||
| 11 | .include "testutils.inc" | |
| 12 | ||
| 13 | start | |
| 14 | ||
| 15 | .data | |
| 16 | .align 4 | |
| 17 | pos: .long 0xffff0001 | |
| 18 | neg: .long 0x00008000 | |
| 19 | ||
| 20 | pos2: .long 0xffffff01 | |
| 21 | neg2: .long 0x00000080 | |
| 22 | ||
| 23 | .text | |
| 24 | ||
| 25 | exts_l_reg32_p: | |
| 26 | set_grs_a5a5 | |
| 27 | set_ccr_zero | |
| 28 | ;; exts.l ern32 | |
| 29 | mov.w #1, r0 | |
| 30 | exts.l er0 | |
| 31 | ||
| 32 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 33 | test_cc_clear | |
| 34 | ||
| 35 | test_h_gr32 0x00000001 er0 ; result of sign extend | |
| 36 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 37 | test_gr_a5a5 2 | |
| 38 | test_gr_a5a5 3 | |
| 39 | test_gr_a5a5 4 | |
| 40 | test_gr_a5a5 5 | |
| 41 | test_gr_a5a5 6 | |
| 42 | test_gr_a5a5 7 | |
| 43 | ||
| 44 | exts_l_reg32_n: | |
| 45 | set_grs_a5a5 | |
| 46 | set_ccr_zero | |
| 47 | ;; exts.l ern32 | |
| 48 | mov.w #0xffff, r0 | |
| 49 | exts.l er0 | |
| 50 | ||
| 51 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 52 | test_neg_set | |
| 53 | test_zero_clear | |
| 54 | test_ovf_clear | |
| 55 | test_carry_clear | |
| 56 | ||
| 57 | test_h_gr32 0xffffffff er0 ; result of sign extend | |
| 58 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 59 | test_gr_a5a5 2 | |
| 60 | test_gr_a5a5 3 | |
| 61 | test_gr_a5a5 4 | |
| 62 | test_gr_a5a5 5 | |
| 63 | test_gr_a5a5 6 | |
| 64 | test_gr_a5a5 7 | |
| 65 | ||
| 66 | extu_l_reg32_n: | |
| 67 | set_grs_a5a5 | |
| 68 | set_ccr_zero | |
| 69 | ;; extu.l ern32 | |
| 70 | mov.w #0xffff, r0 | |
| 71 | extu.l er0 | |
| 72 | ||
| 73 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 74 | test_cc_clear | |
| 75 | ||
| 76 | test_h_gr32 0x0000ffff er0 ; result of zero extend | |
| 77 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 78 | test_gr_a5a5 2 | |
| 79 | test_gr_a5a5 3 | |
| 80 | test_gr_a5a5 4 | |
| 81 | test_gr_a5a5 5 | |
| 82 | test_gr_a5a5 6 | |
| 83 | test_gr_a5a5 7 | |
| 84 | ||
| 85 | .if (sim_cpu == h8sx) | |
| 86 | exts_l_ind_p: | |
| 87 | set_grs_a5a5 | |
| 88 | set_ccr_zero | |
| 89 | ;; exts.l @ern32 | |
| 90 | mov.l #pos, er1 | |
| 91 | exts.l @er1 | |
| 92 | ||
| 93 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 94 | test_cc_clear | |
| 95 | ||
| 96 | test_h_gr32 pos er1 ; er1 still contains target address | |
| 97 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 98 | test_gr_a5a5 2 | |
| 99 | test_gr_a5a5 3 | |
| 100 | test_gr_a5a5 4 | |
| 101 | test_gr_a5a5 5 | |
| 102 | test_gr_a5a5 6 | |
| 103 | test_gr_a5a5 7 | |
| 104 | cmp.l #0x00000001, @pos | |
| 105 | beq .Lslindp | |
| 106 | fail | |
| 107 | .Lslindp: | |
| 108 | mov.l #0xffff0001, @pos ; Restore initial value | |
| 109 | ||
| 110 | exts_l_ind_n: | |
| 111 | set_grs_a5a5 | |
| 112 | set_ccr_zero | |
| 113 | ;; exts.l @ern32 | |
| 114 | mov.l #neg, er1 | |
| 115 | exts.l @er1 | |
| 116 | ||
| 117 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 118 | test_neg_set | |
| 119 | test_zero_clear | |
| 120 | test_ovf_clear | |
| 121 | test_carry_clear | |
| 122 | ||
| 123 | test_h_gr32 neg er1 ; er1 still contains target address | |
| 124 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 125 | test_gr_a5a5 2 | |
| 126 | test_gr_a5a5 3 | |
| 127 | test_gr_a5a5 4 | |
| 128 | test_gr_a5a5 5 | |
| 129 | test_gr_a5a5 6 | |
| 130 | test_gr_a5a5 7 | |
| 131 | cmp.l #0xffff8000, @neg | |
| 132 | beq .Lslindn | |
| 133 | fail | |
| 134 | .Lslindn: | |
| 135 | ;;; Note: leave the value as 0xffff8000, so that extu has work to do. | |
| 136 | ||
| 137 | extu_l_ind_n: | |
| 138 | set_grs_a5a5 | |
| 139 | set_ccr_zero | |
| 140 | ;; extu.l @ern32 | |
| 141 | mov.l #neg, er1 | |
| 142 | extu.l @er1 | |
| 143 | ||
| 144 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 145 | test_cc_clear | |
| 146 | ||
| 147 | test_h_gr32 neg er1 ; er1 still contains target address | |
| 148 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 149 | test_gr_a5a5 2 | |
| 150 | test_gr_a5a5 3 | |
| 151 | test_gr_a5a5 4 | |
| 152 | test_gr_a5a5 5 | |
| 153 | test_gr_a5a5 6 | |
| 154 | test_gr_a5a5 7 | |
| 155 | cmp.l #0x00008000, @neg | |
| 156 | beq .Lulindn | |
| 157 | fail | |
| 158 | .Lulindn: | |
| 159 | ;;; Note: leave the value as 0x00008000, so that extu has work to do. | |
| 160 | ||
| 161 | exts_l_postinc_p: | |
| 162 | set_grs_a5a5 | |
| 163 | set_ccr_zero | |
| 164 | ;; exts.l @ern32+ | |
| 165 | mov.l #pos, er1 | |
| 166 | exts.l @er1+ | |
| 167 | ||
| 168 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 169 | test_cc_clear | |
| 170 | ||
| 171 | test_h_gr32 pos+4 er1 ; er1 still contains target address | |
| 172 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 173 | test_gr_a5a5 2 | |
| 174 | test_gr_a5a5 3 | |
| 175 | test_gr_a5a5 4 | |
| 176 | test_gr_a5a5 5 | |
| 177 | test_gr_a5a5 6 | |
| 178 | test_gr_a5a5 7 | |
| 179 | cmp.l #0x00000001, @pos | |
| 180 | beq .Lslpostincp | |
| 181 | fail | |
| 182 | .Lslpostincp: | |
| 183 | mov.l #0xffff0001, @pos ; Restore initial value | |
| 184 | ||
| 185 | exts_l_postinc_n: | |
| 186 | set_grs_a5a5 | |
| 187 | set_ccr_zero | |
| 188 | ;; exts.l @ern32+ | |
| 189 | mov.l #neg, er1 | |
| 190 | exts.l @er1+ | |
| 191 | ||
| 192 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 193 | test_neg_set | |
| 194 | test_zero_clear | |
| 195 | test_ovf_clear | |
| 196 | test_carry_clear | |
| 197 | ||
| 198 | test_h_gr32 neg+4 er1 ; er1 still contains target address | |
| 199 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 200 | test_gr_a5a5 2 | |
| 201 | test_gr_a5a5 3 | |
| 202 | test_gr_a5a5 4 | |
| 203 | test_gr_a5a5 5 | |
| 204 | test_gr_a5a5 6 | |
| 205 | test_gr_a5a5 7 | |
| 206 | cmp.l #0xffff8000, @neg | |
| 207 | beq .Lslpostincn | |
| 208 | fail | |
| 209 | .Lslpostincn: | |
| 210 | ;;; Note: leave the value as 0xffff8000, so that extu has work to do. | |
| 211 | ||
| 212 | extu_l_postinc_n: | |
| 213 | set_grs_a5a5 | |
| 214 | set_ccr_zero | |
| 215 | ;; extu.l @ern32+ | |
| 216 | mov.l #neg, er1 | |
| 217 | extu.l @er1+ | |
| 218 | ||
| 219 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 220 | test_cc_clear | |
| 221 | ||
| 222 | test_h_gr32 neg+4 er1 ; er1 still contains target address | |
| 223 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 224 | test_gr_a5a5 2 | |
| 225 | test_gr_a5a5 3 | |
| 226 | test_gr_a5a5 4 | |
| 227 | test_gr_a5a5 5 | |
| 228 | test_gr_a5a5 6 | |
| 229 | test_gr_a5a5 7 | |
| 230 | cmp.l #0x00008000, @neg | |
| 231 | beq .Lulpostincn | |
| 232 | fail | |
| 233 | .Lulpostincn: | |
| 234 | ;;; Note: leave the value as 0x00008000, so that extu has work to do. | |
| 235 | ||
| 236 | exts_l_postdec_p: | |
| 237 | set_grs_a5a5 | |
| 238 | set_ccr_zero | |
| 239 | ;; exts.l @ern32- | |
| 240 | mov.l #pos, er1 | |
| 241 | exts.l @er1- | |
| 242 | ||
| 243 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 244 | test_cc_clear | |
| 245 | ||
| 246 | test_h_gr32 pos-4 er1 ; er1 still contains target address | |
| 247 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 248 | test_gr_a5a5 2 | |
| 249 | test_gr_a5a5 3 | |
| 250 | test_gr_a5a5 4 | |
| 251 | test_gr_a5a5 5 | |
| 252 | test_gr_a5a5 6 | |
| 253 | test_gr_a5a5 7 | |
| 254 | cmp.l #0x00000001, @pos | |
| 255 | beq .Lslpostdecp | |
| 256 | fail | |
| 257 | .Lslpostdecp: | |
| 258 | mov.l #0xffff0001, @pos ; Restore initial value | |
| 259 | ||
| 260 | exts_l_postdec_n: | |
| 261 | set_grs_a5a5 | |
| 262 | set_ccr_zero | |
| 263 | ;; exts.l @ern32- | |
| 264 | mov.l #neg, er1 | |
| 265 | exts.l @er1- | |
| 266 | ||
| 267 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 268 | test_neg_set | |
| 269 | test_zero_clear | |
| 270 | test_ovf_clear | |
| 271 | test_carry_clear | |
| 272 | ||
| 273 | test_h_gr32 neg-4 er1 ; er1 still contains target address | |
| 274 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 275 | test_gr_a5a5 2 | |
| 276 | test_gr_a5a5 3 | |
| 277 | test_gr_a5a5 4 | |
| 278 | test_gr_a5a5 5 | |
| 279 | test_gr_a5a5 6 | |
| 280 | test_gr_a5a5 7 | |
| 281 | cmp.l #0xffff8000, @neg | |
| 282 | beq .Lslpostdecn | |
| 283 | fail | |
| 284 | .Lslpostdecn: | |
| 285 | ;;; Note: leave the value as 0xffff8000, so that extu has work to do. | |
| 286 | ||
| 287 | extu_l_postdec_n: | |
| 288 | set_grs_a5a5 | |
| 289 | set_ccr_zero | |
| 290 | ;; extu.l @ern32- | |
| 291 | mov.l #neg, er1 | |
| 292 | extu.l @er1- | |
| 293 | ||
| 294 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 295 | test_cc_clear | |
| 296 | ||
| 297 | test_h_gr32 neg-4 er1 ; er1 still contains target address | |
| 298 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 299 | test_gr_a5a5 2 | |
| 300 | test_gr_a5a5 3 | |
| 301 | test_gr_a5a5 4 | |
| 302 | test_gr_a5a5 5 | |
| 303 | test_gr_a5a5 6 | |
| 304 | test_gr_a5a5 7 | |
| 305 | cmp.l #0x00008000, @neg | |
| 306 | beq .Lulpostdecn | |
| 307 | fail | |
| 308 | .Lulpostdecn: | |
| 309 | ;;; Note: leave the value as 0x00008000, so that extu has work to do. | |
| 310 | ||
| 311 | exts_l_preinc_p: | |
| 312 | set_grs_a5a5 | |
| 313 | set_ccr_zero | |
| 314 | ;; exts.l @+ern32 | |
| 315 | mov.l #pos-4, er1 | |
| 316 | exts.l @+er1 | |
| 317 | ||
| 318 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 319 | test_cc_clear | |
| 320 | ||
| 321 | test_h_gr32 pos er1 ; er1 still contains target address | |
| 322 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 323 | test_gr_a5a5 2 | |
| 324 | test_gr_a5a5 3 | |
| 325 | test_gr_a5a5 4 | |
| 326 | test_gr_a5a5 5 | |
| 327 | test_gr_a5a5 6 | |
| 328 | test_gr_a5a5 7 | |
| 329 | cmp.l #0x00000001, @pos | |
| 330 | beq .Lslpreincp | |
| 331 | fail | |
| 332 | .Lslpreincp: | |
| 333 | mov.l #0xffff0001, @pos ; Restore initial value | |
| 334 | ||
| 335 | exts_l_preinc_n: | |
| 336 | set_grs_a5a5 | |
| 337 | set_ccr_zero | |
| 338 | ;; exts.l @+ern32 | |
| 339 | mov.l #neg-4, er1 | |
| 340 | exts.l @+er1 | |
| 341 | ||
| 342 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 343 | test_neg_set | |
| 344 | test_zero_clear | |
| 345 | test_ovf_clear | |
| 346 | test_carry_clear | |
| 347 | ||
| 348 | test_h_gr32 neg er1 ; er1 still contains target address | |
| 349 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 350 | test_gr_a5a5 2 | |
| 351 | test_gr_a5a5 3 | |
| 352 | test_gr_a5a5 4 | |
| 353 | test_gr_a5a5 5 | |
| 354 | test_gr_a5a5 6 | |
| 355 | test_gr_a5a5 7 | |
| 356 | cmp.l #0xffff8000, @neg | |
| 357 | beq .Lslpreincn | |
| 358 | fail | |
| 359 | .Lslpreincn: | |
| 360 | ;;; Note: leave the value as 0xffff8000, so that extu has work to do. | |
| 361 | ||
| 362 | extu_l_preinc_n: | |
| 363 | set_grs_a5a5 | |
| 364 | set_ccr_zero | |
| 365 | ;; extu.l @+ern32 | |
| 366 | mov.l #neg-4, er1 | |
| 367 | extu.l @+er1 | |
| 368 | ||
| 369 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 370 | test_cc_clear | |
| 371 | ||
| 372 | test_h_gr32 neg er1 ; er1 still contains target address | |
| 373 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 374 | test_gr_a5a5 2 | |
| 375 | test_gr_a5a5 3 | |
| 376 | test_gr_a5a5 4 | |
| 377 | test_gr_a5a5 5 | |
| 378 | test_gr_a5a5 6 | |
| 379 | test_gr_a5a5 7 | |
| 380 | cmp.l #0x00008000, @neg | |
| 381 | beq .Lulpreincn | |
| 382 | fail | |
| 383 | .Lulpreincn: | |
| 384 | ;;; Note: leave the value as 0x00008000, so that extu has work to do. | |
| 385 | ||
| 386 | exts_l_predec_p: | |
| 387 | set_grs_a5a5 | |
| 388 | set_ccr_zero | |
| 389 | ;; exts.l @-ern32 | |
| 390 | mov.l #pos+4, er1 | |
| 391 | exts.l @-er1 | |
| 392 | ||
| 393 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 394 | test_cc_clear | |
| 395 | ||
| 396 | test_h_gr32 pos er1 ; er1 still contains target address | |
| 397 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 398 | test_gr_a5a5 2 | |
| 399 | test_gr_a5a5 3 | |
| 400 | test_gr_a5a5 4 | |
| 401 | test_gr_a5a5 5 | |
| 402 | test_gr_a5a5 6 | |
| 403 | test_gr_a5a5 7 | |
| 404 | cmp.l #0x00000001, @pos | |
| 405 | beq .Lslpredecp | |
| 406 | fail | |
| 407 | .Lslpredecp: | |
| 408 | mov.l #0xffff0001, @pos ; Restore initial value | |
| 409 | ||
| 410 | exts_l_predec_n: | |
| 411 | set_grs_a5a5 | |
| 412 | set_ccr_zero | |
| 413 | ;; exts.l @-ern32 | |
| 414 | mov.l #neg+4, er1 | |
| 415 | exts.l @-er1 | |
| 416 | ||
| 417 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 418 | test_neg_set | |
| 419 | test_zero_clear | |
| 420 | test_ovf_clear | |
| 421 | test_carry_clear | |
| 422 | ||
| 423 | test_h_gr32 neg er1 ; er1 still contains target address | |
| 424 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 425 | test_gr_a5a5 2 | |
| 426 | test_gr_a5a5 3 | |
| 427 | test_gr_a5a5 4 | |
| 428 | test_gr_a5a5 5 | |
| 429 | test_gr_a5a5 6 | |
| 430 | test_gr_a5a5 7 | |
| 431 | cmp.l #0xffff8000, @neg | |
| 432 | beq .Lslpredecn | |
| 433 | fail | |
| 434 | .Lslpredecn: | |
| 435 | ;;; Note: leave the value as 0xffff8000, so that extu has work to do. | |
| 436 | ||
| 437 | extu_l_predec_n: | |
| 438 | set_grs_a5a5 | |
| 439 | set_ccr_zero | |
| 440 | ;; extu.l @-ern32 | |
| 441 | mov.l #neg+4, er1 | |
| 442 | extu.l @-er1 | |
| 443 | ||
| 444 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 445 | test_cc_clear | |
| 446 | ||
| 447 | test_h_gr32 neg er1 ; er1 still contains target address | |
| 448 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 449 | test_gr_a5a5 2 | |
| 450 | test_gr_a5a5 3 | |
| 451 | test_gr_a5a5 4 | |
| 452 | test_gr_a5a5 5 | |
| 453 | test_gr_a5a5 6 | |
| 454 | test_gr_a5a5 7 | |
| 455 | cmp.l #0x00008000, @neg | |
| 456 | beq .Lulpredecn | |
| 457 | fail | |
| 458 | .Lulpredecn: | |
| 459 | ;;; Note: leave the value as 0x00008000, so that extu has work to do. | |
| 460 | ||
| 461 | extu_l_disp2_n: | |
| 462 | set_grs_a5a5 | |
| 463 | set_ccr_zero | |
| 464 | ;; extu.l @(dd:2, ern32) | |
| 465 | mov.l #neg-8, er1 | |
| 466 | extu.l @(8:2, er1) | |
| 467 | ||
| 468 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 469 | test_cc_clear | |
| 470 | ||
| 471 | test_h_gr32 neg-8 er1 ; er1 still contains target address | |
| 472 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 473 | test_gr_a5a5 2 | |
| 474 | test_gr_a5a5 3 | |
| 475 | test_gr_a5a5 4 | |
| 476 | test_gr_a5a5 5 | |
| 477 | test_gr_a5a5 6 | |
| 478 | test_gr_a5a5 7 | |
| 479 | cmp.l #0x00008000, @neg | |
| 480 | beq .Luldisp2n | |
| 481 | fail | |
| 482 | .Luldisp2n: | |
| 483 | ;;; Note: leave the value as 0x00008000, so that extu has work to do. | |
| 484 | ||
| 485 | extu_l_disp16_n: | |
| 486 | set_grs_a5a5 | |
| 487 | set_ccr_zero | |
| 488 | ;; extu.l @(dd:16, ern32) | |
| 489 | mov.l #neg-44, er1 | |
| 490 | extu.l @(44:16, er1) | |
| 491 | ||
| 492 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 493 | test_cc_clear | |
| 494 | ||
| 495 | test_h_gr32 neg-44 er1 ; er1 still contains target address | |
| 496 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 497 | test_gr_a5a5 2 | |
| 498 | test_gr_a5a5 3 | |
| 499 | test_gr_a5a5 4 | |
| 500 | test_gr_a5a5 5 | |
| 501 | test_gr_a5a5 6 | |
| 502 | test_gr_a5a5 7 | |
| 503 | cmp.l #0x00008000, @neg | |
| 504 | beq .Luldisp16n | |
| 505 | fail | |
| 506 | .Luldisp16n: | |
| 507 | ;;; Note: leave the value as 0x00008000, so that extu has work to do. | |
| 508 | ||
| 509 | extu_l_disp32_n: | |
| 510 | set_grs_a5a5 | |
| 511 | set_ccr_zero | |
| 512 | ;; extu.l @(dd:32, ern32) | |
| 513 | mov.l #neg+444, er1 | |
| 514 | extu.l @(-444:32, er1) | |
| 515 | ||
| 516 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 517 | test_cc_clear | |
| 518 | ||
| 519 | test_h_gr32 neg+444 er1 ; er1 still contains target address | |
| 520 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 521 | test_gr_a5a5 2 | |
| 522 | test_gr_a5a5 3 | |
| 523 | test_gr_a5a5 4 | |
| 524 | test_gr_a5a5 5 | |
| 525 | test_gr_a5a5 6 | |
| 526 | test_gr_a5a5 7 | |
| 527 | cmp.l #0x00008000, @neg | |
| 528 | beq .Luldisp32n | |
| 529 | fail | |
| 530 | .Luldisp32n: | |
| 531 | ;;; Note: leave the value as 0x00008000, so that extu has work to do. | |
| 532 | ||
| 533 | extu_l_abs16_n: | |
| 534 | set_grs_a5a5 | |
| 535 | set_ccr_zero | |
| 536 | ;; extu.l @aa:16 | |
| 537 | extu.l @neg:16 | |
| 538 | ||
| 539 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 540 | test_cc_clear | |
| 541 | ||
| 542 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 543 | test_gr_a5a5 1 | |
| 544 | test_gr_a5a5 2 | |
| 545 | test_gr_a5a5 3 | |
| 546 | test_gr_a5a5 4 | |
| 547 | test_gr_a5a5 5 | |
| 548 | test_gr_a5a5 6 | |
| 549 | test_gr_a5a5 7 | |
| 550 | cmp.l #0x00008000, @neg | |
| 551 | beq .Lulabs16n | |
| 552 | fail | |
| 553 | .Lulabs16n: | |
| 554 | ;;; Note: leave the value as 0x00008000, so that extu has work to do. | |
| 555 | ||
| 556 | extu_l_abs32_n: | |
| 557 | set_grs_a5a5 | |
| 558 | set_ccr_zero | |
| 559 | ;; extu.l @aa:32 | |
| 560 | extu.l @neg:32 | |
| 561 | ||
| 562 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 563 | test_cc_clear | |
| 564 | ||
| 565 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 566 | test_gr_a5a5 1 | |
| 567 | test_gr_a5a5 2 | |
| 568 | test_gr_a5a5 3 | |
| 569 | test_gr_a5a5 4 | |
| 570 | test_gr_a5a5 5 | |
| 571 | test_gr_a5a5 6 | |
| 572 | test_gr_a5a5 7 | |
| 573 | cmp.l #0x00008000, @neg | |
| 574 | beq .Lulabs32n | |
| 575 | fail | |
| 576 | .Lulabs32n: | |
| 577 | ;;; Note: leave the value as 0x00008000, so that extu has work to do. | |
| 578 | ||
| 579 | ||
| 580 | ||
| 581 | # | |
| 582 | # exts #2, nn | |
| 583 | # | |
| 584 | ||
| 585 | exts_l_reg32_2_p: | |
| 586 | set_grs_a5a5 | |
| 587 | set_ccr_zero | |
| 588 | ;; exts.l #2, ern32 | |
| 589 | mov.b #1, r0l | |
| 590 | exts.l #2, er0 | |
| 591 | ||
| 592 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 593 | test_cc_clear | |
| 594 | ||
| 595 | test_h_gr32 0x00000001 er0 ; result of sign extend | |
| 596 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 597 | test_gr_a5a5 2 | |
| 598 | test_gr_a5a5 3 | |
| 599 | test_gr_a5a5 4 | |
| 600 | test_gr_a5a5 5 | |
| 601 | test_gr_a5a5 6 | |
| 602 | test_gr_a5a5 7 | |
| 603 | ||
| 604 | exts_l_reg32_2_n: | |
| 605 | set_grs_a5a5 | |
| 606 | set_ccr_zero | |
| 607 | ;; exts.l #2, ern32 | |
| 608 | mov.b #0xff, r0l | |
| 609 | exts.l #2, er0 | |
| 610 | ||
| 611 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 612 | test_neg_set | |
| 613 | test_ovf_clear | |
| 614 | test_zero_clear | |
| 615 | test_carry_clear | |
| 616 | ||
| 617 | test_h_gr32 0xffffffff er0 ; result of sign extend | |
| 618 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 619 | test_gr_a5a5 2 | |
| 620 | test_gr_a5a5 3 | |
| 621 | test_gr_a5a5 4 | |
| 622 | test_gr_a5a5 5 | |
| 623 | test_gr_a5a5 6 | |
| 624 | test_gr_a5a5 7 | |
| 625 | ||
| 626 | extu_l_reg32_2_n: | |
| 627 | set_grs_a5a5 | |
| 628 | set_ccr_zero | |
| 629 | ;; extu.l #2, ern32 | |
| 630 | mov.b #0xff, r0l | |
| 631 | extu.l #2, er0 | |
| 632 | ||
| 633 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 634 | test_cc_clear | |
| 635 | ||
| 636 | test_h_gr32 0x000000ff er0 ; result of zero extend | |
| 637 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 638 | test_gr_a5a5 2 | |
| 639 | test_gr_a5a5 3 | |
| 640 | test_gr_a5a5 4 | |
| 641 | test_gr_a5a5 5 | |
| 642 | test_gr_a5a5 6 | |
| 643 | test_gr_a5a5 7 | |
| 644 | ||
| 645 | exts_l_ind_2_p: | |
| 646 | set_grs_a5a5 | |
| 647 | set_ccr_zero | |
| 648 | ;; exts.l #2, @ern32 | |
| 649 | mov.l #pos2, er1 | |
| 650 | exts.l #2, @er1 | |
| 651 | ||
| 652 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 653 | test_cc_clear | |
| 654 | ||
| 655 | test_h_gr32 pos2 er1 ; result of sign extend | |
| 656 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 657 | test_gr_a5a5 2 | |
| 658 | test_gr_a5a5 3 | |
| 659 | test_gr_a5a5 4 | |
| 660 | test_gr_a5a5 5 | |
| 661 | test_gr_a5a5 6 | |
| 662 | test_gr_a5a5 7 | |
| 663 | cmp.l #0x00000001, @pos2 | |
| 664 | beq .Lslindp2 | |
| 665 | fail | |
| 666 | .Lslindp2: | |
| 667 | mov.l #0xffffff01, @pos2 ; Restore initial value | |
| 668 | ||
| 669 | exts_l_ind_2_n: | |
| 670 | set_grs_a5a5 | |
| 671 | set_ccr_zero | |
| 672 | ;; exts.l #2, @ern32 | |
| 673 | mov.l #neg2, er1 | |
| 674 | exts.l #2, @er1 | |
| 675 | ||
| 676 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 677 | test_neg_set | |
| 678 | test_ovf_clear | |
| 679 | test_zero_clear | |
| 680 | test_carry_clear | |
| 681 | ||
| 682 | test_h_gr32 neg2 er1 ; result of sign extend | |
| 683 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 684 | test_gr_a5a5 2 | |
| 685 | test_gr_a5a5 3 | |
| 686 | test_gr_a5a5 4 | |
| 687 | test_gr_a5a5 5 | |
| 688 | test_gr_a5a5 6 | |
| 689 | test_gr_a5a5 7 | |
| 690 | cmp.l #0xffffff80, @neg2 | |
| 691 | beq .Lslindn2 | |
| 692 | fail | |
| 693 | .Lslindn2: | |
| 694 | ;;; Note: leave the value as 0xffffff80, so that extu has work to do. | |
| 695 | ||
| 696 | extu_l_ind_2_n: | |
| 697 | set_grs_a5a5 | |
| 698 | set_ccr_zero | |
| 699 | ;; extu.l #2, @ern32 | |
| 700 | mov.l #neg2, er1 | |
| 701 | extu.l #2, @er1 | |
| 702 | ||
| 703 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 704 | test_cc_clear | |
| 705 | ||
| 706 | test_h_gr32 neg2 er1 ; result of zero extend | |
| 707 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 708 | test_gr_a5a5 2 | |
| 709 | test_gr_a5a5 3 | |
| 710 | test_gr_a5a5 4 | |
| 711 | test_gr_a5a5 5 | |
| 712 | test_gr_a5a5 6 | |
| 713 | test_gr_a5a5 7 | |
| 714 | cmp.l #0x00000080, @neg2 | |
| 715 | beq .Lulindn2 | |
| 716 | fail | |
| 717 | .Lulindn2: | |
| 718 | ;;; Note: leave the value as 0x00000080, like it started out. | |
| 719 | ||
| 720 | exts_l_postinc_2_p: | |
| 721 | set_grs_a5a5 | |
| 722 | set_ccr_zero | |
| 723 | ;; exts.l #2, @ern32+ | |
| 724 | mov.l #pos2, er1 | |
| 725 | exts.l #2, @er1+ | |
| 726 | ||
| 727 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 728 | test_cc_clear | |
| 729 | ||
| 730 | test_h_gr32 pos2+4 er1 ; result of sign extend | |
| 731 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 732 | test_gr_a5a5 2 | |
| 733 | test_gr_a5a5 3 | |
| 734 | test_gr_a5a5 4 | |
| 735 | test_gr_a5a5 5 | |
| 736 | test_gr_a5a5 6 | |
| 737 | test_gr_a5a5 7 | |
| 738 | cmp.l #0x00000001, @pos2 | |
| 739 | beq .Lslpostincp2 | |
| 740 | fail | |
| 741 | .Lslpostincp2: | |
| 742 | mov.l #0xffffff01, @pos2 ; Restore initial value | |
| 743 | ||
| 744 | exts_l_postinc_2_n: | |
| 745 | set_grs_a5a5 | |
| 746 | set_ccr_zero | |
| 747 | ;; exts.l #2, @ern32+ | |
| 748 | mov.l #neg2, er1 | |
| 749 | exts.l #2, @er1+ | |
| 750 | ||
| 751 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 752 | test_neg_set | |
| 753 | test_ovf_clear | |
| 754 | test_zero_clear | |
| 755 | test_carry_clear | |
| 756 | ||
| 757 | test_h_gr32 neg2+4 er1 ; result of sign extend | |
| 758 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 759 | test_gr_a5a5 2 | |
| 760 | test_gr_a5a5 3 | |
| 761 | test_gr_a5a5 4 | |
| 762 | test_gr_a5a5 5 | |
| 763 | test_gr_a5a5 6 | |
| 764 | test_gr_a5a5 7 | |
| 765 | cmp.l #0xffffff80, @neg2 | |
| 766 | beq .Lslpostincn2 | |
| 767 | fail | |
| 768 | .Lslpostincn2: | |
| 769 | ;;; Note: leave the value as 0xffffff80, so that extu has work to do. | |
| 770 | ||
| 771 | extu_l_postinc_2_n: | |
| 772 | set_grs_a5a5 | |
| 773 | set_ccr_zero | |
| 774 | ;; extu.l #2, @ern32+ | |
| 775 | mov.l #neg2, er1 | |
| 776 | extu.l #2, @er1+ | |
| 777 | ||
| 778 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 779 | test_cc_clear | |
| 780 | ||
| 781 | test_h_gr32 neg2+4 er1 ; result of zero extend | |
| 782 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 783 | test_gr_a5a5 2 | |
| 784 | test_gr_a5a5 3 | |
| 785 | test_gr_a5a5 4 | |
| 786 | test_gr_a5a5 5 | |
| 787 | test_gr_a5a5 6 | |
| 788 | test_gr_a5a5 7 | |
| 789 | cmp.l #0x00000080, @neg2 | |
| 790 | beq .Lulpostincn2 | |
| 791 | fail | |
| 792 | .Lulpostincn2: | |
| 793 | ;;; Note: leave the value as 0x00000080, like it started out. | |
| 794 | ||
| 795 | exts_l_postdec_2_p: | |
| 796 | set_grs_a5a5 | |
| 797 | set_ccr_zero | |
| 798 | ;; exts.l #2, @ern32- | |
| 799 | mov.l #pos2, er1 | |
| 800 | exts.l #2, @er1- | |
| 801 | ||
| 802 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 803 | test_cc_clear | |
| 804 | ||
| 805 | test_h_gr32 pos2-4 er1 ; result of sign extend | |
| 806 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 807 | test_gr_a5a5 2 | |
| 808 | test_gr_a5a5 3 | |
| 809 | test_gr_a5a5 4 | |
| 810 | test_gr_a5a5 5 | |
| 811 | test_gr_a5a5 6 | |
| 812 | test_gr_a5a5 7 | |
| 813 | cmp.l #0x00000001, @pos2 | |
| 814 | beq .Lslpostdecp2 | |
| 815 | fail | |
| 816 | .Lslpostdecp2: | |
| 817 | mov.l #0xffffff01, @pos2 ; Restore initial value | |
| 818 | ||
| 819 | exts_l_postdec_2_n: | |
| 820 | set_grs_a5a5 | |
| 821 | set_ccr_zero | |
| 822 | ;; exts.l #2, @ern32- | |
| 823 | mov.l #neg2, er1 | |
| 824 | exts.l #2, @er1- | |
| 825 | ||
| 826 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 827 | test_neg_set | |
| 828 | test_ovf_clear | |
| 829 | test_zero_clear | |
| 830 | test_carry_clear | |
| 831 | ||
| 832 | test_h_gr32 neg2-4 er1 ; result of sign extend | |
| 833 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 834 | test_gr_a5a5 2 | |
| 835 | test_gr_a5a5 3 | |
| 836 | test_gr_a5a5 4 | |
| 837 | test_gr_a5a5 5 | |
| 838 | test_gr_a5a5 6 | |
| 839 | test_gr_a5a5 7 | |
| 840 | cmp.l #0xffffff80, @neg2 | |
| 841 | beq .Lslpostdecn2 | |
| 842 | fail | |
| 843 | .Lslpostdecn2: | |
| 844 | ;;; Note: leave the value as 0xffffff80, so that extu has work to do. | |
| 845 | ||
| 846 | extu_l_postdec_2_n: | |
| 847 | set_grs_a5a5 | |
| 848 | set_ccr_zero | |
| 849 | ;; extu.l #2, @ern32- | |
| 850 | mov.l #neg2, er1 | |
| 851 | extu.l #2, @er1- | |
| 852 | ||
| 853 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 854 | test_cc_clear | |
| 855 | ||
| 856 | test_h_gr32 neg2-4 er1 ; result of zero extend | |
| 857 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 858 | test_gr_a5a5 2 | |
| 859 | test_gr_a5a5 3 | |
| 860 | test_gr_a5a5 4 | |
| 861 | test_gr_a5a5 5 | |
| 862 | test_gr_a5a5 6 | |
| 863 | test_gr_a5a5 7 | |
| 864 | cmp.l #0x00000080, @neg2 | |
| 865 | beq .Lulpostdecn2 | |
| 866 | fail | |
| 867 | .Lulpostdecn2: | |
| 868 | ;;; Note: leave the value as 0x00000080, like it started out. | |
| 869 | ||
| 870 | exts_l_preinc_2_p: | |
| 871 | set_grs_a5a5 | |
| 872 | set_ccr_zero | |
| 873 | ;; exts.l #2, @+ern32 | |
| 874 | mov.l #pos2-4, er1 | |
| 875 | exts.l #2, @+er1 | |
| 876 | ||
| 877 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 878 | test_cc_clear | |
| 879 | ||
| 880 | test_h_gr32 pos2 er1 ; result of sign extend | |
| 881 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 882 | test_gr_a5a5 2 | |
| 883 | test_gr_a5a5 3 | |
| 884 | test_gr_a5a5 4 | |
| 885 | test_gr_a5a5 5 | |
| 886 | test_gr_a5a5 6 | |
| 887 | test_gr_a5a5 7 | |
| 888 | cmp.l #0x00000001, @pos2 | |
| 889 | beq .Lslpreincp2 | |
| 890 | fail | |
| 891 | .Lslpreincp2: | |
| 892 | mov.l #0xffffff01, @pos2 ; Restore initial value | |
| 893 | ||
| 894 | exts_l_preinc_2_n: | |
| 895 | set_grs_a5a5 | |
| 896 | set_ccr_zero | |
| 897 | ;; exts.l #2, @+ern32 | |
| 898 | mov.l #neg2-4, er1 | |
| 899 | exts.l #2, @+er1 | |
| 900 | ||
| 901 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 902 | test_neg_set | |
| 903 | test_ovf_clear | |
| 904 | test_zero_clear | |
| 905 | test_carry_clear | |
| 906 | ||
| 907 | test_h_gr32 neg2 er1 ; result of sign extend | |
| 908 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 909 | test_gr_a5a5 2 | |
| 910 | test_gr_a5a5 3 | |
| 911 | test_gr_a5a5 4 | |
| 912 | test_gr_a5a5 5 | |
| 913 | test_gr_a5a5 6 | |
| 914 | test_gr_a5a5 7 | |
| 915 | cmp.l #0xffffff80, @neg2 | |
| 916 | beq .Lslpreincn2 | |
| 917 | fail | |
| 918 | .Lslpreincn2: | |
| 919 | ;;; Note: leave the value as 0xffffff80, so that extu has work to do. | |
| 920 | ||
| 921 | extu_l_preinc_2_n: | |
| 922 | set_grs_a5a5 | |
| 923 | set_ccr_zero | |
| 924 | ;; extu.l #2, @+ern32 | |
| 925 | mov.l #neg2-4, er1 | |
| 926 | extu.l #2, @+er1 | |
| 927 | ||
| 928 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 929 | test_cc_clear | |
| 930 | ||
| 931 | test_h_gr32 neg2 er1 ; result of zero extend | |
| 932 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 933 | test_gr_a5a5 2 | |
| 934 | test_gr_a5a5 3 | |
| 935 | test_gr_a5a5 4 | |
| 936 | test_gr_a5a5 5 | |
| 937 | test_gr_a5a5 6 | |
| 938 | test_gr_a5a5 7 | |
| 939 | cmp.l #0x00000080, @neg2 | |
| 940 | beq .Lulpreincn2 | |
| 941 | fail | |
| 942 | .Lulpreincn2: | |
| 943 | ;;; Note: leave the value as 0x00000080, like it started out. | |
| 944 | ||
| 945 | exts_l_predec_2_p: | |
| 946 | set_grs_a5a5 | |
| 947 | set_ccr_zero | |
| 948 | ;; exts.l #2, @-ern32 | |
| 949 | mov.l #pos2+4, er1 | |
| 950 | exts.l #2, @-er1 | |
| 951 | ||
| 952 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 953 | test_cc_clear | |
| 954 | ||
| 955 | test_h_gr32 pos2 er1 ; result of sign extend | |
| 956 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 957 | test_gr_a5a5 2 | |
| 958 | test_gr_a5a5 3 | |
| 959 | test_gr_a5a5 4 | |
| 960 | test_gr_a5a5 5 | |
| 961 | test_gr_a5a5 6 | |
| 962 | test_gr_a5a5 7 | |
| 963 | cmp.l #0x00000001, @pos2 | |
| 964 | beq .Lslpredecp2 | |
| 965 | fail | |
| 966 | .Lslpredecp2: | |
| 967 | mov.l #0xffffff01, @pos2 ; Restore initial value | |
| 968 | ||
| 969 | exts_l_predec_2_n: | |
| 970 | set_grs_a5a5 | |
| 971 | set_ccr_zero | |
| 972 | ;; exts.l #2, @-ern32 | |
| 973 | mov.l #neg2+4, er1 | |
| 974 | exts.l #2, @-er1 | |
| 975 | ||
| 976 | ;; Test ccr H=0 N=1 Z=0 V=0 C=0 | |
| 977 | test_neg_set | |
| 978 | test_ovf_clear | |
| 979 | test_zero_clear | |
| 980 | test_carry_clear | |
| 981 | ||
| 982 | test_h_gr32 neg2 er1 ; result of sign extend | |
| 983 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 984 | test_gr_a5a5 2 | |
| 985 | test_gr_a5a5 3 | |
| 986 | test_gr_a5a5 4 | |
| 987 | test_gr_a5a5 5 | |
| 988 | test_gr_a5a5 6 | |
| 989 | test_gr_a5a5 7 | |
| 990 | cmp.l #0xffffff80, @neg2 | |
| 991 | beq .Lslpredecn2 | |
| 992 | fail | |
| 993 | .Lslpredecn2: | |
| 994 | ;;; Note: leave the value as 0xffffff80, so that extu has work to do. | |
| 995 | ||
| 996 | extu_l_predec_2_n: | |
| 997 | set_grs_a5a5 | |
| 998 | set_ccr_zero | |
| 999 | ;; extu.l #2, @-ern32 | |
| 1000 | mov.l #neg2+4, er1 | |
| 1001 | extu.l #2, @-er1 | |
| 1002 | ||
| 1003 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 1004 | test_cc_clear | |
| 1005 | ||
| 1006 | test_h_gr32 neg2 er1 ; result of zero extend | |
| 1007 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 1008 | test_gr_a5a5 2 | |
| 1009 | test_gr_a5a5 3 | |
| 1010 | test_gr_a5a5 4 | |
| 1011 | test_gr_a5a5 5 | |
| 1012 | test_gr_a5a5 6 | |
| 1013 | test_gr_a5a5 7 | |
| 1014 | cmp.l #0x00000080, @neg2 | |
| 1015 | beq .Lulpredecn2 | |
| 1016 | fail | |
| 1017 | .Lulpredecn2: | |
| 1018 | ;;; Note: leave the value as 0x00000080, like it started out. | |
| 1019 | ||
| 1020 | extu_l_disp2_2_n: | |
| 1021 | set_grs_a5a5 | |
| 1022 | set_ccr_zero | |
| 1023 | ;; extu.l #2, @(dd:2, ern32) | |
| 1024 | mov.l #neg2-8, er1 | |
| 1025 | extu.l #2, @(8:2, er1) | |
| 1026 | ||
| 1027 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 1028 | test_cc_clear | |
| 1029 | ||
| 1030 | test_h_gr32 neg2-8 er1 ; result of zero extend | |
| 1031 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 1032 | test_gr_a5a5 2 | |
| 1033 | test_gr_a5a5 3 | |
| 1034 | test_gr_a5a5 4 | |
| 1035 | test_gr_a5a5 5 | |
| 1036 | test_gr_a5a5 6 | |
| 1037 | test_gr_a5a5 7 | |
| 1038 | cmp.l #0x00000080, @neg2 | |
| 1039 | beq .Luldisp2n2 | |
| 1040 | fail | |
| 1041 | .Luldisp2n2: | |
| 1042 | ;;; Note: leave the value as 0x00000080, like it started out. | |
| 1043 | ||
| 1044 | extu_l_disp16_2_n: | |
| 1045 | set_grs_a5a5 | |
| 1046 | set_ccr_zero | |
| 1047 | ;; extu.l #2, @(dd:16, ern32) | |
| 1048 | mov.l #neg2-44, er1 | |
| 1049 | extu.l #2, @(44:16, er1) | |
| 1050 | ||
| 1051 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 1052 | test_cc_clear | |
| 1053 | ||
| 1054 | test_h_gr32 neg2-44 er1 ; result of zero extend | |
| 1055 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 1056 | test_gr_a5a5 2 | |
| 1057 | test_gr_a5a5 3 | |
| 1058 | test_gr_a5a5 4 | |
| 1059 | test_gr_a5a5 5 | |
| 1060 | test_gr_a5a5 6 | |
| 1061 | test_gr_a5a5 7 | |
| 1062 | cmp.l #0x00000080, @neg2 | |
| 1063 | beq .Luldisp16n2 | |
| 1064 | fail | |
| 1065 | .Luldisp16n2: | |
| 1066 | ;;; Note: leave the value as 0x00000080, like it started out. | |
| 1067 | ||
| 1068 | extu_l_disp32_2_n: | |
| 1069 | set_grs_a5a5 | |
| 1070 | set_ccr_zero | |
| 1071 | ;; extu.l #2, @(dd:32, ern32) | |
| 1072 | mov.l #neg2+444, er1 | |
| 1073 | extu.l #2, @(-444:32, er1) | |
| 1074 | ||
| 1075 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 1076 | test_cc_clear | |
| 1077 | ||
| 1078 | test_h_gr32 neg2+444 er1 ; result of zero extend | |
| 1079 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 1080 | test_gr_a5a5 2 | |
| 1081 | test_gr_a5a5 3 | |
| 1082 | test_gr_a5a5 4 | |
| 1083 | test_gr_a5a5 5 | |
| 1084 | test_gr_a5a5 6 | |
| 1085 | test_gr_a5a5 7 | |
| 1086 | cmp.l #0x00000080, @neg2 | |
| 1087 | beq .Luldisp32n2 | |
| 1088 | fail | |
| 1089 | .Luldisp32n2: | |
| 1090 | ;;; Note: leave the value as 0x00000080, like it started out. | |
| 1091 | ||
| 1092 | extu_l_abs16_2_n: | |
| 1093 | set_grs_a5a5 | |
| 1094 | set_ccr_zero | |
| 1095 | ;; extu.l #2, @aa:16 | |
| 1096 | extu.l #2, @neg2:16 | |
| 1097 | ||
| 1098 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 1099 | test_cc_clear | |
| 1100 | ||
| 1101 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 1102 | test_gr_a5a5 1 | |
| 1103 | test_gr_a5a5 2 | |
| 1104 | test_gr_a5a5 3 | |
| 1105 | test_gr_a5a5 4 | |
| 1106 | test_gr_a5a5 5 | |
| 1107 | test_gr_a5a5 6 | |
| 1108 | test_gr_a5a5 7 | |
| 1109 | cmp.l #0x00000080, @neg2 | |
| 1110 | beq .Lulabs16n2 | |
| 1111 | fail | |
| 1112 | .Lulabs16n2: | |
| 1113 | ;;; Note: leave the value as 0x00000080, like it started out. | |
| 1114 | ||
| 1115 | extu_l_abs32_2_n: | |
| 1116 | set_grs_a5a5 | |
| 1117 | set_ccr_zero | |
| 1118 | ;; extu.l #2, @aa:32 | |
| 1119 | extu.l #2, @neg2:32 | |
| 1120 | ||
| 1121 | ;; Test ccr H=0 N=0 Z=0 V=0 C=0 | |
| 1122 | test_cc_clear | |
| 1123 | ||
| 1124 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 1125 | test_gr_a5a5 1 | |
| 1126 | test_gr_a5a5 2 | |
| 1127 | test_gr_a5a5 3 | |
| 1128 | test_gr_a5a5 4 | |
| 1129 | test_gr_a5a5 5 | |
| 1130 | test_gr_a5a5 6 | |
| 1131 | test_gr_a5a5 7 | |
| 1132 | cmp.l #0x00000080, @neg2 | |
| 1133 | beq .Lulabs32n2 | |
| 1134 | fail | |
| 1135 | .Lulabs32n2: | |
| 1136 | ;;; Note: leave the value as 0x00000080, like it started out. | |
| 1137 | ||
| 1138 | .endif | |
| 1139 | ||
| 1140 | pass | |
| 1141 | ||
| 1142 | exit 0 | |
| 1143 | ||
| 1144 | ||
| 1145 | ||
| 1146 |