projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 5fe8b0df MS |
1 | # Hitachi H8 testcase 'jmp' |
| 2 | # mach(): all | |
| 3 | # as(h8300): --defsym sim_cpu=0 | |
| 4 | # as(h8300h): --defsym sim_cpu=1 | |
| 5 | # as(h8300s): --defsym sim_cpu=2 | |
| 6 | # as(h8sx): --defsym sim_cpu=3 | |
| 7 | # ld(h8300h): -m h8300helf | |
| 8 | # ld(h8300s): -m h8300self | |
| 9 | # ld(h8sx): -m h8300sxelf | |
| 10 | ||
| 11 | .include "testutils.inc" | |
| 12 | ||
| 3df3a316 MS |
13 | .data |
| 14 | vector_area: | |
| 15 | .fill 0x400, 1, 0 | |
| 16 | ||
| 5fe8b0df MS |
17 | start |
| 18 | ||
| 3df3a316 | 19 | .if (sim_cpu == h8sx) |
| 5fe8b0df MS |
20 | jmp_8: |
| 21 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 3df3a316 | 22 | mov.l #.Ltgt_8:32, @0x20 |
| 5fe8b0df | 23 | set_ccr_zero |
| 3df3a316 MS |
24 | ;; jmp @@aa:8 ; 8-bit displacement |
| 25 | jmp @@0x20 | |
| 5fe8b0df MS |
26 | fail |
| 27 | ||
| 28 | .Ltgt_8: | |
| 29 | test_cc_clear | |
| 30 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 31 | test_gr_a5a5 1 | |
| 32 | test_gr_a5a5 2 | |
| 33 | test_gr_a5a5 3 | |
| 34 | test_gr_a5a5 4 | |
| 35 | test_gr_a5a5 5 | |
| 36 | test_gr_a5a5 6 | |
| 37 | test_gr_a5a5 7 | |
| 3df3a316 MS |
38 | |
| 39 | jmp_7: ; vector jump | |
| 40 | mov.l #vector_area, er0 | |
| 41 | ldc.l er0, vbr | |
| 42 | set_grs_a5a5 | |
| 43 | mov.l #.Ltgt_7:32, @vector_area+0x300 | |
| 44 | set_ccr_zero | |
| 45 | ||
| 46 | jmp @@0x300 | |
| 47 | fail | |
| 48 | .Ltgt_7: | |
| 49 | test_cc_clear | |
| 50 | test_grs_a5a5 | |
| 51 | stc.l vbr, er0 | |
| 52 | test_h_gr32 vector_area, er0 | |
| 53 | ||
| 54 | .endif ; h8sx | |
| 5fe8b0df MS |
55 | |
| 56 | jmp_24: | |
| 57 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 58 | set_ccr_zero | |
| 59 | ||
| 60 | ;; jmp @aa:24 ; 24-bit address | |
| 61 | jmp @.Ltgt_24:24 | |
| 62 | fail | |
| 63 | ||
| 64 | .Ltgt_24: | |
| 65 | test_cc_clear | |
| 66 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 67 | test_gr_a5a5 1 | |
| 68 | test_gr_a5a5 2 | |
| 69 | test_gr_a5a5 3 | |
| 70 | test_gr_a5a5 4 | |
| 71 | test_gr_a5a5 5 | |
| 72 | test_gr_a5a5 6 | |
| 73 | test_gr_a5a5 7 | |
| 74 | ||
| 3df3a316 | 75 | .if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx |
| 5fe8b0df MS |
76 | jmp_reg: |
| 77 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 78 | set_ccr_zero | |
| 79 | ||
| 80 | ;; jmp @ern ; register indirect | |
| 81 | mov.l #.Ltgt_reg, er5 | |
| 82 | jmp @er5 | |
| 83 | fail | |
| 84 | ||
| 85 | .Ltgt_reg: | |
| 86 | test_cc_clear | |
| 87 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 88 | test_gr_a5a5 1 | |
| 89 | test_gr_a5a5 2 | |
| 90 | test_gr_a5a5 3 | |
| 91 | test_gr_a5a5 4 | |
| 92 | test_h_gr32 .Ltgt_reg er5 | |
| 93 | test_gr_a5a5 6 | |
| 94 | test_gr_a5a5 7 | |
| 3df3a316 | 95 | .endif ; not h8300 |
| 5fe8b0df MS |
96 | |
| 97 | .if (sim_cpu == h8sx) | |
| 98 | jmp_32: | |
| 99 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 100 | set_ccr_zero | |
| 101 | ||
| 102 | ;; jmp @aa:32 ; 32-bit address | |
| 103 | ; jmp @.Ltgt_32:32 ; NOTE: hard-coded to avoid relaxing | |
| 104 | .word 0x5908 | |
| 105 | .long .Ltgt_32 | |
| 106 | fail | |
| 107 | ||
| 108 | .Ltgt_32: | |
| 109 | test_cc_clear | |
| 110 | test_gr_a5a5 0 ; Make sure other general regs not disturbed | |
| 111 | test_gr_a5a5 1 | |
| 112 | test_gr_a5a5 2 | |
| 113 | test_gr_a5a5 3 | |
| 114 | test_gr_a5a5 4 | |
| 115 | test_gr_a5a5 5 | |
| 116 | test_gr_a5a5 6 | |
| 117 | test_gr_a5a5 7 | |
| 3df3a316 | 118 | .endif ; h8sx |
| 5fe8b0df MS |
119 | |
| 120 | pass | |
| 121 | exit 0 | |
| 122 | ||
| 123 |