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[thirdparty/binutils-gdb.git] / sim / tic80 / ChangeLog
CommitLineData
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1Thu Sep 4 10:48:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2
3 * sim-calls.c (sim_open): Use sim_do_command to add memory, only
4 add memory if none already present.
5 (sim_open): Move init of registers from here.
6 (sim_create_inferior): To here. Init modules.
7
8 * Makefile.in (SIM_OBJS): Add sim-memopt.o module.
9
10 * sim-calls.c (sim_open): Add zero modulo arg to sim_core_attach.
11
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12Mon Sep 1 11:06:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
13
14 * sim-calls.c (sim_open): Use sim_state_alloc
15 (simulation): Delete.
16
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17Sat Aug 30 09:40:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
18
19 * insns (do_trap): Unsigned `i' for unsigned iterator.
20 (do_trap): Ditto for comparison with getpid.
21
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22Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
23
24 * configure: Regenerated to track ../common/aclocal.m4 changes.
25 * config.in: Ditto.
26
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27Wed Aug 27 13:41:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
28
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29 * insns (do_st): Use U8_4 instead of V4_L8.
30
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31 * sim-calls.c (sim_open): Add call to sim_analyze_program, update
32 call to sim_config.
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33
34 * sim-calls.c (sim_kill): Delete.
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35 (sim_create_inferior): Add ABFD argument. Initialize PC from ABFD
36 and not SD.
37 (sim_load): Delete, use sim-hload.c.
38
39 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
7230ff0f 40
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41Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
42
43 * configure: Regenerated to track ../common/aclocal.m4 changes.
44 * config.in: Ditto.
45
46Mon Aug 25 16:33:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
47
48 * sim-calls.c (sim_open): Add ABFD argument.
49 (sim_open): Move sim_config call to just after argument
50 parsing. Check return status.
51
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52Fri Aug 8 21:52:27 1997 Mark Alexander <marka@cygnus.com>
53
54 * sim-calls.c (sim_store_register): Allow accumulators
55 other than A0 to be modified. Correct error message.
56
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57Thu May 29 14:02:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
58
59 * misc.c (tic80_trace_fpu3, tic80_trace_fpu2, tic80_trace_fpu1,
60 tic80_trace_fpu2i): Pass in function prefix.
61 (tic80_trace_ldst): Rewrite so it calls print_one_insn directly.
62
63 * Makefile.in (SIM_OBJS): Include sim-watch.o module.
64
65 * sim-main.h (WITH_WATCHPOINTS): Enable watchpoints.
66
67 * ic (bitnum): Compute bitnum from BITNUM.
68 * insn (bbo, bbz): Use.
69
70 * insn: Convert long immediate instructions to igen long immediate
71 form.
72 * insn: Add disasembler information.
73
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74Thu May 29 12:09:13 1997 Andrew Cagney <cagney@b2.cygnus.com>
75
76 * alu.h (IMEM_IMMED): New macro, fetch 32bit immediate operand N.
77
78 * insns (subu i): Immediate is signed not unsigned.
79
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80Tue May 27 13:22:13 1997 Andrew Cagney <cagney@b1.cygnus.com>
81
82 * sim-calls.c (sim_read): Pass NULL cpu to sim_core_read_buffer.
83 (sim_write): Ditto for write.
84
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85Tue May 20 09:33:31 1997 Andrew Cagney <cagney@b1.cygnus.com>
86
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87 * sim-calls.c (sim_load): Set STATE_LOADED_P.
88
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89 * sim-main.h: Include <unistd.h>.
90
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91 * sim-calls.c (sim_set_callback): Delete.
92 (sim_open): Add/install callback argument.
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93 (sim_size): Delete.
94
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95Mon May 19 18:59:33 1997 Mike Meissner <meissner@cygnus.com>
96
97 * configure.in: Check for getpid, kill functions.
98 * config{.in,ure}: Regenerate.
99
100 * insns (do_trap): Add support for kill, getpid system calls.
101
102 * sim-main.h (errno.h): Include.
103 (getpid,kill): Define as NOPs if the host doesn't have them.
104
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105Mon May 19 14:58:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
106
107 * sim-calls.c (sim_open): Set the simulator base magic number.
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108 (sim_load): Delete prototype of sim_load_file.
109 (sim_open): Define sd to be &simulation.
fd76456b 110
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111Fri May 16 14:35:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
112
113 * insns (illegal, fp_unavailable): Halt instead of abort the
114 simulator.
115
116 * insns: Replace calls to engine_error with sim_engine_abort.
117 Ditto for engine_halt V sim_engine_halt.
118
119Tue May 13 15:24:12 1997 Andrew Cagney <cagney@b2.cygnus.com>
120
121 * interp.c (engine_run_until_stop): Delete. Moved to common.
122 (engine_step): Ditto.
123 (engine_step): Ditto.
124 (engine_halt): Ditto.
125 (engine_restart): Ditto.
126 (engine_halt): Ditto.
127 (engine_error): Ditto.
128
129 * sim-calls.c (sim_stop): Delete. Moved to common.
130 (sim_stop_reason): Ditto.
131 (sim_resume): Ditto.
132
133 * Makefile.in (SIM_OBJS): Link in generic sim-engine, sim-run,
134 sim-resume, sim-reason, sim-stop modules.
135
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136Fri May 16 11:57:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
137
138 * ic (compute): Drop check for REG == 0, now always forced to
139 zero.
140
141 * cpu.h (GPR_SET): New macro update the gpr.
142 * insns (do_add): Use GPR_SET to update the GPR register.
143
144 * sim-calls.c (sim_fetch_register): Pretend that r0 is zero.
145
146 * Makefile.in (tmp-igen): Specify zero-r0 so that every
147 instruction clears r0.
148
149 * interp.c (engine_run_until_stop): Igen now generates code to
150 clear r0.
151 (engine_step): Ditto.
152
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153Thu May 15 11:45:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
154
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155 * insns (do_shift): When rot==0 and zero/sign merge treat it as
156 32.
157 (set_fp_reg): For interger conversion, use sim-fpu fpu2i
158 functions.
159 (do_fmpy): Perform iii and uuu using integer arithmetic.
160
161 * Makefile.in (ENGINE_H): Assume everything depends on the fpu.
162
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163 * insns (get_fp_reg): Use sim_fpu_u32to to perform unsigned
164 conversion.
165 (do_fcmp): Update to use new fp compare functions. Make reg nr arg
166 instead of reg. Stops fp overflow.
167 (get_fp_reg): Assume val is valid when reg == 0.
168 (set_fp_reg): Fix double conversion.
169
170 * misc.c (tic80_trace_fpu1): New function, trace simple fp op.
171
172 * insns (do_frnd): Add tracing.
173
174 * cpu.h (TRACE_FPU1): Ditto.
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175
176 * insns (do_trap): Printf formatting.
177
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178Wed May 14 18:05:50 1997 Mike Meissner <meissner@cygnus.com>
179
180 * misc.c (tic80_trace_fpu{3,2,2i}): Align columns with other
181 insns. Use %g to print floating point instead of %f in case the
182 numbers are real large.
183
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184Tue May 13 18:00:10 1997 Mike Meissner <meissner@cygnus.com>
185
186 * insns (do_trap): For system calls that are defined, but not
187 provided return EINVAL. Temporarily add traps 74-79 to just print
188 the register state.
189
190 * interp.c (engine_{run_until_stop,step}): Before executing
191 instructions, make sure r0 == 0.
192
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193Tue May 13 16:39:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
194
195 * alu.h (IMEM): Take full cia not just IP as argument.
196
197 * interp.c (engine_run_until_stop): Delete handling of annuled
198 instructions.
199 (engine_step): Ditto.
200
201 * insn (do_branch): New function.
202 (do_bbo, do_bbz, do_bcnd, do_bsr, do_jsr): Use do_branch to handle
203 annuled branches.
204
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205Mon May 12 17:15:52 1997 Mike Meissner <meissner@cygnus.com>
206
207 * insns (do_{ld,st}): Fix tracing for ld/st.
208
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209Mon May 12 11:12:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
210
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211 * sim-calls.c (sim_stop_reason): Restore keep_running after a
212 CNTRL-C, don't re-clear it.
213
214 * interp.c (engine_error): stop rather than signal with SIGABRT
215 when an error.
216
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217 * insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
218 rDest + 1. Also done by Michael Meissner <meissner@cygnus.com>
219 (do_st): Converse for store.
220
221 * misc.c (tic80_trace_fpu2i): Correct printf format for int type.
222
223Sun May 11 11:02:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
224
225 * sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
226 was cleared.
227
228 * interp.c (engine_step): New function. Single step the simulator
229 taking care of cntrl-c during a step.
230
231 * sim-calls.c (sim_resume): Differentiate between stepping and
232 running so that a cntrl-c during a step is reported.
233
234Sun May 11 10:54:31 1997 Mark Alexander <marka@cygnus.com>
235
236 * sim-calls.c (sim_fetch_register): Use correct reg base.
237 (sim_store_register): Ditto.
238
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239Sun May 11 10:25:14 1997 Michael Meissner <meissner@cygnus.com>
240
241 * cpu.h (tic80_trace_shift): Add declaration.
242 (TRACE_SHIFT): New macro to trace shift instructions.
243
244 * misc.c (tic80_trace_alu2): Align spacing.
245 (tic80_trace_shift): New function to trace shifts.
246
247 * insns (lmo): Add missing 0b prefix to bits.
248 (do_shift): Use ~ (unsigned32)0, instead of -1. Use TRACE_SHIFT
249 instead of TRACE_ALU2.
250 (sl r): Use EndMask as is, instead of using Source+1 register.
251 (subu): Operands are unsigned, not signed.
8ad60788 252 (do_{ld,st}): Fix endian problems with ld.d/st.d.
450be234 253
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254Sat May 10 12:35:47 1997 Michael Meissner <meissner@cygnus.com>
255
256 * insns (and{.tt,.tf,.ft,.ff}): Immediate values are unsigned, not
257 signed.
258
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259Fri May 9 15:47:36 1997 Mike Meissner <meissner@cygnus.com>
260
261 * insns (cmp_vals,do_cmp): Produce the correct bits as specified
262 by the architecture.
89d1a478 263 (xor): Fix xor immediate patterns to use the correct bits.
aaa7b252 264
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265Fri May 9 09:55:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
266
267 * alu.h (long_immediate): Adjust the CIA delay-pointer as well as
268 the NIA when a 64bit insn.
269
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270Thu May 8 11:57:47 1997 Michael Meissner <meissner@cygnus.com>
271
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272 * insns (jsr,bsr): For non-allulled calls, set r31 so that the
273 return address does not reexecute the instruction in the delay
274 slot.
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275 (bbo,bbz): Complement bit number to reverse the one's complement
276 that the assembler is required to do.
53dcd669 277
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278 * misc.c (tic80_trace_*): Change format slightly to accomidate
279 real large decimal values.
e42224cc 280
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281Thu May 8 14:07:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
282
283 * sim-calls.c (sim_do_command): Implement.
284 (sim_store_register): Fix typo T2H v H2T.
285
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286Wed May 7 11:48:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
287
288 * cpu.h (TRACE_FPU2, TRACE_FPU3, TRACE_FPU2I): Add.
289 * insn: Clean up fpu tracing.
290
291 * sim-calls.c (sim_create_inferior): Start out with interrupts
292 enabled.
293
294 * cpu.h (TRACE_SINK3), misc.c (tic80_trace_sink3): Three argument
295 sink
296
297 * insns (rdcr, swcr, wrcr, brcr, rmo, lmo): Implement.
298
299 * insns (do_*): Remove MY_INDEX/indx argument from support functions,
300 igen now handles this.
301
302 * cpu.h (CR): New macro - access TIc80 control registers.
303
304 * misc.c: New file.
305 (tic80_cr2index): New function, map control register opcode index
306 into the internal CR enum.
307
308 * interp.c
309 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Move from
310 here
311 * misc.c: to here.
312
313 * Makefile.in (SIM_OBJS): Add misc.o.
314
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315Tue May 6 15:22:58 1997 Mike Meissner <meissner@cygnus.com>
316
317 * cpu.h ({,v}{S,D}P_FPR): Delete unused macros that won't work on
318 big endian hosts.
319 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Declare
320 new functions.
321 (TRACE_{ALU{2,3},NOP,SINK{1,2},{,U}COND_BR,LD,ST}): New macros to
322 trace various instruction types.
323
324 * insns: Modify all instructions to support semantic tracing.
325
326 * interp.c (toplevel): Include itable.h.
327 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): New
328 functions to provide semantic level tracing information.
329
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330Mon May 5 11:50:43 1997 Andrew Cagney <cagney@b1.cygnus.com>
331
332 * alu.h: Update usage of core object to reflect recent changes in
333 ../common/sim-*core.
334 * sim-calls.c (sim_open): Ditto.
335
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336Mon May 5 14:10:17 1997 Andrew Cagney <cagney@b1.cygnus.com>
337
338 * insn (cmnd): No-op cache flushes.
339
340 * insns (do_trap): Allow writes to STDERR.
341
342 * Makefile.in (SIM_OBJS): Link in sim-fpu.o.
343 (SIM_EXTRA_LIBS): Link in the math library.
344
345 * alu.h: Add support for floating point unit using sim-alu.
346
347 * insns (fadd, fsub, fmpy, fdiv, fcmp, frnd*): Implement.
348
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349Fri May 2 14:57:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
350
351 * sim-calls.c: Include sim-utils.h and sim-options.h.
352
353 * sim-main.h (sim_state): Drop sim_events and sim_core members,
354 moved to simulator base type.
355
356 * alu.h (IMEM, MEM, STORE): Update track changes in common
357 directory.
358
359 * insns: Drop cia argument from functions, igen now handles this.
360
361 * interp.c (engine_init): Include string.h/strings.h to define
362 memset et.al.
363
364 * sim-main.h (sim_cia): Delcare, tracking common dir changes.
365
366 * cpu.h (sim_cpu): Update instruction_address with sim_cia.
367
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368Wed Apr 30 11:26:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
369
370 * sim-main.h (signal.h): Include so that SIG* available to all
371 callers of sig_halt.
372
373 * insns (do_shift): New function, implement shift operations.
374 (do_trap): Add handler for trap 73 - SIGTRAP.
375
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376Tue Apr 29 10:58:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
377
378 * alu.h (MEM, STORE): Force addresses to be correctly aligned.
379
380 * insns (do_jsr): Fix.
381 (do_st, do_ld): Handle 64bit transfers.
382 (do_trap): Match libgloss.
383 (rdcr): Implement nop - Dest == r0 - variant.
384
385 * sim-calls.c (sim_create_inferior): Initialize SP.
386
387 * Makefile.in (ENGINE_H): Everything now depends on sim-options.h.
388 (support.o): Depends on ENGINE_H.
389
390 * cpu.h: Four accumulators.
391
392 * Makefile.in (tmp-igen): Include line number information in
393 generated files.
394
395 * insns (dld, dst): Fill in.
396
397Mon Apr 28 13:02:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
398
399 * insns (vld): Fix instruction format wrong.
400
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401Thu Apr 24 16:43:09 1997 Andrew Cagney <cagney@b1.cygnus.com>
402
403 * dc: Add additional rules so that minor opcode files are
404 detected.
405 * insns: Enable more instructions.
406
407 * sim-calls.c (sim_fetch_register,sim_store_register, sim_write):
408 Implement.
409
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410Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
411
412 * configure: Regenerated to track ../common/aclocal.m4 changes.
413 * Makefile.in (SIM_OBJS): Add sim-module.o, sim-profile.o.
414 * sim-calls.c (sim_open): Call sim_module_uninstall if argument
415 parsing fails. Call sim_post_argv_init.
416 (sim_close): Call sim_module_uninstall.
417
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418Wed Apr 23 20:05:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
419
420 * insns (and, bbo, bcnd, bsr, dcache, jsr, or, xor, nor): Enable.
421 * ic: Add fields for enabled instructions.
422