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Commit | Line | Data |
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c906108c SS |
1 | #include "sim-main.h" |
2 | #include "sim-options.h" | |
3 | #include "v850_sim.h" | |
4 | #include "sim-assert.h" | |
5 | #include "itable.h" | |
6 | ||
c906108c | 7 | #include <stdlib.h> |
c906108c | 8 | #include <string.h> |
c906108c SS |
9 | |
10 | #include "bfd.h" | |
11 | ||
c906108c SS |
12 | static const char * get_insn_name (sim_cpu *, int); |
13 | ||
a3976a7c | 14 | /* For compatibility. */ |
c906108c SS |
15 | SIM_DESC simulator; |
16 | ||
a3976a7c | 17 | /* V850 interrupt model. */ |
c906108c SS |
18 | |
19 | enum interrupt_type | |
20 | { | |
21 | int_reset, | |
22 | int_nmi, | |
23 | int_intov1, | |
24 | int_intp10, | |
25 | int_intp11, | |
26 | int_intp12, | |
27 | int_intp13, | |
28 | int_intcm4, | |
29 | num_int_types | |
30 | }; | |
31 | ||
a3976a7c NC |
32 | const char *interrupt_names[] = |
33 | { | |
c906108c SS |
34 | "reset", |
35 | "nmi", | |
36 | "intov1", | |
37 | "intp10", | |
38 | "intp11", | |
39 | "intp12", | |
40 | "intp13", | |
41 | "intcm4", | |
42 | NULL | |
43 | }; | |
44 | ||
45 | static void | |
a3976a7c | 46 | do_interrupt (SIM_DESC sd, void *data) |
c906108c | 47 | { |
4e9586f0 | 48 | const char **interrupt_name = (const char**)data; |
c906108c SS |
49 | enum interrupt_type inttype; |
50 | inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names); | |
51 | ||
52 | /* For a hardware reset, drop everything and jump to the start | |
53 | address */ | |
54 | if (inttype == int_reset) | |
55 | { | |
56 | PC = 0; | |
57 | PSW = 0x20; | |
58 | ECR = 0; | |
59 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); | |
60 | } | |
61 | ||
62 | /* Deliver an NMI when allowed */ | |
63 | if (inttype == int_nmi) | |
64 | { | |
65 | if (PSW & PSW_NP) | |
66 | { | |
67 | /* We're already working on an NMI, so this one must wait | |
68 | around until the previous one is done. The processor | |
69 | ignores subsequent NMIs, so we don't need to count them. | |
70 | Just keep re-scheduling a single NMI until it manages to | |
71 | be delivered */ | |
72 | if (STATE_CPU (sd, 0)->pending_nmi != NULL) | |
73 | sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi); | |
74 | STATE_CPU (sd, 0)->pending_nmi = | |
75 | sim_events_schedule (sd, 1, do_interrupt, data); | |
76 | return; | |
77 | } | |
78 | else | |
79 | { | |
80 | /* NMI can be delivered. Do not deschedule pending_nmi as | |
81 | that, if still in the event queue, is a second NMI that | |
82 | needs to be delivered later. */ | |
83 | FEPC = PC; | |
84 | FEPSW = PSW; | |
85 | /* Set the FECC part of the ECR. */ | |
86 | ECR &= 0x0000ffff; | |
87 | ECR |= 0x10; | |
88 | PSW |= PSW_NP; | |
89 | PSW &= ~PSW_EP; | |
90 | PSW |= PSW_ID; | |
91 | PC = 0x10; | |
92 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); | |
93 | } | |
94 | } | |
95 | ||
96 | /* deliver maskable interrupt when allowed */ | |
97 | if (inttype > int_nmi && inttype < num_int_types) | |
98 | { | |
99 | if ((PSW & PSW_NP) || (PSW & PSW_ID)) | |
100 | { | |
101 | /* Can't deliver this interrupt, reschedule it for later */ | |
102 | sim_events_schedule (sd, 1, do_interrupt, data); | |
103 | return; | |
104 | } | |
105 | else | |
106 | { | |
107 | /* save context */ | |
108 | EIPC = PC; | |
109 | EIPSW = PSW; | |
110 | /* Disable further interrupts. */ | |
111 | PSW |= PSW_ID; | |
112 | /* Indicate that we're doing interrupt not exception processing. */ | |
113 | PSW &= ~PSW_EP; | |
114 | /* Clear the EICC part of the ECR, will set below. */ | |
115 | ECR &= 0xffff0000; | |
116 | switch (inttype) | |
117 | { | |
118 | case int_intov1: | |
119 | PC = 0x80; | |
120 | ECR |= 0x80; | |
121 | break; | |
122 | case int_intp10: | |
123 | PC = 0x90; | |
124 | ECR |= 0x90; | |
125 | break; | |
126 | case int_intp11: | |
127 | PC = 0xa0; | |
128 | ECR |= 0xa0; | |
129 | break; | |
130 | case int_intp12: | |
131 | PC = 0xb0; | |
132 | ECR |= 0xb0; | |
133 | break; | |
134 | case int_intp13: | |
135 | PC = 0xc0; | |
136 | ECR |= 0xc0; | |
137 | break; | |
138 | case int_intcm4: | |
139 | PC = 0xd0; | |
140 | ECR |= 0xd0; | |
141 | break; | |
142 | default: | |
143 | /* Should never be possible. */ | |
144 | sim_engine_abort (sd, NULL, NULL_CIA, | |
145 | "do_interrupt - internal error - bad switch"); | |
146 | break; | |
147 | } | |
148 | } | |
149 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); | |
150 | } | |
151 | ||
152 | /* some other interrupt? */ | |
153 | sim_engine_abort (sd, NULL, NULL_CIA, | |
154 | "do_interrupt - internal error - interrupt %d unknown", | |
155 | inttype); | |
156 | } | |
157 | ||
158 | /* Return name of an insn, used by insn profiling. */ | |
159 | ||
160 | static const char * | |
161 | get_insn_name (sim_cpu *cpu, int i) | |
162 | { | |
163 | return itable[i].name; | |
164 | } | |
165 | ||
166 | /* These default values correspond to expected usage for the chip. */ | |
167 | ||
168 | uint32 OP[4]; | |
169 | ||
14c9ad2e MF |
170 | static sim_cia |
171 | v850_pc_get (sim_cpu *cpu) | |
172 | { | |
173 | return PC; | |
174 | } | |
175 | ||
176 | static void | |
177 | v850_pc_set (sim_cpu *cpu, sim_cia pc) | |
178 | { | |
179 | PC = pc; | |
180 | } | |
c906108c | 181 | |
e1211e55 MF |
182 | static int v850_reg_fetch (SIM_CPU *, int, unsigned char *, int); |
183 | static int v850_reg_store (SIM_CPU *, int, unsigned char *, int); | |
184 | ||
c906108c | 185 | SIM_DESC |
a3976a7c NC |
186 | sim_open (SIM_OPEN_KIND kind, |
187 | host_callback * cb, | |
188 | struct bfd * abfd, | |
2e3d4f4d | 189 | char * const * argv) |
c906108c | 190 | { |
14c9ad2e | 191 | int i; |
c906108c SS |
192 | SIM_DESC sd = sim_state_alloc (kind, cb); |
193 | int mach; | |
194 | ||
195 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
196 | ||
14c9ad2e MF |
197 | /* The cpu data is kept in a separately allocated chunk of memory. */ |
198 | if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) | |
199 | return 0; | |
200 | ||
c906108c SS |
201 | /* for compatibility */ |
202 | simulator = sd; | |
203 | ||
204 | /* FIXME: should be better way of setting up interrupts */ | |
205 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
206 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
207 | STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt; | |
208 | STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names; | |
209 | ||
210 | /* Initialize the mechanism for doing insn profiling. */ | |
211 | CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name; | |
212 | CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries; | |
213 | ||
214 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
215 | return 0; | |
216 | ||
217 | /* Allocate core managed memory */ | |
218 | ||
219 | /* "Mirror" the ROM addresses below 1MB. */ | |
220 | sim_do_commandf (sd, "memory region 0,0x100000,0x%lx", V850_ROM_SIZE); | |
221 | /* Chunk of ram adjacent to rom */ | |
222 | sim_do_commandf (sd, "memory region 0x100000,0x%lx", V850_LOW_END-0x100000); | |
223 | /* peripheral I/O region - mirror 1K across 4k (0x1000) */ | |
224 | sim_do_command (sd, "memory region 0xfff000,0x1000,1024"); | |
225 | /* similarly if in the internal RAM region */ | |
226 | sim_do_command (sd, "memory region 0xffe000,0x1000,1024"); | |
227 | ||
77cf2ef5 | 228 | /* The parser will print an error message for us, so we silently return. */ |
c906108c SS |
229 | if (sim_parse_args (sd, argv) != SIM_RC_OK) |
230 | { | |
231 | /* Uninstall the modules to avoid memory leaks, | |
232 | file descriptor leaks, etc. */ | |
233 | sim_module_uninstall (sd); | |
234 | return 0; | |
235 | } | |
236 | ||
237 | /* check for/establish the a reference program image */ | |
238 | if (sim_analyze_program (sd, | |
239 | (STATE_PROG_ARGV (sd) != NULL | |
240 | ? *STATE_PROG_ARGV (sd) | |
241 | : NULL), | |
242 | abfd) != SIM_RC_OK) | |
243 | { | |
244 | sim_module_uninstall (sd); | |
245 | return 0; | |
246 | } | |
247 | ||
248 | /* establish any remaining configuration options */ | |
249 | if (sim_config (sd) != SIM_RC_OK) | |
250 | { | |
251 | sim_module_uninstall (sd); | |
252 | return 0; | |
253 | } | |
254 | ||
255 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
256 | { | |
257 | /* Uninstall the modules to avoid memory leaks, | |
258 | file descriptor leaks, etc. */ | |
259 | sim_module_uninstall (sd); | |
260 | return 0; | |
261 | } | |
262 | ||
263 | ||
264 | /* determine the machine type */ | |
265 | if (STATE_ARCHITECTURE (sd) != NULL | |
85367826 NC |
266 | && (STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850 |
267 | || STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850_rh850)) | |
c906108c SS |
268 | mach = STATE_ARCHITECTURE (sd)->mach; |
269 | else | |
270 | mach = bfd_mach_v850; /* default */ | |
271 | ||
272 | /* set machine specific configuration */ | |
273 | switch (mach) | |
274 | { | |
275 | case bfd_mach_v850: | |
276 | case bfd_mach_v850e: | |
c5ea1d53 | 277 | case bfd_mach_v850e1: |
85367826 NC |
278 | case bfd_mach_v850e2: |
279 | case bfd_mach_v850e2v3: | |
67d7515b | 280 | case bfd_mach_v850e3v5: |
c906108c SS |
281 | STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT |
282 | | PSW_CY | PSW_OV | PSW_S | PSW_Z); | |
283 | break; | |
c906108c SS |
284 | } |
285 | ||
14c9ad2e MF |
286 | /* CPU specific initialization. */ |
287 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
288 | { | |
289 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
290 | ||
e1211e55 MF |
291 | CPU_REG_FETCH (cpu) = v850_reg_fetch; |
292 | CPU_REG_STORE (cpu) = v850_reg_store; | |
14c9ad2e MF |
293 | CPU_PC_FETCH (cpu) = v850_pc_get; |
294 | CPU_PC_STORE (cpu) = v850_pc_set; | |
295 | } | |
296 | ||
c906108c SS |
297 | return sd; |
298 | } | |
299 | ||
c906108c | 300 | SIM_RC |
a3976a7c NC |
301 | sim_create_inferior (SIM_DESC sd, |
302 | struct bfd * prog_bfd, | |
2e3d4f4d MF |
303 | char * const *argv, |
304 | char * const *env) | |
c906108c SS |
305 | { |
306 | memset (&State, 0, sizeof (State)); | |
307 | if (prog_bfd != NULL) | |
308 | PC = bfd_get_start_address (prog_bfd); | |
c906108c SS |
309 | return SIM_RC_OK; |
310 | } | |
311 | ||
e1211e55 MF |
312 | static int |
313 | v850_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) | |
c906108c SS |
314 | { |
315 | *(unsigned32*)memory = H2T_4 (State.regs[rn]); | |
316 | return -1; | |
317 | } | |
e1211e55 MF |
318 | |
319 | static int | |
320 | v850_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) | |
c906108c | 321 | { |
a3976a7c | 322 | State.regs[rn] = T2H_4 (*(unsigned32 *) memory); |
dae477fe | 323 | return length; |
c906108c | 324 | } |