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1 | #include "sim-basics.h" |
2 | ||
3 | typedef address_word sim_cia; | |
4 | ||
5 | /* This simulator doesn't cache state */ | |
6 | #define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0) | |
7 | #define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0) | |
8 | ||
9 | #include "sim-base.h" | |
10 | ||
11 | typedef signed8 int8; | |
12 | typedef unsigned8 uint8; | |
13 | typedef signed16 int16; | |
14 | typedef unsigned16 uint16; | |
15 | typedef signed32 int32; | |
16 | typedef unsigned32 uint32; | |
17 | typedef unsigned32 reg_t; | |
18 | ||
19 | ||
20 | /* The current state of the processor; registers, memory, etc. */ | |
21 | ||
22 | typedef struct _v850_regs { | |
23 | reg_t regs[32]; /* general-purpose registers */ | |
24 | reg_t sregs[32]; /* system registers, including psw */ | |
25 | reg_t pc; | |
26 | int dummy_mem; /* where invalid accesses go */ | |
27 | int exception; | |
28 | int pending_nmi; | |
29 | } v850_regs; | |
30 | ||
31 | struct _sim_cpu | |
32 | { | |
33 | /* ... simulator specific members ... */ | |
34 | v850_regs reg; | |
35 | /* ... base type ... */ | |
36 | sim_cpu_base base; | |
37 | }; | |
38 | ||
39 | struct sim_state { | |
40 | sim_cpu cpu[MAX_NR_PROCESSORS]; | |
41 | #if (WITH_SMP) | |
42 | #define STATE_CPU(sd,n) (&(sd)->cpu[n]) | |
43 | #else | |
44 | #define STATE_CPU(sd,n) (&(sd)->cpu[0]) | |
45 | #endif | |
46 | SIM_ADDR rom_size; | |
47 | SIM_ADDR low_end; | |
48 | SIM_ADDR high_start; | |
49 | SIM_ADDR high_base; | |
b5e935ae | 50 | void *mem; |
cabedd58 AC |
51 | sim_state_base base; |
52 | }; | |
53 | ||
54 | /* For compatibility, until all functions converted to passing | |
55 | SIM_DESC as an argument */ | |
56 | extern SIM_DESC simulator; | |
57 | ||
58 | ||
59 | #define V850_ROM_SIZE 0x8000 | |
60 | #define V850_LOW_END 0x200000 | |
61 | #define V850_HIGH_START 0xffe000 | |
62 | ||
63 | ||
64 | #define DEBUG_TRACE 0x00000001 | |
65 | #define DEBUG_VALUES 0x00000002 | |
66 | ||
67 | extern int v850_debug; | |
68 | ||
69 | #define SIG_V850_EXIT -1 /* indication of a normal exit */ | |
70 | ||
71 | extern uint32 OP[4]; | |
72 | extern struct simops Simops[]; | |
73 | ||
74 | #define State (STATE_CPU (simulator, 0)->reg) | |
75 | #define PC (State.pc) | |
76 | #define SP (State.regs[3]) | |
77 | #define EP (State.regs[30]) | |
78 | ||
79 | #define EIPC (State.sregs[0]) | |
80 | #define EIPSW (State.sregs[1]) | |
81 | #define FEPC (State.sregs[2]) | |
82 | #define FEPSW (State.sregs[3]) | |
83 | #define ECR (State.sregs[4]) | |
84 | #define PSW (State.sregs[5]) | |
85 | /* start-sanitize-v850e */ | |
86 | #define CTPC (State.sregs[16]) | |
87 | #define CTPSW (State.sregs[17]) | |
88 | /* end-sanitize-v850e */ | |
89 | #define DBPC (State.sregs[18]) | |
90 | #define DBPSW (State.sregs[19]) | |
91 | /* start-sanitize-v850e */ | |
92 | #define CTBP (State.sregs[20]) | |
93 | /* end-sanitize-v850e */ | |
94 | ||
95 | #define PSW_NP 0x80 | |
96 | #define PSW_EP 0x40 | |
97 | #define PSW_ID 0x20 | |
98 | #define PSW_SAT 0x10 | |
99 | #define PSW_CY 0x8 | |
100 | #define PSW_OV 0x4 | |
101 | #define PSW_S 0x2 | |
102 | #define PSW_Z 0x1 | |
103 | ||
104 | #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4) | |
105 | ||
106 | /* sign-extend a 4-bit number */ | |
107 | #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8) | |
108 | ||
109 | /* sign-extend a 5-bit number */ | |
110 | #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10) | |
111 | ||
112 | /* sign-extend an 8-bit number */ | |
113 | #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80) | |
114 | ||
115 | /* sign-extend a 9-bit number */ | |
116 | #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100) | |
117 | ||
118 | /* sign-extend a 16-bit number */ | |
119 | #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000) | |
120 | ||
121 | /* sign-extend a 22-bit number */ | |
122 | #define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000) | |
123 | ||
124 | /* sign-extend a 32-bit number */ | |
125 | #define SEXT32(x) ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL) | |
126 | ||
127 | /* sign extend a 40 bit number */ | |
128 | #define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL) | |
129 | ||
130 | /* sign extend a 44 bit number */ | |
131 | #define SEXT44(x) ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL) | |
132 | ||
133 | /* sign extend a 60 bit number */ | |
134 | #define SEXT60(x) ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL) | |
135 | ||
136 | /* No sign extension */ | |
137 | #define NOP(x) (x) | |
138 | ||
139 | #if 0 | |
140 | #define MAX32 0x7fffffffLL | |
141 | #define MIN32 0xff80000000LL | |
142 | #define MASK32 0xffffffffLL | |
143 | #define MASK40 0xffffffffffLL | |
144 | #endif | |
145 | ||
146 | #define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i)) | |
147 | ||
148 | #define RLW(x) load_mem (x, 4) | |
149 | ||
150 | #ifdef _WIN32 | |
151 | #ifndef SIGTRAP | |
152 | #define SIGTRAP 5 | |
153 | #endif | |
154 | #ifndef SIGQUIT | |
155 | #define SIGQUIT 3 | |
156 | #endif | |
157 | #endif | |
158 | ||
159 | /* Function declarations. */ | |
160 | ||
161 | uint32 get_word PARAMS ((uint8 *)); | |
162 | uint16 get_half PARAMS ((uint8 *)); | |
163 | uint8 get_byte PARAMS ((uint8 *)); | |
164 | void put_word PARAMS ((uint8 *, uint32)); | |
165 | void put_half PARAMS ((uint8 *, uint16)); | |
166 | void put_byte PARAMS ((uint8 *, uint8)); | |
167 | ||
168 | extern uint32 load_mem PARAMS ((SIM_ADDR addr, int len)); | |
169 | extern void store_mem PARAMS ((SIM_ADDR addr, int len, uint32 data)); | |
170 | ||
171 | extern uint8 *map PARAMS ((SIM_ADDR addr)); |