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Commit | Line | Data |
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6df01ab8 MF |
1 | /* This must come before any other includes. */ |
2 | #include "defs.h" | |
3 | ||
c906108c SS |
4 | #include "sim-main.h" |
5 | #include "v850_sim.h" | |
6 | #include "simops.h" | |
7 | ||
4389ce38 MK |
8 | #include <sys/types.h> |
9 | ||
c906108c SS |
10 | #ifdef HAVE_UTIME_H |
11 | #include <utime.h> | |
12 | #endif | |
c906108c | 13 | #include <time.h> |
c906108c SS |
14 | #ifdef HAVE_UNISTD_H |
15 | #include <unistd.h> | |
16 | #endif | |
5f05936d | 17 | #include <stdlib.h> |
c906108c | 18 | #include <string.h> |
c906108c SS |
19 | |
20 | #include "targ-vals.h" | |
21 | ||
22 | #include "libiberty.h" | |
23 | ||
24 | #include <errno.h> | |
25 | #if !defined(__GO32__) && !defined(_WIN32) | |
26 | #include <sys/stat.h> | |
27 | #include <sys/times.h> | |
28 | #include <sys/time.h> | |
29 | #endif | |
30 | ||
31 | /* This is an array of the bit positions of registers r20 .. r31 in | |
32 | that order in a prepare/dispose instruction. */ | |
33 | int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 }; | |
34 | /* This is an array of the bit positions of registers r16 .. r31 in | |
35 | that order in a push/pop instruction. */ | |
36 | int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21}; | |
37 | /* This is an array of the bit positions of registers r1 .. r15 in | |
38 | that order in a push/pop instruction. */ | |
39 | int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21}; | |
40 | ||
41 | #ifdef DEBUG | |
42 | #ifndef SIZE_INSTRUCTION | |
43 | #define SIZE_INSTRUCTION 18 | |
44 | #endif | |
45 | ||
46 | #ifndef SIZE_VALUES | |
47 | #define SIZE_VALUES 11 | |
48 | #endif | |
49 | ||
50 | ||
a3976a7c NC |
51 | unsigned32 trace_values[3]; |
52 | int trace_num_values; | |
53 | unsigned32 trace_pc; | |
54 | const char * trace_name; | |
55 | int trace_module; | |
c906108c SS |
56 | |
57 | ||
58 | void | |
a3976a7c | 59 | trace_input (char *name, enum op_types type, int size) |
c906108c | 60 | { |
c906108c SS |
61 | if (!TRACE_ALU_P (STATE_CPU (simulator, 0))) |
62 | return; | |
63 | ||
64 | trace_pc = PC; | |
65 | trace_name = name; | |
66 | trace_module = TRACE_ALU_IDX; | |
67 | ||
68 | switch (type) | |
69 | { | |
70 | default: | |
71 | case OP_UNKNOWN: | |
72 | case OP_NONE: | |
73 | case OP_TRAP: | |
74 | trace_num_values = 0; | |
75 | break; | |
76 | ||
77 | case OP_REG: | |
78 | case OP_REG_REG_MOVE: | |
79 | trace_values[0] = State.regs[OP[0]]; | |
80 | trace_num_values = 1; | |
81 | break; | |
82 | ||
83 | case OP_BIT_CHANGE: | |
84 | case OP_REG_REG: | |
85 | case OP_REG_REG_CMP: | |
86 | trace_values[0] = State.regs[OP[1]]; | |
87 | trace_values[1] = State.regs[OP[0]]; | |
88 | trace_num_values = 2; | |
89 | break; | |
90 | ||
91 | case OP_IMM_REG: | |
92 | case OP_IMM_REG_CMP: | |
93 | trace_values[0] = SEXT5 (OP[0]); | |
94 | trace_values[1] = OP[1]; | |
95 | trace_num_values = 2; | |
96 | break; | |
97 | ||
98 | case OP_IMM_REG_MOVE: | |
99 | trace_values[0] = SEXT5 (OP[0]); | |
100 | trace_num_values = 1; | |
101 | break; | |
102 | ||
103 | case OP_COND_BR: | |
104 | trace_values[0] = State.pc; | |
105 | trace_values[1] = SEXT9 (OP[0]); | |
106 | trace_values[2] = PSW; | |
107 | trace_num_values = 3; | |
108 | break; | |
109 | ||
110 | case OP_LOAD16: | |
111 | trace_values[0] = OP[1] * size; | |
112 | trace_values[1] = State.regs[30]; | |
113 | trace_num_values = 2; | |
114 | break; | |
115 | ||
116 | case OP_STORE16: | |
117 | trace_values[0] = State.regs[OP[0]]; | |
118 | trace_values[1] = OP[1] * size; | |
119 | trace_values[2] = State.regs[30]; | |
120 | trace_num_values = 3; | |
121 | break; | |
122 | ||
123 | case OP_LOAD32: | |
124 | trace_values[0] = EXTEND16 (OP[2]); | |
125 | trace_values[1] = State.regs[OP[0]]; | |
126 | trace_num_values = 2; | |
127 | break; | |
128 | ||
129 | case OP_STORE32: | |
130 | trace_values[0] = State.regs[OP[1]]; | |
131 | trace_values[1] = EXTEND16 (OP[2]); | |
132 | trace_values[2] = State.regs[OP[0]]; | |
133 | trace_num_values = 3; | |
134 | break; | |
135 | ||
136 | case OP_JUMP: | |
137 | trace_values[0] = SEXT22 (OP[0]); | |
138 | trace_values[1] = State.pc; | |
139 | trace_num_values = 2; | |
140 | break; | |
141 | ||
142 | case OP_IMM_REG_REG: | |
143 | trace_values[0] = EXTEND16 (OP[0]) << size; | |
144 | trace_values[1] = State.regs[OP[1]]; | |
145 | trace_num_values = 2; | |
146 | break; | |
147 | ||
148 | case OP_IMM16_REG_REG: | |
149 | trace_values[0] = EXTEND16 (OP[2]) << size; | |
150 | trace_values[1] = State.regs[OP[1]]; | |
151 | trace_num_values = 2; | |
152 | break; | |
153 | ||
154 | case OP_UIMM_REG_REG: | |
155 | trace_values[0] = (OP[0] & 0xffff) << size; | |
156 | trace_values[1] = State.regs[OP[1]]; | |
157 | trace_num_values = 2; | |
158 | break; | |
159 | ||
160 | case OP_UIMM16_REG_REG: | |
161 | trace_values[0] = (OP[2]) << size; | |
162 | trace_values[1] = State.regs[OP[1]]; | |
163 | trace_num_values = 2; | |
164 | break; | |
165 | ||
166 | case OP_BIT: | |
167 | trace_num_values = 0; | |
168 | break; | |
169 | ||
170 | case OP_EX1: | |
171 | trace_values[0] = PSW; | |
172 | trace_num_values = 1; | |
173 | break; | |
174 | ||
175 | case OP_EX2: | |
176 | trace_num_values = 0; | |
177 | break; | |
178 | ||
179 | case OP_LDSR: | |
180 | trace_values[0] = State.regs[OP[0]]; | |
181 | trace_num_values = 1; | |
182 | break; | |
183 | ||
184 | case OP_STSR: | |
185 | trace_values[0] = State.sregs[OP[1]]; | |
186 | trace_num_values = 1; | |
187 | } | |
188 | ||
189 | } | |
190 | ||
191 | void | |
192 | trace_result (int has_result, unsigned32 result) | |
193 | { | |
194 | char buf[1000]; | |
195 | char *chp; | |
196 | ||
197 | buf[0] = '\0'; | |
198 | chp = buf; | |
199 | ||
200 | /* write out the values saved during the trace_input call */ | |
201 | { | |
202 | int i; | |
203 | for (i = 0; i < trace_num_values; i++) | |
204 | { | |
d62274a3 AC |
205 | sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "", |
206 | (long) trace_values[i]); | |
c906108c SS |
207 | chp = strchr (chp, '\0'); |
208 | } | |
209 | while (i++ < 3) | |
210 | { | |
211 | sprintf (chp, "%*s", SIZE_VALUES, ""); | |
212 | chp = strchr (chp, '\0'); | |
213 | } | |
214 | } | |
215 | ||
216 | /* append any result to the end of the buffer */ | |
217 | if (has_result) | |
a3976a7c | 218 | sprintf (chp, " :: 0x%.8lx", (unsigned long) result); |
c906108c | 219 | |
a3976a7c | 220 | trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, "%s", buf); |
c906108c SS |
221 | } |
222 | ||
223 | void | |
a3976a7c | 224 | trace_output (enum op_types result) |
c906108c SS |
225 | { |
226 | if (!TRACE_ALU_P (STATE_CPU (simulator, 0))) | |
227 | return; | |
228 | ||
229 | switch (result) | |
230 | { | |
231 | default: | |
232 | case OP_UNKNOWN: | |
233 | case OP_NONE: | |
234 | case OP_TRAP: | |
235 | case OP_REG: | |
236 | case OP_REG_REG_CMP: | |
237 | case OP_IMM_REG_CMP: | |
238 | case OP_COND_BR: | |
239 | case OP_STORE16: | |
240 | case OP_STORE32: | |
241 | case OP_BIT: | |
242 | case OP_EX2: | |
243 | trace_result (0, 0); | |
244 | break; | |
245 | ||
246 | case OP_LOAD16: | |
247 | case OP_STSR: | |
248 | trace_result (1, State.regs[OP[0]]); | |
249 | break; | |
250 | ||
251 | case OP_REG_REG: | |
252 | case OP_REG_REG_MOVE: | |
253 | case OP_IMM_REG: | |
254 | case OP_IMM_REG_MOVE: | |
255 | case OP_LOAD32: | |
256 | case OP_EX1: | |
257 | trace_result (1, State.regs[OP[1]]); | |
258 | break; | |
259 | ||
260 | case OP_IMM_REG_REG: | |
261 | case OP_UIMM_REG_REG: | |
262 | case OP_IMM16_REG_REG: | |
263 | case OP_UIMM16_REG_REG: | |
264 | trace_result (1, State.regs[OP[1]]); | |
265 | break; | |
266 | ||
267 | case OP_JUMP: | |
268 | if (OP[1] != 0) | |
269 | trace_result (1, State.regs[OP[1]]); | |
270 | else | |
271 | trace_result (0, 0); | |
272 | break; | |
273 | ||
274 | case OP_LDSR: | |
275 | trace_result (1, State.sregs[OP[1]]); | |
276 | break; | |
277 | } | |
278 | } | |
279 | #endif | |
280 | ||
281 | \f | |
282 | /* Returns 1 if the specific condition is met, returns 0 otherwise. */ | |
283 | int | |
284 | condition_met (unsigned code) | |
285 | { | |
286 | unsigned int psw = PSW; | |
287 | ||
288 | switch (code & 0xf) | |
289 | { | |
290 | case 0x0: return ((psw & PSW_OV) != 0); | |
291 | case 0x1: return ((psw & PSW_CY) != 0); | |
292 | case 0x2: return ((psw & PSW_Z) != 0); | |
293 | case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0); | |
294 | case 0x4: return ((psw & PSW_S) != 0); | |
295 | /*case 0x5: return 1;*/ | |
296 | case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0); | |
297 | case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0); | |
298 | case 0x8: return ((psw & PSW_OV) == 0); | |
299 | case 0x9: return ((psw & PSW_CY) == 0); | |
300 | case 0xa: return ((psw & PSW_Z) == 0); | |
301 | case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0); | |
302 | case 0xc: return ((psw & PSW_S) == 0); | |
303 | case 0xd: return ((psw & PSW_SAT) != 0); | |
304 | case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0); | |
305 | case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0); | |
306 | } | |
307 | ||
308 | return 1; | |
309 | } | |
310 | ||
2aaed979 | 311 | unsigned long |
c906108c SS |
312 | Add32 (unsigned long a1, unsigned long a2, int * carry) |
313 | { | |
314 | unsigned long result = (a1 + a2); | |
315 | ||
316 | * carry = (result < a1); | |
317 | ||
318 | return result; | |
319 | } | |
320 | ||
321 | static void | |
0da2b665 | 322 | Multiply64 (int sign, unsigned long op0) |
c906108c SS |
323 | { |
324 | unsigned long op1; | |
325 | unsigned long lo; | |
326 | unsigned long mid1; | |
327 | unsigned long mid2; | |
328 | unsigned long hi; | |
329 | unsigned long RdLo; | |
330 | unsigned long RdHi; | |
331 | int carry; | |
332 | ||
333 | op1 = State.regs[ OP[1] ]; | |
334 | ||
335 | if (sign) | |
336 | { | |
337 | /* Compute sign of result and adjust operands if necessary. */ | |
338 | ||
339 | sign = (op0 ^ op1) & 0x80000000; | |
340 | ||
341 | if (((signed long) op0) < 0) | |
342 | op0 = - op0; | |
343 | ||
344 | if (((signed long) op1) < 0) | |
345 | op1 = - op1; | |
346 | } | |
347 | ||
348 | /* We can split the 32x32 into four 16x16 operations. This ensures | |
349 | that we do not lose precision on 32bit only hosts: */ | |
350 | lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF)); | |
351 | mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
352 | mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF)); | |
353 | hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); | |
354 | ||
355 | /* We now need to add all of these results together, taking care | |
356 | to propogate the carries from the additions: */ | |
357 | RdLo = Add32 (lo, (mid1 << 16), & carry); | |
358 | RdHi = carry; | |
359 | RdLo = Add32 (RdLo, (mid2 << 16), & carry); | |
360 | RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); | |
361 | ||
362 | if (sign) | |
363 | { | |
364 | /* Negate result if necessary. */ | |
365 | ||
366 | RdLo = ~ RdLo; | |
367 | RdHi = ~ RdHi; | |
368 | if (RdLo == 0xFFFFFFFF) | |
369 | { | |
370 | RdLo = 0; | |
371 | RdHi += 1; | |
372 | } | |
373 | else | |
374 | RdLo += 1; | |
375 | } | |
376 | ||
377 | /* Don't store into register 0. */ | |
378 | if (OP[1]) | |
379 | State.regs[ OP[1] ] = RdLo; | |
380 | if (OP[2] >> 11) | |
381 | State.regs[ OP[2] >> 11 ] = RdHi; | |
382 | ||
383 | return; | |
384 | } | |
385 | ||
386 | \f | |
a3976a7c NC |
387 | /* Read a null terminated string from memory, return in a buffer. */ |
388 | ||
c906108c | 389 | static char * |
a3976a7c | 390 | fetch_str (SIM_DESC sd, address_word addr) |
c906108c SS |
391 | { |
392 | char *buf; | |
393 | int nr = 0; | |
a3976a7c | 394 | |
c906108c SS |
395 | while (sim_core_read_1 (STATE_CPU (sd, 0), |
396 | PC, read_map, addr + nr) != 0) | |
397 | nr++; | |
a3976a7c | 398 | |
c906108c | 399 | buf = NZALLOC (char, nr + 1); |
a3976a7c NC |
400 | sim_read (simulator, addr, (unsigned char *) buf, nr); |
401 | ||
c906108c SS |
402 | return buf; |
403 | } | |
404 | ||
405 | /* Read a null terminated argument vector from memory, return in a | |
a3976a7c NC |
406 | buffer. */ |
407 | ||
c906108c | 408 | static char ** |
a3976a7c | 409 | fetch_argv (SIM_DESC sd, address_word addr) |
c906108c SS |
410 | { |
411 | int max_nr = 64; | |
412 | int nr = 0; | |
413 | char **buf = xmalloc (max_nr * sizeof (char*)); | |
a3976a7c | 414 | |
c906108c SS |
415 | while (1) |
416 | { | |
417 | unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0), | |
418 | PC, read_map, addr + nr * 4); | |
419 | if (a == 0) break; | |
420 | buf[nr] = fetch_str (sd, a); | |
421 | nr ++; | |
422 | if (nr == max_nr - 1) | |
423 | { | |
424 | max_nr += 50; | |
425 | buf = xrealloc (buf, max_nr * sizeof (char*)); | |
426 | } | |
427 | } | |
428 | buf[nr] = 0; | |
429 | return buf; | |
430 | } | |
431 | ||
432 | \f | |
433 | /* sst.b */ | |
434 | int | |
a3976a7c | 435 | OP_380 (void) |
c906108c SS |
436 | { |
437 | trace_input ("sst.b", OP_STORE16, 1); | |
438 | ||
439 | store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]); | |
440 | ||
441 | trace_output (OP_STORE16); | |
442 | ||
443 | return 2; | |
444 | } | |
445 | ||
446 | /* sst.h */ | |
447 | int | |
a3976a7c | 448 | OP_480 (void) |
c906108c SS |
449 | { |
450 | trace_input ("sst.h", OP_STORE16, 2); | |
451 | ||
452 | store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]); | |
453 | ||
454 | trace_output (OP_STORE16); | |
455 | ||
456 | return 2; | |
457 | } | |
458 | ||
459 | /* sst.w */ | |
460 | int | |
a3976a7c | 461 | OP_501 (void) |
c906108c SS |
462 | { |
463 | trace_input ("sst.w", OP_STORE16, 4); | |
464 | ||
465 | store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]); | |
466 | ||
467 | trace_output (OP_STORE16); | |
468 | ||
469 | return 2; | |
470 | } | |
471 | ||
472 | /* ld.b */ | |
473 | int | |
a3976a7c | 474 | OP_700 (void) |
c906108c SS |
475 | { |
476 | int adr; | |
477 | ||
478 | trace_input ("ld.b", OP_LOAD32, 1); | |
479 | ||
480 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); | |
481 | ||
482 | State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1)); | |
483 | ||
484 | trace_output (OP_LOAD32); | |
485 | ||
486 | return 4; | |
487 | } | |
488 | ||
489 | /* ld.h */ | |
490 | int | |
a3976a7c | 491 | OP_720 (void) |
c906108c SS |
492 | { |
493 | int adr; | |
494 | ||
495 | trace_input ("ld.h", OP_LOAD32, 2); | |
496 | ||
497 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); | |
498 | adr &= ~0x1; | |
499 | ||
500 | State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2)); | |
501 | ||
502 | trace_output (OP_LOAD32); | |
503 | ||
504 | return 4; | |
505 | } | |
506 | ||
507 | /* ld.w */ | |
508 | int | |
a3976a7c | 509 | OP_10720 (void) |
c906108c SS |
510 | { |
511 | int adr; | |
512 | ||
513 | trace_input ("ld.w", OP_LOAD32, 4); | |
514 | ||
515 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); | |
516 | adr &= ~0x3; | |
517 | ||
518 | State.regs[ OP[1] ] = load_mem (adr, 4); | |
519 | ||
520 | trace_output (OP_LOAD32); | |
521 | ||
522 | return 4; | |
523 | } | |
524 | ||
525 | /* st.b */ | |
526 | int | |
a3976a7c | 527 | OP_740 (void) |
c906108c SS |
528 | { |
529 | trace_input ("st.b", OP_STORE32, 1); | |
530 | ||
531 | store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]); | |
532 | ||
533 | trace_output (OP_STORE32); | |
534 | ||
535 | return 4; | |
536 | } | |
537 | ||
538 | /* st.h */ | |
539 | int | |
a3976a7c | 540 | OP_760 (void) |
c906108c SS |
541 | { |
542 | int adr; | |
543 | ||
544 | trace_input ("st.h", OP_STORE32, 2); | |
545 | ||
546 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); | |
547 | adr &= ~1; | |
548 | ||
549 | store_mem (adr, 2, State.regs[ OP[1] ]); | |
550 | ||
551 | trace_output (OP_STORE32); | |
552 | ||
553 | return 4; | |
554 | } | |
555 | ||
556 | /* st.w */ | |
557 | int | |
a3976a7c | 558 | OP_10760 (void) |
c906108c SS |
559 | { |
560 | int adr; | |
561 | ||
562 | trace_input ("st.w", OP_STORE32, 4); | |
563 | ||
564 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); | |
565 | adr &= ~3; | |
566 | ||
567 | store_mem (adr, 4, State.regs[ OP[1] ]); | |
568 | ||
569 | trace_output (OP_STORE32); | |
570 | ||
571 | return 4; | |
572 | } | |
573 | ||
574 | /* add reg, reg */ | |
575 | int | |
a3976a7c | 576 | OP_1C0 (void) |
c906108c SS |
577 | { |
578 | unsigned int op0, op1, result, z, s, cy, ov; | |
579 | ||
580 | trace_input ("add", OP_REG_REG, 0); | |
581 | ||
582 | /* Compute the result. */ | |
583 | ||
584 | op0 = State.regs[ OP[0] ]; | |
585 | op1 = State.regs[ OP[1] ]; | |
586 | ||
587 | result = op0 + op1; | |
588 | ||
589 | /* Compute the condition codes. */ | |
590 | z = (result == 0); | |
591 | s = (result & 0x80000000); | |
592 | cy = (result < op0 || result < op1); | |
593 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
594 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
595 | ||
596 | /* Store the result and condition codes. */ | |
597 | State.regs[OP[1]] = result; | |
598 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
599 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
600 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
601 | trace_output (OP_REG_REG); | |
602 | ||
603 | return 2; | |
604 | } | |
605 | ||
606 | /* add sign_extend(imm5), reg */ | |
607 | int | |
a3976a7c | 608 | OP_240 (void) |
c906108c SS |
609 | { |
610 | unsigned int op0, op1, result, z, s, cy, ov; | |
611 | int temp; | |
612 | ||
613 | trace_input ("add", OP_IMM_REG, 0); | |
614 | ||
615 | /* Compute the result. */ | |
616 | temp = SEXT5 (OP[0]); | |
617 | op0 = temp; | |
618 | op1 = State.regs[OP[1]]; | |
619 | result = op0 + op1; | |
620 | ||
621 | /* Compute the condition codes. */ | |
622 | z = (result == 0); | |
623 | s = (result & 0x80000000); | |
624 | cy = (result < op0 || result < op1); | |
625 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
626 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
627 | ||
628 | /* Store the result and condition codes. */ | |
629 | State.regs[OP[1]] = result; | |
630 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
631 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
632 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
633 | trace_output (OP_IMM_REG); | |
634 | ||
635 | return 2; | |
636 | } | |
637 | ||
638 | /* addi sign_extend(imm16), reg, reg */ | |
639 | int | |
a3976a7c | 640 | OP_600 (void) |
c906108c SS |
641 | { |
642 | unsigned int op0, op1, result, z, s, cy, ov; | |
643 | ||
644 | trace_input ("addi", OP_IMM16_REG_REG, 0); | |
645 | ||
646 | /* Compute the result. */ | |
647 | ||
648 | op0 = EXTEND16 (OP[2]); | |
649 | op1 = State.regs[ OP[0] ]; | |
650 | result = op0 + op1; | |
651 | ||
652 | /* Compute the condition codes. */ | |
653 | z = (result == 0); | |
654 | s = (result & 0x80000000); | |
655 | cy = (result < op0 || result < op1); | |
656 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
657 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
658 | ||
659 | /* Store the result and condition codes. */ | |
660 | State.regs[OP[1]] = result; | |
661 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
662 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
663 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
664 | trace_output (OP_IMM16_REG_REG); | |
665 | ||
666 | return 4; | |
667 | } | |
668 | ||
669 | /* sub reg1, reg2 */ | |
670 | int | |
a3976a7c | 671 | OP_1A0 (void) |
c906108c SS |
672 | { |
673 | unsigned int op0, op1, result, z, s, cy, ov; | |
674 | ||
675 | trace_input ("sub", OP_REG_REG, 0); | |
676 | /* Compute the result. */ | |
677 | op0 = State.regs[ OP[0] ]; | |
678 | op1 = State.regs[ OP[1] ]; | |
679 | result = op1 - op0; | |
680 | ||
681 | /* Compute the condition codes. */ | |
682 | z = (result == 0); | |
683 | s = (result & 0x80000000); | |
684 | cy = (op1 < op0); | |
685 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
686 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
687 | ||
688 | /* Store the result and condition codes. */ | |
689 | State.regs[OP[1]] = result; | |
690 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
691 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
692 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
693 | trace_output (OP_REG_REG); | |
694 | ||
695 | return 2; | |
696 | } | |
697 | ||
698 | /* subr reg1, reg2 */ | |
699 | int | |
a3976a7c | 700 | OP_180 (void) |
c906108c SS |
701 | { |
702 | unsigned int op0, op1, result, z, s, cy, ov; | |
703 | ||
704 | trace_input ("subr", OP_REG_REG, 0); | |
705 | /* Compute the result. */ | |
706 | op0 = State.regs[ OP[0] ]; | |
707 | op1 = State.regs[ OP[1] ]; | |
708 | result = op0 - op1; | |
709 | ||
710 | /* Compute the condition codes. */ | |
711 | z = (result == 0); | |
712 | s = (result & 0x80000000); | |
713 | cy = (op0 < op1); | |
714 | ov = ((op0 & 0x80000000) != (op1 & 0x80000000) | |
715 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
716 | ||
717 | /* Store the result and condition codes. */ | |
718 | State.regs[OP[1]] = result; | |
719 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
720 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
721 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
722 | trace_output (OP_REG_REG); | |
723 | ||
724 | return 2; | |
725 | } | |
726 | ||
727 | /* sxh reg1 */ | |
728 | int | |
a3976a7c | 729 | OP_E0 (void) |
c906108c SS |
730 | { |
731 | trace_input ("mulh", OP_REG_REG, 0); | |
732 | ||
733 | State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ])); | |
734 | ||
735 | trace_output (OP_REG_REG); | |
736 | ||
737 | return 2; | |
738 | } | |
739 | ||
740 | /* mulh sign_extend(imm5), reg2 */ | |
741 | int | |
a3976a7c | 742 | OP_2E0 (void) |
c906108c SS |
743 | { |
744 | trace_input ("mulh", OP_IMM_REG, 0); | |
745 | ||
746 | State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]); | |
747 | ||
748 | trace_output (OP_IMM_REG); | |
749 | ||
750 | return 2; | |
751 | } | |
752 | ||
753 | /* mulhi imm16, reg1, reg2 */ | |
754 | int | |
a3976a7c | 755 | OP_6E0 (void) |
c906108c SS |
756 | { |
757 | trace_input ("mulhi", OP_IMM16_REG_REG, 0); | |
758 | ||
759 | State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]); | |
760 | ||
761 | trace_output (OP_IMM16_REG_REG); | |
762 | ||
763 | return 4; | |
764 | } | |
765 | ||
c906108c SS |
766 | /* cmp reg, reg */ |
767 | int | |
a3976a7c | 768 | OP_1E0 (void) |
c906108c SS |
769 | { |
770 | unsigned int op0, op1, result, z, s, cy, ov; | |
771 | ||
772 | trace_input ("cmp", OP_REG_REG_CMP, 0); | |
773 | /* Compute the result. */ | |
774 | op0 = State.regs[ OP[0] ]; | |
775 | op1 = State.regs[ OP[1] ]; | |
776 | result = op1 - op0; | |
777 | ||
778 | /* Compute the condition codes. */ | |
779 | z = (result == 0); | |
780 | s = (result & 0x80000000); | |
781 | cy = (op1 < op0); | |
782 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
783 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
784 | ||
785 | /* Set condition codes. */ | |
786 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
787 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
788 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
789 | trace_output (OP_REG_REG_CMP); | |
790 | ||
791 | return 2; | |
792 | } | |
793 | ||
794 | /* cmp sign_extend(imm5), reg */ | |
795 | int | |
a3976a7c | 796 | OP_260 (void) |
c906108c SS |
797 | { |
798 | unsigned int op0, op1, result, z, s, cy, ov; | |
799 | int temp; | |
800 | ||
801 | /* Compute the result. */ | |
802 | trace_input ("cmp", OP_IMM_REG_CMP, 0); | |
803 | temp = SEXT5 (OP[0]); | |
804 | op0 = temp; | |
805 | op1 = State.regs[OP[1]]; | |
806 | result = op1 - op0; | |
807 | ||
808 | /* Compute the condition codes. */ | |
809 | z = (result == 0); | |
810 | s = (result & 0x80000000); | |
811 | cy = (op1 < op0); | |
812 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
813 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
814 | ||
815 | /* Set condition codes. */ | |
816 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
817 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
818 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | |
819 | trace_output (OP_IMM_REG_CMP); | |
820 | ||
821 | return 2; | |
822 | } | |
823 | ||
824 | /* setf cccc,reg2 */ | |
825 | int | |
a3976a7c | 826 | OP_7E0 (void) |
c906108c SS |
827 | { |
828 | trace_input ("setf", OP_EX1, 0); | |
829 | ||
830 | State.regs[ OP[1] ] = condition_met (OP[0]); | |
831 | ||
832 | trace_output (OP_EX1); | |
833 | ||
834 | return 4; | |
835 | } | |
836 | ||
837 | /* satadd reg,reg */ | |
838 | int | |
a3976a7c | 839 | OP_C0 (void) |
c906108c SS |
840 | { |
841 | unsigned int op0, op1, result, z, s, cy, ov, sat; | |
842 | ||
843 | trace_input ("satadd", OP_REG_REG, 0); | |
844 | /* Compute the result. */ | |
845 | op0 = State.regs[ OP[0] ]; | |
846 | op1 = State.regs[ OP[1] ]; | |
847 | result = op0 + op1; | |
848 | ||
849 | /* Compute the condition codes. */ | |
850 | z = (result == 0); | |
851 | s = (result & 0x80000000); | |
852 | cy = (result < op0 || result < op1); | |
853 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
854 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
855 | sat = ov; | |
856 | ||
c5fbc25b DD |
857 | /* Handle saturated results. */ |
858 | if (sat && s) | |
859 | { | |
860 | /* An overflow that results in a negative result implies that we | |
861 | became too positive. */ | |
862 | result = 0x7fffffff; | |
863 | s = 0; | |
864 | } | |
865 | else if (sat) | |
866 | { | |
867 | /* Any other overflow must have thus been too negative. */ | |
868 | result = 0x80000000; | |
869 | s = 1; | |
870 | z = 0; | |
871 | } | |
872 | ||
c906108c SS |
873 | /* Store the result and condition codes. */ |
874 | State.regs[OP[1]] = result; | |
875 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
876 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
877 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
878 | | (sat ? PSW_SAT : 0)); | |
c5fbc25b | 879 | |
c906108c SS |
880 | trace_output (OP_REG_REG); |
881 | ||
882 | return 2; | |
883 | } | |
884 | ||
885 | /* satadd sign_extend(imm5), reg */ | |
886 | int | |
a3976a7c | 887 | OP_220 (void) |
c906108c SS |
888 | { |
889 | unsigned int op0, op1, result, z, s, cy, ov, sat; | |
890 | ||
891 | int temp; | |
892 | ||
893 | trace_input ("satadd", OP_IMM_REG, 0); | |
894 | ||
895 | /* Compute the result. */ | |
896 | temp = SEXT5 (OP[0]); | |
897 | op0 = temp; | |
898 | op1 = State.regs[OP[1]]; | |
899 | result = op0 + op1; | |
900 | ||
901 | /* Compute the condition codes. */ | |
902 | z = (result == 0); | |
903 | s = (result & 0x80000000); | |
904 | cy = (result < op0 || result < op1); | |
905 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
906 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
907 | sat = ov; | |
908 | ||
c5fbc25b DD |
909 | /* Handle saturated results. */ |
910 | if (sat && s) | |
911 | { | |
912 | /* An overflow that results in a negative result implies that we | |
913 | became too positive. */ | |
914 | result = 0x7fffffff; | |
915 | s = 0; | |
916 | } | |
917 | else if (sat) | |
918 | { | |
919 | /* Any other overflow must have thus been too negative. */ | |
920 | result = 0x80000000; | |
921 | s = 1; | |
922 | z = 0; | |
923 | } | |
924 | ||
c906108c SS |
925 | /* Store the result and condition codes. */ |
926 | State.regs[OP[1]] = result; | |
927 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
928 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
929 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
930 | | (sat ? PSW_SAT : 0)); | |
c906108c SS |
931 | trace_output (OP_IMM_REG); |
932 | ||
933 | return 2; | |
934 | } | |
935 | ||
936 | /* satsub reg1, reg2 */ | |
937 | int | |
a3976a7c | 938 | OP_A0 (void) |
c906108c SS |
939 | { |
940 | unsigned int op0, op1, result, z, s, cy, ov, sat; | |
941 | ||
942 | trace_input ("satsub", OP_REG_REG, 0); | |
943 | ||
944 | /* Compute the result. */ | |
945 | op0 = State.regs[ OP[0] ]; | |
946 | op1 = State.regs[ OP[1] ]; | |
947 | result = op1 - op0; | |
948 | ||
949 | /* Compute the condition codes. */ | |
950 | z = (result == 0); | |
951 | s = (result & 0x80000000); | |
952 | cy = (op1 < op0); | |
953 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
954 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
955 | sat = ov; | |
c5fbc25b DD |
956 | |
957 | /* Handle saturated results. */ | |
958 | if (sat && s) | |
959 | { | |
960 | /* An overflow that results in a negative result implies that we | |
961 | became too positive. */ | |
962 | result = 0x7fffffff; | |
963 | s = 0; | |
964 | } | |
965 | else if (sat) | |
966 | { | |
967 | /* Any other overflow must have thus been too negative. */ | |
968 | result = 0x80000000; | |
969 | s = 1; | |
970 | z = 0; | |
971 | } | |
972 | ||
c906108c SS |
973 | /* Store the result and condition codes. */ |
974 | State.regs[OP[1]] = result; | |
975 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
976 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
977 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
978 | | (sat ? PSW_SAT : 0)); | |
979 | ||
c906108c SS |
980 | trace_output (OP_REG_REG); |
981 | return 2; | |
982 | } | |
983 | ||
984 | /* satsubi sign_extend(imm16), reg */ | |
985 | int | |
a3976a7c | 986 | OP_660 (void) |
c906108c SS |
987 | { |
988 | unsigned int op0, op1, result, z, s, cy, ov, sat; | |
989 | int temp; | |
990 | ||
991 | trace_input ("satsubi", OP_IMM_REG, 0); | |
992 | ||
993 | /* Compute the result. */ | |
994 | temp = EXTEND16 (OP[2]); | |
995 | op0 = temp; | |
996 | op1 = State.regs[ OP[0] ]; | |
997 | result = op1 - op0; | |
998 | ||
999 | /* Compute the condition codes. */ | |
1000 | z = (result == 0); | |
1001 | s = (result & 0x80000000); | |
1002 | cy = (op1 < op0); | |
1003 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
1004 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
1005 | sat = ov; | |
1006 | ||
c5fbc25b DD |
1007 | /* Handle saturated results. */ |
1008 | if (sat && s) | |
1009 | { | |
1010 | /* An overflow that results in a negative result implies that we | |
1011 | became too positive. */ | |
1012 | result = 0x7fffffff; | |
1013 | s = 0; | |
1014 | } | |
1015 | else if (sat) | |
1016 | { | |
1017 | /* Any other overflow must have thus been too negative. */ | |
1018 | result = 0x80000000; | |
1019 | s = 1; | |
1020 | z = 0; | |
1021 | } | |
1022 | ||
c906108c SS |
1023 | /* Store the result and condition codes. */ |
1024 | State.regs[OP[1]] = result; | |
1025 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
1026 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1027 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
1028 | | (sat ? PSW_SAT : 0)); | |
1029 | ||
c906108c SS |
1030 | trace_output (OP_IMM_REG); |
1031 | ||
1032 | return 4; | |
1033 | } | |
1034 | ||
1035 | /* satsubr reg,reg */ | |
1036 | int | |
a3976a7c | 1037 | OP_80 (void) |
c906108c SS |
1038 | { |
1039 | unsigned int op0, op1, result, z, s, cy, ov, sat; | |
1040 | ||
1041 | trace_input ("satsubr", OP_REG_REG, 0); | |
1042 | ||
1043 | /* Compute the result. */ | |
1044 | op0 = State.regs[ OP[0] ]; | |
1045 | op1 = State.regs[ OP[1] ]; | |
1046 | result = op0 - op1; | |
1047 | ||
1048 | /* Compute the condition codes. */ | |
1049 | z = (result == 0); | |
1050 | s = (result & 0x80000000); | |
c5fbc25b DD |
1051 | cy = (op0 < op1); |
1052 | ov = ((op0 & 0x80000000) != (op1 & 0x80000000) | |
1053 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
c906108c | 1054 | sat = ov; |
c5fbc25b DD |
1055 | |
1056 | /* Handle saturated results. */ | |
1057 | if (sat && s) | |
1058 | { | |
1059 | /* An overflow that results in a negative result implies that we | |
1060 | became too positive. */ | |
1061 | result = 0x7fffffff; | |
1062 | s = 0; | |
1063 | } | |
1064 | else if (sat) | |
1065 | { | |
1066 | /* Any other overflow must have thus been too negative. */ | |
1067 | result = 0x80000000; | |
1068 | s = 1; | |
1069 | z = 0; | |
1070 | } | |
c906108c SS |
1071 | |
1072 | /* Store the result and condition codes. */ | |
1073 | State.regs[OP[1]] = result; | |
1074 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
1075 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1076 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
1077 | | (sat ? PSW_SAT : 0)); | |
1078 | ||
c906108c SS |
1079 | trace_output (OP_REG_REG); |
1080 | ||
1081 | return 2; | |
1082 | } | |
1083 | ||
1084 | /* tst reg,reg */ | |
1085 | int | |
a3976a7c | 1086 | OP_160 (void) |
c906108c SS |
1087 | { |
1088 | unsigned int op0, op1, result, z, s; | |
1089 | ||
1090 | trace_input ("tst", OP_REG_REG_CMP, 0); | |
1091 | ||
1092 | /* Compute the result. */ | |
1093 | op0 = State.regs[ OP[0] ]; | |
1094 | op1 = State.regs[ OP[1] ]; | |
1095 | result = op0 & op1; | |
1096 | ||
1097 | /* Compute the condition codes. */ | |
1098 | z = (result == 0); | |
1099 | s = (result & 0x80000000); | |
1100 | ||
1101 | /* Store the condition codes. */ | |
1102 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1103 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1104 | trace_output (OP_REG_REG_CMP); | |
1105 | ||
1106 | return 2; | |
1107 | } | |
1108 | ||
1109 | /* mov sign_extend(imm5), reg */ | |
1110 | int | |
a3976a7c | 1111 | OP_200 (void) |
c906108c SS |
1112 | { |
1113 | int value = SEXT5 (OP[0]); | |
1114 | ||
1115 | trace_input ("mov", OP_IMM_REG_MOVE, 0); | |
1116 | ||
1117 | State.regs[ OP[1] ] = value; | |
1118 | ||
1119 | trace_output (OP_IMM_REG_MOVE); | |
1120 | ||
1121 | return 2; | |
1122 | } | |
1123 | ||
1124 | /* movhi imm16, reg, reg */ | |
1125 | int | |
a3976a7c | 1126 | OP_640 (void) |
c906108c SS |
1127 | { |
1128 | trace_input ("movhi", OP_UIMM16_REG_REG, 16); | |
1129 | ||
1130 | State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16); | |
1131 | ||
1132 | trace_output (OP_UIMM16_REG_REG); | |
1133 | ||
1134 | return 4; | |
1135 | } | |
1136 | ||
1137 | /* sar zero_extend(imm5),reg1 */ | |
1138 | int | |
a3976a7c | 1139 | OP_2A0 (void) |
c906108c SS |
1140 | { |
1141 | unsigned int op0, op1, result, z, s, cy; | |
1142 | ||
1143 | trace_input ("sar", OP_IMM_REG, 0); | |
1144 | op0 = OP[0]; | |
1145 | op1 = State.regs[ OP[1] ]; | |
1146 | result = (signed)op1 >> op0; | |
1147 | ||
1148 | /* Compute the condition codes. */ | |
1149 | z = (result == 0); | |
1150 | s = (result & 0x80000000); | |
c5fbc25b | 1151 | cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; |
c906108c SS |
1152 | |
1153 | /* Store the result and condition codes. */ | |
1154 | State.regs[ OP[1] ] = result; | |
1155 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1156 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1157 | | (cy ? PSW_CY : 0)); | |
1158 | trace_output (OP_IMM_REG); | |
1159 | ||
1160 | return 2; | |
1161 | } | |
1162 | ||
1163 | /* sar reg1, reg2 */ | |
1164 | int | |
a3976a7c | 1165 | OP_A007E0 (void) |
c906108c SS |
1166 | { |
1167 | unsigned int op0, op1, result, z, s, cy; | |
1168 | ||
1169 | trace_input ("sar", OP_REG_REG, 0); | |
1170 | ||
1171 | op0 = State.regs[ OP[0] ] & 0x1f; | |
1172 | op1 = State.regs[ OP[1] ]; | |
1173 | result = (signed)op1 >> op0; | |
1174 | ||
1175 | /* Compute the condition codes. */ | |
1176 | z = (result == 0); | |
1177 | s = (result & 0x80000000); | |
c5fbc25b | 1178 | cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; |
c906108c SS |
1179 | |
1180 | /* Store the result and condition codes. */ | |
1181 | State.regs[OP[1]] = result; | |
1182 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1183 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1184 | | (cy ? PSW_CY : 0)); | |
1185 | trace_output (OP_REG_REG); | |
1186 | ||
1187 | return 4; | |
1188 | } | |
1189 | ||
1190 | /* shl zero_extend(imm5),reg1 */ | |
1191 | int | |
a3976a7c | 1192 | OP_2C0 (void) |
c906108c SS |
1193 | { |
1194 | unsigned int op0, op1, result, z, s, cy; | |
1195 | ||
1196 | trace_input ("shl", OP_IMM_REG, 0); | |
1197 | op0 = OP[0]; | |
1198 | op1 = State.regs[ OP[1] ]; | |
1199 | result = op1 << op0; | |
1200 | ||
1201 | /* Compute the condition codes. */ | |
1202 | z = (result == 0); | |
1203 | s = (result & 0x80000000); | |
c5fbc25b | 1204 | cy = op0 ? (op1 & (1 << (32 - op0))) : 0; |
c906108c SS |
1205 | |
1206 | /* Store the result and condition codes. */ | |
1207 | State.regs[OP[1]] = result; | |
1208 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1209 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1210 | | (cy ? PSW_CY : 0)); | |
1211 | trace_output (OP_IMM_REG); | |
1212 | ||
1213 | return 2; | |
1214 | } | |
1215 | ||
1216 | /* shl reg1, reg2 */ | |
1217 | int | |
a3976a7c | 1218 | OP_C007E0 (void) |
c906108c SS |
1219 | { |
1220 | unsigned int op0, op1, result, z, s, cy; | |
1221 | ||
1222 | trace_input ("shl", OP_REG_REG, 0); | |
1223 | op0 = State.regs[ OP[0] ] & 0x1f; | |
1224 | op1 = State.regs[ OP[1] ]; | |
1225 | result = op1 << op0; | |
1226 | ||
1227 | /* Compute the condition codes. */ | |
1228 | z = (result == 0); | |
1229 | s = (result & 0x80000000); | |
c5fbc25b | 1230 | cy = op0 ? (op1 & (1 << (32 - op0))) : 0; |
c906108c SS |
1231 | |
1232 | /* Store the result and condition codes. */ | |
1233 | State.regs[OP[1]] = result; | |
1234 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1235 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1236 | | (cy ? PSW_CY : 0)); | |
1237 | trace_output (OP_REG_REG); | |
1238 | ||
1239 | return 4; | |
1240 | } | |
1241 | ||
1242 | /* shr zero_extend(imm5),reg1 */ | |
1243 | int | |
a3976a7c | 1244 | OP_280 (void) |
c906108c SS |
1245 | { |
1246 | unsigned int op0, op1, result, z, s, cy; | |
1247 | ||
1248 | trace_input ("shr", OP_IMM_REG, 0); | |
1249 | op0 = OP[0]; | |
1250 | op1 = State.regs[ OP[1] ]; | |
1251 | result = op1 >> op0; | |
1252 | ||
1253 | /* Compute the condition codes. */ | |
1254 | z = (result == 0); | |
1255 | s = (result & 0x80000000); | |
c5fbc25b | 1256 | cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; |
c906108c SS |
1257 | |
1258 | /* Store the result and condition codes. */ | |
1259 | State.regs[OP[1]] = result; | |
1260 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1261 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1262 | | (cy ? PSW_CY : 0)); | |
1263 | trace_output (OP_IMM_REG); | |
1264 | ||
1265 | return 2; | |
1266 | } | |
1267 | ||
1268 | /* shr reg1, reg2 */ | |
1269 | int | |
a3976a7c | 1270 | OP_8007E0 (void) |
c906108c SS |
1271 | { |
1272 | unsigned int op0, op1, result, z, s, cy; | |
1273 | ||
1274 | trace_input ("shr", OP_REG_REG, 0); | |
1275 | op0 = State.regs[ OP[0] ] & 0x1f; | |
1276 | op1 = State.regs[ OP[1] ]; | |
1277 | result = op1 >> op0; | |
1278 | ||
1279 | /* Compute the condition codes. */ | |
1280 | z = (result == 0); | |
1281 | s = (result & 0x80000000); | |
c5fbc25b | 1282 | cy = op0 ? (op1 & (1 << (op0 - 1))) : 0; |
c906108c SS |
1283 | |
1284 | /* Store the result and condition codes. */ | |
1285 | State.regs[OP[1]] = result; | |
1286 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
1287 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
1288 | | (cy ? PSW_CY : 0)); | |
1289 | trace_output (OP_REG_REG); | |
1290 | ||
1291 | return 4; | |
1292 | } | |
1293 | ||
1294 | /* or reg, reg */ | |
1295 | int | |
a3976a7c | 1296 | OP_100 (void) |
c906108c SS |
1297 | { |
1298 | unsigned int op0, op1, result, z, s; | |
1299 | ||
1300 | trace_input ("or", OP_REG_REG, 0); | |
1301 | ||
1302 | /* Compute the result. */ | |
1303 | op0 = State.regs[ OP[0] ]; | |
1304 | op1 = State.regs[ OP[1] ]; | |
1305 | result = op0 | op1; | |
1306 | ||
1307 | /* Compute the condition codes. */ | |
1308 | z = (result == 0); | |
1309 | s = (result & 0x80000000); | |
1310 | ||
1311 | /* Store the result and condition codes. */ | |
1312 | State.regs[OP[1]] = result; | |
1313 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1314 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1315 | trace_output (OP_REG_REG); | |
1316 | ||
1317 | return 2; | |
1318 | } | |
1319 | ||
1320 | /* ori zero_extend(imm16), reg, reg */ | |
1321 | int | |
a3976a7c | 1322 | OP_680 (void) |
c906108c SS |
1323 | { |
1324 | unsigned int op0, op1, result, z, s; | |
1325 | ||
1326 | trace_input ("ori", OP_UIMM16_REG_REG, 0); | |
1327 | op0 = OP[2]; | |
1328 | op1 = State.regs[ OP[0] ]; | |
1329 | result = op0 | op1; | |
1330 | ||
1331 | /* Compute the condition codes. */ | |
1332 | z = (result == 0); | |
1333 | s = (result & 0x80000000); | |
1334 | ||
1335 | /* Store the result and condition codes. */ | |
1336 | State.regs[OP[1]] = result; | |
1337 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1338 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1339 | trace_output (OP_UIMM16_REG_REG); | |
1340 | ||
1341 | return 4; | |
1342 | } | |
1343 | ||
1344 | /* and reg, reg */ | |
1345 | int | |
a3976a7c | 1346 | OP_140 (void) |
c906108c SS |
1347 | { |
1348 | unsigned int op0, op1, result, z, s; | |
1349 | ||
1350 | trace_input ("and", OP_REG_REG, 0); | |
1351 | ||
1352 | /* Compute the result. */ | |
1353 | op0 = State.regs[ OP[0] ]; | |
1354 | op1 = State.regs[ OP[1] ]; | |
1355 | result = op0 & op1; | |
1356 | ||
1357 | /* Compute the condition codes. */ | |
1358 | z = (result == 0); | |
1359 | s = (result & 0x80000000); | |
1360 | ||
1361 | /* Store the result and condition codes. */ | |
1362 | State.regs[OP[1]] = result; | |
1363 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1364 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1365 | trace_output (OP_REG_REG); | |
1366 | ||
1367 | return 2; | |
1368 | } | |
1369 | ||
1370 | /* andi zero_extend(imm16), reg, reg */ | |
1371 | int | |
a3976a7c | 1372 | OP_6C0 (void) |
c906108c SS |
1373 | { |
1374 | unsigned int result, z; | |
1375 | ||
1376 | trace_input ("andi", OP_UIMM16_REG_REG, 0); | |
1377 | ||
1378 | result = OP[2] & State.regs[ OP[0] ]; | |
1379 | ||
1380 | /* Compute the condition codes. */ | |
1381 | z = (result == 0); | |
1382 | ||
1383 | /* Store the result and condition codes. */ | |
1384 | State.regs[ OP[1] ] = result; | |
1385 | ||
1386 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1387 | PSW |= (z ? PSW_Z : 0); | |
1388 | ||
1389 | trace_output (OP_UIMM16_REG_REG); | |
1390 | ||
1391 | return 4; | |
1392 | } | |
1393 | ||
1394 | /* xor reg, reg */ | |
1395 | int | |
a3976a7c | 1396 | OP_120 (void) |
c906108c SS |
1397 | { |
1398 | unsigned int op0, op1, result, z, s; | |
1399 | ||
1400 | trace_input ("xor", OP_REG_REG, 0); | |
1401 | ||
1402 | /* Compute the result. */ | |
1403 | op0 = State.regs[ OP[0] ]; | |
1404 | op1 = State.regs[ OP[1] ]; | |
1405 | result = op0 ^ op1; | |
1406 | ||
1407 | /* Compute the condition codes. */ | |
1408 | z = (result == 0); | |
1409 | s = (result & 0x80000000); | |
1410 | ||
1411 | /* Store the result and condition codes. */ | |
1412 | State.regs[OP[1]] = result; | |
1413 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1414 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1415 | trace_output (OP_REG_REG); | |
1416 | ||
1417 | return 2; | |
1418 | } | |
1419 | ||
1420 | /* xori zero_extend(imm16), reg, reg */ | |
1421 | int | |
a3976a7c | 1422 | OP_6A0 (void) |
c906108c SS |
1423 | { |
1424 | unsigned int op0, op1, result, z, s; | |
1425 | ||
1426 | trace_input ("xori", OP_UIMM16_REG_REG, 0); | |
1427 | op0 = OP[2]; | |
1428 | op1 = State.regs[ OP[0] ]; | |
1429 | result = op0 ^ op1; | |
1430 | ||
1431 | /* Compute the condition codes. */ | |
1432 | z = (result == 0); | |
1433 | s = (result & 0x80000000); | |
1434 | ||
1435 | /* Store the result and condition codes. */ | |
1436 | State.regs[OP[1]] = result; | |
1437 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1438 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1439 | trace_output (OP_UIMM16_REG_REG); | |
1440 | ||
1441 | return 4; | |
1442 | } | |
1443 | ||
1444 | /* not reg1, reg2 */ | |
1445 | int | |
a3976a7c | 1446 | OP_20 (void) |
c906108c SS |
1447 | { |
1448 | unsigned int op0, result, z, s; | |
1449 | ||
1450 | trace_input ("not", OP_REG_REG_MOVE, 0); | |
1451 | /* Compute the result. */ | |
1452 | op0 = State.regs[ OP[0] ]; | |
1453 | result = ~op0; | |
1454 | ||
1455 | /* Compute the condition codes. */ | |
1456 | z = (result == 0); | |
1457 | s = (result & 0x80000000); | |
1458 | ||
1459 | /* Store the result and condition codes. */ | |
1460 | State.regs[OP[1]] = result; | |
1461 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
1462 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); | |
1463 | trace_output (OP_REG_REG_MOVE); | |
1464 | ||
1465 | return 2; | |
1466 | } | |
1467 | ||
1468 | /* set1 */ | |
1469 | int | |
a3976a7c | 1470 | OP_7C0 (void) |
c906108c SS |
1471 | { |
1472 | unsigned int op0, op1, op2; | |
1473 | int temp; | |
1474 | ||
1475 | trace_input ("set1", OP_BIT, 0); | |
1476 | op0 = State.regs[ OP[0] ]; | |
1477 | op1 = OP[1] & 0x7; | |
1478 | temp = EXTEND16 (OP[2]); | |
1479 | op2 = temp; | |
1480 | temp = load_mem (op0 + op2, 1); | |
1481 | PSW &= ~PSW_Z; | |
1482 | if ((temp & (1 << op1)) == 0) | |
1483 | PSW |= PSW_Z; | |
1484 | temp |= (1 << op1); | |
1485 | store_mem (op0 + op2, 1, temp); | |
1486 | trace_output (OP_BIT); | |
1487 | ||
1488 | return 4; | |
1489 | } | |
1490 | ||
1491 | /* not1 */ | |
1492 | int | |
a3976a7c | 1493 | OP_47C0 (void) |
c906108c SS |
1494 | { |
1495 | unsigned int op0, op1, op2; | |
1496 | int temp; | |
1497 | ||
1498 | trace_input ("not1", OP_BIT, 0); | |
1499 | op0 = State.regs[ OP[0] ]; | |
1500 | op1 = OP[1] & 0x7; | |
1501 | temp = EXTEND16 (OP[2]); | |
1502 | op2 = temp; | |
1503 | temp = load_mem (op0 + op2, 1); | |
1504 | PSW &= ~PSW_Z; | |
1505 | if ((temp & (1 << op1)) == 0) | |
1506 | PSW |= PSW_Z; | |
1507 | temp ^= (1 << op1); | |
1508 | store_mem (op0 + op2, 1, temp); | |
1509 | trace_output (OP_BIT); | |
1510 | ||
1511 | return 4; | |
1512 | } | |
1513 | ||
1514 | /* clr1 */ | |
1515 | int | |
a3976a7c | 1516 | OP_87C0 (void) |
c906108c SS |
1517 | { |
1518 | unsigned int op0, op1, op2; | |
1519 | int temp; | |
1520 | ||
1521 | trace_input ("clr1", OP_BIT, 0); | |
1522 | op0 = State.regs[ OP[0] ]; | |
1523 | op1 = OP[1] & 0x7; | |
1524 | temp = EXTEND16 (OP[2]); | |
1525 | op2 = temp; | |
1526 | temp = load_mem (op0 + op2, 1); | |
1527 | PSW &= ~PSW_Z; | |
1528 | if ((temp & (1 << op1)) == 0) | |
1529 | PSW |= PSW_Z; | |
1530 | temp &= ~(1 << op1); | |
1531 | store_mem (op0 + op2, 1, temp); | |
1532 | trace_output (OP_BIT); | |
1533 | ||
1534 | return 4; | |
1535 | } | |
1536 | ||
1537 | /* tst1 */ | |
1538 | int | |
a3976a7c | 1539 | OP_C7C0 (void) |
c906108c SS |
1540 | { |
1541 | unsigned int op0, op1, op2; | |
1542 | int temp; | |
1543 | ||
1544 | trace_input ("tst1", OP_BIT, 0); | |
1545 | op0 = State.regs[ OP[0] ]; | |
1546 | op1 = OP[1] & 0x7; | |
1547 | temp = EXTEND16 (OP[2]); | |
1548 | op2 = temp; | |
1549 | temp = load_mem (op0 + op2, 1); | |
1550 | PSW &= ~PSW_Z; | |
1551 | if ((temp & (1 << op1)) == 0) | |
1552 | PSW |= PSW_Z; | |
1553 | trace_output (OP_BIT); | |
1554 | ||
1555 | return 4; | |
1556 | } | |
1557 | ||
1558 | /* di */ | |
1559 | int | |
a3976a7c | 1560 | OP_16007E0 (void) |
c906108c SS |
1561 | { |
1562 | trace_input ("di", OP_NONE, 0); | |
1563 | PSW |= PSW_ID; | |
1564 | trace_output (OP_NONE); | |
1565 | ||
1566 | return 4; | |
1567 | } | |
1568 | ||
1569 | /* ei */ | |
1570 | int | |
a3976a7c | 1571 | OP_16087E0 (void) |
c906108c SS |
1572 | { |
1573 | trace_input ("ei", OP_NONE, 0); | |
1574 | PSW &= ~PSW_ID; | |
1575 | trace_output (OP_NONE); | |
1576 | ||
1577 | return 4; | |
1578 | } | |
1579 | ||
1580 | /* halt */ | |
1581 | int | |
a3976a7c | 1582 | OP_12007E0 (void) |
c906108c SS |
1583 | { |
1584 | trace_input ("halt", OP_NONE, 0); | |
1585 | /* FIXME this should put processor into a mode where NMI still handled */ | |
1586 | trace_output (OP_NONE); | |
1587 | sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, | |
1588 | sim_stopped, SIM_SIGTRAP); | |
1589 | return 0; | |
1590 | } | |
1591 | ||
1592 | /* trap */ | |
1593 | int | |
a3976a7c | 1594 | OP_10007E0 (void) |
c906108c SS |
1595 | { |
1596 | trace_input ("trap", OP_TRAP, 0); | |
1597 | trace_output (OP_TRAP); | |
1598 | ||
1599 | /* Trap 31 is used for simulating OS I/O functions */ | |
1600 | ||
1601 | if (OP[0] == 31) | |
1602 | { | |
1603 | int save_errno = errno; | |
1604 | errno = 0; | |
1605 | ||
1606 | /* Registers passed to trap 0 */ | |
1607 | ||
1608 | #define FUNC State.regs[6] /* function number, return value */ | |
1609 | #define PARM1 State.regs[7] /* optional parm 1 */ | |
1610 | #define PARM2 State.regs[8] /* optional parm 2 */ | |
1611 | #define PARM3 State.regs[9] /* optional parm 3 */ | |
1612 | ||
1613 | /* Registers set by trap 0 */ | |
1614 | ||
1615 | #define RETVAL State.regs[10] /* return value */ | |
1616 | #define RETERR State.regs[11] /* return error code */ | |
1617 | ||
1618 | /* Turn a pointer in a register into a pointer into real memory. */ | |
1619 | ||
1620 | #define MEMPTR(x) (map (x)) | |
1621 | ||
d0f0baa2 KB |
1622 | RETERR = 0; |
1623 | ||
c906108c SS |
1624 | switch (FUNC) |
1625 | { | |
1626 | ||
1627 | #ifdef HAVE_FORK | |
1628 | #ifdef TARGET_SYS_fork | |
1629 | case TARGET_SYS_fork: | |
1630 | RETVAL = fork (); | |
d0f0baa2 | 1631 | RETERR = errno; |
c906108c SS |
1632 | break; |
1633 | #endif | |
1634 | #endif | |
1635 | ||
1636 | #ifdef HAVE_EXECVE | |
1637 | #ifdef TARGET_SYS_execv | |
1638 | case TARGET_SYS_execve: | |
1639 | { | |
1640 | char *path = fetch_str (simulator, PARM1); | |
1641 | char **argv = fetch_argv (simulator, PARM2); | |
1642 | char **envp = fetch_argv (simulator, PARM3); | |
1f8ef36f | 1643 | RETVAL = execve (path, (void *)argv, (void *)envp); |
d79fe0d6 | 1644 | free (path); |
c906108c SS |
1645 | freeargv (argv); |
1646 | freeargv (envp); | |
d0f0baa2 | 1647 | RETERR = errno; |
c906108c SS |
1648 | break; |
1649 | } | |
1650 | #endif | |
1651 | #endif | |
1652 | ||
1653 | #if HAVE_EXECV | |
1654 | #ifdef TARGET_SYS_execv | |
1655 | case TARGET_SYS_execv: | |
1656 | { | |
1657 | char *path = fetch_str (simulator, PARM1); | |
1658 | char **argv = fetch_argv (simulator, PARM2); | |
1f8ef36f | 1659 | RETVAL = execv (path, (void *)argv); |
d79fe0d6 | 1660 | free (path); |
c906108c | 1661 | freeargv (argv); |
d0f0baa2 | 1662 | RETERR = errno; |
c906108c SS |
1663 | break; |
1664 | } | |
1665 | #endif | |
1666 | #endif | |
1667 | ||
1668 | #if 0 | |
1669 | #ifdef TARGET_SYS_pipe | |
1670 | case TARGET_SYS_pipe: | |
1671 | { | |
1672 | reg_t buf; | |
1673 | int host_fd[2]; | |
1674 | ||
1675 | buf = PARM1; | |
1676 | RETVAL = pipe (host_fd); | |
1677 | SW (buf, host_fd[0]); | |
a3976a7c | 1678 | buf += sizeof (uint16); |
c906108c | 1679 | SW (buf, host_fd[1]); |
d0f0baa2 | 1680 | RETERR = errno; |
c906108c SS |
1681 | } |
1682 | break; | |
1683 | #endif | |
1684 | #endif | |
1685 | ||
1686 | #if 0 | |
1687 | #ifdef TARGET_SYS_wait | |
1688 | case TARGET_SYS_wait: | |
1689 | { | |
1690 | int status; | |
1691 | ||
1692 | RETVAL = wait (&status); | |
1693 | SW (PARM1, status); | |
d0f0baa2 | 1694 | RETERR = errno; |
c906108c SS |
1695 | } |
1696 | break; | |
1697 | #endif | |
1698 | #endif | |
1699 | ||
1700 | #ifdef TARGET_SYS_read | |
1701 | case TARGET_SYS_read: | |
1702 | { | |
1703 | char *buf = zalloc (PARM3); | |
1704 | RETVAL = sim_io_read (simulator, PARM1, buf, PARM3); | |
a3976a7c | 1705 | sim_write (simulator, PARM2, (unsigned char *) buf, PARM3); |
d79fe0d6 | 1706 | free (buf); |
d0f0baa2 KB |
1707 | if ((int) RETVAL < 0) |
1708 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1709 | break; |
1710 | } | |
1711 | #endif | |
1712 | ||
1713 | #ifdef TARGET_SYS_write | |
1714 | case TARGET_SYS_write: | |
1715 | { | |
1716 | char *buf = zalloc (PARM3); | |
a3976a7c | 1717 | sim_read (simulator, PARM2, (unsigned char *) buf, PARM3); |
c906108c SS |
1718 | if (PARM1 == 1) |
1719 | RETVAL = sim_io_write_stdout (simulator, buf, PARM3); | |
1720 | else | |
1721 | RETVAL = sim_io_write (simulator, PARM1, buf, PARM3); | |
d79fe0d6 | 1722 | free (buf); |
d0f0baa2 KB |
1723 | if ((int) RETVAL < 0) |
1724 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1725 | break; |
1726 | } | |
1727 | #endif | |
1728 | ||
1729 | #ifdef TARGET_SYS_lseek | |
1730 | case TARGET_SYS_lseek: | |
1731 | RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3); | |
d0f0baa2 KB |
1732 | if ((int) RETVAL < 0) |
1733 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1734 | break; |
1735 | #endif | |
1736 | ||
1737 | #ifdef TARGET_SYS_close | |
1738 | case TARGET_SYS_close: | |
1739 | RETVAL = sim_io_close (simulator, PARM1); | |
d0f0baa2 KB |
1740 | if ((int) RETVAL < 0) |
1741 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1742 | break; |
1743 | #endif | |
1744 | ||
1745 | #ifdef TARGET_SYS_open | |
1746 | case TARGET_SYS_open: | |
1747 | { | |
1748 | char *buf = fetch_str (simulator, PARM1); | |
1749 | RETVAL = sim_io_open (simulator, buf, PARM2); | |
d79fe0d6 | 1750 | free (buf); |
d0f0baa2 KB |
1751 | if ((int) RETVAL < 0) |
1752 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1753 | break; |
1754 | } | |
1755 | #endif | |
1756 | ||
1757 | #ifdef TARGET_SYS_exit | |
1758 | case TARGET_SYS_exit: | |
1759 | if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0) | |
1760 | /* get signal encoded by kill */ | |
1761 | sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, | |
1762 | sim_signalled, PARM1 & 0xffff); | |
1763 | else if (PARM1 == 0xdead) | |
1764 | /* old libraries */ | |
1765 | sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, | |
1766 | sim_stopped, SIM_SIGABRT); | |
1767 | else | |
1768 | /* PARM1 has exit status */ | |
1769 | sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, | |
1770 | sim_exited, PARM1); | |
1771 | break; | |
1772 | #endif | |
1773 | ||
c906108c SS |
1774 | #ifdef TARGET_SYS_stat |
1775 | case TARGET_SYS_stat: /* added at hmsi */ | |
1776 | /* stat system call */ | |
1777 | { | |
1778 | struct stat host_stat; | |
1779 | reg_t buf; | |
1780 | char *path = fetch_str (simulator, PARM1); | |
1781 | ||
d0f0baa2 | 1782 | RETVAL = sim_io_stat (simulator, path, &host_stat); |
c906108c | 1783 | |
d79fe0d6 | 1784 | free (path); |
c906108c SS |
1785 | buf = PARM2; |
1786 | ||
1787 | /* Just wild-assed guesses. */ | |
1788 | store_mem (buf, 2, host_stat.st_dev); | |
1789 | store_mem (buf + 2, 2, host_stat.st_ino); | |
1790 | store_mem (buf + 4, 4, host_stat.st_mode); | |
1791 | store_mem (buf + 8, 2, host_stat.st_nlink); | |
1792 | store_mem (buf + 10, 2, host_stat.st_uid); | |
1793 | store_mem (buf + 12, 2, host_stat.st_gid); | |
1794 | store_mem (buf + 14, 2, host_stat.st_rdev); | |
1795 | store_mem (buf + 16, 4, host_stat.st_size); | |
1796 | store_mem (buf + 20, 4, host_stat.st_atime); | |
1797 | store_mem (buf + 28, 4, host_stat.st_mtime); | |
1798 | store_mem (buf + 36, 4, host_stat.st_ctime); | |
d0f0baa2 KB |
1799 | |
1800 | if ((int) RETVAL < 0) | |
1801 | RETERR = sim_io_get_errno (simulator); | |
1802 | } | |
1803 | break; | |
1804 | #endif | |
1805 | ||
1806 | #ifdef TARGET_SYS_fstat | |
1807 | case TARGET_SYS_fstat: | |
1808 | /* fstat system call */ | |
1809 | { | |
1810 | struct stat host_stat; | |
1811 | reg_t buf; | |
1812 | ||
1813 | RETVAL = sim_io_fstat (simulator, PARM1, &host_stat); | |
1814 | ||
1815 | buf = PARM2; | |
1816 | ||
1817 | /* Just wild-assed guesses. */ | |
1818 | store_mem (buf, 2, host_stat.st_dev); | |
1819 | store_mem (buf + 2, 2, host_stat.st_ino); | |
1820 | store_mem (buf + 4, 4, host_stat.st_mode); | |
1821 | store_mem (buf + 8, 2, host_stat.st_nlink); | |
1822 | store_mem (buf + 10, 2, host_stat.st_uid); | |
1823 | store_mem (buf + 12, 2, host_stat.st_gid); | |
1824 | store_mem (buf + 14, 2, host_stat.st_rdev); | |
1825 | store_mem (buf + 16, 4, host_stat.st_size); | |
1826 | store_mem (buf + 20, 4, host_stat.st_atime); | |
1827 | store_mem (buf + 28, 4, host_stat.st_mtime); | |
1828 | store_mem (buf + 36, 4, host_stat.st_ctime); | |
1829 | ||
1830 | if ((int) RETVAL < 0) | |
1831 | RETERR = sim_io_get_errno (simulator); | |
c906108c SS |
1832 | } |
1833 | break; | |
1834 | #endif | |
d0f0baa2 KB |
1835 | |
1836 | #ifdef TARGET_SYS_rename | |
1837 | case TARGET_SYS_rename: | |
1838 | { | |
1839 | char *oldpath = fetch_str (simulator, PARM1); | |
1840 | char *newpath = fetch_str (simulator, PARM2); | |
1841 | RETVAL = sim_io_rename (simulator, oldpath, newpath); | |
1842 | free (oldpath); | |
1843 | free (newpath); | |
1844 | if ((int) RETVAL < 0) | |
1845 | RETERR = sim_io_get_errno (simulator); | |
1846 | } | |
1847 | break; | |
1848 | #endif | |
1849 | ||
1850 | #ifdef TARGET_SYS_unlink | |
1851 | case TARGET_SYS_unlink: | |
1852 | { | |
1853 | char *path = fetch_str (simulator, PARM1); | |
1854 | RETVAL = sim_io_unlink (simulator, path); | |
1855 | free (path); | |
1856 | if ((int) RETVAL < 0) | |
1857 | RETERR = sim_io_get_errno (simulator); | |
1858 | } | |
1859 | break; | |
c906108c SS |
1860 | #endif |
1861 | ||
c906108c SS |
1862 | #ifdef TARGET_SYS_chown |
1863 | case TARGET_SYS_chown: | |
1864 | { | |
1865 | char *path = fetch_str (simulator, PARM1); | |
1866 | RETVAL = chown (path, PARM2, PARM3); | |
d79fe0d6 | 1867 | free (path); |
d0f0baa2 | 1868 | RETERR = errno; |
c906108c SS |
1869 | } |
1870 | break; | |
1871 | #endif | |
c906108c SS |
1872 | |
1873 | #if HAVE_CHMOD | |
1874 | #ifdef TARGET_SYS_chmod | |
1875 | case TARGET_SYS_chmod: | |
1876 | { | |
1877 | char *path = fetch_str (simulator, PARM1); | |
1878 | RETVAL = chmod (path, PARM2); | |
d79fe0d6 | 1879 | free (path); |
d0f0baa2 | 1880 | RETERR = errno; |
c906108c SS |
1881 | } |
1882 | break; | |
1883 | #endif | |
1884 | #endif | |
1885 | ||
1886 | #ifdef TARGET_SYS_time | |
1887 | #if HAVE_TIME | |
1888 | case TARGET_SYS_time: | |
1889 | { | |
1890 | time_t now; | |
1891 | RETVAL = time (&now); | |
1892 | store_mem (PARM1, 4, now); | |
d0f0baa2 | 1893 | RETERR = errno; |
c906108c SS |
1894 | } |
1895 | break; | |
1896 | #endif | |
1897 | #endif | |
1898 | ||
1899 | #if !defined(__GO32__) && !defined(_WIN32) | |
1900 | #ifdef TARGET_SYS_times | |
1901 | case TARGET_SYS_times: | |
1902 | { | |
1903 | struct tms tms; | |
1904 | RETVAL = times (&tms); | |
1905 | store_mem (PARM1, 4, tms.tms_utime); | |
1906 | store_mem (PARM1 + 4, 4, tms.tms_stime); | |
1907 | store_mem (PARM1 + 8, 4, tms.tms_cutime); | |
1908 | store_mem (PARM1 + 12, 4, tms.tms_cstime); | |
44b30b7f | 1909 | RETERR = errno; |
c906108c SS |
1910 | break; |
1911 | } | |
1912 | #endif | |
1913 | #endif | |
1914 | ||
1915 | #ifdef TARGET_SYS_gettimeofday | |
1916 | #if !defined(__GO32__) && !defined(_WIN32) | |
1917 | case TARGET_SYS_gettimeofday: | |
1918 | { | |
1919 | struct timeval t; | |
1920 | struct timezone tz; | |
1921 | RETVAL = gettimeofday (&t, &tz); | |
1922 | store_mem (PARM1, 4, t.tv_sec); | |
1923 | store_mem (PARM1 + 4, 4, t.tv_usec); | |
1924 | store_mem (PARM2, 4, tz.tz_minuteswest); | |
1925 | store_mem (PARM2 + 4, 4, tz.tz_dsttime); | |
d0f0baa2 | 1926 | RETERR = errno; |
c906108c SS |
1927 | break; |
1928 | } | |
1929 | #endif | |
1930 | #endif | |
1931 | ||
1932 | #ifdef TARGET_SYS_utime | |
1933 | #if HAVE_UTIME | |
1934 | case TARGET_SYS_utime: | |
1935 | { | |
1936 | /* Cast the second argument to void *, to avoid type mismatch | |
1937 | if a prototype is present. */ | |
1938 | sim_io_error (simulator, "Utime not supported"); | |
1939 | /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */ | |
1940 | } | |
1941 | break; | |
1942 | #endif | |
1943 | #endif | |
1944 | ||
1945 | default: | |
1946 | abort (); | |
1947 | } | |
c906108c SS |
1948 | errno = save_errno; |
1949 | ||
1950 | return 4; | |
1951 | } | |
1952 | else | |
1953 | { /* Trap 0 -> 30 */ | |
1954 | EIPC = PC + 4; | |
1955 | EIPSW = PSW; | |
1956 | /* Mask out EICC */ | |
1957 | ECR &= 0xffff0000; | |
1958 | ECR |= 0x40 + OP[0]; | |
1959 | /* Flag that we are now doing exception processing. */ | |
1960 | PSW |= PSW_EP | PSW_ID; | |
2e8162ce | 1961 | PC = (OP[0] < 0x10) ? 0x40 : 0x50; |
c906108c SS |
1962 | |
1963 | return 0; | |
1964 | } | |
1965 | } | |
1966 | ||
1967 | /* tst1 reg2, [reg1] */ | |
1968 | int | |
1969 | OP_E607E0 (void) | |
1970 | { | |
1971 | int temp; | |
1972 | ||
1973 | trace_input ("tst1", OP_BIT, 1); | |
1974 | ||
1975 | temp = load_mem (State.regs[ OP[0] ], 1); | |
1976 | ||
1977 | PSW &= ~PSW_Z; | |
30458d39 | 1978 | if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0) |
c906108c SS |
1979 | PSW |= PSW_Z; |
1980 | ||
1981 | trace_output (OP_BIT); | |
1982 | ||
1983 | return 4; | |
1984 | } | |
1985 | ||
1986 | /* mulu reg1, reg2, reg3 */ | |
1987 | int | |
1988 | OP_22207E0 (void) | |
1989 | { | |
1990 | trace_input ("mulu", OP_REG_REG_REG, 0); | |
1991 | ||
0da2b665 | 1992 | Multiply64 (0, State.regs[ OP[0] ]); |
c906108c SS |
1993 | |
1994 | trace_output (OP_REG_REG_REG); | |
1995 | ||
1996 | return 4; | |
1997 | } | |
1998 | ||
1999 | #define BIT_CHANGE_OP( name, binop ) \ | |
2000 | unsigned int bit; \ | |
2001 | unsigned int temp; \ | |
2002 | \ | |
2003 | trace_input (name, OP_BIT_CHANGE, 0); \ | |
2004 | \ | |
30458d39 | 2005 | bit = 1 << (State.regs[ OP[1] ] & 0x7); \ |
c906108c SS |
2006 | temp = load_mem (State.regs[ OP[0] ], 1); \ |
2007 | \ | |
2008 | PSW &= ~PSW_Z; \ | |
2009 | if ((temp & bit) == 0) \ | |
2010 | PSW |= PSW_Z; \ | |
2011 | temp binop bit; \ | |
2012 | \ | |
2013 | store_mem (State.regs[ OP[0] ], 1, temp); \ | |
2014 | \ | |
2015 | trace_output (OP_BIT_CHANGE); \ | |
2016 | \ | |
2017 | return 4; | |
2018 | ||
2019 | /* clr1 reg2, [reg1] */ | |
2020 | int | |
2021 | OP_E407E0 (void) | |
2022 | { | |
2023 | BIT_CHANGE_OP ("clr1", &= ~ ); | |
2024 | } | |
2025 | ||
2026 | /* not1 reg2, [reg1] */ | |
2027 | int | |
2028 | OP_E207E0 (void) | |
2029 | { | |
2030 | BIT_CHANGE_OP ("not1", ^= ); | |
2031 | } | |
2032 | ||
2033 | /* set1 */ | |
2034 | int | |
2035 | OP_E007E0 (void) | |
2036 | { | |
2037 | BIT_CHANGE_OP ("set1", |= ); | |
2038 | } | |
2039 | ||
2040 | /* sasf */ | |
2041 | int | |
2042 | OP_20007E0 (void) | |
2043 | { | |
2044 | trace_input ("sasf", OP_EX1, 0); | |
2045 | ||
2046 | State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]); | |
2047 | ||
2048 | trace_output (OP_EX1); | |
2049 | ||
2050 | return 4; | |
2051 | } | |
2052 | ||
2053 | /* This function is courtesy of Sugimoto at NEC, via Seow Tan | |
2054 | (Soew_Tan@el.nec.com) */ | |
2055 | void | |
2056 | divun | |
2057 | ( | |
2058 | unsigned int N, | |
2059 | unsigned long int als, | |
2060 | unsigned long int sfi, | |
2061 | unsigned32 /*unsigned long int*/ * quotient_ptr, | |
2062 | unsigned32 /*unsigned long int*/ * remainder_ptr, | |
0da2b665 | 2063 | int * overflow_ptr |
c906108c SS |
2064 | ) |
2065 | { | |
2066 | unsigned long ald = sfi >> (N - 1); | |
2067 | unsigned long alo = als; | |
2068 | unsigned int Q = 1; | |
2069 | unsigned int C; | |
2070 | unsigned int S = 0; | |
2071 | unsigned int i; | |
2072 | unsigned int R1 = 1; | |
2073 | unsigned int DBZ = (als == 0) ? 1 : 0; | |
2074 | unsigned long alt = Q ? ~als : als; | |
2075 | ||
2076 | /* 1st Loop */ | |
2077 | alo = ald + alt + Q; | |
2078 | C = (((alt >> 31) & (ald >> 31)) | |
2079 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2080 | C = C ^ Q; | |
2081 | Q = ~(C ^ S) & 1; | |
2082 | R1 = (alo == 0) ? 0 : (R1 & Q); | |
2083 | if ((S ^ (alo>>31)) && !C) | |
2084 | { | |
2085 | DBZ = 1; | |
2086 | } | |
2087 | S = alo >> 31; | |
2088 | sfi = (sfi << (32-N+1)) | Q; | |
2089 | ald = (alo << 1) | (sfi >> 31); | |
2090 | ||
2091 | /* 2nd - N-1th Loop */ | |
2092 | for (i = 2; i < N; i++) | |
2093 | { | |
2094 | alt = Q ? ~als : als; | |
2095 | alo = ald + alt + Q; | |
2096 | C = (((alt >> 31) & (ald >> 31)) | |
2097 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2098 | C = C ^ Q; | |
2099 | Q = ~(C ^ S) & 1; | |
2100 | R1 = (alo == 0) ? 0 : (R1 & Q); | |
2101 | if ((S ^ (alo>>31)) && !C && !DBZ) | |
2102 | { | |
2103 | DBZ = 1; | |
2104 | } | |
2105 | S = alo >> 31; | |
2106 | sfi = (sfi << 1) | Q; | |
2107 | ald = (alo << 1) | (sfi >> 31); | |
2108 | } | |
2109 | ||
2110 | /* Nth Loop */ | |
2111 | alt = Q ? ~als : als; | |
2112 | alo = ald + alt + Q; | |
2113 | C = (((alt >> 31) & (ald >> 31)) | |
2114 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2115 | C = C ^ Q; | |
2116 | Q = ~(C ^ S) & 1; | |
2117 | R1 = (alo == 0) ? 0 : (R1 & Q); | |
2118 | if ((S ^ (alo>>31)) && !C) | |
2119 | { | |
2120 | DBZ = 1; | |
2121 | } | |
2122 | ||
2123 | * quotient_ptr = (sfi << 1) | Q; | |
2124 | * remainder_ptr = Q ? alo : (alo + als); | |
2125 | * overflow_ptr = DBZ | R1; | |
2126 | } | |
2127 | ||
2128 | /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */ | |
2129 | void | |
2130 | divn | |
2131 | ( | |
2132 | unsigned int N, | |
2133 | unsigned long int als, | |
2134 | unsigned long int sfi, | |
2135 | signed32 /*signed long int*/ * quotient_ptr, | |
2136 | signed32 /*signed long int*/ * remainder_ptr, | |
0da2b665 | 2137 | int * overflow_ptr |
c906108c SS |
2138 | ) |
2139 | { | |
2140 | unsigned long ald = (signed long) sfi >> (N - 1); | |
2141 | unsigned long alo = als; | |
2142 | unsigned int SS = als >> 31; | |
2143 | unsigned int SD = sfi >> 31; | |
2144 | unsigned int R1 = 1; | |
2145 | unsigned int OV; | |
2146 | unsigned int DBZ = als == 0 ? 1 : 0; | |
2147 | unsigned int Q = ~(SS ^ SD) & 1; | |
2148 | unsigned int C; | |
2149 | unsigned int S; | |
2150 | unsigned int i; | |
2151 | unsigned long alt = Q ? ~als : als; | |
2152 | ||
2153 | ||
2154 | /* 1st Loop */ | |
2155 | ||
2156 | alo = ald + alt + Q; | |
2157 | C = (((alt >> 31) & (ald >> 31)) | |
2158 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2159 | Q = C ^ SS; | |
2160 | R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); | |
2161 | S = alo >> 31; | |
2162 | sfi = (sfi << (32-N+1)) | Q; | |
2163 | ald = (alo << 1) | (sfi >> 31); | |
2164 | if ((alo >> 31) ^ (ald >> 31)) | |
2165 | { | |
2166 | DBZ = 1; | |
2167 | } | |
2168 | ||
2169 | /* 2nd - N-1th Loop */ | |
2170 | ||
2171 | for (i = 2; i < N; i++) | |
2172 | { | |
2173 | alt = Q ? ~als : als; | |
2174 | alo = ald + alt + Q; | |
2175 | C = (((alt >> 31) & (ald >> 31)) | |
2176 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2177 | Q = C ^ SS; | |
2178 | R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); | |
2179 | S = alo >> 31; | |
2180 | sfi = (sfi << 1) | Q; | |
2181 | ald = (alo << 1) | (sfi >> 31); | |
2182 | if ((alo >> 31) ^ (ald >> 31)) | |
2183 | { | |
2184 | DBZ = 1; | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | /* Nth Loop */ | |
2189 | alt = Q ? ~als : als; | |
2190 | alo = ald + alt + Q; | |
2191 | C = (((alt >> 31) & (ald >> 31)) | |
2192 | | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); | |
2193 | Q = C ^ SS; | |
2194 | R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); | |
2195 | sfi = (sfi << (32-N+1)); | |
2196 | ald = alo; | |
2197 | ||
2198 | /* End */ | |
2199 | if (alo != 0) | |
2200 | { | |
2201 | alt = Q ? ~als : als; | |
2202 | alo = ald + alt + Q; | |
2203 | } | |
2204 | R1 = R1 & ((~alo >> 31) ^ SD); | |
2205 | if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald; | |
2206 | if (N != 32) | |
2207 | ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q; | |
2208 | else | |
2209 | ald = sfi = sfi | Q; | |
2210 | ||
2211 | OV = DBZ | ((alo == 0) ? 0 : R1); | |
2212 | ||
2213 | * remainder_ptr = alo; | |
2214 | ||
2215 | /* Adj */ | |
2216 | if (((alo != 0) && ((SS ^ SD) ^ R1)) | |
2217 | || ((alo == 0) && (SS ^ R1))) | |
2218 | alo = ald + 1; | |
2219 | else | |
2220 | alo = ald; | |
2221 | ||
2222 | OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31)); | |
2223 | ||
2224 | * quotient_ptr = alo; | |
2225 | * overflow_ptr = OV; | |
2226 | } | |
2227 | ||
2228 | /* sdivun imm5, reg1, reg2, reg3 */ | |
2229 | int | |
2230 | OP_1C207E0 (void) | |
2231 | { | |
2232 | unsigned32 /*unsigned long int*/ quotient; | |
2233 | unsigned32 /*unsigned long int*/ remainder; | |
2234 | unsigned long int divide_by; | |
2235 | unsigned long int divide_this; | |
0da2b665 | 2236 | int overflow = 0; |
c906108c SS |
2237 | unsigned int imm5; |
2238 | ||
2239 | trace_input ("sdivun", OP_IMM_REG_REG_REG, 0); | |
2240 | ||
2241 | imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); | |
2242 | ||
2243 | divide_by = State.regs[ OP[0] ]; | |
2244 | divide_this = State.regs[ OP[1] ] << imm5; | |
2245 | ||
2246 | divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); | |
2247 | ||
2248 | State.regs[ OP[1] ] = quotient; | |
2249 | State.regs[ OP[2] >> 11 ] = remainder; | |
2250 | ||
2251 | /* Set condition codes. */ | |
2252 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
2253 | ||
2254 | if (overflow) PSW |= PSW_OV; | |
2255 | if (quotient == 0) PSW |= PSW_Z; | |
2256 | if (quotient & 0x80000000) PSW |= PSW_S; | |
2257 | ||
2258 | trace_output (OP_IMM_REG_REG_REG); | |
2259 | ||
2260 | return 4; | |
2261 | } | |
2262 | ||
2263 | /* sdivn imm5, reg1, reg2, reg3 */ | |
2264 | int | |
2265 | OP_1C007E0 (void) | |
2266 | { | |
2267 | signed32 /*signed long int*/ quotient; | |
2268 | signed32 /*signed long int*/ remainder; | |
2269 | signed long int divide_by; | |
2270 | signed long int divide_this; | |
0da2b665 | 2271 | int overflow = 0; |
c906108c SS |
2272 | unsigned int imm5; |
2273 | ||
2274 | trace_input ("sdivn", OP_IMM_REG_REG_REG, 0); | |
2275 | ||
2276 | imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); | |
2277 | ||
98e460c3 DD |
2278 | divide_by = (signed32) State.regs[ OP[0] ]; |
2279 | divide_this = (signed32) (State.regs[ OP[1] ] << imm5); | |
c906108c SS |
2280 | |
2281 | divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); | |
2282 | ||
2283 | State.regs[ OP[1] ] = quotient; | |
2284 | State.regs[ OP[2] >> 11 ] = remainder; | |
2285 | ||
2286 | /* Set condition codes. */ | |
2287 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
2288 | ||
2289 | if (overflow) PSW |= PSW_OV; | |
2290 | if (quotient == 0) PSW |= PSW_Z; | |
2291 | if (quotient < 0) PSW |= PSW_S; | |
2292 | ||
2293 | trace_output (OP_IMM_REG_REG_REG); | |
2294 | ||
2295 | return 4; | |
2296 | } | |
2297 | ||
2298 | /* sdivhun imm5, reg1, reg2, reg3 */ | |
2299 | int | |
2300 | OP_18207E0 (void) | |
2301 | { | |
2302 | unsigned32 /*unsigned long int*/ quotient; | |
2303 | unsigned32 /*unsigned long int*/ remainder; | |
2304 | unsigned long int divide_by; | |
2305 | unsigned long int divide_this; | |
0da2b665 | 2306 | int overflow = 0; |
c906108c SS |
2307 | unsigned int imm5; |
2308 | ||
2309 | trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0); | |
2310 | ||
2311 | imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); | |
2312 | ||
2313 | divide_by = State.regs[ OP[0] ] & 0xffff; | |
2314 | divide_this = State.regs[ OP[1] ] << imm5; | |
2315 | ||
2316 | divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); | |
2317 | ||
2318 | State.regs[ OP[1] ] = quotient; | |
2319 | State.regs[ OP[2] >> 11 ] = remainder; | |
2320 | ||
2321 | /* Set condition codes. */ | |
2322 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
2323 | ||
2324 | if (overflow) PSW |= PSW_OV; | |
2325 | if (quotient == 0) PSW |= PSW_Z; | |
2326 | if (quotient & 0x80000000) PSW |= PSW_S; | |
2327 | ||
2328 | trace_output (OP_IMM_REG_REG_REG); | |
2329 | ||
2330 | return 4; | |
2331 | } | |
2332 | ||
2333 | /* sdivhn imm5, reg1, reg2, reg3 */ | |
2334 | int | |
2335 | OP_18007E0 (void) | |
2336 | { | |
2337 | signed32 /*signed long int*/ quotient; | |
2338 | signed32 /*signed long int*/ remainder; | |
2339 | signed long int divide_by; | |
2340 | signed long int divide_this; | |
0da2b665 | 2341 | int overflow = 0; |
c906108c SS |
2342 | unsigned int imm5; |
2343 | ||
2344 | trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0); | |
2345 | ||
2346 | imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); | |
2347 | ||
2348 | divide_by = EXTEND16 (State.regs[ OP[0] ]); | |
98e460c3 | 2349 | divide_this = (signed32) (State.regs[ OP[1] ] << imm5); |
c906108c SS |
2350 | |
2351 | divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); | |
2352 | ||
2353 | State.regs[ OP[1] ] = quotient; | |
2354 | State.regs[ OP[2] >> 11 ] = remainder; | |
2355 | ||
2356 | /* Set condition codes. */ | |
2357 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
2358 | ||
2359 | if (overflow) PSW |= PSW_OV; | |
2360 | if (quotient == 0) PSW |= PSW_Z; | |
2361 | if (quotient < 0) PSW |= PSW_S; | |
2362 | ||
2363 | trace_output (OP_IMM_REG_REG_REG); | |
2364 | ||
2365 | return 4; | |
2366 | } | |
2367 | ||
2368 | /* divu reg1, reg2, reg3 */ | |
2369 | int | |
2370 | OP_2C207E0 (void) | |
2371 | { | |
2372 | unsigned long int quotient; | |
2373 | unsigned long int remainder; | |
2374 | unsigned long int divide_by; | |
2375 | unsigned long int divide_this; | |
0da2b665 | 2376 | int overflow = 0; |
c906108c SS |
2377 | |
2378 | trace_input ("divu", OP_REG_REG_REG, 0); | |
2379 | ||
2380 | /* Compute the result. */ | |
2381 | ||
2382 | divide_by = State.regs[ OP[0] ]; | |
2383 | divide_this = State.regs[ OP[1] ]; | |
2384 | ||
2385 | if (divide_by == 0) | |
2386 | { | |
c5fbc25b | 2387 | PSW |= PSW_OV; |
c906108c | 2388 | } |
c5fbc25b DD |
2389 | else |
2390 | { | |
2391 | State.regs[ OP[1] ] = quotient = divide_this / divide_by; | |
2392 | State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; | |
c906108c | 2393 | |
c5fbc25b DD |
2394 | /* Set condition codes. */ |
2395 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
c906108c | 2396 | |
c5fbc25b DD |
2397 | if (overflow) PSW |= PSW_OV; |
2398 | if (quotient == 0) PSW |= PSW_Z; | |
2399 | if (quotient & 0x80000000) PSW |= PSW_S; | |
2400 | } | |
c906108c SS |
2401 | |
2402 | trace_output (OP_REG_REG_REG); | |
2403 | ||
2404 | return 4; | |
2405 | } | |
2406 | ||
2407 | /* div reg1, reg2, reg3 */ | |
2408 | int | |
2409 | OP_2C007E0 (void) | |
2410 | { | |
2411 | signed long int quotient; | |
2412 | signed long int remainder; | |
2413 | signed long int divide_by; | |
2414 | signed long int divide_this; | |
c906108c SS |
2415 | |
2416 | trace_input ("div", OP_REG_REG_REG, 0); | |
2417 | ||
2418 | /* Compute the result. */ | |
2419 | ||
98e460c3 | 2420 | divide_by = (signed32) State.regs[ OP[0] ]; |
c906108c SS |
2421 | divide_this = State.regs[ OP[1] ]; |
2422 | ||
c5fbc25b | 2423 | if (divide_by == 0) |
c906108c | 2424 | { |
c5fbc25b | 2425 | PSW |= PSW_OV; |
c906108c | 2426 | } |
98e460c3 | 2427 | else if (divide_by == -1 && divide_this == (1L << 31)) |
c5fbc25b DD |
2428 | { |
2429 | PSW &= ~PSW_Z; | |
2430 | PSW |= PSW_OV | PSW_S; | |
2431 | State.regs[ OP[1] ] = (1 << 31); | |
2432 | State.regs[ OP[2] >> 11 ] = 0; | |
2433 | } | |
2434 | else | |
2435 | { | |
98e460c3 | 2436 | divide_this = (signed32) divide_this; |
c5fbc25b DD |
2437 | State.regs[ OP[1] ] = quotient = divide_this / divide_by; |
2438 | State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; | |
98e460c3 | 2439 | |
c5fbc25b DD |
2440 | /* Set condition codes. */ |
2441 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
c906108c | 2442 | |
c5fbc25b DD |
2443 | if (quotient == 0) PSW |= PSW_Z; |
2444 | if (quotient < 0) PSW |= PSW_S; | |
2445 | } | |
c906108c SS |
2446 | |
2447 | trace_output (OP_REG_REG_REG); | |
2448 | ||
2449 | return 4; | |
2450 | } | |
2451 | ||
2452 | /* divhu reg1, reg2, reg3 */ | |
2453 | int | |
2454 | OP_28207E0 (void) | |
2455 | { | |
2456 | unsigned long int quotient; | |
2457 | unsigned long int remainder; | |
2458 | unsigned long int divide_by; | |
2459 | unsigned long int divide_this; | |
0da2b665 | 2460 | int overflow = 0; |
c906108c SS |
2461 | |
2462 | trace_input ("divhu", OP_REG_REG_REG, 0); | |
2463 | ||
2464 | /* Compute the result. */ | |
2465 | ||
2466 | divide_by = State.regs[ OP[0] ] & 0xffff; | |
2467 | divide_this = State.regs[ OP[1] ]; | |
2468 | ||
2469 | if (divide_by == 0) | |
2470 | { | |
c5fbc25b | 2471 | PSW |= PSW_OV; |
c906108c | 2472 | } |
c5fbc25b DD |
2473 | else |
2474 | { | |
2475 | State.regs[ OP[1] ] = quotient = divide_this / divide_by; | |
2476 | State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; | |
c906108c | 2477 | |
c5fbc25b DD |
2478 | /* Set condition codes. */ |
2479 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
c906108c | 2480 | |
c5fbc25b DD |
2481 | if (overflow) PSW |= PSW_OV; |
2482 | if (quotient == 0) PSW |= PSW_Z; | |
2483 | if (quotient & 0x80000000) PSW |= PSW_S; | |
2484 | } | |
c906108c SS |
2485 | |
2486 | trace_output (OP_REG_REG_REG); | |
2487 | ||
2488 | return 4; | |
2489 | } | |
2490 | ||
2491 | /* divh reg1, reg2, reg3 */ | |
2492 | int | |
2493 | OP_28007E0 (void) | |
2494 | { | |
2495 | signed long int quotient; | |
2496 | signed long int remainder; | |
2497 | signed long int divide_by; | |
2498 | signed long int divide_this; | |
0da2b665 | 2499 | int overflow = 0; |
c906108c SS |
2500 | |
2501 | trace_input ("divh", OP_REG_REG_REG, 0); | |
2502 | ||
2503 | /* Compute the result. */ | |
2504 | ||
c5fbc25b DD |
2505 | divide_by = EXTEND16 (State.regs[ OP[0] ]); |
2506 | divide_this = State.regs[ OP[1] ]; | |
c906108c | 2507 | |
c5fbc25b DD |
2508 | if (divide_by == 0) |
2509 | { | |
2510 | PSW |= PSW_OV; | |
2511 | } | |
98e460c3 | 2512 | else if (divide_by == -1 && divide_this == (1L << 31)) |
c906108c | 2513 | { |
c5fbc25b DD |
2514 | PSW &= ~PSW_Z; |
2515 | PSW |= PSW_OV | PSW_S; | |
2516 | State.regs[ OP[1] ] = (1 << 31); | |
2517 | State.regs[ OP[2] >> 11 ] = 0; | |
c906108c | 2518 | } |
c5fbc25b DD |
2519 | else |
2520 | { | |
98e460c3 | 2521 | divide_this = (signed32) divide_this; |
c5fbc25b DD |
2522 | State.regs[ OP[1] ] = quotient = divide_this / divide_by; |
2523 | State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; | |
c906108c | 2524 | |
c5fbc25b DD |
2525 | /* Set condition codes. */ |
2526 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
c906108c | 2527 | |
c5fbc25b DD |
2528 | if (quotient == 0) PSW |= PSW_Z; |
2529 | if (quotient < 0) PSW |= PSW_S; | |
2530 | } | |
c906108c SS |
2531 | |
2532 | trace_output (OP_REG_REG_REG); | |
2533 | ||
2534 | return 4; | |
2535 | } | |
2536 | ||
2537 | /* mulu imm9, reg2, reg3 */ | |
2538 | int | |
2539 | OP_24207E0 (void) | |
2540 | { | |
2541 | trace_input ("mulu", OP_IMM_REG_REG, 0); | |
2542 | ||
0da2b665 | 2543 | Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)); |
c906108c SS |
2544 | |
2545 | trace_output (OP_IMM_REG_REG); | |
2546 | ||
2547 | return 4; | |
2548 | } | |
2549 | ||
2550 | /* mul imm9, reg2, reg3 */ | |
2551 | int | |
2552 | OP_24007E0 (void) | |
2553 | { | |
2554 | trace_input ("mul", OP_IMM_REG_REG, 0); | |
2555 | ||
0da2b665 | 2556 | Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0))); |
c906108c SS |
2557 | |
2558 | trace_output (OP_IMM_REG_REG); | |
2559 | ||
2560 | return 4; | |
2561 | } | |
2562 | ||
2563 | /* ld.hu */ | |
2564 | int | |
2565 | OP_107E0 (void) | |
2566 | { | |
2567 | int adr; | |
2568 | ||
2569 | trace_input ("ld.hu", OP_LOAD32, 2); | |
2570 | ||
2571 | adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); | |
2572 | adr &= ~0x1; | |
2573 | ||
2574 | State.regs[ OP[1] ] = load_mem (adr, 2); | |
2575 | ||
2576 | trace_output (OP_LOAD32); | |
2577 | ||
2578 | return 4; | |
2579 | } | |
2580 | ||
2581 | ||
2582 | /* ld.bu */ | |
2583 | int | |
2584 | OP_10780 (void) | |
2585 | { | |
2586 | int adr; | |
2587 | ||
2588 | trace_input ("ld.bu", OP_LOAD32, 1); | |
2589 | ||
2590 | adr = (State.regs[ OP[0] ] | |
2591 | + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1))); | |
2592 | ||
2593 | State.regs[ OP[1] ] = load_mem (adr, 1); | |
2594 | ||
2595 | trace_output (OP_LOAD32); | |
2596 | ||
2597 | return 4; | |
2598 | } | |
2599 | ||
2600 | /* prepare list12, imm5, imm32 */ | |
2601 | int | |
2602 | OP_1B0780 (void) | |
2603 | { | |
2604 | int i; | |
2605 | ||
2606 | trace_input ("prepare", OP_PUSHPOP1, 0); | |
2607 | ||
2608 | /* Store the registers with lower number registers being placed at higher addresses. */ | |
2609 | for (i = 0; i < 12; i++) | |
2610 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
2611 | { | |
2612 | SP -= 4; | |
2613 | store_mem (SP, 4, State.regs[ 20 + i ]); | |
2614 | } | |
2615 | ||
2616 | SP -= (OP[3] & 0x3e) << 1; | |
2617 | ||
2618 | EP = load_mem (PC + 4, 4); | |
2619 | ||
2620 | trace_output (OP_PUSHPOP1); | |
2621 | ||
2622 | return 8; | |
2623 | } | |
2624 | ||
2625 | /* prepare list12, imm5, imm16-32 */ | |
2626 | int | |
2627 | OP_130780 (void) | |
2628 | { | |
2629 | int i; | |
2630 | ||
2631 | trace_input ("prepare", OP_PUSHPOP1, 0); | |
2632 | ||
2633 | /* Store the registers with lower number registers being placed at higher addresses. */ | |
2634 | for (i = 0; i < 12; i++) | |
2635 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
2636 | { | |
2637 | SP -= 4; | |
2638 | store_mem (SP, 4, State.regs[ 20 + i ]); | |
2639 | } | |
2640 | ||
2641 | SP -= (OP[3] & 0x3e) << 1; | |
2642 | ||
2643 | EP = load_mem (PC + 4, 2) << 16; | |
2644 | ||
2645 | trace_output (OP_PUSHPOP1); | |
2646 | ||
2647 | return 6; | |
2648 | } | |
2649 | ||
2650 | /* prepare list12, imm5, imm16 */ | |
2651 | int | |
2652 | OP_B0780 (void) | |
2653 | { | |
2654 | int i; | |
2655 | ||
2656 | trace_input ("prepare", OP_PUSHPOP1, 0); | |
2657 | ||
2658 | /* Store the registers with lower number registers being placed at higher addresses. */ | |
2659 | for (i = 0; i < 12; i++) | |
2660 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
2661 | { | |
2662 | SP -= 4; | |
2663 | store_mem (SP, 4, State.regs[ 20 + i ]); | |
2664 | } | |
2665 | ||
2666 | SP -= (OP[3] & 0x3e) << 1; | |
2667 | ||
2668 | EP = EXTEND16 (load_mem (PC + 4, 2)); | |
2669 | ||
2670 | trace_output (OP_PUSHPOP1); | |
2671 | ||
2672 | return 6; | |
2673 | } | |
2674 | ||
2675 | /* prepare list12, imm5, sp */ | |
2676 | int | |
2677 | OP_30780 (void) | |
2678 | { | |
2679 | int i; | |
2680 | ||
2681 | trace_input ("prepare", OP_PUSHPOP1, 0); | |
2682 | ||
2683 | /* Store the registers with lower number registers being placed at higher addresses. */ | |
2684 | for (i = 0; i < 12; i++) | |
2685 | if ((OP[3] & (1 << type1_regs[ i ]))) | |
2686 | { | |
2687 | SP -= 4; | |
2688 | store_mem (SP, 4, State.regs[ 20 + i ]); | |
2689 | } | |
2690 | ||
2691 | SP -= (OP[3] & 0x3e) << 1; | |
2692 | ||
2693 | EP = SP; | |
2694 | ||
2695 | trace_output (OP_PUSHPOP1); | |
2696 | ||
2697 | return 4; | |
2698 | } | |
2699 | ||
2700 | /* mul reg1, reg2, reg3 */ | |
2701 | int | |
2702 | OP_22007E0 (void) | |
2703 | { | |
2704 | trace_input ("mul", OP_REG_REG_REG, 0); | |
2705 | ||
0da2b665 | 2706 | Multiply64 (1, State.regs[ OP[0] ]); |
c906108c SS |
2707 | |
2708 | trace_output (OP_REG_REG_REG); | |
2709 | ||
2710 | return 4; | |
2711 | } | |
2712 | ||
2713 | /* popmh list18 */ | |
2714 | int | |
2715 | OP_307F0 (void) | |
2716 | { | |
2717 | int i; | |
2718 | ||
2719 | trace_input ("popmh", OP_PUSHPOP2, 0); | |
2720 | ||
2721 | if (OP[3] & (1 << 19)) | |
2722 | { | |
2723 | if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) | |
2724 | { | |
2725 | FEPSW = load_mem ( SP & ~ 3, 4); | |
2726 | FEPC = load_mem ((SP + 4) & ~ 3, 4); | |
2727 | } | |
2728 | else | |
2729 | { | |
2730 | EIPSW = load_mem ( SP & ~ 3, 4); | |
2731 | EIPC = load_mem ((SP + 4) & ~ 3, 4); | |
2732 | } | |
2733 | ||
2734 | SP += 8; | |
2735 | } | |
2736 | ||
2737 | /* Load the registers with lower number registers being retrieved from higher addresses. */ | |
2738 | for (i = 16; i--;) | |
2739 | if ((OP[3] & (1 << type2_regs[ i ]))) | |
2740 | { | |
2741 | State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4); | |
2742 | SP += 4; | |
2743 | } | |
2744 | ||
2745 | trace_output (OP_PUSHPOP2); | |
2746 | ||
2747 | return 4; | |
2748 | } | |
2749 | ||
2750 | /* popml lsit18 */ | |
2751 | int | |
2752 | OP_107F0 (void) | |
2753 | { | |
2754 | int i; | |
2755 | ||
2756 | trace_input ("popml", OP_PUSHPOP3, 0); | |
2757 | ||
2758 | if (OP[3] & (1 << 19)) | |
2759 | { | |
2760 | if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) | |
2761 | { | |
2762 | FEPSW = load_mem ( SP & ~ 3, 4); | |
2763 | FEPC = load_mem ((SP + 4) & ~ 3, 4); | |
2764 | } | |
2765 | else | |
2766 | { | |
2767 | EIPSW = load_mem ( SP & ~ 3, 4); | |
2768 | EIPC = load_mem ((SP + 4) & ~ 3, 4); | |
2769 | } | |
2770 | ||
2771 | SP += 8; | |
2772 | } | |
2773 | ||
2774 | if (OP[3] & (1 << 3)) | |
2775 | { | |
2776 | PSW = load_mem (SP & ~ 3, 4); | |
2777 | SP += 4; | |
2778 | } | |
2779 | ||
2780 | /* Load the registers with lower number registers being retrieved from higher addresses. */ | |
2781 | for (i = 15; i--;) | |
2782 | if ((OP[3] & (1 << type3_regs[ i ]))) | |
2783 | { | |
2784 | State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4); | |
2785 | SP += 4; | |
2786 | } | |
2787 | ||
2788 | trace_output (OP_PUSHPOP2); | |
2789 | ||
2790 | return 4; | |
2791 | } | |
2792 | ||
2793 | /* pushmh list18 */ | |
2794 | int | |
2795 | OP_307E0 (void) | |
2796 | { | |
2797 | int i; | |
2798 | ||
2799 | trace_input ("pushmh", OP_PUSHPOP2, 0); | |
2800 | ||
2801 | /* Store the registers with lower number registers being placed at higher addresses. */ | |
2802 | for (i = 0; i < 16; i++) | |
2803 | if ((OP[3] & (1 << type2_regs[ i ]))) | |
2804 | { | |
2805 | SP -= 4; | |
2806 | store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]); | |
2807 | } | |
2808 | ||
2809 | if (OP[3] & (1 << 19)) | |
2810 | { | |
2811 | SP -= 8; | |
2812 | ||
2813 | if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) | |
2814 | { | |
2815 | store_mem ((SP + 4) & ~ 3, 4, FEPC); | |
2816 | store_mem ( SP & ~ 3, 4, FEPSW); | |
2817 | } | |
2818 | else | |
2819 | { | |
2820 | store_mem ((SP + 4) & ~ 3, 4, EIPC); | |
2821 | store_mem ( SP & ~ 3, 4, EIPSW); | |
2822 | } | |
2823 | } | |
2824 | ||
2825 | trace_output (OP_PUSHPOP2); | |
2826 | ||
2827 | return 4; | |
2828 | } | |
2829 | ||
2aaed979 KB |
2830 | /* V850E2R FPU functions */ |
2831 | /* | |
2832 | sim_fpu_status_invalid_snan = 1, -V--- (sim spec.) | |
2833 | sim_fpu_status_invalid_qnan = 2, ----- (sim spec.) | |
2834 | sim_fpu_status_invalid_isi = 4, (inf - inf) -V--- | |
2835 | sim_fpu_status_invalid_idi = 8, (inf / inf) -V--- | |
2836 | sim_fpu_status_invalid_zdz = 16, (0 / 0) -V--- | |
2837 | sim_fpu_status_invalid_imz = 32, (inf * 0) -V--- | |
2838 | sim_fpu_status_invalid_cvi = 64, convert to integer -V--- | |
2839 | sim_fpu_status_invalid_div0 = 128, (X / 0) --Z-- | |
2840 | sim_fpu_status_invalid_cmp = 256, compare ----- (sim spec.) | |
2841 | sim_fpu_status_invalid_sqrt = 512, -V--- | |
2842 | sim_fpu_status_rounded = 1024, I---- | |
2843 | sim_fpu_status_inexact = 2048, I---- (sim spec.) | |
2844 | sim_fpu_status_overflow = 4096, I--O- | |
2845 | sim_fpu_status_underflow = 8192, I---U | |
2846 | sim_fpu_status_denorm = 16384, ----U (sim spec.) | |
2847 | */ | |
2848 | ||
a3976a7c NC |
2849 | void |
2850 | update_fpsr (SIM_DESC sd, sim_fpu_status status, unsigned int mask, unsigned int double_op_p) | |
2aaed979 KB |
2851 | { |
2852 | unsigned int fpsr = FPSR & mask; | |
2853 | ||
2854 | unsigned int flags = 0; | |
2855 | ||
2856 | if (fpsr & FPSR_XEI | |
2857 | && ((status & (sim_fpu_status_rounded | |
2858 | | sim_fpu_status_overflow | |
2859 | | sim_fpu_status_inexact)) | |
2860 | || (status & sim_fpu_status_underflow | |
2861 | && (fpsr & (FPSR_XEU | FPSR_XEI)) == 0 | |
2862 | && fpsr & FPSR_FS))) | |
2863 | { | |
2864 | flags |= FPSR_XCI | FPSR_XPI; | |
2865 | } | |
2866 | ||
2867 | if (fpsr & FPSR_XEV | |
2868 | && (status & (sim_fpu_status_invalid_isi | |
2869 | | sim_fpu_status_invalid_imz | |
2870 | | sim_fpu_status_invalid_zdz | |
2871 | | sim_fpu_status_invalid_idi | |
2872 | | sim_fpu_status_invalid_cvi | |
2873 | | sim_fpu_status_invalid_sqrt | |
2874 | | sim_fpu_status_invalid_snan))) | |
2875 | { | |
2876 | flags |= FPSR_XCV | FPSR_XPV; | |
2877 | } | |
2878 | ||
2879 | if (fpsr & FPSR_XEZ | |
2880 | && (status & sim_fpu_status_invalid_div0)) | |
2881 | { | |
2882 | flags |= FPSR_XCV | FPSR_XPV; | |
2883 | } | |
2884 | ||
2885 | if (fpsr & FPSR_XEO | |
2886 | && (status & sim_fpu_status_overflow)) | |
2887 | { | |
2888 | flags |= FPSR_XCO | FPSR_XPO; | |
2889 | } | |
2890 | ||
2891 | if (((fpsr & FPSR_XEU) || (fpsr & FPSR_FS) == 0) | |
2892 | && (status & (sim_fpu_status_underflow | |
2893 | | sim_fpu_status_denorm))) | |
2894 | { | |
2895 | flags |= FPSR_XCU | FPSR_XPU; | |
2896 | } | |
2897 | ||
2898 | if (flags) | |
2899 | { | |
2900 | FPSR &= ~FPSR_XC; | |
2901 | FPSR |= flags; | |
2902 | ||
a3976a7c | 2903 | SignalExceptionFPE (sd, double_op_p); |
2aaed979 KB |
2904 | } |
2905 | } | |
2906 | ||
a3976a7c | 2907 | /* Exception. */ |
2aaed979 | 2908 | |
a3976a7c NC |
2909 | void |
2910 | SignalException (SIM_DESC sd) | |
2aaed979 KB |
2911 | { |
2912 | if (MPM & MPM_AUE) | |
2913 | { | |
2914 | PSW = PSW & ~(PSW_NPV | PSW_DMP | PSW_IMP); | |
2915 | } | |
2916 | } | |
2917 | ||
a3976a7c NC |
2918 | void |
2919 | SignalExceptionFPE (SIM_DESC sd, unsigned int double_op_p) | |
2aaed979 KB |
2920 | { |
2921 | if (((PSW & (PSW_NP|PSW_ID)) == 0) | |
2922 | || !(FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM))) | |
2923 | { | |
2924 | EIPC = PC; | |
2925 | EIPSW = PSW; | |
2926 | EIIC = (FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM)) | |
2927 | ? 0x71 : 0x72; | |
2928 | PSW |= (PSW_EP | PSW_ID); | |
2929 | PC = 0x70; | |
2930 | ||
a3976a7c | 2931 | SignalException (sd); |
2aaed979 KB |
2932 | } |
2933 | } | |
2934 | ||
a3976a7c NC |
2935 | void |
2936 | check_invalid_snan (SIM_DESC sd, sim_fpu_status status, unsigned int double_op_p) | |
2aaed979 KB |
2937 | { |
2938 | if ((FPSR & FPSR_XEI) | |
2939 | && (status & sim_fpu_status_invalid_snan)) | |
2940 | { | |
2941 | FPSR &= ~FPSR_XC; | |
2942 | FPSR |= FPSR_XCV; | |
2943 | FPSR |= FPSR_XPV; | |
a3976a7c | 2944 | SignalExceptionFPE (sd, double_op_p); |
2aaed979 KB |
2945 | } |
2946 | } | |
2947 | ||
a3976a7c NC |
2948 | int |
2949 | v850_float_compare (SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p) | |
2aaed979 KB |
2950 | { |
2951 | int result = -1; | |
2952 | ||
a3976a7c | 2953 | if (sim_fpu_is_nan (&wop1) || sim_fpu_is_nan (&wop2)) |
2aaed979 KB |
2954 | { |
2955 | if (cmp & 0x8) | |
2956 | { | |
2957 | if (FPSR & FPSR_XEV) | |
2958 | { | |
2959 | FPSR |= FPSR_XCV | FPSR_XPV; | |
a3976a7c | 2960 | SignalExceptionFPE (sd, double_op_p); |
2aaed979 KB |
2961 | } |
2962 | } | |
2963 | ||
2964 | switch (cmp) | |
2965 | { | |
2966 | case FPU_CMP_F: | |
2967 | result = 0; | |
2968 | break; | |
2969 | case FPU_CMP_UN: | |
2970 | result = 1; | |
2971 | break; | |
2972 | case FPU_CMP_EQ: | |
2973 | result = 0; | |
2974 | break; | |
2975 | case FPU_CMP_UEQ: | |
2976 | result = 1; | |
2977 | break; | |
2978 | case FPU_CMP_OLT: | |
2979 | result = 0; | |
2980 | break; | |
2981 | case FPU_CMP_ULT: | |
2982 | result = 1; | |
2983 | break; | |
2984 | case FPU_CMP_OLE: | |
2985 | result = 0; | |
2986 | break; | |
2987 | case FPU_CMP_ULE: | |
2988 | result = 1; | |
2989 | break; | |
2990 | case FPU_CMP_SF: | |
2991 | result = 0; | |
2992 | break; | |
2993 | case FPU_CMP_NGLE: | |
2994 | result = 1; | |
2995 | break; | |
2996 | case FPU_CMP_SEQ: | |
2997 | result = 0; | |
2998 | break; | |
2999 | case FPU_CMP_NGL: | |
3000 | result = 1; | |
3001 | break; | |
3002 | case FPU_CMP_LT: | |
3003 | result = 0; | |
3004 | break; | |
3005 | case FPU_CMP_NGE: | |
3006 | result = 1; | |
3007 | break; | |
3008 | case FPU_CMP_LE: | |
3009 | result = 0; | |
3010 | break; | |
3011 | case FPU_CMP_NGT: | |
3012 | result = 1; | |
3013 | break; | |
3014 | default: | |
a3976a7c | 3015 | abort (); |
2aaed979 KB |
3016 | } |
3017 | } | |
a3976a7c NC |
3018 | else if (sim_fpu_is_infinity (&wop1) && sim_fpu_is_infinity (&wop2) |
3019 | && sim_fpu_sign (&wop1) == sim_fpu_sign (&wop2)) | |
2aaed979 KB |
3020 | { |
3021 | switch (cmp) | |
3022 | { | |
3023 | case FPU_CMP_F: | |
3024 | result = 0; | |
3025 | break; | |
3026 | case FPU_CMP_UN: | |
3027 | result = 0; | |
3028 | break; | |
3029 | case FPU_CMP_EQ: | |
3030 | result = 1; | |
3031 | break; | |
3032 | case FPU_CMP_UEQ: | |
3033 | result = 1; | |
3034 | break; | |
3035 | case FPU_CMP_OLT: | |
3036 | result = 0; | |
3037 | break; | |
3038 | case FPU_CMP_ULT: | |
3039 | result = 0; | |
3040 | break; | |
3041 | case FPU_CMP_OLE: | |
3042 | result = 1; | |
3043 | break; | |
3044 | case FPU_CMP_ULE: | |
3045 | result = 1; | |
3046 | break; | |
3047 | case FPU_CMP_SF: | |
3048 | result = 0; | |
3049 | break; | |
3050 | case FPU_CMP_NGLE: | |
3051 | result = 0; | |
3052 | break; | |
3053 | case FPU_CMP_SEQ: | |
3054 | result = 1; | |
3055 | break; | |
3056 | case FPU_CMP_NGL: | |
3057 | result = 1; | |
3058 | break; | |
3059 | case FPU_CMP_LT: | |
3060 | result = 0; | |
3061 | break; | |
3062 | case FPU_CMP_NGE: | |
3063 | result = 0; | |
3064 | break; | |
3065 | case FPU_CMP_LE: | |
3066 | result = 1; | |
3067 | break; | |
3068 | case FPU_CMP_NGT: | |
3069 | result = 1; | |
3070 | break; | |
3071 | default: | |
a3976a7c | 3072 | abort (); |
2aaed979 KB |
3073 | } |
3074 | } | |
3075 | else | |
3076 | { | |
3077 | int gt = 0,lt = 0,eq = 0, status; | |
3078 | ||
a3976a7c NC |
3079 | status = sim_fpu_cmp (&wop1, &wop2); |
3080 | ||
3081 | switch (status) | |
3082 | { | |
3083 | case SIM_FPU_IS_SNAN: | |
3084 | case SIM_FPU_IS_QNAN: | |
3085 | abort (); | |
3086 | break; | |
3087 | ||
3088 | case SIM_FPU_IS_NINF: | |
3089 | lt = 1; | |
3090 | break; | |
3091 | case SIM_FPU_IS_PINF: | |
3092 | gt = 1; | |
3093 | break; | |
3094 | case SIM_FPU_IS_NNUMBER: | |
3095 | lt = 1; | |
3096 | break; | |
3097 | case SIM_FPU_IS_PNUMBER: | |
3098 | gt = 1; | |
3099 | break; | |
3100 | case SIM_FPU_IS_NDENORM: | |
3101 | lt = 1; | |
3102 | break; | |
3103 | case SIM_FPU_IS_PDENORM: | |
3104 | gt = 1; | |
3105 | break; | |
3106 | case SIM_FPU_IS_NZERO: | |
3107 | case SIM_FPU_IS_PZERO: | |
3108 | eq = 1; | |
3109 | break; | |
3110 | } | |
2aaed979 KB |
3111 | |
3112 | switch (cmp) | |
3113 | { | |
3114 | case FPU_CMP_F: | |
3115 | result = 0; | |
3116 | break; | |
3117 | case FPU_CMP_UN: | |
3118 | result = 0; | |
3119 | break; | |
3120 | case FPU_CMP_EQ: | |
3121 | result = eq; | |
3122 | break; | |
3123 | case FPU_CMP_UEQ: | |
3124 | result = eq; | |
3125 | break; | |
3126 | case FPU_CMP_OLT: | |
3127 | result = lt; | |
3128 | break; | |
3129 | case FPU_CMP_ULT: | |
3130 | result = lt; | |
3131 | break; | |
3132 | case FPU_CMP_OLE: | |
3133 | result = lt || eq; | |
3134 | break; | |
3135 | case FPU_CMP_ULE: | |
3136 | result = lt || eq; | |
3137 | break; | |
3138 | case FPU_CMP_SF: | |
3139 | result = 0; | |
3140 | break; | |
3141 | case FPU_CMP_NGLE: | |
3142 | result = 0; | |
3143 | break; | |
3144 | case FPU_CMP_SEQ: | |
3145 | result = eq; | |
3146 | break; | |
3147 | case FPU_CMP_NGL: | |
3148 | result = eq; | |
3149 | break; | |
3150 | case FPU_CMP_LT: | |
3151 | result = lt; | |
3152 | break; | |
3153 | case FPU_CMP_NGE: | |
3154 | result = lt; | |
3155 | break; | |
3156 | case FPU_CMP_LE: | |
3157 | result = lt || eq; | |
3158 | break; | |
3159 | case FPU_CMP_NGT: | |
3160 | result = lt || eq; | |
3161 | break; | |
3162 | } | |
3163 | } | |
3164 | ||
a3976a7c | 3165 | ASSERT (result != -1); |
2aaed979 KB |
3166 | return result; |
3167 | } | |
3168 | ||
a3976a7c NC |
3169 | void |
3170 | v850_div (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p) | |
2aaed979 KB |
3171 | { |
3172 | signed long int quotient; | |
3173 | signed long int remainder; | |
3174 | signed long int divide_by; | |
3175 | signed long int divide_this; | |
3176 | bfd_boolean overflow = FALSE; | |
3177 | ||
3178 | /* Compute the result. */ | |
3179 | divide_by = op0; | |
3180 | divide_this = op1; | |
a3976a7c | 3181 | |
2aaed979 KB |
3182 | if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31))) |
3183 | { | |
3184 | overflow = TRUE; | |
3185 | divide_by = 1; | |
3186 | } | |
3187 | ||
3188 | quotient = divide_this / divide_by; | |
3189 | remainder = divide_this % divide_by; | |
3190 | ||
3191 | /* Set condition codes. */ | |
3192 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
3193 | ||
3194 | if (overflow) PSW |= PSW_OV; | |
3195 | if (quotient == 0) PSW |= PSW_Z; | |
3196 | if (quotient < 0) PSW |= PSW_S; | |
3197 | ||
3198 | *op2p = quotient; | |
3199 | *op3p = remainder; | |
3200 | } | |
3201 | ||
a3976a7c NC |
3202 | void |
3203 | v850_divu (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p) | |
2aaed979 KB |
3204 | { |
3205 | unsigned long int quotient; | |
3206 | unsigned long int remainder; | |
3207 | unsigned long int divide_by; | |
3208 | unsigned long int divide_this; | |
3209 | bfd_boolean overflow = FALSE; | |
3210 | ||
3211 | /* Compute the result. */ | |
3212 | ||
3213 | divide_by = op0; | |
3214 | divide_this = op1; | |
3215 | ||
3216 | if (divide_by == 0) | |
3217 | { | |
3218 | overflow = TRUE; | |
3219 | divide_by = 1; | |
3220 | } | |
3221 | ||
3222 | quotient = divide_this / divide_by; | |
3223 | remainder = divide_this % divide_by; | |
3224 | ||
3225 | /* Set condition codes. */ | |
3226 | PSW &= ~(PSW_Z | PSW_S | PSW_OV); | |
3227 | ||
3228 | if (overflow) PSW |= PSW_OV; | |
3229 | if (quotient == 0) PSW |= PSW_Z; | |
3230 | if (quotient & 0x80000000) PSW |= PSW_S; | |
3231 | ||
3232 | *op2p = quotient; | |
3233 | *op3p = remainder; | |
3234 | } | |
3235 | ||
a3976a7c NC |
3236 | void |
3237 | v850_sar (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) | |
2aaed979 KB |
3238 | { |
3239 | unsigned int result, z, s, cy; | |
3240 | ||
3241 | op0 &= 0x1f; | |
3242 | result = (signed)op1 >> op0; | |
3243 | ||
3244 | /* Compute the condition codes. */ | |
3245 | z = (result == 0); | |
3246 | s = (result & 0x80000000); | |
3247 | cy = (op1 & (1 << (op0 - 1))); | |
3248 | ||
3249 | /* Store the result and condition codes. */ | |
3250 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
3251 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3252 | | (cy ? PSW_CY : 0)); | |
3253 | ||
3254 | *op2p = result; | |
3255 | } | |
3256 | ||
a3976a7c NC |
3257 | void |
3258 | v850_shl (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) | |
2aaed979 KB |
3259 | { |
3260 | unsigned int result, z, s, cy; | |
3261 | ||
3262 | op0 &= 0x1f; | |
3263 | result = op1 << op0; | |
3264 | ||
3265 | /* Compute the condition codes. */ | |
3266 | z = (result == 0); | |
3267 | s = (result & 0x80000000); | |
3268 | cy = (op1 & (1 << (32 - op0))); | |
3269 | ||
3270 | /* Store the result and condition codes. */ | |
3271 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
3272 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3273 | | (cy ? PSW_CY : 0)); | |
3274 | ||
3275 | *op2p = result; | |
3276 | } | |
3277 | ||
67d7515b NC |
3278 | void |
3279 | v850_rotl (SIM_DESC sd, unsigned int amount, unsigned int src, unsigned int * dest) | |
3280 | { | |
3281 | unsigned int result, z, s, cy; | |
3282 | ||
3283 | amount &= 0x1f; | |
3284 | result = src << amount; | |
3285 | result |= src >> (32 - amount); | |
3286 | ||
3287 | /* Compute the condition codes. */ | |
3288 | z = (result == 0); | |
3289 | s = (result & 0x80000000); | |
3290 | cy = ! (result & 1); | |
3291 | ||
3292 | /* Store the result and condition codes. */ | |
3293 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
3294 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3295 | | (cy ? PSW_CY : 0)); | |
3296 | ||
3297 | * dest = result; | |
3298 | } | |
3299 | ||
3300 | void | |
3301 | v850_bins (SIM_DESC sd, unsigned int source, unsigned int lsb, unsigned int msb, | |
3302 | unsigned int * dest) | |
3303 | { | |
3304 | unsigned int mask; | |
3305 | unsigned int result, pos, width; | |
3306 | unsigned int z, s; | |
3307 | ||
3308 | pos = lsb; | |
3309 | width = (msb - lsb) + 1; | |
3310 | ||
1d19cae7 | 3311 | mask = ~ (-(1 << width)); |
67d7515b NC |
3312 | source &= mask; |
3313 | mask <<= pos; | |
3314 | result = (* dest) & ~ mask; | |
3315 | result |= source << pos; | |
3316 | ||
3317 | /* Compute the condition codes. */ | |
3318 | z = (result == 0); | |
3319 | s = result & 0x80000000; | |
3320 | ||
3321 | /* Store the result and condition codes. */ | |
3322 | PSW &= ~(PSW_Z | PSW_S | PSW_OV ); | |
3323 | PSW |= (z ? PSW_Z : 0) | (s ? PSW_S : 0); | |
3324 | ||
3325 | * dest = result; | |
3326 | } | |
3327 | ||
a3976a7c NC |
3328 | void |
3329 | v850_shr (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) | |
2aaed979 KB |
3330 | { |
3331 | unsigned int result, z, s, cy; | |
3332 | ||
3333 | op0 &= 0x1f; | |
3334 | result = op1 >> op0; | |
3335 | ||
3336 | /* Compute the condition codes. */ | |
3337 | z = (result == 0); | |
3338 | s = (result & 0x80000000); | |
3339 | cy = (op1 & (1 << (op0 - 1))); | |
3340 | ||
3341 | /* Store the result and condition codes. */ | |
3342 | PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); | |
3343 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3344 | | (cy ? PSW_CY : 0)); | |
3345 | ||
3346 | *op2p = result; | |
3347 | } | |
3348 | ||
a3976a7c NC |
3349 | void |
3350 | v850_satadd (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) | |
2aaed979 KB |
3351 | { |
3352 | unsigned int result, z, s, cy, ov, sat; | |
3353 | ||
3354 | result = op0 + op1; | |
3355 | ||
3356 | /* Compute the condition codes. */ | |
3357 | z = (result == 0); | |
3358 | s = (result & 0x80000000); | |
3359 | cy = (result < op0 || result < op1); | |
3360 | ov = ((op0 & 0x80000000) == (op1 & 0x80000000) | |
3361 | && (op0 & 0x80000000) != (result & 0x80000000)); | |
3362 | sat = ov; | |
3363 | ||
3364 | /* Store the result and condition codes. */ | |
3365 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
3366 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3367 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
3368 | | (sat ? PSW_SAT : 0)); | |
3369 | ||
3370 | /* Handle saturated results. */ | |
3371 | if (sat && s) | |
3372 | { | |
3373 | result = 0x7fffffff; | |
3374 | PSW &= ~PSW_S; | |
3375 | } | |
3376 | else if (sat) | |
3377 | { | |
3378 | result = 0x80000000; | |
3379 | PSW |= PSW_S; | |
3380 | } | |
3381 | ||
3382 | *op2p = result; | |
3383 | } | |
3384 | ||
a3976a7c NC |
3385 | void |
3386 | v850_satsub (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p) | |
2aaed979 KB |
3387 | { |
3388 | unsigned int result, z, s, cy, ov, sat; | |
3389 | ||
3390 | /* Compute the result. */ | |
3391 | result = op1 - op0; | |
3392 | ||
3393 | /* Compute the condition codes. */ | |
3394 | z = (result == 0); | |
3395 | s = (result & 0x80000000); | |
3396 | cy = (op1 < op0); | |
3397 | ov = ((op1 & 0x80000000) != (op0 & 0x80000000) | |
3398 | && (op1 & 0x80000000) != (result & 0x80000000)); | |
3399 | sat = ov; | |
3400 | ||
3401 | /* Store the result and condition codes. */ | |
3402 | PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); | |
3403 | PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | |
3404 | | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) | |
3405 | | (sat ? PSW_SAT : 0)); | |
3406 | ||
3407 | /* Handle saturated results. */ | |
3408 | if (sat && s) | |
3409 | { | |
3410 | result = 0x7fffffff; | |
3411 | PSW &= ~PSW_S; | |
3412 | } | |
3413 | else if (sat) | |
3414 | { | |
3415 | result = 0x80000000; | |
3416 | PSW |= PSW_S; | |
3417 | } | |
3418 | ||
3419 | *op2p = result; | |
3420 | } | |
3421 | ||
3422 | unsigned32 | |
a3976a7c NC |
3423 | load_data_mem (SIM_DESC sd, |
3424 | SIM_ADDR addr, | |
3425 | int len) | |
2aaed979 KB |
3426 | { |
3427 | uint32 data; | |
3428 | ||
3429 | switch (len) | |
3430 | { | |
3431 | case 1: | |
3432 | data = sim_core_read_unaligned_1 (STATE_CPU (sd, 0), | |
3433 | PC, read_map, addr); | |
3434 | break; | |
3435 | case 2: | |
3436 | data = sim_core_read_unaligned_2 (STATE_CPU (sd, 0), | |
3437 | PC, read_map, addr); | |
3438 | break; | |
3439 | case 4: | |
3440 | data = sim_core_read_unaligned_4 (STATE_CPU (sd, 0), | |
3441 | PC, read_map, addr); | |
3442 | break; | |
3443 | default: | |
3444 | abort (); | |
3445 | } | |
3446 | return data; | |
3447 | } | |
3448 | ||
3449 | void | |
a3976a7c NC |
3450 | store_data_mem (SIM_DESC sd, |
3451 | SIM_ADDR addr, | |
3452 | int len, | |
3453 | unsigned32 data) | |
2aaed979 KB |
3454 | { |
3455 | switch (len) | |
3456 | { | |
3457 | case 1: | |
a3976a7c | 3458 | store_mem (addr, 1, data); |
2aaed979 KB |
3459 | break; |
3460 | case 2: | |
a3976a7c | 3461 | store_mem (addr, 2, data); |
2aaed979 KB |
3462 | break; |
3463 | case 4: | |
a3976a7c | 3464 | store_mem (addr, 4, data); |
2aaed979 KB |
3465 | break; |
3466 | default: | |
3467 | abort (); | |
3468 | } | |
3469 | } | |
3470 | ||
a3976a7c NC |
3471 | int |
3472 | mpu_load_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg) | |
2aaed979 KB |
3473 | { |
3474 | int result = 1; | |
3475 | ||
3476 | if (PSW & PSW_DMP) | |
3477 | { | |
a3976a7c | 3478 | if (IPE0 && addr >= IPA2ADDR (IPA0L) && addr <= IPA2ADDR (IPA0L) && IPR0) |
2aaed979 KB |
3479 | { |
3480 | /* text area */ | |
3481 | } | |
a3976a7c | 3482 | else if (IPE1 && addr >= IPA2ADDR (IPA1L) && addr <= IPA2ADDR (IPA1L) && IPR1) |
2aaed979 KB |
3483 | { |
3484 | /* text area */ | |
3485 | } | |
a3976a7c | 3486 | else if (IPE2 && addr >= IPA2ADDR (IPA2L) && addr <= IPA2ADDR (IPA2L) && IPR2) |
2aaed979 KB |
3487 | { |
3488 | /* text area */ | |
3489 | } | |
a3976a7c | 3490 | else if (IPE3 && addr >= IPA2ADDR (IPA3L) && addr <= IPA2ADDR (IPA3L) && IPR3) |
2aaed979 KB |
3491 | { |
3492 | /* text area */ | |
3493 | } | |
a3976a7c | 3494 | else if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM)) |
2aaed979 KB |
3495 | { |
3496 | /* preifarallel area */ | |
3497 | } | |
a3976a7c | 3498 | else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU)) |
2aaed979 KB |
3499 | { |
3500 | /* stack area */ | |
3501 | } | |
a3976a7c | 3502 | else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPR0 |
2aaed979 KB |
3503 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) |
3504 | { | |
3505 | /* data area */ | |
3506 | } | |
a3976a7c | 3507 | else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPR1 |
2aaed979 KB |
3508 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) |
3509 | { | |
3510 | /* data area */ | |
3511 | } | |
a3976a7c | 3512 | else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPR2 |
2aaed979 KB |
3513 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) |
3514 | { | |
3515 | /* data area */ | |
3516 | } | |
a3976a7c | 3517 | else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPR3 |
2aaed979 KB |
3518 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) |
3519 | { | |
3520 | /* data area */ | |
3521 | } | |
3522 | else | |
3523 | { | |
3524 | VMECR &= ~(VMECR_VMW | VMECR_VMX); | |
3525 | VMECR |= VMECR_VMR; | |
3526 | VMADR = addr; | |
3527 | VMTID = TID; | |
3528 | FEIC = 0x431; | |
3529 | ||
3530 | PC = 0x30; | |
3531 | ||
a3976a7c | 3532 | SignalException (sd); |
2aaed979 KB |
3533 | result = 0; |
3534 | } | |
3535 | } | |
3536 | ||
3537 | return result; | |
3538 | } | |
3539 | ||
a3976a7c NC |
3540 | int |
3541 | mpu_store_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg) | |
2aaed979 KB |
3542 | { |
3543 | int result = 1; | |
3544 | ||
3545 | if (PSW & PSW_DMP) | |
3546 | { | |
a3976a7c | 3547 | if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM)) |
2aaed979 KB |
3548 | { |
3549 | /* preifarallel area */ | |
3550 | } | |
a3976a7c | 3551 | else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU)) |
2aaed979 KB |
3552 | { |
3553 | /* stack area */ | |
3554 | } | |
a3976a7c | 3555 | else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPW0 |
2aaed979 KB |
3556 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) |
3557 | { | |
3558 | /* data area */ | |
3559 | } | |
a3976a7c | 3560 | else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPW1 |
2aaed979 KB |
3561 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) |
3562 | { | |
3563 | /* data area */ | |
3564 | } | |
a3976a7c | 3565 | else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPW2 |
2aaed979 KB |
3566 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) |
3567 | { | |
3568 | /* data area */ | |
3569 | } | |
a3976a7c | 3570 | else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPW3 |
2aaed979 KB |
3571 | && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1)) |
3572 | { | |
3573 | /* data area */ | |
3574 | } | |
3575 | else | |
3576 | { | |
a3976a7c | 3577 | if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM)) |
2aaed979 KB |
3578 | { |
3579 | FEIC = 0x432; | |
3580 | VPTID = TID; | |
3581 | VPADR = PC; | |
3582 | #ifdef NOT_YET | |
3583 | VIP_PP; | |
3584 | VPECR; | |
3585 | #endif | |
3586 | } | |
3587 | else | |
3588 | { | |
3589 | FEIC = 0x431; | |
3590 | VMTID = TID; | |
3591 | VMADR = VMECR; | |
3592 | VMECR &= ~(VMECR_VMW | VMECR_VMX); | |
3593 | VMECR |= VMECR_VMR; | |
3594 | PC = 0x30; | |
3595 | } | |
3596 | result = 0; | |
3597 | } | |
3598 | } | |
3599 | ||
3600 | return result; | |
3601 | } | |
3602 |