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[thirdparty/binutils-gdb.git] / sim / v850 / simops.c
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c906108c
SS		 1#include "sim-main.h"
2#include "v850_sim.h"
3#include "simops.h"
4
4389ce38
MK		 5#include <sys/types.h>
6
c906108c
SS		 7#ifdef HAVE_UTIME_H
8#include <utime.h>
9#endif
10
11#ifdef HAVE_TIME_H
12#include <time.h>
13#endif
14
15#ifdef HAVE_UNISTD_H
16#include <unistd.h>
17#endif
18
19#ifdef HAVE_STRING_H
20#include <string.h>
21#else
22#ifdef HAVE_STRINGS_H
23#include <strings.h>
24#endif
25#endif
26
27#include "targ-vals.h"
28
29#include "libiberty.h"
30
31#include <errno.h>
32#if !defined(__GO32__) && !defined(_WIN32)
33#include <sys/stat.h>
34#include <sys/times.h>
35#include <sys/time.h>
36#endif
37
38/* This is an array of the bit positions of registers r20 .. r31 in
39 that order in a prepare/dispose instruction. */
40int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
41/* This is an array of the bit positions of registers r16 .. r31 in
42 that order in a push/pop instruction. */
43int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
44/* This is an array of the bit positions of registers r1 .. r15 in
45 that order in a push/pop instruction. */
46int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
47
48#ifdef DEBUG
49#ifndef SIZE_INSTRUCTION
50#define SIZE_INSTRUCTION 18
51#endif
52
53#ifndef SIZE_VALUES
54#define SIZE_VALUES 11
55#endif
56
57
58unsigned32 trace_values[3];
59int trace_num_values;
60unsigned32 trace_pc;
61const char *trace_name;
62int trace_module;
63
64
65void
66trace_input (name, type, size)
67 char *name;
68 enum op_types type;
69 int size;
70{
71
72 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
73 return;
74
75 trace_pc = PC;
76 trace_name = name;
77 trace_module = TRACE_ALU_IDX;
78
79 switch (type)
80 {
81 default:
82 case OP_UNKNOWN:
83 case OP_NONE:
84 case OP_TRAP:
85 trace_num_values = 0;
86 break;
87
88 case OP_REG:
89 case OP_REG_REG_MOVE:
90 trace_values[0] = State.regs[OP[0]];
91 trace_num_values = 1;
92 break;
93
94 case OP_BIT_CHANGE:
95 case OP_REG_REG:
96 case OP_REG_REG_CMP:
97 trace_values[0] = State.regs[OP[1]];
98 trace_values[1] = State.regs[OP[0]];
99 trace_num_values = 2;
100 break;
101
102 case OP_IMM_REG:
103 case OP_IMM_REG_CMP:
104 trace_values[0] = SEXT5 (OP[0]);
105 trace_values[1] = OP[1];
106 trace_num_values = 2;
107 break;
108
109 case OP_IMM_REG_MOVE:
110 trace_values[0] = SEXT5 (OP[0]);
111 trace_num_values = 1;
112 break;
113
114 case OP_COND_BR:
115 trace_values[0] = State.pc;
116 trace_values[1] = SEXT9 (OP[0]);
117 trace_values[2] = PSW;
118 trace_num_values = 3;
119 break;
120
121 case OP_LOAD16:
122 trace_values[0] = OP[1] * size;
123 trace_values[1] = State.regs[30];
124 trace_num_values = 2;
125 break;
126
127 case OP_STORE16:
128 trace_values[0] = State.regs[OP[0]];
129 trace_values[1] = OP[1] * size;
130 trace_values[2] = State.regs[30];
131 trace_num_values = 3;
132 break;
133
134 case OP_LOAD32:
135 trace_values[0] = EXTEND16 (OP[2]);
136 trace_values[1] = State.regs[OP[0]];
137 trace_num_values = 2;
138 break;
139
140 case OP_STORE32:
141 trace_values[0] = State.regs[OP[1]];
142 trace_values[1] = EXTEND16 (OP[2]);
143 trace_values[2] = State.regs[OP[0]];
144 trace_num_values = 3;
145 break;
146
147 case OP_JUMP:
148 trace_values[0] = SEXT22 (OP[0]);
149 trace_values[1] = State.pc;
150 trace_num_values = 2;
151 break;
152
153 case OP_IMM_REG_REG:
154 trace_values[0] = EXTEND16 (OP[0]) << size;
155 trace_values[1] = State.regs[OP[1]];
156 trace_num_values = 2;
157 break;
158
159 case OP_IMM16_REG_REG:
160 trace_values[0] = EXTEND16 (OP[2]) << size;
161 trace_values[1] = State.regs[OP[1]];
162 trace_num_values = 2;
163 break;
164
165 case OP_UIMM_REG_REG:
166 trace_values[0] = (OP[0] & 0xffff) << size;
167 trace_values[1] = State.regs[OP[1]];
168 trace_num_values = 2;
169 break;
170
171 case OP_UIMM16_REG_REG:
172 trace_values[0] = (OP[2]) << size;
173 trace_values[1] = State.regs[OP[1]];
174 trace_num_values = 2;
175 break;
176
177 case OP_BIT:
178 trace_num_values = 0;
179 break;
180
181 case OP_EX1:
182 trace_values[0] = PSW;
183 trace_num_values = 1;
184 break;
185
186 case OP_EX2:
187 trace_num_values = 0;
188 break;
189
190 case OP_LDSR:
191 trace_values[0] = State.regs[OP[0]];
192 trace_num_values = 1;
193 break;
194
195 case OP_STSR:
196 trace_values[0] = State.sregs[OP[1]];
197 trace_num_values = 1;
198 }
199
200}
201
202void
203trace_result (int has_result, unsigned32 result)
204{
205 char buf[1000];
206 char *chp;
207
208 buf[0] = '\0';
209 chp = buf;
210
211 /* write out the values saved during the trace_input call */
212 {
213 int i;
214 for (i = 0; i < trace_num_values; i++)
215 {
d62274a3
AC		 216 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "",
217 (long) trace_values[i]);
c906108c
SS		 218 chp = strchr (chp, '\0');
219 }
220 while (i++ < 3)
221 {
222 sprintf (chp, "%*s", SIZE_VALUES, "");
223 chp = strchr (chp, '\0');
224 }
225 }
226
227 /* append any result to the end of the buffer */
228 if (has_result)
229 sprintf (chp, " :: 0x%.8lx", (unsigned long)result);
230
231 trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, buf);
232}
233
234void
235trace_output (result)
236 enum op_types result;
237{
238 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
239 return;
240
241 switch (result)
242 {
243 default:
244 case OP_UNKNOWN:
245 case OP_NONE:
246 case OP_TRAP:
247 case OP_REG:
248 case OP_REG_REG_CMP:
249 case OP_IMM_REG_CMP:
250 case OP_COND_BR:
251 case OP_STORE16:
252 case OP_STORE32:
253 case OP_BIT:
254 case OP_EX2:
255 trace_result (0, 0);
256 break;
257
258 case OP_LOAD16:
259 case OP_STSR:
260 trace_result (1, State.regs[OP[0]]);
261 break;
262
263 case OP_REG_REG:
264 case OP_REG_REG_MOVE:
265 case OP_IMM_REG:
266 case OP_IMM_REG_MOVE:
267 case OP_LOAD32:
268 case OP_EX1:
269 trace_result (1, State.regs[OP[1]]);
270 break;
271
272 case OP_IMM_REG_REG:
273 case OP_UIMM_REG_REG:
274 case OP_IMM16_REG_REG:
275 case OP_UIMM16_REG_REG:
276 trace_result (1, State.regs[OP[1]]);
277 break;
278
279 case OP_JUMP:
280 if (OP[1] != 0)
281 trace_result (1, State.regs[OP[1]]);
282 else
283 trace_result (0, 0);
284 break;
285
286 case OP_LDSR:
287 trace_result (1, State.sregs[OP[1]]);
288 break;
289 }
290}
291#endif
292
293\f
294/* Returns 1 if the specific condition is met, returns 0 otherwise. */
295int
296condition_met (unsigned code)
297{
298 unsigned int psw = PSW;
299
300 switch (code & 0xf)
301 {
302 case 0x0: return ((psw & PSW_OV) != 0);
303 case 0x1: return ((psw & PSW_CY) != 0);
304 case 0x2: return ((psw & PSW_Z) != 0);
305 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
306 case 0x4: return ((psw & PSW_S) != 0);
307 /*case 0x5: return 1;*/
308 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
309 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
310 case 0x8: return ((psw & PSW_OV) == 0);
311 case 0x9: return ((psw & PSW_CY) == 0);
312 case 0xa: return ((psw & PSW_Z) == 0);
313 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
314 case 0xc: return ((psw & PSW_S) == 0);
315 case 0xd: return ((psw & PSW_SAT) != 0);
316 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
317 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
318 }
319
320 return 1;
321}
322
323static unsigned long
324Add32 (unsigned long a1, unsigned long a2, int * carry)
325{
326 unsigned long result = (a1 + a2);
327
328 * carry = (result < a1);
329
330 return result;
331}
332
333static void
0da2b665 334Multiply64 (int sign, unsigned long op0)
c906108c
SS		 335{
336 unsigned long op1;
337 unsigned long lo;
338 unsigned long mid1;
339 unsigned long mid2;
340 unsigned long hi;
341 unsigned long RdLo;
342 unsigned long RdHi;
343 int carry;
344
345 op1 = State.regs[ OP[1] ];
346
347 if (sign)
348 {
349 /* Compute sign of result and adjust operands if necessary. */
350
351 sign = (op0 ^ op1) & 0x80000000;
352
353 if (((signed long) op0) < 0)
354 op0 = - op0;
355
356 if (((signed long) op1) < 0)
357 op1 = - op1;
358 }
359
360 /* We can split the 32x32 into four 16x16 operations. This ensures
361 that we do not lose precision on 32bit only hosts: */
362 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
363 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
364 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
365 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
366
367 /* We now need to add all of these results together, taking care
368 to propogate the carries from the additions: */
369 RdLo = Add32 (lo, (mid1 << 16), & carry);
370 RdHi = carry;
371 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
372 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
373
374 if (sign)
375 {
376 /* Negate result if necessary. */
377
378 RdLo = ~ RdLo;
379 RdHi = ~ RdHi;
380 if (RdLo == 0xFFFFFFFF)
381 {
382 RdLo = 0;
383 RdHi += 1;
384 }
385 else
386 RdLo += 1;
387 }
388
389 /* Don't store into register 0. */
390 if (OP[1])
391 State.regs[ OP[1] ] = RdLo;
392 if (OP[2] >> 11)
393 State.regs[ OP[2] >> 11 ] = RdHi;
394
395 return;
396}
397
398\f
399/* Read a null terminated string from memory, return in a buffer */
400static char *
401fetch_str (sd, addr)
402 SIM_DESC sd;
403 address_word addr;
404{
405 char *buf;
406 int nr = 0;
407 while (sim_core_read_1 (STATE_CPU (sd, 0),
408 PC, read_map, addr + nr) != 0)
409 nr++;
410 buf = NZALLOC (char, nr + 1);
411 sim_read (simulator, addr, buf, nr);
412 return buf;
413}
414
415/* Read a null terminated argument vector from memory, return in a
416 buffer */
417static char **
418fetch_argv (sd, addr)
419 SIM_DESC sd;
420 address_word addr;
421{
422 int max_nr = 64;
423 int nr = 0;
424 char **buf = xmalloc (max_nr * sizeof (char*));
425 while (1)
426 {
427 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
428 PC, read_map, addr + nr * 4);
429 if (a == 0) break;
430 buf[nr] = fetch_str (sd, a);
431 nr ++;
432 if (nr == max_nr - 1)
433 {
434 max_nr += 50;
435 buf = xrealloc (buf, max_nr * sizeof (char*));
436 }
437 }
438 buf[nr] = 0;
439 return buf;
440}
441
442\f
443/* sst.b */
444int
445OP_380 ()
446{
447 trace_input ("sst.b", OP_STORE16, 1);
448
449 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
450
451 trace_output (OP_STORE16);
452
453 return 2;
454}
455
456/* sst.h */
457int
458OP_480 ()
459{
460 trace_input ("sst.h", OP_STORE16, 2);
461
462 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
463
464 trace_output (OP_STORE16);
465
466 return 2;
467}
468
469/* sst.w */
470int
471OP_501 ()
472{
473 trace_input ("sst.w", OP_STORE16, 4);
474
475 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
476
477 trace_output (OP_STORE16);
478
479 return 2;
480}
481
482/* ld.b */
483int
484OP_700 ()
485{
486 int adr;
487
488 trace_input ("ld.b", OP_LOAD32, 1);
489
490 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
491
492 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
493
494 trace_output (OP_LOAD32);
495
496 return 4;
497}
498
499/* ld.h */
500int
501OP_720 ()
502{
503 int adr;
504
505 trace_input ("ld.h", OP_LOAD32, 2);
506
507 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
508 adr &= ~0x1;
509
510 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
511
512 trace_output (OP_LOAD32);
513
514 return 4;
515}
516
517/* ld.w */
518int
519OP_10720 ()
520{
521 int adr;
522
523 trace_input ("ld.w", OP_LOAD32, 4);
524
525 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
526 adr &= ~0x3;
527
528 State.regs[ OP[1] ] = load_mem (adr, 4);
529
530 trace_output (OP_LOAD32);
531
532 return 4;
533}
534
535/* st.b */
536int
537OP_740 ()
538{
539 trace_input ("st.b", OP_STORE32, 1);
540
541 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
542
543 trace_output (OP_STORE32);
544
545 return 4;
546}
547
548/* st.h */
549int
550OP_760 ()
551{
552 int adr;
553
554 trace_input ("st.h", OP_STORE32, 2);
555
556 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
557 adr &= ~1;
558
559 store_mem (adr, 2, State.regs[ OP[1] ]);
560
561 trace_output (OP_STORE32);
562
563 return 4;
564}
565
566/* st.w */
567int
568OP_10760 ()
569{
570 int adr;
571
572 trace_input ("st.w", OP_STORE32, 4);
573
574 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
575 adr &= ~3;
576
577 store_mem (adr, 4, State.regs[ OP[1] ]);
578
579 trace_output (OP_STORE32);
580
581 return 4;
582}
583
584/* add reg, reg */
585int
586OP_1C0 ()
587{
588 unsigned int op0, op1, result, z, s, cy, ov;
589
590 trace_input ("add", OP_REG_REG, 0);
591
592 /* Compute the result. */
593
594 op0 = State.regs[ OP[0] ];
595 op1 = State.regs[ OP[1] ];
596
597 result = op0 + op1;
598
599 /* Compute the condition codes. */
600 z = (result == 0);
601 s = (result & 0x80000000);
602 cy = (result < op0 || result < op1);
603 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
604 && (op0 & 0x80000000) != (result & 0x80000000));
605
606 /* Store the result and condition codes. */
607 State.regs[OP[1]] = result;
608 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
609 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
610 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
611 trace_output (OP_REG_REG);
612
613 return 2;
614}
615
616/* add sign_extend(imm5), reg */
617int
618OP_240 ()
619{
620 unsigned int op0, op1, result, z, s, cy, ov;
621 int temp;
622
623 trace_input ("add", OP_IMM_REG, 0);
624
625 /* Compute the result. */
626 temp = SEXT5 (OP[0]);
627 op0 = temp;
628 op1 = State.regs[OP[1]];
629 result = op0 + op1;
630
631 /* Compute the condition codes. */
632 z = (result == 0);
633 s = (result & 0x80000000);
634 cy = (result < op0 || result < op1);
635 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
636 && (op0 & 0x80000000) != (result & 0x80000000));
637
638 /* Store the result and condition codes. */
639 State.regs[OP[1]] = result;
640 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
641 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
642 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
643 trace_output (OP_IMM_REG);
644
645 return 2;
646}
647
648/* addi sign_extend(imm16), reg, reg */
649int
650OP_600 ()
651{
652 unsigned int op0, op1, result, z, s, cy, ov;
653
654 trace_input ("addi", OP_IMM16_REG_REG, 0);
655
656 /* Compute the result. */
657
658 op0 = EXTEND16 (OP[2]);
659 op1 = State.regs[ OP[0] ];
660 result = op0 + op1;
661
662 /* Compute the condition codes. */
663 z = (result == 0);
664 s = (result & 0x80000000);
665 cy = (result < op0 || result < op1);
666 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
667 && (op0 & 0x80000000) != (result & 0x80000000));
668
669 /* Store the result and condition codes. */
670 State.regs[OP[1]] = result;
671 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
672 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
673 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
674 trace_output (OP_IMM16_REG_REG);
675
676 return 4;
677}
678
679/* sub reg1, reg2 */
680int
681OP_1A0 ()
682{
683 unsigned int op0, op1, result, z, s, cy, ov;
684
685 trace_input ("sub", OP_REG_REG, 0);
686 /* Compute the result. */
687 op0 = State.regs[ OP[0] ];
688 op1 = State.regs[ OP[1] ];
689 result = op1 - op0;
690
691 /* Compute the condition codes. */
692 z = (result == 0);
693 s = (result & 0x80000000);
694 cy = (op1 < op0);
695 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
696 && (op1 & 0x80000000) != (result & 0x80000000));
697
698 /* Store the result and condition codes. */
699 State.regs[OP[1]] = result;
700 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
701 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
702 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
703 trace_output (OP_REG_REG);
704
705 return 2;
706}
707
708/* subr reg1, reg2 */
709int
710OP_180 ()
711{
712 unsigned int op0, op1, result, z, s, cy, ov;
713
714 trace_input ("subr", OP_REG_REG, 0);
715 /* Compute the result. */
716 op0 = State.regs[ OP[0] ];
717 op1 = State.regs[ OP[1] ];
718 result = op0 - op1;
719
720 /* Compute the condition codes. */
721 z = (result == 0);
722 s = (result & 0x80000000);
723 cy = (op0 < op1);
724 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
725 && (op0 & 0x80000000) != (result & 0x80000000));
726
727 /* Store the result and condition codes. */
728 State.regs[OP[1]] = result;
729 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
730 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
731 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
732 trace_output (OP_REG_REG);
733
734 return 2;
735}
736
737/* sxh reg1 */
738int
739OP_E0 ()
740{
741 trace_input ("mulh", OP_REG_REG, 0);
742
743 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
744
745 trace_output (OP_REG_REG);
746
747 return 2;
748}
749
750/* mulh sign_extend(imm5), reg2 */
751int
752OP_2E0 ()
753{
754 trace_input ("mulh", OP_IMM_REG, 0);
755
756 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
757
758 trace_output (OP_IMM_REG);
759
760 return 2;
761}
762
763/* mulhi imm16, reg1, reg2 */
764int
765OP_6E0 ()
766{
767 trace_input ("mulhi", OP_IMM16_REG_REG, 0);
768
769 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
770
771 trace_output (OP_IMM16_REG_REG);
772
773 return 4;
774}
775
c906108c
SS		 776/* cmp reg, reg */
777int
778OP_1E0 ()
779{
780 unsigned int op0, op1, result, z, s, cy, ov;
781
782 trace_input ("cmp", OP_REG_REG_CMP, 0);
783 /* Compute the result. */
784 op0 = State.regs[ OP[0] ];
785 op1 = State.regs[ OP[1] ];
786 result = op1 - op0;
787
788 /* Compute the condition codes. */
789 z = (result == 0);
790 s = (result & 0x80000000);
791 cy = (op1 < op0);
792 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
793 && (op1 & 0x80000000) != (result & 0x80000000));
794
795 /* Set condition codes. */
796 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
797 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
798 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
799 trace_output (OP_REG_REG_CMP);
800
801 return 2;
802}
803
804/* cmp sign_extend(imm5), reg */
805int
806OP_260 ()
807{
808 unsigned int op0, op1, result, z, s, cy, ov;
809 int temp;
810
811 /* Compute the result. */
812 trace_input ("cmp", OP_IMM_REG_CMP, 0);
813 temp = SEXT5 (OP[0]);
814 op0 = temp;
815 op1 = State.regs[OP[1]];
816 result = op1 - op0;
817
818 /* Compute the condition codes. */
819 z = (result == 0);
820 s = (result & 0x80000000);
821 cy = (op1 < op0);
822 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
823 && (op1 & 0x80000000) != (result & 0x80000000));
824
825 /* Set condition codes. */
826 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
827 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
828 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
829 trace_output (OP_IMM_REG_CMP);
830
831 return 2;
832}
833
834/* setf cccc,reg2 */
835int
836OP_7E0 ()
837{
838 trace_input ("setf", OP_EX1, 0);
839
840 State.regs[ OP[1] ] = condition_met (OP[0]);
841
842 trace_output (OP_EX1);
843
844 return 4;
845}
846
847/* satadd reg,reg */
848int
849OP_C0 ()
850{
851 unsigned int op0, op1, result, z, s, cy, ov, sat;
852
853 trace_input ("satadd", OP_REG_REG, 0);
854 /* Compute the result. */
855 op0 = State.regs[ OP[0] ];
856 op1 = State.regs[ OP[1] ];
857 result = op0 + op1;
858
859 /* Compute the condition codes. */
860 z = (result == 0);
861 s = (result & 0x80000000);
862 cy = (result < op0 || result < op1);
863 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
864 && (op0 & 0x80000000) != (result & 0x80000000));
865 sat = ov;
866
c5fbc25b
DD		 867 /* Handle saturated results. */
868 if (sat && s)
869 {
870 /* An overflow that results in a negative result implies that we
871 became too positive. */
872 result = 0x7fffffff;
873 s = 0;
874 }
875 else if (sat)
876 {
877 /* Any other overflow must have thus been too negative. */
878 result = 0x80000000;
879 s = 1;
880 z = 0;
881 }
882
c906108c
SS		 883 /* Store the result and condition codes. */
884 State.regs[OP[1]] = result;
885 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
886 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
887 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
888 | (sat ? PSW_SAT : 0));
c5fbc25b 889
c906108c
SS		 890 trace_output (OP_REG_REG);
891
892 return 2;
893}
894
895/* satadd sign_extend(imm5), reg */
896int
897OP_220 ()
898{
899 unsigned int op0, op1, result, z, s, cy, ov, sat;
900
901 int temp;
902
903 trace_input ("satadd", OP_IMM_REG, 0);
904
905 /* Compute the result. */
906 temp = SEXT5 (OP[0]);
907 op0 = temp;
908 op1 = State.regs[OP[1]];
909 result = op0 + op1;
910
911 /* Compute the condition codes. */
912 z = (result == 0);
913 s = (result & 0x80000000);
914 cy = (result < op0 || result < op1);
915 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
916 && (op0 & 0x80000000) != (result & 0x80000000));
917 sat = ov;
918
c5fbc25b
DD		 919 /* Handle saturated results. */
920 if (sat && s)
921 {
922 /* An overflow that results in a negative result implies that we
923 became too positive. */
924 result = 0x7fffffff;
925 s = 0;
926 }
927 else if (sat)
928 {
929 /* Any other overflow must have thus been too negative. */
930 result = 0x80000000;
931 s = 1;
932 z = 0;
933 }
934
c906108c
SS		 935 /* Store the result and condition codes. */
936 State.regs[OP[1]] = result;
937 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
938 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
939 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
940 | (sat ? PSW_SAT : 0));
c906108c
SS		 941 trace_output (OP_IMM_REG);
942
943 return 2;
944}
945
946/* satsub reg1, reg2 */
947int
948OP_A0 ()
949{
950 unsigned int op0, op1, result, z, s, cy, ov, sat;
951
952 trace_input ("satsub", OP_REG_REG, 0);
953
954 /* Compute the result. */
955 op0 = State.regs[ OP[0] ];
956 op1 = State.regs[ OP[1] ];
957 result = op1 - op0;
958
959 /* Compute the condition codes. */
960 z = (result == 0);
961 s = (result & 0x80000000);
962 cy = (op1 < op0);
963 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
964 && (op1 & 0x80000000) != (result & 0x80000000));
965 sat = ov;
c5fbc25b
DD		 966
967 /* Handle saturated results. */
968 if (sat && s)
969 {
970 /* An overflow that results in a negative result implies that we
971 became too positive. */
972 result = 0x7fffffff;
973 s = 0;
974 }
975 else if (sat)
976 {
977 /* Any other overflow must have thus been too negative. */
978 result = 0x80000000;
979 s = 1;
980 z = 0;
981 }
982
c906108c
SS		 983 /* Store the result and condition codes. */
984 State.regs[OP[1]] = result;
985 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
986 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
987 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
988 | (sat ? PSW_SAT : 0));
989
c906108c
SS		 990 trace_output (OP_REG_REG);
991 return 2;
992}
993
994/* satsubi sign_extend(imm16), reg */
995int
996OP_660 ()
997{
998 unsigned int op0, op1, result, z, s, cy, ov, sat;
999 int temp;
1000
1001 trace_input ("satsubi", OP_IMM_REG, 0);
1002
1003 /* Compute the result. */
1004 temp = EXTEND16 (OP[2]);
1005 op0 = temp;
1006 op1 = State.regs[ OP[0] ];
1007 result = op1 - op0;
1008
1009 /* Compute the condition codes. */
1010 z = (result == 0);
1011 s = (result & 0x80000000);
1012 cy = (op1 < op0);
1013 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1014 && (op1 & 0x80000000) != (result & 0x80000000));
1015 sat = ov;
1016
c5fbc25b
DD		 1017 /* Handle saturated results. */
1018 if (sat && s)
1019 {
1020 /* An overflow that results in a negative result implies that we
1021 became too positive. */
1022 result = 0x7fffffff;
1023 s = 0;
1024 }
1025 else if (sat)
1026 {
1027 /* Any other overflow must have thus been too negative. */
1028 result = 0x80000000;
1029 s = 1;
1030 z = 0;
1031 }
1032
c906108c
SS		 1033 /* Store the result and condition codes. */
1034 State.regs[OP[1]] = result;
1035 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1036 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1037 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1038 | (sat ? PSW_SAT : 0));
1039
c906108c
SS		 1040 trace_output (OP_IMM_REG);
1041
1042 return 4;
1043}
1044
1045/* satsubr reg,reg */
1046int
1047OP_80 ()
1048{
1049 unsigned int op0, op1, result, z, s, cy, ov, sat;
1050
1051 trace_input ("satsubr", OP_REG_REG, 0);
1052
1053 /* Compute the result. */
1054 op0 = State.regs[ OP[0] ];
1055 op1 = State.regs[ OP[1] ];
1056 result = op0 - op1;
1057
1058 /* Compute the condition codes. */
1059 z = (result == 0);
1060 s = (result & 0x80000000);
c5fbc25b
DD		 1061 cy = (op0 < op1);
1062 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1063 && (op0 & 0x80000000) != (result & 0x80000000));
c906108c 1064 sat = ov;
c5fbc25b
DD		 1065
1066 /* Handle saturated results. */
1067 if (sat && s)
1068 {
1069 /* An overflow that results in a negative result implies that we
1070 became too positive. */
1071 result = 0x7fffffff;
1072 s = 0;
1073 }
1074 else if (sat)
1075 {
1076 /* Any other overflow must have thus been too negative. */
1077 result = 0x80000000;
1078 s = 1;
1079 z = 0;
1080 }
c906108c
SS		 1081
1082 /* Store the result and condition codes. */
1083 State.regs[OP[1]] = result;
1084 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1085 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1086 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1087 | (sat ? PSW_SAT : 0));
1088
c906108c
SS		 1089 trace_output (OP_REG_REG);
1090
1091 return 2;
1092}
1093
1094/* tst reg,reg */
1095int
1096OP_160 ()
1097{
1098 unsigned int op0, op1, result, z, s;
1099
1100 trace_input ("tst", OP_REG_REG_CMP, 0);
1101
1102 /* Compute the result. */
1103 op0 = State.regs[ OP[0] ];
1104 op1 = State.regs[ OP[1] ];
1105 result = op0 & op1;
1106
1107 /* Compute the condition codes. */
1108 z = (result == 0);
1109 s = (result & 0x80000000);
1110
1111 /* Store the condition codes. */
1112 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1113 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1114 trace_output (OP_REG_REG_CMP);
1115
1116 return 2;
1117}
1118
1119/* mov sign_extend(imm5), reg */
1120int
1121OP_200 ()
1122{
1123 int value = SEXT5 (OP[0]);
1124
1125 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1126
1127 State.regs[ OP[1] ] = value;
1128
1129 trace_output (OP_IMM_REG_MOVE);
1130
1131 return 2;
1132}
1133
1134/* movhi imm16, reg, reg */
1135int
1136OP_640 ()
1137{
1138 trace_input ("movhi", OP_UIMM16_REG_REG, 16);
1139
1140 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1141
1142 trace_output (OP_UIMM16_REG_REG);
1143
1144 return 4;
1145}
1146
1147/* sar zero_extend(imm5),reg1 */
1148int
1149OP_2A0 ()
1150{
1151 unsigned int op0, op1, result, z, s, cy;
1152
1153 trace_input ("sar", OP_IMM_REG, 0);
1154 op0 = OP[0];
1155 op1 = State.regs[ OP[1] ];
1156 result = (signed)op1 >> op0;
1157
1158 /* Compute the condition codes. */
1159 z = (result == 0);
1160 s = (result & 0x80000000);
c5fbc25b 1161 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
c906108c
SS		 1162
1163 /* Store the result and condition codes. */
1164 State.regs[ OP[1] ] = result;
1165 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1166 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1167 | (cy ? PSW_CY : 0));
1168 trace_output (OP_IMM_REG);
1169
1170 return 2;
1171}
1172
1173/* sar reg1, reg2 */
1174int
1175OP_A007E0 ()
1176{
1177 unsigned int op0, op1, result, z, s, cy;
1178
1179 trace_input ("sar", OP_REG_REG, 0);
1180
1181 op0 = State.regs[ OP[0] ] & 0x1f;
1182 op1 = State.regs[ OP[1] ];
1183 result = (signed)op1 >> op0;
1184
1185 /* Compute the condition codes. */
1186 z = (result == 0);
1187 s = (result & 0x80000000);
c5fbc25b 1188 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
c906108c
SS		 1189
1190 /* Store the result and condition codes. */
1191 State.regs[OP[1]] = result;
1192 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1193 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1194 | (cy ? PSW_CY : 0));
1195 trace_output (OP_REG_REG);
1196
1197 return 4;
1198}
1199
1200/* shl zero_extend(imm5),reg1 */
1201int
1202OP_2C0 ()
1203{
1204 unsigned int op0, op1, result, z, s, cy;
1205
1206 trace_input ("shl", OP_IMM_REG, 0);
1207 op0 = OP[0];
1208 op1 = State.regs[ OP[1] ];
1209 result = op1 << op0;
1210
1211 /* Compute the condition codes. */
1212 z = (result == 0);
1213 s = (result & 0x80000000);
c5fbc25b 1214 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
c906108c
SS		 1215
1216 /* Store the result and condition codes. */
1217 State.regs[OP[1]] = result;
1218 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1219 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1220 | (cy ? PSW_CY : 0));
1221 trace_output (OP_IMM_REG);
1222
1223 return 2;
1224}
1225
1226/* shl reg1, reg2 */
1227int
1228OP_C007E0 ()
1229{
1230 unsigned int op0, op1, result, z, s, cy;
1231
1232 trace_input ("shl", OP_REG_REG, 0);
1233 op0 = State.regs[ OP[0] ] & 0x1f;
1234 op1 = State.regs[ OP[1] ];
1235 result = op1 << op0;
1236
1237 /* Compute the condition codes. */
1238 z = (result == 0);
1239 s = (result & 0x80000000);
c5fbc25b 1240 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
c906108c
SS		 1241
1242 /* Store the result and condition codes. */
1243 State.regs[OP[1]] = result;
1244 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1245 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1246 | (cy ? PSW_CY : 0));
1247 trace_output (OP_REG_REG);
1248
1249 return 4;
1250}
1251
1252/* shr zero_extend(imm5),reg1 */
1253int
1254OP_280 ()
1255{
1256 unsigned int op0, op1, result, z, s, cy;
1257
1258 trace_input ("shr", OP_IMM_REG, 0);
1259 op0 = OP[0];
1260 op1 = State.regs[ OP[1] ];
1261 result = op1 >> op0;
1262
1263 /* Compute the condition codes. */
1264 z = (result == 0);
1265 s = (result & 0x80000000);
c5fbc25b 1266 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
c906108c
SS		 1267
1268 /* Store the result and condition codes. */
1269 State.regs[OP[1]] = result;
1270 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1271 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1272 | (cy ? PSW_CY : 0));
1273 trace_output (OP_IMM_REG);
1274
1275 return 2;
1276}
1277
1278/* shr reg1, reg2 */
1279int
1280OP_8007E0 ()
1281{
1282 unsigned int op0, op1, result, z, s, cy;
1283
1284 trace_input ("shr", OP_REG_REG, 0);
1285 op0 = State.regs[ OP[0] ] & 0x1f;
1286 op1 = State.regs[ OP[1] ];
1287 result = op1 >> op0;
1288
1289 /* Compute the condition codes. */
1290 z = (result == 0);
1291 s = (result & 0x80000000);
c5fbc25b 1292 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
c906108c
SS		 1293
1294 /* Store the result and condition codes. */
1295 State.regs[OP[1]] = result;
1296 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1297 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1298 | (cy ? PSW_CY : 0));
1299 trace_output (OP_REG_REG);
1300
1301 return 4;
1302}
1303
1304/* or reg, reg */
1305int
1306OP_100 ()
1307{
1308 unsigned int op0, op1, result, z, s;
1309
1310 trace_input ("or", OP_REG_REG, 0);
1311
1312 /* Compute the result. */
1313 op0 = State.regs[ OP[0] ];
1314 op1 = State.regs[ OP[1] ];
1315 result = op0 | op1;
1316
1317 /* Compute the condition codes. */
1318 z = (result == 0);
1319 s = (result & 0x80000000);
1320
1321 /* Store the result and condition codes. */
1322 State.regs[OP[1]] = result;
1323 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1324 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1325 trace_output (OP_REG_REG);
1326
1327 return 2;
1328}
1329
1330/* ori zero_extend(imm16), reg, reg */
1331int
1332OP_680 ()
1333{
1334 unsigned int op0, op1, result, z, s;
1335
1336 trace_input ("ori", OP_UIMM16_REG_REG, 0);
1337 op0 = OP[2];
1338 op1 = State.regs[ OP[0] ];
1339 result = op0 | op1;
1340
1341 /* Compute the condition codes. */
1342 z = (result == 0);
1343 s = (result & 0x80000000);
1344
1345 /* Store the result and condition codes. */
1346 State.regs[OP[1]] = result;
1347 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1348 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1349 trace_output (OP_UIMM16_REG_REG);
1350
1351 return 4;
1352}
1353
1354/* and reg, reg */
1355int
1356OP_140 ()
1357{
1358 unsigned int op0, op1, result, z, s;
1359
1360 trace_input ("and", OP_REG_REG, 0);
1361
1362 /* Compute the result. */
1363 op0 = State.regs[ OP[0] ];
1364 op1 = State.regs[ OP[1] ];
1365 result = op0 & op1;
1366
1367 /* Compute the condition codes. */
1368 z = (result == 0);
1369 s = (result & 0x80000000);
1370
1371 /* Store the result and condition codes. */
1372 State.regs[OP[1]] = result;
1373 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1374 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1375 trace_output (OP_REG_REG);
1376
1377 return 2;
1378}
1379
1380/* andi zero_extend(imm16), reg, reg */
1381int
1382OP_6C0 ()
1383{
1384 unsigned int result, z;
1385
1386 trace_input ("andi", OP_UIMM16_REG_REG, 0);
1387
1388 result = OP[2] & State.regs[ OP[0] ];
1389
1390 /* Compute the condition codes. */
1391 z = (result == 0);
1392
1393 /* Store the result and condition codes. */
1394 State.regs[ OP[1] ] = result;
1395
1396 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1397 PSW |= (z ? PSW_Z : 0);
1398
1399 trace_output (OP_UIMM16_REG_REG);
1400
1401 return 4;
1402}
1403
1404/* xor reg, reg */
1405int
1406OP_120 ()
1407{
1408 unsigned int op0, op1, result, z, s;
1409
1410 trace_input ("xor", OP_REG_REG, 0);
1411
1412 /* Compute the result. */
1413 op0 = State.regs[ OP[0] ];
1414 op1 = State.regs[ OP[1] ];
1415 result = op0 ^ op1;
1416
1417 /* Compute the condition codes. */
1418 z = (result == 0);
1419 s = (result & 0x80000000);
1420
1421 /* Store the result and condition codes. */
1422 State.regs[OP[1]] = result;
1423 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1424 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1425 trace_output (OP_REG_REG);
1426
1427 return 2;
1428}
1429
1430/* xori zero_extend(imm16), reg, reg */
1431int
1432OP_6A0 ()
1433{
1434 unsigned int op0, op1, result, z, s;
1435
1436 trace_input ("xori", OP_UIMM16_REG_REG, 0);
1437 op0 = OP[2];
1438 op1 = State.regs[ OP[0] ];
1439 result = op0 ^ op1;
1440
1441 /* Compute the condition codes. */
1442 z = (result == 0);
1443 s = (result & 0x80000000);
1444
1445 /* Store the result and condition codes. */
1446 State.regs[OP[1]] = result;
1447 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1448 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1449 trace_output (OP_UIMM16_REG_REG);
1450
1451 return 4;
1452}
1453
1454/* not reg1, reg2 */
1455int
1456OP_20 ()
1457{
1458 unsigned int op0, result, z, s;
1459
1460 trace_input ("not", OP_REG_REG_MOVE, 0);
1461 /* Compute the result. */
1462 op0 = State.regs[ OP[0] ];
1463 result = ~op0;
1464
1465 /* Compute the condition codes. */
1466 z = (result == 0);
1467 s = (result & 0x80000000);
1468
1469 /* Store the result and condition codes. */
1470 State.regs[OP[1]] = result;
1471 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1472 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1473 trace_output (OP_REG_REG_MOVE);
1474
1475 return 2;
1476}
1477
1478/* set1 */
1479int
1480OP_7C0 ()
1481{
1482 unsigned int op0, op1, op2;
1483 int temp;
1484
1485 trace_input ("set1", OP_BIT, 0);
1486 op0 = State.regs[ OP[0] ];
1487 op1 = OP[1] & 0x7;
1488 temp = EXTEND16 (OP[2]);
1489 op2 = temp;
1490 temp = load_mem (op0 + op2, 1);
1491 PSW &= ~PSW_Z;
1492 if ((temp & (1 << op1)) == 0)
1493 PSW |= PSW_Z;
1494 temp |= (1 << op1);
1495 store_mem (op0 + op2, 1, temp);
1496 trace_output (OP_BIT);
1497
1498 return 4;
1499}
1500
1501/* not1 */
1502int
1503OP_47C0 ()
1504{
1505 unsigned int op0, op1, op2;
1506 int temp;
1507
1508 trace_input ("not1", OP_BIT, 0);
1509 op0 = State.regs[ OP[0] ];
1510 op1 = OP[1] & 0x7;
1511 temp = EXTEND16 (OP[2]);
1512 op2 = temp;
1513 temp = load_mem (op0 + op2, 1);
1514 PSW &= ~PSW_Z;
1515 if ((temp & (1 << op1)) == 0)
1516 PSW |= PSW_Z;
1517 temp ^= (1 << op1);
1518 store_mem (op0 + op2, 1, temp);
1519 trace_output (OP_BIT);
1520
1521 return 4;
1522}
1523
1524/* clr1 */
1525int
1526OP_87C0 ()
1527{
1528 unsigned int op0, op1, op2;
1529 int temp;
1530
1531 trace_input ("clr1", OP_BIT, 0);
1532 op0 = State.regs[ OP[0] ];
1533 op1 = OP[1] & 0x7;
1534 temp = EXTEND16 (OP[2]);
1535 op2 = temp;
1536 temp = load_mem (op0 + op2, 1);
1537 PSW &= ~PSW_Z;
1538 if ((temp & (1 << op1)) == 0)
1539 PSW |= PSW_Z;
1540 temp &= ~(1 << op1);
1541 store_mem (op0 + op2, 1, temp);
1542 trace_output (OP_BIT);
1543
1544 return 4;
1545}
1546
1547/* tst1 */
1548int
1549OP_C7C0 ()
1550{
1551 unsigned int op0, op1, op2;
1552 int temp;
1553
1554 trace_input ("tst1", OP_BIT, 0);
1555 op0 = State.regs[ OP[0] ];
1556 op1 = OP[1] & 0x7;
1557 temp = EXTEND16 (OP[2]);
1558 op2 = temp;
1559 temp = load_mem (op0 + op2, 1);
1560 PSW &= ~PSW_Z;
1561 if ((temp & (1 << op1)) == 0)
1562 PSW |= PSW_Z;
1563 trace_output (OP_BIT);
1564
1565 return 4;
1566}
1567
1568/* di */
1569int
1570OP_16007E0 ()
1571{
1572 trace_input ("di", OP_NONE, 0);
1573 PSW |= PSW_ID;
1574 trace_output (OP_NONE);
1575
1576 return 4;
1577}
1578
1579/* ei */
1580int
1581OP_16087E0 ()
1582{
1583 trace_input ("ei", OP_NONE, 0);
1584 PSW &= ~PSW_ID;
1585 trace_output (OP_NONE);
1586
1587 return 4;
1588}
1589
1590/* halt */
1591int
1592OP_12007E0 ()
1593{
1594 trace_input ("halt", OP_NONE, 0);
1595 /* FIXME this should put processor into a mode where NMI still handled */
1596 trace_output (OP_NONE);
1597 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1598 sim_stopped, SIM_SIGTRAP);
1599 return 0;
1600}
1601
1602/* trap */
1603int
1604OP_10007E0 ()
1605{
1606 trace_input ("trap", OP_TRAP, 0);
1607 trace_output (OP_TRAP);
1608
1609 /* Trap 31 is used for simulating OS I/O functions */
1610
1611 if (OP[0] == 31)
1612 {
1613 int save_errno = errno;
1614 errno = 0;
1615
1616/* Registers passed to trap 0 */
1617
1618#define FUNC State.regs[6] /* function number, return value */
1619#define PARM1 State.regs[7] /* optional parm 1 */
1620#define PARM2 State.regs[8] /* optional parm 2 */
1621#define PARM3 State.regs[9] /* optional parm 3 */
1622
1623/* Registers set by trap 0 */
1624
1625#define RETVAL State.regs[10] /* return value */
1626#define RETERR State.regs[11] /* return error code */
1627
1628/* Turn a pointer in a register into a pointer into real memory. */
1629
1630#define MEMPTR(x) (map (x))
1631
1632 switch (FUNC)
1633 {
1634
1635#ifdef HAVE_FORK
1636#ifdef TARGET_SYS_fork
1637 case TARGET_SYS_fork:
1638 RETVAL = fork ();
1639 break;
1640#endif
1641#endif
1642
1643#ifdef HAVE_EXECVE
1644#ifdef TARGET_SYS_execv
1645 case TARGET_SYS_execve:
1646 {
1647 char *path = fetch_str (simulator, PARM1);
1648 char **argv = fetch_argv (simulator, PARM2);
1649 char **envp = fetch_argv (simulator, PARM3);
1650 RETVAL = execve (path, argv, envp);
1651 zfree (path);
1652 freeargv (argv);
1653 freeargv (envp);
1654 break;
1655 }
1656#endif
1657#endif
1658
1659#if HAVE_EXECV
1660#ifdef TARGET_SYS_execv
1661 case TARGET_SYS_execv:
1662 {
1663 char *path = fetch_str (simulator, PARM1);
1664 char **argv = fetch_argv (simulator, PARM2);
1665 RETVAL = execv (path, argv);
1666 zfree (path);
1667 freeargv (argv);
1668 break;
1669 }
1670#endif
1671#endif
1672
1673#if 0
1674#ifdef TARGET_SYS_pipe
1675 case TARGET_SYS_pipe:
1676 {
1677 reg_t buf;
1678 int host_fd[2];
1679
1680 buf = PARM1;
1681 RETVAL = pipe (host_fd);
1682 SW (buf, host_fd[0]);
1683 buf += sizeof(uint16);
1684 SW (buf, host_fd[1]);
1685 }
1686 break;
1687#endif
1688#endif
1689
1690#if 0
1691#ifdef TARGET_SYS_wait
1692 case TARGET_SYS_wait:
1693 {
1694 int status;
1695
1696 RETVAL = wait (&status);
1697 SW (PARM1, status);
1698 }
1699 break;
1700#endif
1701#endif
1702
1703#ifdef TARGET_SYS_read
1704 case TARGET_SYS_read:
1705 {
1706 char *buf = zalloc (PARM3);
1707 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
1708 sim_write (simulator, PARM2, buf, PARM3);
1709 zfree (buf);
1710 break;
1711 }
1712#endif
1713
1714#ifdef TARGET_SYS_write
1715 case TARGET_SYS_write:
1716 {
1717 char *buf = zalloc (PARM3);
1718 sim_read (simulator, PARM2, buf, PARM3);
1719 if (PARM1 == 1)
1720 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
1721 else
1722 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
1723 zfree (buf);
1724 break;
1725 }
1726#endif
1727
1728#ifdef TARGET_SYS_lseek
1729 case TARGET_SYS_lseek:
1730 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
1731 break;
1732#endif
1733
1734#ifdef TARGET_SYS_close
1735 case TARGET_SYS_close:
1736 RETVAL = sim_io_close (simulator, PARM1);
1737 break;
1738#endif
1739
1740#ifdef TARGET_SYS_open
1741 case TARGET_SYS_open:
1742 {
1743 char *buf = fetch_str (simulator, PARM1);
1744 RETVAL = sim_io_open (simulator, buf, PARM2);
1745 zfree (buf);
1746 break;
1747 }
1748#endif
1749
1750#ifdef TARGET_SYS_exit
1751 case TARGET_SYS_exit:
1752 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
1753 /* get signal encoded by kill */
1754 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1755 sim_signalled, PARM1 & 0xffff);
1756 else if (PARM1 == 0xdead)
1757 /* old libraries */
1758 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1759 sim_stopped, SIM_SIGABRT);
1760 else
1761 /* PARM1 has exit status */
1762 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1763 sim_exited, PARM1);
1764 break;
1765#endif
1766
1767#if !defined(__GO32__) && !defined(_WIN32)
1768#ifdef TARGET_SYS_stat
1769 case TARGET_SYS_stat: /* added at hmsi */
1770 /* stat system call */
1771 {
1772 struct stat host_stat;
1773 reg_t buf;
1774 char *path = fetch_str (simulator, PARM1);
1775
1776 RETVAL = stat (path, &host_stat);
1777
1778 zfree (path);
1779 buf = PARM2;
1780
1781 /* Just wild-assed guesses. */
1782 store_mem (buf, 2, host_stat.st_dev);
1783 store_mem (buf + 2, 2, host_stat.st_ino);
1784 store_mem (buf + 4, 4, host_stat.st_mode);
1785 store_mem (buf + 8, 2, host_stat.st_nlink);
1786 store_mem (buf + 10, 2, host_stat.st_uid);
1787 store_mem (buf + 12, 2, host_stat.st_gid);
1788 store_mem (buf + 14, 2, host_stat.st_rdev);
1789 store_mem (buf + 16, 4, host_stat.st_size);
1790 store_mem (buf + 20, 4, host_stat.st_atime);
1791 store_mem (buf + 28, 4, host_stat.st_mtime);
1792 store_mem (buf + 36, 4, host_stat.st_ctime);
1793 }
1794 break;
1795#endif
1796#endif
1797
1798#ifdef HAVE_CHOWN
1799#ifdef TARGET_SYS_chown
1800 case TARGET_SYS_chown:
1801 {
1802 char *path = fetch_str (simulator, PARM1);
1803 RETVAL = chown (path, PARM2, PARM3);
1804 zfree (path);
1805 }
1806 break;
1807#endif
1808#endif
1809
1810#if HAVE_CHMOD
1811#ifdef TARGET_SYS_chmod
1812 case TARGET_SYS_chmod:
1813 {
1814 char *path = fetch_str (simulator, PARM1);
1815 RETVAL = chmod (path, PARM2);
1816 zfree (path);
1817 }
1818 break;
1819#endif
1820#endif
1821
1822#ifdef TARGET_SYS_time
1823#if HAVE_TIME
1824 case TARGET_SYS_time:
1825 {
1826 time_t now;
1827 RETVAL = time (&now);
1828 store_mem (PARM1, 4, now);
1829 }
1830 break;
1831#endif
1832#endif
1833
1834#if !defined(__GO32__) && !defined(_WIN32)
1835#ifdef TARGET_SYS_times
1836 case TARGET_SYS_times:
1837 {
1838 struct tms tms;
1839 RETVAL = times (&tms);
1840 store_mem (PARM1, 4, tms.tms_utime);
1841 store_mem (PARM1 + 4, 4, tms.tms_stime);
1842 store_mem (PARM1 + 8, 4, tms.tms_cutime);
1843 store_mem (PARM1 + 12, 4, tms.tms_cstime);
1844 break;
1845 }
1846#endif
1847#endif
1848
1849#ifdef TARGET_SYS_gettimeofday
1850#if !defined(__GO32__) && !defined(_WIN32)
1851 case TARGET_SYS_gettimeofday:
1852 {
1853 struct timeval t;
1854 struct timezone tz;
1855 RETVAL = gettimeofday (&t, &tz);
1856 store_mem (PARM1, 4, t.tv_sec);
1857 store_mem (PARM1 + 4, 4, t.tv_usec);
1858 store_mem (PARM2, 4, tz.tz_minuteswest);
1859 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
1860 break;
1861 }
1862#endif
1863#endif
1864
1865#ifdef TARGET_SYS_utime
1866#if HAVE_UTIME
1867 case TARGET_SYS_utime:
1868 {
1869 /* Cast the second argument to void *, to avoid type mismatch
1870 if a prototype is present. */
1871 sim_io_error (simulator, "Utime not supported");
1872 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1873 }
1874 break;
1875#endif
1876#endif
1877
1878 default:
1879 abort ();
1880 }
1881 RETERR = errno;
1882 errno = save_errno;
1883
1884 return 4;
1885 }
1886 else
1887 { /* Trap 0 -> 30 */
1888 EIPC = PC + 4;
1889 EIPSW = PSW;
1890 /* Mask out EICC */
1891 ECR &= 0xffff0000;
1892 ECR |= 0x40 + OP[0];
1893 /* Flag that we are now doing exception processing. */
1894 PSW |= PSW_EP | PSW_ID;
2e8162ce 1895 PC = (OP[0] < 0x10) ? 0x40 : 0x50;
c906108c
SS		 1896
1897 return 0;
1898 }
1899}
1900
1901/* tst1 reg2, [reg1] */
1902int
1903OP_E607E0 (void)
1904{
1905 int temp;
1906
1907 trace_input ("tst1", OP_BIT, 1);
1908
1909 temp = load_mem (State.regs[ OP[0] ], 1);
1910
1911 PSW &= ~PSW_Z;
30458d39 1912 if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0)
c906108c
SS		 1913 PSW |= PSW_Z;
1914
1915 trace_output (OP_BIT);
1916
1917 return 4;
1918}
1919
1920/* mulu reg1, reg2, reg3 */
1921int
1922OP_22207E0 (void)
1923{
1924 trace_input ("mulu", OP_REG_REG_REG, 0);
1925
0da2b665 1926 Multiply64 (0, State.regs[ OP[0] ]);
c906108c
SS		 1927
1928 trace_output (OP_REG_REG_REG);
1929
1930 return 4;
1931}
1932
1933#define BIT_CHANGE_OP( name, binop ) \
1934 unsigned int bit; \
1935 unsigned int temp; \
1936 \
1937 trace_input (name, OP_BIT_CHANGE, 0); \
1938 \
30458d39 1939 bit = 1 << (State.regs[ OP[1] ] & 0x7); \
c906108c
SS		 1940 temp = load_mem (State.regs[ OP[0] ], 1); \
1941 \
1942 PSW &= ~PSW_Z; \
1943 if ((temp & bit) == 0) \
1944 PSW |= PSW_Z; \
1945 temp binop bit; \
1946 \
1947 store_mem (State.regs[ OP[0] ], 1, temp); \
1948 \
1949 trace_output (OP_BIT_CHANGE); \
1950 \
1951 return 4;
1952
1953/* clr1 reg2, [reg1] */
1954int
1955OP_E407E0 (void)
1956{
1957 BIT_CHANGE_OP ("clr1", &= ~ );
1958}
1959
1960/* not1 reg2, [reg1] */
1961int
1962OP_E207E0 (void)
1963{
1964 BIT_CHANGE_OP ("not1", ^= );
1965}
1966
1967/* set1 */
1968int
1969OP_E007E0 (void)
1970{
1971 BIT_CHANGE_OP ("set1", |= );
1972}
1973
1974/* sasf */
1975int
1976OP_20007E0 (void)
1977{
1978 trace_input ("sasf", OP_EX1, 0);
1979
1980 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
1981
1982 trace_output (OP_EX1);
1983
1984 return 4;
1985}
1986
1987/* This function is courtesy of Sugimoto at NEC, via Seow Tan
1988 (Soew_Tan@el.nec.com) */
1989void
1990divun
1991(
1992 unsigned int N,
1993 unsigned long int als,
1994 unsigned long int sfi,
1995 unsigned32 /*unsigned long int*/ * quotient_ptr,
1996 unsigned32 /*unsigned long int*/ * remainder_ptr,
0da2b665 1997 int * overflow_ptr
c906108c
SS		 1998)
1999{
2000 unsigned long ald = sfi >> (N - 1);
2001 unsigned long alo = als;
2002 unsigned int Q = 1;
2003 unsigned int C;
2004 unsigned int S = 0;
2005 unsigned int i;
2006 unsigned int R1 = 1;
2007 unsigned int DBZ = (als == 0) ? 1 : 0;
2008 unsigned long alt = Q ? ~als : als;
2009
2010 /* 1st Loop */
2011 alo = ald + alt + Q;
2012 C = (((alt >> 31) & (ald >> 31))
2013 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2014 C = C ^ Q;
2015 Q = ~(C ^ S) & 1;
2016 R1 = (alo == 0) ? 0 : (R1 & Q);
2017 if ((S ^ (alo>>31)) && !C)
2018 {
2019 DBZ = 1;
2020 }
2021 S = alo >> 31;
2022 sfi = (sfi << (32-N+1)) | Q;
2023 ald = (alo << 1) | (sfi >> 31);
2024
2025 /* 2nd - N-1th Loop */
2026 for (i = 2; i < N; i++)
2027 {
2028 alt = Q ? ~als : als;
2029 alo = ald + alt + Q;
2030 C = (((alt >> 31) & (ald >> 31))
2031 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2032 C = C ^ Q;
2033 Q = ~(C ^ S) & 1;
2034 R1 = (alo == 0) ? 0 : (R1 & Q);
2035 if ((S ^ (alo>>31)) && !C && !DBZ)
2036 {
2037 DBZ = 1;
2038 }
2039 S = alo >> 31;
2040 sfi = (sfi << 1) | Q;
2041 ald = (alo << 1) | (sfi >> 31);
2042 }
2043
2044 /* Nth Loop */
2045 alt = Q ? ~als : als;
2046 alo = ald + alt + Q;
2047 C = (((alt >> 31) & (ald >> 31))
2048 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2049 C = C ^ Q;
2050 Q = ~(C ^ S) & 1;
2051 R1 = (alo == 0) ? 0 : (R1 & Q);
2052 if ((S ^ (alo>>31)) && !C)
2053 {
2054 DBZ = 1;
2055 }
2056
2057 * quotient_ptr = (sfi << 1) | Q;
2058 * remainder_ptr = Q ? alo : (alo + als);
2059 * overflow_ptr = DBZ | R1;
2060}
2061
2062/* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2063void
2064divn
2065(
2066 unsigned int N,
2067 unsigned long int als,
2068 unsigned long int sfi,
2069 signed32 /*signed long int*/ * quotient_ptr,
2070 signed32 /*signed long int*/ * remainder_ptr,
0da2b665 2071 int * overflow_ptr
c906108c
SS		 2072)
2073{
2074 unsigned long ald = (signed long) sfi >> (N - 1);
2075 unsigned long alo = als;
2076 unsigned int SS = als >> 31;
2077 unsigned int SD = sfi >> 31;
2078 unsigned int R1 = 1;
2079 unsigned int OV;
2080 unsigned int DBZ = als == 0 ? 1 : 0;
2081 unsigned int Q = ~(SS ^ SD) & 1;
2082 unsigned int C;
2083 unsigned int S;
2084 unsigned int i;
2085 unsigned long alt = Q ? ~als : als;
2086
2087
2088 /* 1st Loop */
2089
2090 alo = ald + alt + Q;
2091 C = (((alt >> 31) & (ald >> 31))
2092 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2093 Q = C ^ SS;
2094 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2095 S = alo >> 31;
2096 sfi = (sfi << (32-N+1)) | Q;
2097 ald = (alo << 1) | (sfi >> 31);
2098 if ((alo >> 31) ^ (ald >> 31))
2099 {
2100 DBZ = 1;
2101 }
2102
2103 /* 2nd - N-1th Loop */
2104
2105 for (i = 2; i < N; i++)
2106 {
2107 alt = Q ? ~als : als;
2108 alo = ald + alt + Q;
2109 C = (((alt >> 31) & (ald >> 31))
2110 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2111 Q = C ^ SS;
2112 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2113 S = alo >> 31;
2114 sfi = (sfi << 1) | Q;
2115 ald = (alo << 1) | (sfi >> 31);
2116 if ((alo >> 31) ^ (ald >> 31))
2117 {
2118 DBZ = 1;
2119 }
2120 }
2121
2122 /* Nth Loop */
2123 alt = Q ? ~als : als;
2124 alo = ald + alt + Q;
2125 C = (((alt >> 31) & (ald >> 31))
2126 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2127 Q = C ^ SS;
2128 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2129 sfi = (sfi << (32-N+1));
2130 ald = alo;
2131
2132 /* End */
2133 if (alo != 0)
2134 {
2135 alt = Q ? ~als : als;
2136 alo = ald + alt + Q;
2137 }
2138 R1 = R1 & ((~alo >> 31) ^ SD);
2139 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2140 if (N != 32)
2141 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2142 else
2143 ald = sfi = sfi | Q;
2144
2145 OV = DBZ | ((alo == 0) ? 0 : R1);
2146
2147 * remainder_ptr = alo;
2148
2149 /* Adj */
2150 if (((alo != 0) && ((SS ^ SD) ^ R1))
2151 || ((alo == 0) && (SS ^ R1)))
2152 alo = ald + 1;
2153 else
2154 alo = ald;
2155
2156 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2157
2158 * quotient_ptr = alo;
2159 * overflow_ptr = OV;
2160}
2161
2162/* sdivun imm5, reg1, reg2, reg3 */
2163int
2164OP_1C207E0 (void)
2165{
2166 unsigned32 /*unsigned long int*/ quotient;
2167 unsigned32 /*unsigned long int*/ remainder;
2168 unsigned long int divide_by;
2169 unsigned long int divide_this;
0da2b665 2170 int overflow = 0;
c906108c
SS		 2171 unsigned int imm5;
2172
2173 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2174
2175 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2176
2177 divide_by = State.regs[ OP[0] ];
2178 divide_this = State.regs[ OP[1] ] << imm5;
2179
2180 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2181
2182 State.regs[ OP[1] ] = quotient;
2183 State.regs[ OP[2] >> 11 ] = remainder;
2184
2185 /* Set condition codes. */
2186 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2187
2188 if (overflow) PSW |= PSW_OV;
2189 if (quotient == 0) PSW |= PSW_Z;
2190 if (quotient & 0x80000000) PSW |= PSW_S;
2191
2192 trace_output (OP_IMM_REG_REG_REG);
2193
2194 return 4;
2195}
2196
2197/* sdivn imm5, reg1, reg2, reg3 */
2198int
2199OP_1C007E0 (void)
2200{
2201 signed32 /*signed long int*/ quotient;
2202 signed32 /*signed long int*/ remainder;
2203 signed long int divide_by;
2204 signed long int divide_this;
0da2b665 2205 int overflow = 0;
c906108c
SS		 2206 unsigned int imm5;
2207
2208 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2209
2210 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2211
98e460c3
DD		 2212 divide_by = (signed32) State.regs[ OP[0] ];
2213 divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
c906108c
SS		 2214
2215 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2216
2217 State.regs[ OP[1] ] = quotient;
2218 State.regs[ OP[2] >> 11 ] = remainder;
2219
2220 /* Set condition codes. */
2221 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2222
2223 if (overflow) PSW |= PSW_OV;
2224 if (quotient == 0) PSW |= PSW_Z;
2225 if (quotient < 0) PSW |= PSW_S;
2226
2227 trace_output (OP_IMM_REG_REG_REG);
2228
2229 return 4;
2230}
2231
2232/* sdivhun imm5, reg1, reg2, reg3 */
2233int
2234OP_18207E0 (void)
2235{
2236 unsigned32 /*unsigned long int*/ quotient;
2237 unsigned32 /*unsigned long int*/ remainder;
2238 unsigned long int divide_by;
2239 unsigned long int divide_this;
0da2b665 2240 int overflow = 0;
c906108c
SS		 2241 unsigned int imm5;
2242
2243 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2244
2245 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2246
2247 divide_by = State.regs[ OP[0] ] & 0xffff;
2248 divide_this = State.regs[ OP[1] ] << imm5;
2249
2250 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2251
2252 State.regs[ OP[1] ] = quotient;
2253 State.regs[ OP[2] >> 11 ] = remainder;
2254
2255 /* Set condition codes. */
2256 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2257
2258 if (overflow) PSW |= PSW_OV;
2259 if (quotient == 0) PSW |= PSW_Z;
2260 if (quotient & 0x80000000) PSW |= PSW_S;
2261
2262 trace_output (OP_IMM_REG_REG_REG);
2263
2264 return 4;
2265}
2266
2267/* sdivhn imm5, reg1, reg2, reg3 */
2268int
2269OP_18007E0 (void)
2270{
2271 signed32 /*signed long int*/ quotient;
2272 signed32 /*signed long int*/ remainder;
2273 signed long int divide_by;
2274 signed long int divide_this;
0da2b665 2275 int overflow = 0;
c906108c
SS		 2276 unsigned int imm5;
2277
2278 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2279
2280 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2281
2282 divide_by = EXTEND16 (State.regs[ OP[0] ]);
98e460c3 2283 divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
c906108c
SS		 2284
2285 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2286
2287 State.regs[ OP[1] ] = quotient;
2288 State.regs[ OP[2] >> 11 ] = remainder;
2289
2290 /* Set condition codes. */
2291 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2292
2293 if (overflow) PSW |= PSW_OV;
2294 if (quotient == 0) PSW |= PSW_Z;
2295 if (quotient < 0) PSW |= PSW_S;
2296
2297 trace_output (OP_IMM_REG_REG_REG);
2298
2299 return 4;
2300}
2301
2302/* divu reg1, reg2, reg3 */
2303int
2304OP_2C207E0 (void)
2305{
2306 unsigned long int quotient;
2307 unsigned long int remainder;
2308 unsigned long int divide_by;
2309 unsigned long int divide_this;
0da2b665 2310 int overflow = 0;
c906108c
SS		 2311
2312 trace_input ("divu", OP_REG_REG_REG, 0);
2313
2314 /* Compute the result. */
2315
2316 divide_by = State.regs[ OP[0] ];
2317 divide_this = State.regs[ OP[1] ];
2318
2319 if (divide_by == 0)
2320 {
c5fbc25b 2321 PSW |= PSW_OV;
c906108c 2322 }
c5fbc25b
DD		 2323 else
2324 {
2325 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2326 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
c906108c 2327
c5fbc25b
DD		 2328 /* Set condition codes. */
2329 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
c906108c 2330
c5fbc25b
DD		 2331 if (overflow) PSW |= PSW_OV;
2332 if (quotient == 0) PSW |= PSW_Z;
2333 if (quotient & 0x80000000) PSW |= PSW_S;
2334 }
c906108c
SS		 2335
2336 trace_output (OP_REG_REG_REG);
2337
2338 return 4;
2339}
2340
2341/* div reg1, reg2, reg3 */
2342int
2343OP_2C007E0 (void)
2344{
2345 signed long int quotient;
2346 signed long int remainder;
2347 signed long int divide_by;
2348 signed long int divide_this;
c906108c
SS		 2349
2350 trace_input ("div", OP_REG_REG_REG, 0);
2351
2352 /* Compute the result. */
2353
98e460c3 2354 divide_by = (signed32) State.regs[ OP[0] ];
c906108c
SS		 2355 divide_this = State.regs[ OP[1] ];
2356
c5fbc25b 2357 if (divide_by == 0)
c906108c 2358 {
c5fbc25b 2359 PSW |= PSW_OV;
c906108c 2360 }
98e460c3 2361 else if (divide_by == -1 && divide_this == (1L << 31))
c5fbc25b
DD		 2362 {
2363 PSW &= ~PSW_Z;
2364 PSW |= PSW_OV | PSW_S;
2365 State.regs[ OP[1] ] = (1 << 31);
2366 State.regs[ OP[2] >> 11 ] = 0;
2367 }
2368 else
2369 {
98e460c3 2370 divide_this = (signed32) divide_this;
c5fbc25b
DD		 2371 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2372 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
98e460c3 2373
c5fbc25b
DD		 2374 /* Set condition codes. */
2375 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
c906108c 2376
c5fbc25b
DD		 2377 if (quotient == 0) PSW |= PSW_Z;
2378 if (quotient < 0) PSW |= PSW_S;
2379 }
c906108c
SS		 2380
2381 trace_output (OP_REG_REG_REG);
2382
2383 return 4;
2384}
2385
2386/* divhu reg1, reg2, reg3 */
2387int
2388OP_28207E0 (void)
2389{
2390 unsigned long int quotient;
2391 unsigned long int remainder;
2392 unsigned long int divide_by;
2393 unsigned long int divide_this;
0da2b665 2394 int overflow = 0;
c906108c
SS		 2395
2396 trace_input ("divhu", OP_REG_REG_REG, 0);
2397
2398 /* Compute the result. */
2399
2400 divide_by = State.regs[ OP[0] ] & 0xffff;
2401 divide_this = State.regs[ OP[1] ];
2402
2403 if (divide_by == 0)
2404 {
c5fbc25b 2405 PSW |= PSW_OV;
c906108c 2406 }
c5fbc25b
DD		 2407 else
2408 {
2409 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2410 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
c906108c 2411
c5fbc25b
DD		 2412 /* Set condition codes. */
2413 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
c906108c 2414
c5fbc25b
DD		 2415 if (overflow) PSW |= PSW_OV;
2416 if (quotient == 0) PSW |= PSW_Z;
2417 if (quotient & 0x80000000) PSW |= PSW_S;
2418 }
c906108c
SS		 2419
2420 trace_output (OP_REG_REG_REG);
2421
2422 return 4;
2423}
2424
2425/* divh reg1, reg2, reg3 */
2426int
2427OP_28007E0 (void)
2428{
2429 signed long int quotient;
2430 signed long int remainder;
2431 signed long int divide_by;
2432 signed long int divide_this;
0da2b665 2433 int overflow = 0;
c906108c
SS		 2434
2435 trace_input ("divh", OP_REG_REG_REG, 0);
2436
2437 /* Compute the result. */
2438
c5fbc25b
DD		 2439 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2440 divide_this = State.regs[ OP[1] ];
c906108c 2441
c5fbc25b
DD		 2442 if (divide_by == 0)
2443 {
2444 PSW |= PSW_OV;
2445 }
98e460c3 2446 else if (divide_by == -1 && divide_this == (1L << 31))
c906108c 2447 {
c5fbc25b
DD		 2448 PSW &= ~PSW_Z;
2449 PSW |= PSW_OV | PSW_S;
2450 State.regs[ OP[1] ] = (1 << 31);
2451 State.regs[ OP[2] >> 11 ] = 0;
c906108c 2452 }
c5fbc25b
DD		 2453 else
2454 {
98e460c3 2455 divide_this = (signed32) divide_this;
c5fbc25b
DD		 2456 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2457 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
c906108c 2458
c5fbc25b
DD		 2459 /* Set condition codes. */
2460 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
c906108c 2461
c5fbc25b
DD		 2462 if (quotient == 0) PSW |= PSW_Z;
2463 if (quotient < 0) PSW |= PSW_S;
2464 }
c906108c
SS		 2465
2466 trace_output (OP_REG_REG_REG);
2467
2468 return 4;
2469}
2470
2471/* mulu imm9, reg2, reg3 */
2472int
2473OP_24207E0 (void)
2474{
2475 trace_input ("mulu", OP_IMM_REG_REG, 0);
2476
0da2b665 2477 Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
c906108c
SS		 2478
2479 trace_output (OP_IMM_REG_REG);
2480
2481 return 4;
2482}
2483
2484/* mul imm9, reg2, reg3 */
2485int
2486OP_24007E0 (void)
2487{
2488 trace_input ("mul", OP_IMM_REG_REG, 0);
2489
0da2b665 2490 Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)));
c906108c
SS		 2491
2492 trace_output (OP_IMM_REG_REG);
2493
2494 return 4;
2495}
2496
2497/* ld.hu */
2498int
2499OP_107E0 (void)
2500{
2501 int adr;
2502
2503 trace_input ("ld.hu", OP_LOAD32, 2);
2504
2505 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
2506 adr &= ~0x1;
2507
2508 State.regs[ OP[1] ] = load_mem (adr, 2);
2509
2510 trace_output (OP_LOAD32);
2511
2512 return 4;
2513}
2514
2515
2516/* ld.bu */
2517int
2518OP_10780 (void)
2519{
2520 int adr;
2521
2522 trace_input ("ld.bu", OP_LOAD32, 1);
2523
2524 adr = (State.regs[ OP[0] ]
2525 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
2526
2527 State.regs[ OP[1] ] = load_mem (adr, 1);
2528
2529 trace_output (OP_LOAD32);
2530
2531 return 4;
2532}
2533
2534/* prepare list12, imm5, imm32 */
2535int
2536OP_1B0780 (void)
2537{
2538 int i;
2539
2540 trace_input ("prepare", OP_PUSHPOP1, 0);
2541
2542 /* Store the registers with lower number registers being placed at higher addresses. */
2543 for (i = 0; i < 12; i++)
2544 if ((OP[3] & (1 << type1_regs[ i ])))
2545 {
2546 SP -= 4;
2547 store_mem (SP, 4, State.regs[ 20 + i ]);
2548 }
2549
2550 SP -= (OP[3] & 0x3e) << 1;
2551
2552 EP = load_mem (PC + 4, 4);
2553
2554 trace_output (OP_PUSHPOP1);
2555
2556 return 8;
2557}
2558
2559/* prepare list12, imm5, imm16-32 */
2560int
2561OP_130780 (void)
2562{
2563 int i;
2564
2565 trace_input ("prepare", OP_PUSHPOP1, 0);
2566
2567 /* Store the registers with lower number registers being placed at higher addresses. */
2568 for (i = 0; i < 12; i++)
2569 if ((OP[3] & (1 << type1_regs[ i ])))
2570 {
2571 SP -= 4;
2572 store_mem (SP, 4, State.regs[ 20 + i ]);
2573 }
2574
2575 SP -= (OP[3] & 0x3e) << 1;
2576
2577 EP = load_mem (PC + 4, 2) << 16;
2578
2579 trace_output (OP_PUSHPOP1);
2580
2581 return 6;
2582}
2583
2584/* prepare list12, imm5, imm16 */
2585int
2586OP_B0780 (void)
2587{
2588 int i;
2589
2590 trace_input ("prepare", OP_PUSHPOP1, 0);
2591
2592 /* Store the registers with lower number registers being placed at higher addresses. */
2593 for (i = 0; i < 12; i++)
2594 if ((OP[3] & (1 << type1_regs[ i ])))
2595 {
2596 SP -= 4;
2597 store_mem (SP, 4, State.regs[ 20 + i ]);
2598 }
2599
2600 SP -= (OP[3] & 0x3e) << 1;
2601
2602 EP = EXTEND16 (load_mem (PC + 4, 2));
2603
2604 trace_output (OP_PUSHPOP1);
2605
2606 return 6;
2607}
2608
2609/* prepare list12, imm5, sp */
2610int
2611OP_30780 (void)
2612{
2613 int i;
2614
2615 trace_input ("prepare", OP_PUSHPOP1, 0);
2616
2617 /* Store the registers with lower number registers being placed at higher addresses. */
2618 for (i = 0; i < 12; i++)
2619 if ((OP[3] & (1 << type1_regs[ i ])))
2620 {
2621 SP -= 4;
2622 store_mem (SP, 4, State.regs[ 20 + i ]);
2623 }
2624
2625 SP -= (OP[3] & 0x3e) << 1;
2626
2627 EP = SP;
2628
2629 trace_output (OP_PUSHPOP1);
2630
2631 return 4;
2632}
2633
2634/* mul reg1, reg2, reg3 */
2635int
2636OP_22007E0 (void)
2637{
2638 trace_input ("mul", OP_REG_REG_REG, 0);
2639
0da2b665 2640 Multiply64 (1, State.regs[ OP[0] ]);
c906108c
SS		 2641
2642 trace_output (OP_REG_REG_REG);
2643
2644 return 4;
2645}
2646
2647/* popmh list18 */
2648int
2649OP_307F0 (void)
2650{
2651 int i;
2652
2653 trace_input ("popmh", OP_PUSHPOP2, 0);
2654
2655 if (OP[3] & (1 << 19))
2656 {
2657 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2658 {
2659 FEPSW = load_mem ( SP & ~ 3, 4);
2660 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2661 }
2662 else
2663 {
2664 EIPSW = load_mem ( SP & ~ 3, 4);
2665 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2666 }
2667
2668 SP += 8;
2669 }
2670
2671 /* Load the registers with lower number registers being retrieved from higher addresses. */
2672 for (i = 16; i--;)
2673 if ((OP[3] & (1 << type2_regs[ i ])))
2674 {
2675 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
2676 SP += 4;
2677 }
2678
2679 trace_output (OP_PUSHPOP2);
2680
2681 return 4;
2682}
2683
2684/* popml lsit18 */
2685int
2686OP_107F0 (void)
2687{
2688 int i;
2689
2690 trace_input ("popml", OP_PUSHPOP3, 0);
2691
2692 if (OP[3] & (1 << 19))
2693 {
2694 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2695 {
2696 FEPSW = load_mem ( SP & ~ 3, 4);
2697 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2698 }
2699 else
2700 {
2701 EIPSW = load_mem ( SP & ~ 3, 4);
2702 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2703 }
2704
2705 SP += 8;
2706 }
2707
2708 if (OP[3] & (1 << 3))
2709 {
2710 PSW = load_mem (SP & ~ 3, 4);
2711 SP += 4;
2712 }
2713
2714 /* Load the registers with lower number registers being retrieved from higher addresses. */
2715 for (i = 15; i--;)
2716 if ((OP[3] & (1 << type3_regs[ i ])))
2717 {
2718 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
2719 SP += 4;
2720 }
2721
2722 trace_output (OP_PUSHPOP2);
2723
2724 return 4;
2725}
2726
2727/* pushmh list18 */
2728int
2729OP_307E0 (void)
2730{
2731 int i;
2732
2733 trace_input ("pushmh", OP_PUSHPOP2, 0);
2734
2735 /* Store the registers with lower number registers being placed at higher addresses. */
2736 for (i = 0; i < 16; i++)
2737 if ((OP[3] & (1 << type2_regs[ i ])))
2738 {
2739 SP -= 4;
2740 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
2741 }
2742
2743 if (OP[3] & (1 << 19))
2744 {
2745 SP -= 8;
2746
2747 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2748 {
2749 store_mem ((SP + 4) & ~ 3, 4, FEPC);
2750 store_mem ( SP & ~ 3, 4, FEPSW);
2751 }
2752 else
2753 {
2754 store_mem ((SP + 4) & ~ 3, 4, EIPC);
2755 store_mem ( SP & ~ 3, 4, EIPSW);
2756 }
2757 }
2758
2759 trace_output (OP_PUSHPOP2);
2760
2761 return 4;
2762}
2763
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