]> git.ipfire.org Git - thirdparty/glibc.git/blame - sysdeps/hppa/hppa1.1/mul_1.S
Update copyright dates with scripts/update-copyrights.
[thirdparty/glibc.git] / sysdeps / hppa / hppa1.1 / mul_1.S
CommitLineData
acc97172
UD
1;! HP-PA-1.1 __mpn_mul_1 -- Multiply a limb vector with a limb and store
2;! the result in a second limb vector.
7def3d92 3
04277e02 4;! Copyright (C) 1992-2019 Free Software Foundation, Inc.
7def3d92 5
acc97172 6;! This file is part of the GNU MP Library.
7def3d92 7
acc97172 8;! The GNU MP Library is free software; you can redistribute it and/or modify
f01ec467
AJ
9;! it under the terms of the GNU Lesser General Public License as published by
10;! the Free Software Foundation; either version 2.1 of the License, or (at your
acc97172 11;! option) any later version.
7def3d92 12
acc97172
UD
13;! The GNU MP Library is distributed in the hope that it will be useful, but
14;! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
f01ec467 15;! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
acc97172 16;! License for more details.
7def3d92 17
f01ec467 18;! You should have received a copy of the GNU Lesser General Public License
ab84e3ff
PE
19;! along with the GNU MP Library. If not, see
20;! <http://www.gnu.org/licenses/>.
7def3d92
RM
21
22
acc97172
UD
23;! INPUT PARAMETERS
24;! res_ptr r26
25;! s1_ptr r25
26;! size r24
27;! s2_limb r23
7def3d92 28
acc97172
UD
29;! This runs at 9 cycles/limb on a PA7000. With the used instructions, it can
30;! not become faster due to data cache contention after a store. On the
31;! PA7100 it runs at 7 cycles/limb, and that can not be improved either, since
32;! only the xmpyu does not need the integer pipeline, so the only dual-issue
33;! we will get are addc+xmpyu. Unrolling would not help either CPU.
7def3d92 34
acc97172
UD
35;! We could use fldds to read two limbs at a time from the S1 array, and that
36;! could bring down the times to 8.5 and 6.5 cycles/limb for the PA7000 and
37;! PA7100, respectively. We don't do that since it does not seem worth the
38;! (alignment) troubles...
7def3d92 39
acc97172
UD
40;! At least the PA7100 is rumored to be able to deal with cache-misses
41;! without stalling instruction issue. If this is true, and the cache is
42;! actually also lockup-free, we should use a deeper software pipeline, and
43;! load from S1 very early; (The loads and stores to -12(sp) will surely be
44;! in the cache.)
7def3d92 45
acc97172 46 .text
7def3d92 47 .export __mpn_mul_1
5556231d 48__mpn_mul_1:
7def3d92
RM
49 .proc
50 .callinfo frame=64,no_calls
51 .entry
52
53 ldo 64(%r30),%r30
54 fldws,ma 4(%r25),%fr5
acc97172 55 stw %r23,-16(%r30) ;! move s2_limb ...
7def3d92 56 addib,= -1,%r24,L$just_one_limb
acc97172
UD
57 fldws -16(%r30),%fr4 ;! ... into fr4
58 add %r0,%r0,%r0 ;! clear carry
7def3d92
RM
59 xmpyu %fr4,%fr5,%fr6
60 fldws,ma 4(%r25),%fr7
61 fstds %fr6,-16(%r30)
62 xmpyu %fr4,%fr7,%fr8
acc97172 63 ldw -12(%r30),%r20 ;! least significant limb in product
7def3d92
RM
64 ldw -16(%r30),%r28
65
66 fstds %fr8,-16(%r30)
67 addib,= -1,%r24,L$end
68 ldw -12(%r30),%r1
69
acc97172 70;! Main loop
5556231d 71L$loop:
acc97172
UD
72 fldws,ma 4(%r25),%fr5
73 stws,ma %r20,4(%r26)
74 addc %r28,%r1,%r20
7def3d92
RM
75 xmpyu %fr4,%fr5,%fr6
76 ldw -16(%r30),%r28
77 fstds %fr6,-16(%r30)
78 addib,<> -1,%r24,L$loop
79 ldw -12(%r30),%r1
80
5556231d 81L$end:
acc97172
UD
82 stws,ma %r20,4(%r26)
83 addc %r28,%r1,%r20
7def3d92 84 ldw -16(%r30),%r28
acc97172 85 stws,ma %r20,4(%r26)
7def3d92
RM
86 addc %r0,%r28,%r28
87 bv 0(%r2)
88 ldo -64(%r30),%r30
89
5556231d 90L$just_one_limb:
7def3d92
RM
91 xmpyu %fr4,%fr5,%fr6
92 fstds %fr6,-16(%r30)
93 ldw -16(%r30),%r28
94 ldo -64(%r30),%r30
95 bv 0(%r2)
96 fstws %fr6R,0(%r26)
97
98 .exit
99 .procend